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  pxd10 microcontroller reference manual devices supported: pxd1005 pxd1010 PXD10RM rev. 1 09/2011
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com document number: PXD10RM rev. 1 09/2011 information in this document is provided solely to enable system and software implementers to use freescale semicond uctor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the ri ght to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of an y product or circuit, and specifically disclaims any and all liability, includ ing without limitati on consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical expe rts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semico nductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. ? freescale semiconductor, inc. 2011. all rights reserved.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor iii chapter 1 overview 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 pxd10 family comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.4 chip-level features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.5 feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.5.1 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.5.2 e200z0h core processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.5.3 display control unit (dcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.5.4 parallel data interface (pdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.5.5 liquid crystal display (lcd) driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.5.6 stepper motor controller (smc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.5.7 stepper stall detector (ssd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.5.8 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.5.9 static random-access memory (sram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.5.10 on-chip graphics sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 1.5.11 quadspi serial flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.5.12 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 1.5.13 sound generation logic (sgl) module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.5.14 serial communication interface module (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.5.15 serial peripheral interface (spi) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 1.5.16 controller area network (can) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.5.17 inter-ic communications (i2c) module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 1.5.18 real time counter (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.5.19 enhanced modular input/output system (timers, pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 1.5.20 periodic interrupt timer (pit) module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 1.5.21 system timer module (stm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.5.22 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.5.23 interrupt controller (intc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22 1.5.24 system integration unit (siu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.5.25 system clocks and clock generation modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 1.5.26 crossbar switch (xbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 1.5.27 enhanced direct memory access (edma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.5.28 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 1.5.29 boot assist module (bam). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 1.5.30 ieee 1149.1 jtag controller (jtagc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 1.5.31 nexus development interface (ndi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 1.6 developer environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 1.7 how to use the pxd10 documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 1.7.1 the pxd10 document set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 1.7.2 reference manual content. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 1.8 using the pxd10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 1.8.1 hardware design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 1.8.2 input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 1.8.3 software design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 1.8.4 other features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 chapter 2 memory map chapter 3 signal description 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 pad configuration during reset phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4 voltage supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.5 pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.6 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
pxd10 microcontroller reference manual, rev. 1 iv freescale semiconductor 3.7 debug pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.8 functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.9 signal details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 chapter 4 safety 4.1 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1.3 modes of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.1.3.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.1.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.1.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.1.4.2 change lock settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.1.4.3 access errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.1.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.2 software watchdog timer (swt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.2.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.2.4 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.2.5.2 swt control register (swt_cr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.2.5.3 swt interrupt register (swt_ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.2.5.4 swt time-out register (swt_to) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.2.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 chapter 5 analog-to-digital converter (adc) 5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.1 device-specific features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1.2 device-specific implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.1 analog channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.1.1 normal conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.1.2 start of normal conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.1.3 normal conversion operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.3.1.4 injected channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.3.1.5 abort conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 5.3.2 analog clock generator and conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.3.3 adc sampling and conversion timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 5.3.4 programmable analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.3.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.3.5 dma functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.3.7 external decode signals delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3.8 power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.3.9 auto-clock-off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.4.2 control logic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.4.2.1 main configuration register (mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 5.4.2.2 main status register (msr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 5.4.3 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor v 5.4.3.1 interrupt status register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19 5.4.3.2 channel pending registers (ceocfr[1..2]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20 5.4.3.3 interrupt mask register (imr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21 5.4.3.4 channel interrupt mask register (cimr[1..2]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23 5.4.3.5 watchdog threshold interrupt status register (wtisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.4.3.6 watchdog threshold interrupt mask register (wtimr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 5.4.4 dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.4.4.1 dma enable register (dmae) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26 5.4.4.2 dma channel select register (dmar[1..2]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 5.4.5 threshold registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.5.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.5.2 threshold control register (trcx, x = [0..3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28 5.4.5.3 threshold register (thrhlr[0:3]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29 5.4.6 conversion timing registers ctr[1..2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30 5.4.7 mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.4.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.4.7.2 normal conversion mask registers (ncmr[1..2]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 5.4.7.3 injected conversion mask registers (jcmr[1..2]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32 5.4.8 delay registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.4.8.1 decode signals delay register (dsdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.4.8.2 power-down exit delay register (pdedr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33 5.4.9 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 5.4.9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 5.4.9.2 channel data register (cdr[0..95]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 chapter 6 boot assist module (bam) 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.3 boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.5.1 entering boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.5.2 reset configuration half word source (rchw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.5.3 single chip boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.5.3.1 boot and alternate boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5.4 boot through bam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5.4.1 executing bam . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.5.4.2 bam software flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.5.4.3 bam resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.5.4.4 download and execute the new code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.5.4.5 download 64-bit password and password check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 6.5.4.6 download start address, vle bit and code size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.5.4.7 download data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.5.4.8 execute code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.5.5 boot from uart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.5.5.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.5.5.2 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.5.6 bootstrap with can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.5.6.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.6 protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 chapter 7 can sampler 7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.3.1 can sampler control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.3.2 can sampler sample registers 0?11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
pxd10 microcontroller reference manual, rev. 1 vi freescale semiconductor 7.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.4.1 enabling/disabling the can sampler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.4.2 selecting the rx port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.4.3 baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.5 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 chapter 8 clock description 8.1 clock architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 auxiliary clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.3 clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.4 clock generation module (mc_cgm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.4.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.4.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.4.1.3 modes of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.4.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.4.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.4.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10 8.4.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 8.4.4.1 system clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 8.4.4.2 auxiliary clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 8.4.4.3 output clock multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 8.4.4.4 output clock division selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 8.5 fxosc external oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24 8.5.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25 8.5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25 8.5.3 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26 8.6 32 khz osc digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 8.6.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 8.6.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 8.6.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27 8.6.4 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28 8.7 sirc digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 8.7.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 8.7.2 low power rc oscillator (128 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 8.7.3 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 8.8 firc digital interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 8.8.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 8.8.2 functional description (16 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31 8.8.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31 8.9 frequency-modulated phase locked l oops and system clocks (fmpll0 and fmpll1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 8.9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 8.9.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 8.9.3 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32 8.9.4 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33 8.9.5 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33 8.9.5.1 control register (cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-34 8.9.5.2 modulation register (mr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36 8.9.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 8.9.6.1 normal mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 8.9.6.2 progressive clock cwitching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37 8.9.6.3 normal mode with frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38 8.9.6.4 powerdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-39 8.9.6.5 1:1 mode (fmpll0 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-39 8.9.7 recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40 8.10 clock monitor unit (cmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40 8.10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40 8.10.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41 8.10.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42 8.10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42 8.10.4.1crystal clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor vii 8.10.4.2pll clock monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43 8.10.4.3frequency meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43 8.10.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44 8.10.5.1control status register (cmu_csr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44 8.10.5.2frequency display register (cmu_fdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-45 8.10.5.3high frequency reference register fmpll0 (cmu_hfrefr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46 8.10.5.4low frequency reference register fmpll0 (cmu_lfrefr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-46 8.10.5.5interrupt status register (cmu_isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-47 8.10.5.6measurement duration register (cmu_mdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48 8.10.6 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-48 chapter 9 configurable enhanced modu lar io subsyst em (emios200) 9.1 device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1.1 unsupported features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1.2 device-specific configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.1.3 emios clocking configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.1.4 pxd10 family comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.1.5 channel types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.1.6 unified channel block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.1.6.1 channel mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.2.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.3 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.2.1 emiosi[n] - emios200 channel input signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.2.2 emioso[n] - emios200 channel output signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.3.2.3 emios_flag_out[n] - emios200 channel flag signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.4.1.1 unified channel memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 9.4.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.4.2.1 emios200 module configuration register (emiosmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.4.2.2 emios200 global flag register (emiosgflag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.4.2.3 emios200 output update disable (emiosoudis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.4.2.4 emios200 disable channel (emiosucdis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.4.2.5 emios200 uc a register (emiosa[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9.4.2.6 emios200 uc b register (emiosb[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 9.4.2.7 emios200 uc counter register (emioscnt[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.4.2.8 emios200 uc control register (emiosc[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 9.4.2.9 emios200 uc status register (emioss[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 9.4.2.10emios200 uc alternate a register (emiosalta[n]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 9.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 9.5.1 unified channel (uc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 9.5.1.1 uc modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28 9.5.1.2 input programmable filter (ipf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-42 9.5.1.3 clock prescaler (cp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43 9.5.1.4 effect of freeze on the unified channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 9.5.2 ip bus interface unit (biu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 9.5.2.1 effect of freeze on the biu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 9.5.3 real-time signal client submodule (re dc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-44 9.5.3.1 effect of freeze on the redc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-45 9.5.4 global clock prescaler submodule (gcp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-45 9.5.4.1 effect of freeze on the gcp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-45 9.6 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-46 9.6.1 considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-46 9.6.2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-46 9.6.2.1 time base generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-46 9.6.2.2 coherent accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48
pxd10 microcontroller reference manual, rev. 1 viii freescale semiconductor 9.6.2.3 channel/modes initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-48 chapter 10 crossbar switch (xbar) 10.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.5.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.5.2 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 10.6.2 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.6.3 master ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.6.4 slave ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.6.5 priority assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.6.6 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.6.6.1fixed priority operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 chapter 11 deserial serial peripheral interface (dspi) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.5.3 module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.5.4 external stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.5.5 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.6 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.6.1 signal overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.6.2 signal names and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.6.2.1peripheral chip select / slave select (cs_0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.6.2.2peripheral chip selects 1?2 (cs1:2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.6.2.3serial input (sin_x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.6.2.4serial output (sout_x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.6.2.5serial clock (sck_ x ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.7 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.7.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.7.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.7.2.1dspi module configuration register (dspix_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.7.2.2dspi transfer count register (dspix_tcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7.2.3dspi clock and transfer attributes registers 0?7 (dspix_ctarn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.7.2.4dspi status register (dspix_sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16 11.7.2.5dspi dma / interrupt request select and enable register (dspix_rser). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 11.7.2.6dspi push tx fifo register (dspix_pushr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-20 11.7.2.7dspi pop rx fifo register (dspix_popr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22 11.7.2.8dspi transmit fifo registers 0?4 (dspix_txfrn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23 11.7.2.9dspi receive fifo registers 0?4 (dspix_rxfrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 11.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 11.8.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-25 11.8.1.1master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.8.1.2slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.8.1.3module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.8.1.4external stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.8.1.5debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-26 11.8.2 start and stop of dspi transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor ix 11.8.3 serial peripheral interface (spi) configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 11.8.3.1spi master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11.8.3.2spi slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11.8.3.3fifo disable operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 11.8.3.4transmit first in first out (tx fifo) buffering mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 11.8.3.5receive first in first out (rx fifo ) buffering mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-30 11.8.4 dspi baud rate and clock delay generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11.8.4.1baud rate generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11.8.4.2cs to sck delay (tcsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-31 11.8.4.3after sck delay (tasc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11.8.4.4delay after transfer (tdt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 11.8.5 transfer formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 11.8.5.1classic spi transfer format (cpha = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-35 11.8.5.2classic spi transfer format (cpha = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-36 11.8.5.3modified spi transfer format (mtfe = 1, cpha = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 11.8.5.4modified spi transfer format (mtfe = 1, cpha = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38 11.8.5.5continuous selection format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-39 11.8.5.6clock polarity switching between dspi transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-40 11.8.6 continuous serial communications clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-41 11.8.7 interrupts/dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 11.8.7.1end of queue interrupt request (eoqf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 11.8.7.2transmit fifo fill interrupt or dma request (tfff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 11.8.7.3transfer complete interrupt request (tcf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 11.8.7.4transmit fifo underflow interrupt request (tfuf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.8.7.5receive fifo drain interrupt or dma request (rfdf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.8.7.6receive fifo overflow interrupt request (rfof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.8.7.7fifo overrun request (tfuf) or (rfof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.8.8 power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.8.8.1external stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 11.8.8.2module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11.8.8.3slave interface signal gating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11.9 initialization and application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11.9.1 how to change queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-45 11.9.2 baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 11.9.3 delay settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-47 11.9.4 calculation of fifo pointer addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-47 11.9.4.1address calculation for the first-in entry and last-in entry in the tx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48 11.9.4.2address calculation for the first-in entry and last-in entry in the rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-48 chapter 12 display control unit (dcu) 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.2.2 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-5 12.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.3.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.3.3 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 12.3.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 12.3.4.1control descriptor l0_1 register (ctrldescl0_1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-22 12.3.4.2control descriptor l0_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-23 12.3.4.3control descriptor l0_3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24 12.3.4.4control descriptor l0_4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25 12.3.4.5control descriptor l0_5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-27 12.3.4.6control descriptor l0_6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28 12.3.4.7control descriptor l0_7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 12.3.4.8control descriptor cursor 1 register (ctrldesccursor_1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-30 12.3.4.9control descriptor cursor 2 register (ctrldesccursor_2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
pxd10 microcontroller reference manual, rev. 1 x freescale semiconductor 12.3.4.10control descriptor cursor 3 register (ctrldesccursor_3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32 12.3.4.11control descriptor cursor 4 register (ctrldesccursor_4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32 12.3.4.12dcu mode register (dcu_mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33 12.3.4.13bgnd register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35 12.3.4.14disp_size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36 12.3.4.15hsyn_para register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37 12.3.4.16vsyn_para register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37 12.3.4.17syn_pol register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-38 12.3.4.18threshold register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40 12.3.4.19interrupt status register (int_status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-40 12.3.4.20interrupt mask register (int_mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-42 12.3.4.21colbar registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-44 12.3.4.22divide ratio register (div_ratio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-48 12.3.4.23sign_calc_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-49 12.3.4.24sign_calc_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50 12.3.4.25crc_val register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-50 12.3.4.26pdi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51 12.3.4.27pdi status mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-52 12.3.4.28parr_err status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54 12.3.4.29mask parr_err status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-56 12.3.4.30threshold_inp_buf_1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-58 12.3.4.31threshold_inp_buf_2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59 12.3.4.32luma component register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60 12.3.4.33red chroma components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-60 12.3.4.34green chroma component register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-61 12.3.4.35blue chroma component register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-62 12.3.4.36crc_pos register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-62 12.3.4.37fg0_fcolor register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-63 12.3.4.38fg0_bcolor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-64 12.3.4.39global protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-65 12.3.4.40soft lock bit register l0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-66 12.3.4.41soft lock bit register l1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-68 12.3.4.42soft lock disp_size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-69 12.3.4.43soft lock hsync/vsync para register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-70 12.3.4.44soft lock pol register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-71 12.3.4.45soft lock l0_transp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-71 12.3.4.46soft lock l1_transp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-73 12.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-73 12.4.1 graphic sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-74 12.4.2 tft lcd panel configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-74 12.4.3 dcu mode selection and background color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-76 12.4.4 proper sequence for enabling and disabling the dcu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-77 12.4.5 layer configuration and blending. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-77 12.4.5.1blending priority of layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-77 12.4.5.2control descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-80 12.4.5.3layer size and positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-80 12.4.5.4graphics and data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-81 12.4.5.5alpha and chroma-key blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-83 12.4.5.6transparency mode and blending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-90 12.4.5.7luminance mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-93 12.4.5.8tile mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-93 12.4.6 hardware cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-94 12.4.7 clut/tile ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-96 12.4.8 gamma correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-97 12.5 timing, error and interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-97 12.5.1 synchronizing to panel frame rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-98 12.5.2 managing the dcu fifos and dma activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-98 12.5.3 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-100 12.5.4 interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-100 12.6 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-101 12.6.1 operation of scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-101 12.6.2 list of protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-102 12.7 safety mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-102
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor xi 12.7.1 crc area description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-103 12.7.1.1relationship between various input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-103 12.7.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-105 12.7.3 programming for debug mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-106 12.7.4 programming of tag mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-106 12.8 parallel data interface (camera interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-106 12.8.1 itu-r bt.656 sync information extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-107 12.8.2 pdi interface description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-108 12.8.2.1introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-108 12.8.2.2pdi interaction with other modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-109 12.8.2.3features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-110 12.8.2.4normal and narrow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-110 12.8.2.5modes of operation based on sync extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-112 12.8.2.6mode of operation depending on pdi_datain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-116 12.8.2.7pdi-related interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-117 12.9 dcu initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-117 12.10 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-118 chapter 13 dma channel mux (dmachmux) 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3.1.1channel configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.4.1 dma channels with periodic triggering capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.4.2 dma channels with no triggering capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.4.3 "always enabled" dma sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.5 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.5.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.5.2 enabling and configuring sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 chapter 14 e200z0h core 14.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.2.1 microarchitecture summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.2.1.1block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2.1.2instruction unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 14.2.1.3integer unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.2.1.4load/store unit features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.2.1.5e200z0h system bus features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.3 core registers and programmer?s model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.3.1 unimplemented sprs and read-only sprs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 14.4 instruction summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 chapter 15 enhanced direct me mory access (edma) 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2 memory map/register definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.2.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
pxd10 microcontroller reference manual, rev. 1 xii freescale semiconductor 15.2.1.1dma control register (dmacr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.2.1.2dma error status (dmaes). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.2.1.3dma enable request (dmaerqh, dmaerql). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.2.1.4dma enable error interrupt (dmaeeih, dmaeeil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.2.1.5dma set enable request (dmaserq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 15.2.1.6dma clear enable request (dmacerq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.2.1.7dma set enable error interrupt (dmaseei) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.2.1.8dma clear enable error interrupt (dmaceei) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 15.2.1.9dma clear interrupt request (dmacint). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.2.1.10dma clear error (dmacerr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.2.1.11dma set start bit (dmassrt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 15.2.1.12dma clear done status (dmacdne) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 15.2.1.13dma interrupt request (dmainth, dmaintl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22 15.2.1.14dma error (dmaerrh, dmaerrl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23 15.2.1.15dma hardware request status (dmahrsh, dmahrsl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24 15.2.1.16dma general purpose output register (dmagpor). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 15.2.1.17dma channel n priority (dchprin), n = 0,..., {15,31,63} . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-26 15.2.1.18transfer control descriptor (tcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27 15.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39 15.3.1 dma microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-39 15.3.2 dma basic data flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-40 15.3.3 dma performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-43 15.4 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-46 15.4.1 dma initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-46 15.4.2 dma programming errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-47 15.4.3 dma arbitration mode considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-48 15.4.3.1fixed group arbitration, fixed channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-48 15.4.3.2round-robin group arbitration, fixed channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-48 15.4.3.3round-robin group arbitrati on, round-robin channel arbitratio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-48 15.4.3.4fixed group arbitration, round-robin channel arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-49 15.4.4 dma transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-49 15.4.4.1single request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-49 15.4.4.2multiple requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-50 15.4.5 tcd status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-52 15.4.5.1minor loop complete. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-52 15.4.5.2active channel tcd reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-53 15.4.5.3preemption status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-53 15.4.6 channel linking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-53 15.4.7 dynamic programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-54 15.4.7.1dynamic priority changing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-54 15.4.7.2dynamic channel linking and dynamic scatter/gather . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-54 15.4.8 hardware request release timi ng. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-55 chapter 16 error correction status module (ecsm) 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.4.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.4.2.1processor core type (pct) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.4.2.2revision (rev) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.4.2.3miscellaneous reset status register (mrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.4.2.4miscellaneous wakeup control register (mwcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.4.2.5miscellaneous interrupt register (mir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.4.2.6miscellaneous user-defined control register (mudcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.4.2.7ecc registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.4.2.8ecc configuration register (ecr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 16.4.2.9ecc status register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 16.4.2.10ecc error generation register (eegr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.4.2.11flash ecc address register (fear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor xiii 16.4.2.12flash ecc master number register (femr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.4.2.13flash ecc attributes (feat) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 16.4.2.14flash ecc data register (fedr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 16.4.2.15ram ecc address register (rear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 16.4.2.16ram ecc syndrome register (resr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 16.4.2.17ram ecc master number register (remr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 16.4.2.18ram ecc attributes (reat) register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21 16.4.2.19ram ecc data register (redr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21 16.4.3 high priority enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 16.4.4 spp_ips_reg_protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-23 chapter 17 flash memory 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2 program flash memory (code flash 0 and code flash 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.2.4.1macrocell structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.2.4.2flash module sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.5 user mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.2.5.1reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.2.5.2power-down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.2.5.3low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.2.6 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.2.6.1module configuration register (mcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17.2.6.2low/mid address space block locking register (lml) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 17.2.6.3non-volatile low/mid address space block locking register (nvlml) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 17.2.6.4high address space block locking register (hbl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 17.2.6.5non-volatile high address space block locking register (n vhbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 17.2.6.6secondary low/mid address space block locking register (sll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17.2.6.7non-volatile secondary low/mid address space block locking reg (nvsll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20 17.2.6.8low/mid address space block select register (lms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22 17.2.6.9high address space block select register (hbs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23 17.2.6.10address register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24 17.2.6.11bus interface unit 0 register (biu0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17.2.6.12bus interface unit 1 register (biu1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26 17.2.6.13bus interface unit 2 register (biu2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-26 17.2.6.14non-volatile bus interface unit 2 register (nvbiu2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 17.2.6.15user test 0 register (ut0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-28 17.2.6.16user test 1 register (ut1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 17.2.6.17user test 2 register (ut2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 17.2.6.18user multiple input signature register 0 (umisr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-31 17.2.6.19user multiple input signature register 1 (umisr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32 17.2.6.20user multiple input signature register 2 (umisr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32 17.2.6.21user multiple input signature register 3 (umisr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-33 17.2.6.22user multiple input signature register 4 (umisr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34 17.2.6.23non-volatile private censorship password 0 register (nvpwd0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34 17.2.6.24non-volatile private censorship password 1 register (nvpwd1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-35 17.2.6.25non-volatile system censoring information 0 register (nvsci0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-35 17.2.6.26non-volatile system censoring information 1 register (nvsci1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-36 17.2.6.27non-volatile user options register (nvusro) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37 17.2.7 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-38 17.2.7.1modify operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-38 17.2.7.2error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-46 17.2.7.3protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-46 17.3 data flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-48 17.3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-48 17.3.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-49 17.3.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-49 17.3.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-50
pxd10 microcontroller reference manual, rev. 1 xiv freescale semiconductor 17.3.4.1macrocell structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-50 17.3.4.2flash module sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-50 17.3.5 user mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-52 17.3.5.1reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-52 17.3.5.2power-down mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-53 17.3.5.3low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-53 17.3.6 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-54 17.3.6.1module configuration register (mcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-55 17.3.6.2low/mid address space block locking register (lml) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-59 17.3.6.3non-volatile low/mid address space block locking register (nvlml) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-59 17.3.6.4high address space block locking register (hbl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-61 17.3.6.5non-volatile high address space block locking register (n vhbl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-61 17.3.6.6secondary low/mid address space block locking register (sll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-62 17.3.6.7non-volatile secondary low/mid address space block locking reg (nvsll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-63 17.3.6.8low/mid address space block select register (lms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-65 17.3.6.9high address space block select register (hbs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-66 17.3.6.10address register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-67 17.3.6.11user test 0 register (ut0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-68 17.3.6.12user test 1 register (ut1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-70 17.3.6.13user test 2 register (ut2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-71 17.3.6.14user multiple input signature register 0 (umisr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-72 17.3.6.15user multiple input signature register 1 (umisr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-72 17.3.6.16user multiple input signature register 2 (umisr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-73 17.3.6.17user multiple input signature register 3 (umisr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-74 17.3.6.18user multiple input signature register 4 (umisr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-74 17.3.7 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-75 17.3.7.1modify operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-75 17.3.7.2double word program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-76 17.3.7.3sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-78 17.3.7.4user test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-80 17.3.8 error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-83 17.3.8.1ecc algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-83 17.3.8.2bit manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-84 17.3.8.3eeprom emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-84 17.3.9 protection strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-84 17.3.9.1modify protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-85 17.3.9.2censored mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-85 17.4 platform flash controller (pflash2p_lca) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-86 17.4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-86 17.4.1.1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-88 17.4.1.2features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-88 17.4.1.3modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-91 17.4.2 external signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-91 17.4.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-91 17.4.3.1memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-91 17.4.3.2register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-93 17.4.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-101 17.4.4.1access protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-102 17.4.4.2read cycles - buffer miss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-102 17.4.4.3read cycles - buffer hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-103 17.4.4.4write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-103 17.4.4.5error termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-103 17.4.4.6access pipelining. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-104 17.4.4.7flash error response operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-104 17.4.4.8bank 0 and 2 page read buffers and prefetch operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-104 17.4.4.9bank1 temporary holding registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-107 17.4.4.10input port arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-107 17.4.4.11read-while-write functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-108 17.4.4.12wait-state emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-109 17.4.4.13timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-110 17.5 initialization / applic ation information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-116 17.5.1 background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-116 17.5.2 flash memory setting recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-117
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor xv chapter 18 flexcan 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.1.2 flexcan module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.2.2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.2.2.1can rx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.2.2.2can tx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.3.1 flexcan memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.3.2 message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.3.3 rx fifo structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 18.3.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11 18.3.4.1module configuration register (mcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11 18.3.4.2control register (ctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 18.3.4.3free running timer (timer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18 18.3.4.4rx global mask (rxgmask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 18.3.4.5rx 14 mask (rx14mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 18.3.4.6rx 15 mask (rx15mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 18.3.4.7error counter register (ecr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21 18.3.4.8error and status register (esr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 18.3.4.9interrupt mask register high (imrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-25 18.3.4.10interrupt mask register low (imrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-26 18.3.4.11interrupt flag register high (ifrh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-26 18.3.4.12interrupt flag register low (ifrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 18.3.4.13rx individual mask registers (rximr0?rximr63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-28 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29 18.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-29 18.4.2 transmit process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30 18.4.3 arbitration process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-30 18.4.4 receive process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-31 18.4.5 matching process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-33 18.4.6 data coherence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-34 18.4.6.1transmission abort mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-34 18.4.6.2message buffer deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-35 18.4.6.3message buffer lock mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-36 18.4.7 rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-36 18.4.8 can protocol related features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-37 18.4.8.1remote frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-37 18.4.8.2overload frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-38 18.4.8.3time stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-38 18.4.8.4protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-38 18.4.8.5arbitration and matching timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-41 18.4.9 modes of operation: details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42 18.4.9.1freeze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42 18.4.9.2module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-42 18.4.10interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43 18.4.11bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43 18.5 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-44 18.5.1 flexcan initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-44 18.5.2 flexcan addressing and ram size configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-45 chapter 19 ieee 1149.1 test access port controller (jtagc) 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1
pxd10 microcontroller reference manual, rev. 1 xvi freescale semiconductor 19.4 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.5 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.5.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.5.2 ieee 1149.1-2001 defined test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.5.2.1bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.5.2.2tap sharing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.6 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.7 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.7.1 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.7.2 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.7.3 device identification register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.7.4 boundary scan register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.8.1 jtagc reset configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.8.2 ieee 1149.1-2001 (jtag) test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.8.3 tap controller state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.8.3.1selecting an ieee 1149.1-2001 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8 19.8.4 jtagc instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8 19.8.4.1bypass instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.8.4.2access_aux_tap_ x instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.8.4.3extest ? external test instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-9 19.8.4.4idcode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 19.8.4.5sample instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 19.8.4.6sample/preload instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 19.8.5 boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 19.9 e200z0 once controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 19.9.1 e200z0 once controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 19.9.2 e200z0 once controller functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 19.9.2.1enabling the tap controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 19.9.3 e200z0 once controller register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 19.9.3.1once command register (ocmd). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 19.10 initialization/application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 chapter 20 inter-integrated circuit bus controller module (i 2 c) 20.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.3.2 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.3.2.1scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.3.2.2sda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4.2 module memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4.3 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4.3.1i 2 c bus address register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.4.3.2i 2 c bus frequency divider register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.4.3.3i 2 c bus control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 20.4.3.4i 2 c bus status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11 20.4.3.5i 2 c bus data i/o register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 20.4.3.6i 2 c bus interrupt configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 20.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 20.5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 20.5.2 i-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 20.5.2.1start signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 20.5.2.2slave address transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15 20.5.2.3data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15 20.5.2.4stop signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor xvii 20.5.2.5repeated start signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16 20.5.2.6arbitration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16 20.5.2.7clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16 20.5.2.8handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.5.2.9clock stretching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.5.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.5.3.1general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.5.3.2interrupt description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.6 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.1 i 2 c programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.1.1initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.1.2generation of start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.1.3post-transfer software response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.1.4generation of stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 20.6.1.5generation of repeated start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20 20.6.1.6slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20 20.6.1.7arbitration lost. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20 20.6.2 dma application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 chapter 21 interrupt controller (intc) 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.4.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.4.1.1software vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.4.1.2hardware vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.4.1.3debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.4.1.4stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.5.1 module memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.5.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.5.2.1intc module configuration register (intc_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6 21.5.2.2intc current priority register for processor (intc_cpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6 21.5.2.3intc interrupt acknowledge register (intc_iackr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.5.2.4intc end-of-interrupt register (intc_eoir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.5.2.5intc software set/clear interrupt registers (intc_sscir0_3?intc_sscir4_7). . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.5.2.6intc priority select registers (intc_psr0_3?intc_psr204_207) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 21.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 21.6.1 interrupt request sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22 21.6.1.1peripheral interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 21.6.1.2software configurable interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 21.6.1.3unique vector for each interrupt request source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 21.6.2 priority management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 21.6.2.1current priority and preemption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 21.6.2.2last-in first-out (lifo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24 21.6.3 handshaking with processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-25 21.6.3.1software vector mode handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-25 21.6.3.2hardware vector mode handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26 21.7 initialization/application info rmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27 21.7.1 initialization flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27 21.7.2 interrupt exception handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27 21.7.2.1software vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28 21.7.2.2hardware vector mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28 21.7.3 isr, rtos, and task hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29 21.7.4 order of execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30 21.7.5 priority ceiling protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31 21.7.5.1elevating priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31 21.7.5.2ensuring coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31 21.7.6 selecting priorities according to request rates and deadli nes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31 21.7.7 software configurable interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32
pxd10 microcontroller reference manual, rev. 1 xviii freescale semiconductor 21.7.7.1scheduling a lower priority portion of an isr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 21.7.7.2scheduling an isr on another processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33 21.7.8 lowering priority within an isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33 21.7.9 negating an interrupt request outside of its isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33 21.7.9.1negating an interrupt request as a side effect of an isr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33 21.7.9.2negating multiple interrupt requests in one isr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33 21.7.9.3proper setting of interrupt request priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-34 21.7.10examining lifo contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-34 chapter 22 lcd driver (lcd64f6b) 22.1 information specific to this device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.1 number of front and back planes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.2 lcd clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.3 settings during standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.2.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.3 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.3.1 detailed signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.4.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.4.2.1lcd control register (lcdcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.4.2.2lcd prescaler control register (lcdpcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 22.4.2.3lcd contrast control register (lcdccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 22.4.2.4lcd frontplane enable register 0 (fpenr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.4.2.5lcd frontplane enable register 1 (fpenr1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 22.4.2.6lcdram (location 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13 22.4.2.7lcdram (location 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14 22.4.2.8lcdram (location 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15 22.4.2.9lcdram (location 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16 22.4.2.10lcdram (location 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17 22.4.2.11lcdram (location 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-18 22.4.2.12lcdram (location 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-19 22.4.2.13lcdram (location 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20 22.4.2.14lcdram (location 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-21 22.4.2.15lcdram (location 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 22.4.2.16lcdram (location 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23 22.4.2.17lcdram (location 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-24 22.4.2.18lcdram (location 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-25 22.4.2.19lcdram (location 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-26 22.4.2.20lcdram (location 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-27 22.4.2.21lcdram (location 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-28 22.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 22.5.1 frontplane, backplane, and lcd system during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 22.5.2 lcd clock and frame frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 22.5.3 contrast adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30 22.5.3.1adjusting the supply voltage (vlcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30 22.5.3.2adding contrast adjustment phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-30 22.5.4 lcd ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-31 22.5.5 lcd driver system enable and frontplane enable sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-31 22.5.6 lcd driver backplane remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-32 22.5.7 lcd bias and modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-33 22.5.8 operation in power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34 22.5.8.1operation in stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34 22.5.8.2operation in standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34 22.5.9 other power saving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-34 22.5.9.1lcd reference clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-35 22.5.9.2boost at switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-35 22.5.9.3standard drive selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-35
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor xix 22.5.9.4usage recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-35 22.5.10interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-36 22.5.10.1eof interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-36 22.6 lcd waveform examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-37 22.6.1 1/1 duty multiplexed with 1/1 bias mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-37 22.6.2 1/2 duty multiplexed with 1/2 bias mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-38 22.6.3 1/2 duty multiplexed with 1/3 bias mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-39 22.6.4 1/3 duty multiplexed with 1/3 bias mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-40 22.6.5 1/4 duty multiplexed with 1/3 bias mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-41 22.6.6 1/5 duty multiplexed with 1/3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-42 22.6.7 1/6 duty multiplexed with 1/3 bias mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-43 22.7 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-44 chapter 23 serial controller (uart) 23.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.2 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.2.1 lin mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.2.2 uart mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.2.3 features common to lin and uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.3 general description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.4 fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.5 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.5.1 initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.5.2 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.5.3 low power mode (sleep). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.6 test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.6.1 loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.6.2 self test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.7 memory map and registers description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.7.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 23.7.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 23.7.2.1lin control register 1 (lincr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 23.7.2.2lin interrupt enable register (linier) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.7.2.3lin status register (linsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-14 23.7.2.4lin error status register (linesr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17 23.7.2.5uart mode control register (uartcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-18 23.7.2.6uart mode status register (uartsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-20 23.7.2.7lin timeout control status register (lintcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22 23.7.2.8lin output compare register (linocr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 23.7.2.9lin timeout control register (lintocr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 23.7.2.10lin fractional baud rate register (linfbrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-24 23.7.2.11lin integer baud rate register (linibrr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-25 23.7.2.12lin checksum field register (lincfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.7.2.13lin control register 2 (lincr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.7.2.14buffer identifier register (bidr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-28 23.7.2.15buffer data register lsb (bdrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-29 23.7.2.16buffer data register msb (bdrm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-29 23.7.2.17identifier filter enable register (ifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-30 23.7.2.18identifier filter match index (ifmi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-31 23.7.2.19identifier filter mode register (ifmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-32 23.7.2.20identifier filter control register (ifcr2 n ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-33 23.7.2.21identifier filter control register (ifcr2 n + 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-34 23.7.3 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-35 23.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-39 23.8.1 uart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-39 23.8.1.1buffer in uart mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-39 23.8.1.2uart transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-40 23.8.1.3uart receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-40 23.8.1.4clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-41 23.8.2 lin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-41 23.8.2.1master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-41
pxd10 microcontroller reference manual, rev. 1 xx freescale semiconductor 23.8.2.2slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-43 23.8.2.3slave mode with identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-45 23.8.2.4slave mode with automatic resynchr onization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-47 23.8.2.5clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-49 23.8.3 8-bit timeout counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-49 23.8.3.1lin timeout mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-49 23.8.3.2output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-50 23.8.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-51 chapter 24 memory protection unit (mpu) 24.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.1.4 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2.2 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.2.2.1mpu control/error status register (mpu_cesr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.2.2.2mpu error address register, slave port n (mpu_earn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.2.2.3mpu error detail register, slave port n (mpu_edrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 24.2.2.4mpu region descriptor n (mpu_rgdn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 24.2.2.5mpu region descriptor alternate access control n (mpu_rgdaacn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 24.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15 24.3.1 access evaluation macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-15 24.3.1.1access evaluation - hit determination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16 24.3.1.2access evaluation - privil ege violation determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16 24.3.2 putting it all together and ahb error terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17 24.4 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19 24.5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19 chapter 25 mode entry module (mc_me) 25.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5 25.3.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.3.2.1global status register (me_gs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.3.2.2mode control register (me_mctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14 25.3.2.3mode enable register (me_me) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25.3.2.4interrupt status register (me_is) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17 25.3.2.5interrupt mask register (me_im). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18 25.3.2.6invalid mode transition status regi ster (me_imts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-19 25.3.2.7debug mode transition status register (me_dmts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20 25.3.2.8reset mode configuration register (me_reset_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22 25.3.2.9test mode configuration register (me_test_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23 25.3.2.10safe mode configuration register (me_safe_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23 25.3.2.11drun mode configuration register (me_drun_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24 25.3.2.12run0?3 mode configuration registers (me_run0?3_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25 25.3.2.13halt mode configuration register (me_halt_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25 25.3.2.14stop mode configuration register (me_stop_mc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-26 25.3.2.15standby mode configuration register (me_standby_mc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-26 25.3.2.16peripheral status register 0 (me_ps0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28 25.3.2.17peripheral status register 1 (me_ps1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-29 25.3.2.18peripheral status register 2 (me_ps2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-30
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor xxi 25.3.2.19peripheral status register 3 (me_ps3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-30 25.3.2.20run peripheral configuration registers (me_run_pc0?7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-31 25.3.2.21low-power peripheral configuration registers (me_lp_pc0?7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-32 25.3.2.22peripheral control registers (me_pctl0?143) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33 25.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33 25.4.1 mode transition request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-33 25.4.2 modes details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35 25.4.2.1reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35 25.4.2.2drun mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35 25.4.2.3safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-35 25.4.2.4test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-36 25.4.2.5run0?3 modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-37 25.4.2.6halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-37 25.4.2.7 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-38 25.4.2.8standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-38 25.4.3 mode transition process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-39 25.4.3.1target mode request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-39 25.4.3.2target mode configuration loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-40 25.4.3.3peripheral clocks disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41 25.4.3.4processor low-power mode entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41 25.4.3.5processor and system memory clock disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-41 25.4.3.6clock sources switch-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-42 25.4.3.7main voltage regulator switch-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-42 25.4.3.8flash modules switch-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-42 25.4.3.9fmpll0 switch-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43 25.4.3.10power domain #2 switch-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43 25.4.3.11pad outputs-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43 25.4.3.12peripheral clocks enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43 25.4.3.13processor and memory clock enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-43 25.4.3.14processor low-power mode exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-44 25.4.3.15system clock switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-44 25.4.3.16power domain #2 switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-45 25.4.3.17pad switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-45 25.4.3.18fmpll0 switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-45 25.4.3.19clock sources switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46 25.4.3.20flash switch-off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46 25.4.3.21main voltage regulator switch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46 25.4.3.22current mode update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-46 25.4.4 protection of mode configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49 25.4.5 mode transition interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49 25.4.5.1invalid mode configuration interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49 25.4.5.2invalid mode transition interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-49 25.4.5.3 safe mode transition interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-51 25.4.5.4mode transition complete interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-51 25.4.6 peripheral clock gating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-51 25.4.7 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-52 chapter 26 nexus development interface (ndi) 26.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.2 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 26.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3 26.4.1 nexus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-3 26.4.2 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.4.2.1disabled-port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.4.2.2censored mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.4.2.3stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.5 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.5.1 nexus signal reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.6 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 26.6.1 nexus debug interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5
pxd10 microcontroller reference manual, rev. 1 xxii freescale semiconductor 26.6.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 26.6.2.1nexus device id register (did) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5 26.6.2.2port configuration register (pcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6 26.6.2.3development control register 1, 2 (dc1, dc2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8 26.6.2.4development status register (ds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11 26.6.2.5read/write access control/status (rwcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12 26.6.2.6read/write access address (rwa). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13 26.6.2.7read/write access data (rwd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-13 26.6.2.8watchpoint trigger register (wt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-14 26.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-15 26.7.1 npc_hndshk module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-15 26.7.2 enabling nexus clients for tap access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-16 26.7.3 configuring the ndi for nexus messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-17 26.7.4 programmable mcko frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-17 26.7.5 nexus messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-18 26.7.6 evto sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-18 26.7.7 debug mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-18 26.7.7.1evti generated break request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-18 26.7.8 nexus reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-18 chapter 27 periodic interrupt timer (pit) 27.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.3 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.3.2.1pit module control register (pitmcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.3.2.2timer load value register (ldval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.3.2.3current timer value register (cval) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.3.2.4timer control register (tctrl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-5 27.3.2.5timer flag register (tflg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.4.1.1timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.4.1.2debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.4.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 27.5 initialization and application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.5.1 example configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 chapter 28 peripheral bridge (pbridge) 28.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.2.1 access support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.2.1.1peripheral write buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.2.1.2read cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.2.1.3write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.2.2 general operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 chapter 29 power control unit (mc_pcu) 29.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor xxiii 29.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.3.2.1power domain #0 configuration register (pcu_pconf0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.3.2.2power domain #1 configuration register (pcu_pconf1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.3.2.3power domain #2 configuration register (pcu_pconf2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.3.2.4power domain status register (pcu_pstat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.4.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.4.2 reset / power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.4.3 mc_pcu configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.4.4 mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8 29.4.4.1drun, safe, test, run0?3, halt, and stop mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-8 29.4.4.2standby mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 29.4.4.3power saving for memories during standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 29.5 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 29.6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11 29.6.1 standby mode considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-11 chapter 30 quad serial peripheral interface (quadspi) 30.1 preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.1.1 conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.1.2 acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.1.3 glossary for quadspi module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-3 30.2.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.2.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.2.3 quadspi modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.3.1spi master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.3.2spi slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.3.3serial flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.3.4module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.3.5stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-6 30.2.3.6debug mode (spi modes only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.3.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.3.2 detailed signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.3.2.1pcs_c0 ? peripheral chip select/slave select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.3.2.2pcs[3:1] ? peripheral chip selects 1 - 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.3.2.3pcs4 ? peripheral chip select 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.3.2.4pcs[7:5] ? peripheral chip selects 5 - 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.3.2.5si_io0 ? serial input, quadspi data io_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.3.2.6so_io1 ? serial output, quadspi data io_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-8 30.3.2.7qspi_io2 - quadspi data io_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9 30.3.2.8qspi_io3 - quadspi data io_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9 30.3.2.9sck ? serial clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9 30.4 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9 30.4.1 ip bus register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-9 30.4.2 amba bus register memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-10 30.4.3 ip bus register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11 30.4.3.1register write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11 30.4.3.2module configuration register (qspi_mcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-11 30.4.3.3transfer count register (qspi_tcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-14 30.4.3.4clock and transfer attributes registers 0 ? 1 (qspi_ctar0 ? qspi_ctar1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-15 30.4.3.5spi status register (qspi_spisr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20 30.4.3.6spi interrupt and dma request select and enable register (qspi_spirser) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21 30.4.3.7push tx fifo register (qspi_pushr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-23
pxd10 microcontroller reference manual, rev. 1 xxiv freescale semiconductor 30.4.3.8pop rx fifo register (qspi_popr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-24 30.4.3.9transmit fifo registers 0 ? 14 (qspi_txfr0 ? qspi_txfr14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-25 30.4.3.10rx fifo registers 0 ? 14 (qspi_rxfr0 ? qspi_rxfr14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-26 30.4.3.11serial flash address register (qspi_sfar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-26 30.4.3.12instruction code register (qspi_icr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-27 30.4.3.13sampling register (qspi_smpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-28 30.4.3.14rx buffer status register (qspi_rbsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-29 30.4.3.15rx buffer data registers 0?14 (qspi_rbdr0?qspi_rbdr14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-30 30.4.3.16tx buffer status register (qspi_tbsr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-31 30.4.3.17tx buffer data register (qspi_tbdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-32 30.4.3.18amba control register (qspi_acr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-32 30.4.3.19serial flash mode status register (qspi_sfmsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-33 30.4.3.20serial flash mode flag register (qspi_sfmfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-35 30.4.3.21sfm interrupt and dma request select and enable register (qspi_sfmrser) . . . . . . . . . . . . . . . . . . . . . . . . 30-37 30.4.4 ahb bus register memory map descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-37 30.4.4.1ahb bus access considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-38 30.4.4.2memory mapped serial flash data (qspi_sfd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-38 30.4.4.3ahb rx data buffer (qspi_ardb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-38 30.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-39 30.5.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-39 30.5.2 spi (serial peripheral interface) modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-40 30.5.2.1start and stop of spi transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-41 30.5.2.2master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-42 30.5.2.3slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-42 30.5.2.4fifo disable operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-42 30.5.2.5transmit first in first out (tx fifo) buffering mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-42 30.5.2.6receive first in first out (rx fifo ) buffering mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-43 30.5.2.7baud rate and clock delay generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-44 30.5.2.8spi transfer formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-46 30.5.2.9continuous serial communications clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-53 30.5.2.10spi mode interrupt and dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-54 30.5.3 sfm (serial flash) mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-55 30.5.3.1issuing sfm commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-56 30.5.3.2flash programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-57 30.5.3.3flash read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-57 30.5.3.4byte ordering of serial flash data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-59 30.5.3.5serial flash mode interrupt and dma requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-60 30.5.3.6tx buffer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-61 30.5.4 power saving features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-62 30.5.4.1stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-62 30.5.4.2module disable mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-63 30.5.4.3leaving power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-64 30.5.4.4slave bus signal gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-64 30.6 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-64 30.6.1 how to change queues - spi modes only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-64 30.6.2 baud rate settings - spi modes only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-65 30.6.3 delay settings - spi modes only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-65 30.6.4 oak family compatibility with the quadspi - spi modes only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-66 30.6.5 calculation of fifo pointer addresses - spi modes only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-67 30.6.5.1address calculation for the first-in entry and last-in entry in the tx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-68 30.6.5.2address calculation for the first-in entry and last-in entry in the rx fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-68 30.6.6 available status/flag information - sfm mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-69 30.6.6.1ip bus related commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-69 30.6.6.2ahb bus related commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-69 30.6.6.3overview of error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-70 30.6.6.4ip bus and ahb access command collisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-70 30.6.7 command arbitration - sfm mode only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-70 30.6.8 dma usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-71 30.6.8.1dma usage in spi slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-71 30.6.8.2dma usage in sfm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-71 30.7 serial flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-72 30.7.1 supported instruction codes in winbond devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-73 30.7.2 serial flash clock frequency limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-75
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor xxv 30.8 internal sampling of serial flash input data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-75 chapter 31 real-time clock (rtc/api) 31.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-1 31.3 device specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.5 debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.6 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.6.1 rtc supervisor control register (rtcsupv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.6.2 rtc control register (rtcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.6.3 rtc status register (rtcs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.6.4 rtc counter register (rtccnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.7 rtc functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.8 api functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 chapter 32 reset generation module (mc_rgm) 32.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 32.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 32.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-3 32.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 32.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-4 32.3.1 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-6 32.3.1.1functional event status register (rgm_fes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7 32.3.1.2destructive event status register (rgm_des) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-8 32.3.1.3functional event reset disable register (rgm_ferd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-9 32.3.1.4destructive event reset disable register (rgm_derd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-11 32.3.1.5functional event alternate request register (rgm_fear). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12 32.3.1.6destructive event alternate request register (rgm_dear). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-13 32.3.1.7functional event short sequence register (rgm_fess) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-14 32.3.1.8 standby reset sequence register (rgm_stdby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-15 32.3.1.9functional bidirectional reset enable register (rgm_fbre) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-16 32.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-17 32.4.1 reset state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-17 32.4.1.1phase0 phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-18 32.4.1.2phase1 phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-19 32.4.1.3phase2 phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-19 32.4.1.4phase3 phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-19 32.4.1.5idle phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-19 32.4.2 destructive resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-20 32.4.3 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-20 32.4.4 functional resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-21 32.4.5 standby entry sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-21 32.4.6 alternate event generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-21 32.4.7 boot mode capturing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-22 chapter 33 sound generation logic (sgl) 33.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 33.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.2.1 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-2 33.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3 33.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3
pxd10 microcontroller reference manual, rev. 1 xxvi freescale semiconductor 33.3.2 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3 33.3.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3 33.3.3.1mode_sel register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3 33.3.3.2sound_duration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4 33.3.3.3high_period register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5 33.3.3.4low_period register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-5 33.3.3.5sgl_status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6 33.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-6 33.4.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-9 chapter 34 static ram (sram) 34.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.2 general-purpose sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.3 graphics sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.4 low power configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-1 34.5 register memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 34.6 sram ecc mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 34.6.1 access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-2 34.6.2 reset effects on sram accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-3 34.8 initialization and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34-4 chapter 35 stepper motor controller (smc) 35.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-1 35.1.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-1 35.1.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-1 35.1.2.1functional modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-1 35.1.2.2pwm channel configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-1 35.1.2.3pwm alignment modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-2 35.1.2.4low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-2 35.1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-3 35.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4 35.2.1 m0c0m/m0c0p/m0c1m/m0c1p ? pwm output pins for motor 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-4 35.2.2 m1c0m/m1c0p/m1c1m/m1c1p ? pwm output pins for motor 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5 35.2.3 m2c0m/m2c0p/m2c1m/m2c1p ? pwm output pins for motor 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5 35.2.4 m3c0m/m3c0p/m3c1m/m3c1p ? pwm output pins for motor 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5 35.2.5 m4c0m/m4c0p/m4c1m/m4c1p ? pwm output pins for motor 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5 35.2.6 m5c0m/m5c0p/m5c1m/m5c1p ? pwm output pins for motor 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5 35.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5 35.3.1 module memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-5 35.3.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-7 35.3.2.1motor controller control register 0 (mcctl0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-8 35.3.2.2motor controller control register 1 (mcctl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-9 35.3.2.3motor controller period register (mcper) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-10 35.3.2.4motor controller channel control register (mccc0..11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-10 35.3.2.5motor controller duty cycle register (mcdc0..11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-11 35.3.2.6short-circuit detector time-out register (mcsdto). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-13 35.3.2.7short-circuit detector enable register 0 (mcsde0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-13 35.3.2.8short-circuit detector enable register 1 (mcsde1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-14 35.3.2.9short-circuit detector enable register 2 (mcsde2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-14 35.3.2.10short-circuit detector interrupt enable register 0 (mcsdien0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-15 35.3.2.11short-circuit detector interrupt enable register 1 (mcsdien1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-15 35.3.2.12short-circuit detector interrupt enable register 2 (mcsdien2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-16 35.3.2.13short-circuit detector interrupt register 0 (mcsdi0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-16 35.3.2.14short-circuit detector interrupt register 1 (mcsdi1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-17 35.3.2.15short-circuit detector interrupt register 2 (mcsdi2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-17 35.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-18 35.4.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-18
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor xxvii 35.4.1.1pwm output modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-18 35.4.1.2relationship between pwm mode and pwm channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-21 35.4.1.3relationship between sign, duty, dither, recirc, period, and pwm mode functions35-21 35.4.2 pwm duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-31 35.4.3 motor controller counter clock source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-31 35.4.4 output switching delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-32 35.4.5 operation in smc stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-32 35.4.6 short-circuit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-32 35.5 reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-37 35.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35-37 chapter 36 stepper stall detect (ssd) 36.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1 36.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-1 36.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 36.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 36.1.3.1disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 36.1.3.2normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 36.1.3.3power down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-3 36.2 external signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4 36.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4 36.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-4 36.3.2 register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-5 36.3.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-5 36.3.3.1ssd control and status register (control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-6 36.3.3.2interrupt enable and flag register (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-7 36.3.3.3integration accumulator register (itgacc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8 36.3.3.4down counter register (dcnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-8 36.3.3.5blanking counter load register (blncntld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-9 36.3.3.6integration counter load register (itgcntld) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-9 36.3.3.7ssd prescale and divider register (prescale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-10 36.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-11 36.4.1 main building blocks of the ssd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-11 36.4.1.1analog block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-11 36.4.1.2analog wrapper + port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-13 36.4.1.3register interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-15 36.4.1.4bis control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-16 36.4.2 stepper stall detection measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-19 36.4.2.1overview of the ssd measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-19 36.4.2.2details of the ssd measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-20 36.4.3 additional modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-22 36.4.3.1blanking with no drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-22 36.4.3.2integration with no drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-22 36.5 initialization information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-22 36.5.1 analog block startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-22 36.5.2 analog block polarity switching time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-22 36.5.3 ssd startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-23 36.6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-23 36.6.1 current flow examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-23 36.6.2 setting of the prescale register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-25 36.6.2.1timing resolution considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-25 36.6.2.2offset cancellation consi derations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-26 36.6.3 watching internal states of the ssd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-26 36.6.4 stepper motor transition considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-27 36.6.4.1ssd phase-in and phase-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-27 36.6.4.2changing of ssd internal states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-27 36.6.5 legacy modes - separate blanking and integr ation phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36-28
pxd10 microcontroller reference manual, rev. 1 xxviii freescale semiconductor chapter 37 system integration unit lite (siul) 37.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-1 37.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-1 37.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-3 37.4 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-3 37.4.1 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-4 37.4.1.1general-purpose i/o pins (gpio[0:132]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-4 37.4.1.2external interrupt request input pins (eirq[0:13]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-4 37.5 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-4 37.5.1 siul memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-4 37.5.2 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-6 37.5.3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-6 37.5.3.1mcu id register #1 (midr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-6 37.5.3.2mcu id register #2 (midr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-7 37.5.3.3interrupt status flag register (isr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-9 37.5.3.4interrupt request enable register (irer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-9 37.5.3.5interrupt rising-edge event enable register (ireer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-10 37.5.3.6interrupt falling-edge event enable register (ifeer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-10 37.5.3.7interrupt filter enable register (ifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-11 37.5.3.8pad configuration registers (pcr0 - pcr132) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-11 37.5.3.9pad selection for multiplexed inputs registers (psmi0_3 - psmi40_42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-14 37.5.3.10gpio pad data output registers (gpdo0_3 - gpdo132_135) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-18 37.5.3.11gpio pad data input registers (gpdi0_3 - gpdi132_135). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-18 37.5.3.12parallel gpio pad data out registers (pgpdo0 - pgpdo4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-19 37.5.3.13parallel gpio pad data in register (pgpdi0?pgpdi4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-21 37.5.3.14masked parallel gpio pad data out register (mpgpdo0?mpgpdo8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-22 37.5.3.15interrupt filter maximum counter registers (ifmc0 - ifmc15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-23 37.5.3.16interrupt filter clock prescaler register (ifcpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-23 37.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-24 37.6.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-24 37.6.2 pad control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-24 37.6.3 general purpose input and output pads (gpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-24 37.6.4 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-25 37.6.4.1external interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-26 37.7 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37-26 chapter 38 system status and conf iguration module (sscm) 38.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1 38.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1 38.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-1 38.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2 38.2 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2 38.2.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2 38.2.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-2 38.2.2.1system status register (status). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3 38.2.2.2system memory configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-3 38.2.2.3error configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-4 38.2.2.4debug status port register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-5 38.2.2.5password comparison registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-6 38.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-8 38.4 initialization/applicat ion information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-8 38.4.1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38-8 chapter 39 system timer module (stm) 39.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1 39.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor xxix 39.1.2 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1 39.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1 39.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1 39.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1 39.3.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-1 39.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2 39.3.2.1stm control register (stm_cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-2 39.3.2.2stm count register (stm_cnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-3 39.3.2.3stm channel control register (stm_ccrn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4 39.3.2.4stm channel interrupt register (stm_cirn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-4 39.3.2.5stm channel compare register (stm_cmpn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-5 39.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39-6 chapter 40 voltage regulators and power supplies 40.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 40.2 voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-1 40.2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2 40.2.2 external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-2 40.2.3 detailed signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3 40.2.3.1vddr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3 40.2.3.2vrc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3 40.3 memory map and register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3 40.3.1 voltage regulator control register (vreg_ctl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-3 40.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.4.1 high power or main regulator (hpreg). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.4.2 low power regulator (lpreg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.4.3 ultra low power regulator (ulpreg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.4.4 low voltage detectors (lvd) and power on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-4 40.4.5 vreg digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-5 40.5 gpio power supply configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-6 40.6 power domain organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-7 chapter 41 wakeup unit (wkpu) 41.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-1 41.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-2 41.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3 41.4 memory map and register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3 41.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-3 41.4.2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-4 41.4.2.1nmi status flag register (nsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-4 41.4.2.2nmi configuration register (ncr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-5 41.4.2.3wakeup/interrupt status flag register (wisr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-6 41.4.2.4interrupt request enable register (irer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-7 41.4.2.5wakeup request enable register (wrer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-7 41.4.2.6wakeup/interrupt rising-edge event enable register (wireer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-7 41.4.2.7wakeup/interrupt falling-edge event enable register (wifeer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-8 41.4.2.8wakeup/interrupt filter enable register (wifer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-8 41.4.2.9wakeup/interrupt pullup enable register (wipuer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-9 41.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-9 41.5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-9 41.5.2 non-maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-9 41.5.2.1nmi management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-10 41.5.3 external wakeups/interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-11 41.5.3.1external interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-12 41.5.4 on-chip wakeups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-13 41.5.4.1on-chip wakeup management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41-13
pxd10 microcontroller reference manual, rev. 1 xxx freescale semiconductor appendix a registers under protection appendix b register map appendix c revision history
pxd10 microcontroller reference ma nual, rev. 1, release candidate freescale semiconductor xli preliminary?subject to change without notice preface overview the primary objective of th is document is to define the functionali ty of the pxd10 microcontroller for use by software and hardware developers. th e pxd10 is built on power architecture ? technology and integrates technologies that are important for today?s industrial hmi applications. the information in this document is subject to change without notice, as descri bed in the disclaimers on the title page. as with any technical documentation, it is the reader?s responsibility to be sure he or she is using the most recent vers ion of the documentation. to locate any published errata or updates for th is document, visit the freescale web site at www.freescale.com. audience this manual is intended for system software and hardware developers and applications programmers who want to develop products with the pxd10 device. it is assumed that the re ader understands operating systems, microprocessor syst em design, basic principles of software and hardware, and basic details of the power architecture. organization this document includes chapters that describe: ? the microcontroller as a whole ? the functionality of the indivi dual modules on the microcontroller when the microcontroller is specified as ?pxd10,? the reader is instructed to apply this information to all of the microcontrollers specified on the front cover of this manual, unl ess individual devi ce-specific details are provided in that chapter. the following summary provides a brief description of the majo r sections of this manual: ? chapter 1, overview, includes general descriptions of the m odules and features in corporated in the device while focusing on new features. ? chapter 2, memory map, provides a high-level listi ng of the pxd10 memory map. ? chapter 3, signal description, summarizes the external signal functions, their static electrical characteristics, and pad confi guration settings for the pxd10. ? chapter 4, safety, describes a set of features to support using the pxd10 fo r applications that need to fulfill functional safety requirements. ? chapter 5, analog-to-digital converter (adc), describes the adc module implemented on the pxd10.
pxd10 microcontroller reference ma nual, rev. 1, release candidate xlii freescale semiconductor preliminary?subject to change without notice ? chapter 6, boot assist module (bam), describes the bam, whic h contains the mcu boot program code supporting the differ ent booting modes for this device. ? chapter 7, can sampler, describes detecting a can message while no precise clock is running. ? chapter 8, clock description, describes the various clock sources that are availa ble on the pxd10. ? chapter 9, configurable enhanced modular io subsystem (emios200), ? chapter 10, crossbar switch (xbar), describes the multi-port axbs crossbar switch that supports simultaneous connec tions between the master ports and slave ports on the pxd10. ? chapter 11, deserial serial peripheral interface (dspi), describes the serial peripheral interface (spi) block, which provides a s ynchronous serial interface for communication between the pxd10 and external devices. ? chapter 12, display control unit (dcu), describes the module whic h displays to a tft lcd panel. ? chapter 13, dma channel mux (dmachmux), describes the dma multiplexer block implemented on the pxd10. ? chapter 14, e200z0h core, describes the organization of the e200z0 power processor cores and an overview of the programming models as they are implemented on the device. ? chapter 15, enhanced direct memory access (edma), describes the enhanced dma controller implemented on the pxd10. ? chapter 16, error correction status module (ecsm), describes the ecsm block, which provides monitoring and control functions to report memory errors and apply error-correcting code (ecc) implementations. ? chapter 17, flash memory, describes the flash memory block and the flash memory controller. ? chapter 18, flexcan, describes the can module, a communi cation controller implementing the can protocol according to bosch specifica tion version 2.0b and iso standard 11898. ? chapter 19, ieee 1149.1 test access port controller (jtagc), describes configuration and operation of the joint test action group (jtag) controller implementati on. it describes those items required by the ieee ? 1149.1 standard and provides additional information speocific to the device. for internal details and sample applications, see the ieee 1149.1 document. ? chapter 20, inter-integrated circ uit bus controller module (i2c), describes the i 2 c module, including i 2 c protocol, clock synchronization, and i 2 c programming model registers. ? chapter 21, interrupt controller (intc), summarizes the software a nd hardware interrupts for the pxd10 device. ? chapter 22, lcd driver (lcd64f6b), describes the liquid-crystal display (lcd) driver on the pxd10 device. ? chapter 23, serial controller (uart), describes a serial controller interface that provides uart capabilities as well as an interface to a lin network. ? chapter 24, memory protection unit (mpu), describes the block that provides hardware access control for all memory references generated in the pxd10. ? chapter 25, mode entry module (mc_me), describes the module that controls the pxd10 mode and mode transition sequences in all functional states.
pxd10 microcontroller reference ma nual, rev. 1, release candidate freescale semiconductor xliii preliminary?subject to change without notice ? chapter 26, nexus development interface (ndi), describes the nexus development interface (ndi) block, which provides real-time devel opment support capabilities for the pxd10 in compliance with the ieee-isto 5001-2003 standard. ? chapter 27, periodic interrupt timer (pit), describes an array of timers that can be used to initiate interrupts and trigger dma channels. ? chapter 28, peripheral bridge (pbridge), describes the interface between the system bus and lower bandwidth peripherals via the aips bridge. ? chapter 29, power control unit (mc_pcu), describes the controls for the bridge that maps the pmc peripheral to the mc_pcu address space. ? chapter 30, quad serial peripheral interface (quadspi), describes a module that provides a synchronous serial bus for communication with an external peripheral device. ? chapter 31, real-time clock (rtc/api), describes a free running count er used for time keeping applications that may be configured to gene rate an interrupt at a predefined interval. ? chapter 32, reset generation module (mc_rgm), describes the module that centralizes the different reset sources and manages the reset sequence of the device. ? chapter 33, sound generation logic (sgl), describes the module that provides an output to the speaker or buzzer interface. ? chapter 34, static ram (sram), describes the on-chip static ram (sram) implementation, covers general operations, configuration, and in itialization. it also provides information and examples of how to minimize power consumption when using the sram. ? chapter 35, stepper motor controller (smc), describes the smc block, a pwm motor controller suitable for driving small stepper and air core motors used in instru mentation applications. ? chapter 36, stepper stall detect (ssd), describes a block that conn ects to a stepper motor (sm) with two coils and monitors the movement of the sm. ? chapter 37, system integration unit lite (siul), describes the siu modul e, which controls mcu reset configuration, pad configur ation, external interrupt, genera l-purpose i/o (gpio), internal peripheral multiplexing, and th e system reset operation. ? chapter 38, system status and configuration module (sscm), describes the module that provides information about the current state and configur ation of the system, which may be useful for configuring application softwa re and for debugging the system. ? chapter 39, system timer module (stm), describes the timer control module. ? chapter 40, voltage regulators and power supplies, describes the three on- chip voltage regulators for power management and distribution, allowing low-power operation and optimization of power consumption. ? chapter 41, wakeup unit (wkpu), describes the module that supports an external source that can cause non-maskable interrupt requests or wakeup events. ? appendix a, registers under protection, lists the registers under protection on the pxd10. ? appendix b, register map, provides a detailed listing of the memory-mapped registers for the pxd10. ? appendix c, revision history, describes the revision hi story of this document.
pxd10 microcontroller reference ma nual, rev. 1, release candidate xliv freescale semiconductor preliminary?subject to change without notice document conventions this document uses the foll owing notational conventions: cleared/set when a bit takes the valu e 0, it is said to be cleared; when it takes a value of 1, it is said to be set. reserved when a bit or address is reserved, it should not be writ ten. if read, its value is not guaranteed. reading or wr iting to reserved bits or addresses may cause unexpected results. mnemonics in text, instruction mn emonics are shown in uppercase. mnemonics in code and tables, instruction mnemonics are shown in lowercase. italics italics indicate variable command parameters. book titles in text are set in italics. 0x prefix to denote hexadecimal number 0b prefix to denote binary number reg[field] abbreviations for regist ers are shown in uppercase. sp ecific bits, fields, or ranges appear in brackets. for example, rambar [ba] identifies the base address field in the ram base address register. nibble a 4-bit data unit byte an 8-bit data unit halfword a 16-bit data unit 1 word a 32-bit data unit doubleword a 64-bit data unit x in some contexts, such as signal encodi ngs, x (without italics) indicates a ?don?t care? condition. x with italics, used to express an undefi ned alphanumeric value (e.g., a variable in an equation); or a variable alphabetic character in a bit, register, or module name (e.g., dspi_ x could refer to dspi_a or dspi_b). n used to express an undefined numerical valu e; or a variable numeric character in a bit, register, or module name (e.g., eif n could refer to eif1 or eif0). ~ not logical operator & and logical operator | or logical operator || field concatenation operator overbar an overbar indicates that a signal is active-low. register figure conventions 1. the only exceptions to this appear in the discussion of serial communication modules that support variable-length data transmission units. to simplify the discussion these un its are referred to as words regardless of length.
pxd10 microcontroller reference ma nual, rev. 1, release candidate freescale semiconductor xlv preliminary?subject to change without notice this document uses the following conventions for the register rese t values in register figures: ? bit value is undefined at reset. u bit value is unchanged by reset. pr evious value preserved during reset. [ signal_name ] reset value is determined by th e polarity of the indicated signal. the following descriptions are used in register bit field description tables: acronyms and abbreviated terms the following table lists some acronyms a nd abbreviations used in this document. r 0 indicates a reserved bit field in a memory-mapped register. these bits are always read as 0. w r 1 indicates a reserved bit field in a memory-mapped register. these bits are always read as 1. w r fieldname indicates a read/write bit in a memory-mapped register. w r fieldname indicates a read-only bit field in a memory-mapped register. w r indicates a write-only bit field in a memory-mapped register. w fieldname r fieldname write 1 to clear: indicates that writing a 1 to this bit field clears it. ww1c r 0 indicates a self-clearing bit. w fieldname term meaning gpio general-purpose i/o ieee institute for electric al and electronics engineers jedec joint electron device engineering council jtag joint test action group mux multiplex rx receive rtl register transfer language
pxd10 microcontroller reference ma nual, rev. 1, release candidate xlvi freescale semiconductor preliminary?subject to change without notice references in addition to this reference manual, the followi ng documents provide additi onal information on the operation of the pxd10: ? ieee-isto 5001-2003 standard for a global embedded processor interface (nexus) ? ieee 1149.1-2001 standard - ieee standard test access port and boundary-scan architecture ? power architecture book e v1.0 (http://www.freescale.com/files/ 32bit/doc/user_guide/book_eum.pdf) tx transmit uart universal asynchronous/synch ronous receiver transmitter term meaning
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-1 preliminary?subject to change without notice chapter 1 overview 1.1 introduction the pxd10 family represents a new generation of 32-bit microcontrollers based on the power architecture ? . these devices provide a cost-effective, si ngle chip display solution for the industrial market. an integrated tft driver wi th digital video input ability from an external video source, significant on-chip memory, and low power de sign methodologies provide flexibil ity and reliability in meeting display demands in rugged envir onments. the advanced processor core offers high performance processing optimized for low power c onsumption, operating at sp eeds as high as 64 mhz. the family itself is fully scalable from 512 kb to 1 mb internal flash memory. the memory capacity can be further expanded via the on-chip quadspi se rial flash controller module. the pxd10 platform has a single leve l of memory hierarchy and supports a wide ra nge of on-chip sram and internal flash memories. the 1 mb flash memory version (pxd1010) outlined in detail within this document features 160 kb of on-chip graphics sram to buffer cost-effective color tft displays driven via the on-chip display control unit (dcu). refer to table 1-1 , table 1-2 , and table 1-3 for specific memory and feature sets of the product family members. the pxd10 family benefits from the extensive de velopment infrastructure for power architecture devices, which is already well established. this includes full suppor t from available software drivers, operating systems, and configuration code to assist with users? implementations. see section 1.6, developer environment, for more information. 1.2 pxd10 family comparison table 1-1 and table 1-2 report the memory scaling of code flash memory and ram. table 1-1. code flash memory scaling memory size start address end address 512 kb (pxd1005) 0x0000_0000 0x0007_ffff 1 mb (pxd1010) 0x0000_0000 0x000f_ffff table 1-2. ram memory scaling memory size start address end address 48 kb (pxd1005 and pxd1010) 0x4000_0000 0x4000_bfff
pxd10 microcontroller reference manual, rev. 1 1-2 freescale semiconductor preliminary?subject to change without notice table 1-3 provides a summary of the different members of the pxd10 family. this information is intended to provide an understanding of the range of functionality offered by this famil table 1-3. pxd10 family feature set feature pxd1005 pxd1010 cpu e200z0h execution speed static ? 64 mhz flash (ecc) 512 kb 1 mb eeprom emulation block (ecc) 4 16 kb ram (ecc) 48 kb graphics ram no 160 kb mpu 12 entry edma 16 channels display control unit (dcu) no yes parallel data interface no yes stepper motor controller (smc) 6 motors stepper stall detect (ssd) yes sound generation logic (sgl) yes lcd driver 64 6 40 4, 38 6 32 khz slow external crystal oscillator yes real-time counter and autonomous periodic interrupt ye s periodic interrupt timer (pit) 4 ch, 32-bit software watchdog timer (swt) yes system timer module (stm) 4 ch, 32-bit timed i/o (emios) 8 ch, 16-bit ic/oc 16 ch, 16-bit pwm/ic/oc adc 16 channels, 10-bit can (64 mailboxes) 2 can can sampler yes sci 2 uart spi 2 spi 3 spi quadspi serial flash interface no yes i 2 c24 gpio 105 105 (144-pin package) 133 (176-pin package)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-3 preliminary?subject to change without notice debug nexus 1 nexus 2+ package 144 lqfp 144 lqfp 176 lqfp table 1-3. pxd10 family feature set (continued) feature pxd1005 pxd1010
pxd10 microcontroller reference manual, rev. 1 1-4 freescale semiconductor preliminary?subject to change without notice 1.3 block diagram figure 1-1 shows a top-level block diagram of the pxd10. figure 1-1. pxd10 block diagram 1.4 chip-level features on-chip modules available within the fa mily include the fo llowing features: crossbar switch (xbar) pxd10 block diagram integer multiply e200z0 core unit execution unit instruction unit vle general load/store unit purpose registers (32 x 32-bit) branch unit intc jtag peripheral i/o bridge (pbridge) oscillators bam rtc pll pit swt aux pll vreg stm data bus instruction bus memory protection unit (mpu) uart/lin adc lcd seg spi i 2 c emios can siu smd ssd ram controller quadspi eeprom (emulation) flash (ecc) ram controller flash controller flash (ecc) graphics sram sram (ecc) nexus2+ display control unit (tfts) edma adc ? analog-to-digital converter bam ? boot assist module can ? controller area network controller ecc ? error correction code edma ? enhanced direct memory access controller emios ? timed input/output i 2 c ? inter-integrated circuit controller intc ? interrupt controller jtag ? joint test action group interface lcd ? liquid crystal display pit ? periodic interrupt timer pll ? phase-locked loop rtc ? real time clock siu ? system integration unit smd ssd ? stepper motor driver/stepper stall detect spi ? serial peripheral interface controller sram ? static random-access memory stm ? system timer module swt ? software watchdog timer uart/lin ? universal asynchronous receiver/transmitter/ local interconnect network vle ? variable-length execution set vreg ? voltage regulator
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-5 preliminary?subject to change without notice ? single issue, 32-bit power architecture t echnology compliant cpu core complex (e200z0h) ? compatible with power architecture instruction set ? includes variable length encoding (vle) instruction set for smalle r code size footprint; with the encoding of mixed 16-bit and 32-bit instructions, it is possibl e to achieve significant code size footprint reduction over conventional book e compliant code ? on-chip ecc flash memory with flash controller ? as much as 1 mb primary flas h?two 512 kb modules with pref etch buffer and 128-bit data access port ? 64 kb data flash?separate 4 ? 16 kb flash block for eeprom em ulation with prefetch buffer and 128-bit data access port ? as much as 48 kb on-chip ecc sram with sram controller ? as much as 160 kb on-chip non-ecc gr aphics sram with sram controller ? memory protection unit (mpu) with as many as 12 region descriptors and 32-byte region granularity to provide basi c memory access permission ? interrupt controller (intc) wi th as many as 127 peripheral interr upt sources and eight software interrupts ? two frequency-modulated ph ase-locked loops (fmplls) ? primary fmpll provides a 64 mhz system clock ? auxiliary fmpll is available for use as an alternate, modulated or non-modulated clock source to emios modules and as alternate cl ock to the dcu for pixel clock generation ? crossbar switch architecture enables concurrent access of peripherals, flash memory or ram from multiple bus masters (amba 2.0 v6 ahb) ? 16-channel enhanced direct memory access cont roller (edma) with multiple transfer request sources using a dma channel multiplexer ? boot assist module (bam) supports internal fl ash programming via a se rial link (flexcan or linflex) ? display control unit to drive tft lcd displays ? includes processing of as many as four planes that can be blended together ? offers a direct unbuffered hardwa re bit-blitter of as many as 16 software -configurable dynamic layers in order to drastically minimize gr aphic memory requireme nts and provide fast animations ? programmable display resoluti ons are available up to wvga ? parallel data interface (p di) for digital video input ? lcd segment driver module with two software programmable configurations: ? as many as 40 frontplane driver s and four backplane drivers ? as many as 38 frontplane drivers and six backplane drivers ? stepper motor controller (smc) module with high-current driver s for as many as six stepper motors driven in full dual h-bridge configurat ion including full diagnostics for short circuit detection
pxd10 microcontroller reference manual, rev. 1 1-6 freescale semiconductor preliminary?subject to change without notice ? stepper motor return-to-zero and stall detection module ? sound generation and playback utilizing pwm channels and edma; supports monotonic and polyphonic sound ? 24 emios channels providing as many as 16 pwm and 24 input capture / output compare channels ? 10-bit analog-to-digital converter (adc) ? maximum conversion time of 1 s ? as many as 16 internal channels, expa ndable to 23 via external multiplexing ? as many as two serial peripheral interface (dspi) modules for full-duplex, synchronous, communications with external devices (extendable to include up to 8 multiplexed external channels) ? quadspi serial flash memory controller suppor ting single, dual and quad modes of operation to interface to external serial flash memory. quadspi can be configured to function as another dspi module. ? two local interconnect network flexible (lin flex) controller modules capable of autonomous message handling (master), autonomous header handling (slave mode), and uart support. compliant with lin protocol rev 2.1 ? two full can 2.0b controllers with 64 configurable buffers each; bi t rate programmable as fast as 1 mbit/s ? as many as four inter- integrated circuit (i 2 c) internal bus controller s with master/slave bus interface ? as many as 133 configurable general purpose pins supporting input and output operations ? real time counter (rtc) w ith multiple clock sources: ? 128 khz slow internal rc os cillator or 16 mhz fast inte rnal rc oscillator supporting autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds ? 32 khz slow external crysta l oscillator, supporting wakeup wi th 1 s resolution and maximum timeout of one hour ? 4?16 mhz fast external crystal oscillator ? system timers: ? four-channel 32-bit system timer module (stm)?included in processor platform ? four-channel 32-bit periodic interrupt timer (pit) module ? software watchdog timer (swt) ? system integration unit (siu) module to manage re sets, external interrupts, gpio and pad control ? system status and configuration module (sscm) to provide inform ation for identification of the device, last boot mode, or debug status and provi des an entry point for the censorship password mechanism ? clock generation module (mc_cgm) to generate system clock sources and provide a unified register interface, enabling access to all clock sources ? clock monitor unit (cmu) to monitor the integrit y of the main crystal oscillator and the pll and act as a frequency meter, meas uring the frequency of one clock source and comparing it to a reference clock
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-7 preliminary?subject to change without notice ? mode entry module (mc_me) to control the de vice power mode, i.e., run, halt, stop, or standby, control mode transition sequences, and manage the power control, voltage regulator, clock generation and cl ock management modules ? reset generation module (mc_rgm) to manage rese t assertion and release to the device at initial power-up ? nexus development interf ace (ndi) per ieee-isto 5001- 2003 class two plus standard ? device/board boundary-sca n testing supported per joint test action group (jtag) of ieee (ieee 1149.1) ? on-chip voltage regulator contro ller for regulating the 3.3 or 5 v supply voltage down to 1.2 v for core logic (requires exte rnal ballast transistor) ? the pxd10 microcontrollers are of fered in the following packages: 1 ? 144 lqfp, 0.5 mm pitch, 20 mm ? 20 mm outline ? 176 lqfp, 0.5 mm pitch, 24 mm ? 24 mm outline 1.5 feature details 1.5.1 low-power operation pxd10 devices are designed for opt imized low-power operation and dynam ic power management of the core processor and peripherals. powe r management features include so ftware-controlled clock gating of peripherals and multiple power domains to minimize leakage in low-power modes. there are two static low-power modes, standby and stop, and two dynamic power modes?run and halt. both low power modes use clock gating to halt the clock for all or part of the device. the standby mode also uses power gatin g to automatically turn off the pow er supply to parts of the device to minimize leakage. standby mode turns off the power to the majority of the chip to offer the lowest power consumption mode. the contents of the cores, on-chip peripheral re gisters and potentially some of the volatile memory are lost. standby mode is configurable to make cert ain features available with the disadvantage that these consume additional current: ? it is possible to retain the contents of the full ram or only 8 kb. ? it is possible to enable the internal 16 mhz or 128 khz rc oscillator, the external 4?16 mhz oscillator, or the external 32 khz oscillator. ? it is possible to keep the lcd module active. the device can be awakened from standby mode vi a from any of as many as 19 i/o pins, a reset or from a periodic wake-up usi ng a low power oscillator. stop mode maintains power to the entire device al lowing the retention of al l on-chip registers and memory, and providing a faster rec overy low power mode than the lo west standby mode. there is no need to reconfigure the de vice before executing code. the clocks to the core and peripherals are halted and can be optionally stopped to the oscillator or pll at the expense of a slower start-up time. 1. see the device comparison table or orderable parts summary for package offerings for each device in the family.
pxd10 microcontroller reference manual, rev. 1 1-8 freescale semiconductor preliminary?subject to change without notice stop is entered from run mode onl y. wake-up from stop mode is tr iggered by an external event or by the internal periodic wake-up, if enabled. run modes are the main operating mode where the enti re device can be powered and clocked and from which most processing activity is done. four dynamic run modes are s upported?run0 - run3. the ability to configure and se lect different run modes en ables different clocks and power configurations to be supported with respect to each other and to allow switching between different operating conditions. the necessary peripherals, clock sources , clock speed and system clock prescalers can be independently configured for each of the f our run modes of the device. halt mode is a reduced activity, low power mode intended for modera te periods of lower processing activity. in this mode the core sy stem clocks are stopped but user-selec ted peripheral tasks can continue to run. it can be configured to provi de more efficient power management features (switch-off pll, flash memory, main regulator, etc.) at the cost of longer wake up latency. the system returns to run mode as soon as an event or interrupt is pending.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-9 preliminary?subject to change without notice table 4 summarizes the operating modes of pxd10 devices. table 4. operating mode summary 1 table key: on?powered and clocked op?optionally configurable to be enabled or disabled (clock gated) cg?clock gated, powered but clock stopped off?powered off and clock gated fp?vreg full performance mode lp?vreg low power mode, reduced output capabi lity of vreg but lower power consumption var?variable duration, based on the requir ed reconfiguration and execution clock speed bam?boot assist module software and hardware used for device start-up and configuration o perating modes soc features clock sources periodic wake-up wake-up input vreg mode wake-up time 2 a high level summary of some key durations that need to be consi dered when recovering from low power modes. this does not accou nt for all duratio n at wake up. other delays will be necessary to consider includi ng, but not limited to the external supply start-up time. irc wake-up time must not be added to the overall wake -up time as it starts in parallel with the vreg. all other wake-up times must be added to determine the total start-up time core peripherals flash ram graphics ram main pll auxiliary pll 16 mhz irc x osc 128 khz irc 32 khz x osc vreg start-up irc wake-up flash recovery osc stabilization pll lock s/w reconfig mode switch over un on op op on on op op on op on op ? ? fp ? ? ? ? ? ? ? alt cgopopon onopoponoponopopopfp ? ? ? ? ? ?tb d t op cg cg cg on on cg cg op op on op op op lp 50 s 4 s 20 s 1ms 200 s ? 24 t andby off off 3 the lcd can optionally be kept running while the device is in standby mode. off cg 4 all of the ram contents is retained, but not accessible in standby mode. off off off op op on op op op lp 50 s 8 s 100 s 1ms 200 s var 28 off off off 8k 5 8 kb of the ram contents is retained, but not accessible in standby mode. off off off op op on op op op lp 50 s 8 s 100 s 1ms 200 s var 28 o r 500 s 8 s 100 s 1ms 200 s ba m
pxd10 microcontroller reference manual, rev. 1 1-10 freescale semiconductor preliminary?subject to change without notice additional notes on low power operation: ? fast wake-up using the on-chip 16 mhz internal rc oscillator allows rapid execution from ram on exit from low power modes ? the 16 mhz internal rc oscillat or supports low speed code execut ion and clocking of peripherals when it is selected as the system clock and can also be used as the pll input clock source to provide fast start-up without th e external oscillator delay ? pxd10 devices include an intern al voltage regulator that includes the following features: ? regulates input to genera te all internal supplies ? manages power gating ? low power regulators support operation when in stop and standby modes to minimize power consumption ? startup on-chip regulators in <50 s for rapid exit of stop and standby modes ? low voltage detection on main supply and 1.2 v regulated supplies 1.5.2 e200z0h core processor the e200z0h processor is similar to other processors in the e200zx series but supports only the vle instruction set and does not include the signal processing extension for ds p applications or a floating point unit. the e200z0h has all the feat ures of the e200z0 plus: ? branch acceleration using br anch target buffer (btb) ? supports independent instruction and data accesse s to different memory subsystems, such as sram and flash memory via indepe ndent instruction and data bius the e200z0h processor uses a four stage in-order pipe line for instruction execution. the instruction fetch (stage 1), instruction decode/regis ter file read/effective address calculation (s tage 2), execute/memory access (stage 3), and regist er writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. the integer execution unit consists of a 32-bit arithmet ic unit (au), a logic unit (lu), a 32-bit barrel shifter (shifter), a mask-inserti on unit (miu), a condition regist er manipulation unit (cru), a count-leading-zeros unit (clz), an 8 32 hardware multip lier array, result feed-forward hardware, and a hardware divider. most arithmetic and logical operations are executed in a single cycl e with the exception of the divide and multiply instructions. a count-lead ing-zeros unit operates in a single clock cycle. the instruction unit contains a pc incrementer and a dedicated branch a ddress adder to minimize delays during change of flow operations. branch target prefet ching from the btb is performed to accelerate certain taken branches. sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. branch target prefetching is performed to accelerate taken branches. prefetched instructions are placed into an instruction buffer capable of holding four instructions.
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 1-11 conditional branches not taken execu te in a single clock. branches with successful target prefetch ing have an effective executi on time of one clock on e200z0h. all other taken branch es have an execution time of two clocks. memory load and store operations are provided for byte, halfword, a nd word (32-bit) data with auto matic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. these instructions can be pipelined to allow effective s ingle cycle throughput. load and store multiple word instructions allow low overhead context save and restore operations. the load/store un it contains a dedicated effective address adde r to allow effective address generation to be optimized. also, a load-to-use depende ncy does not incur any pipeline bubbles for most cases. the condition register unit supports the condition register (cr) and condition register operations defined by the power archite cture. the condition register consists of eight 4-bit fields that reflect the results of certain ope rations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provi de a mechanism for testing and branching. vectored and autovectored interrupts are supported. hardware vectored interrupt suppor t is provided to allow multiple interrupt sources to have unique interrupt handl ers invoked with no software overhead. the cpu includes support for variable lengt h encoding (vle) instruction enhancemen ts. this allows the classic powerpc instruction set to be represented by a modi fied instruction set made up from a mixture of 16-bit a nd 32-bit instructions. this results in a significantly smaller code size footprint without affect ing performance noticeably. the cpu core is enhanced by an additional interrupt source?non maskable interrupt. this interrupt source is routed directly fro m package pins, via edge detecti on logic in the siu to the cpu, bypassing the inte rrupt controller completely. once the edge dete ction logic is programmed, it can not be disable d, except by reset. the non maskable interr upt is, as the name suggests, completely un-maskable and when asserted will always result in the immediate execution of the re spective interrupt service routine. the no n maskable interrupt is not guaranteed to be recoverable. the cpu core has an additional ?wait for in terrupt? instruction that is used in conjunction with low power stop mode. when low power stop mode is selected, this instructi on is executed to allow the system clock to be stopped. an exte rnal interrupt source or the system wake-up timer is used to restart the system clock and allow the cpu to service the interrupt. additional features include: ? load/store unit ? 1-cycle load latency ? misaligned access support ? no load-to-use pipeline bubbles ? thirty-two 32-bit genera l purpose registers (gprs) ? separate instruction bus and load/store bus harvard architecture ? reservation instructions for implem enting read-modify-write constructs
pxd10 microcontroller reference manual, rev. 1 1-12 freescale semiconductor preliminary?subject to change without notice ? multi-cycle divide (divw) and load multipl e (lmw) store multiple (smw) multiple class instructions, can be interrupted to pr event increases in interrupt latency ? extensive system developmen t support through nexus debug port 1.5.3 display control unit (dcu) the dcu is a display controller designed to drive tft lcd displays capable of driving up to wqvga resolution screens with 16 layers and 4 planes with real time alpha-blending. the dcu generates all the necessary signals required to drive the displa y: up to 24-bit rg b data bus, pixel clock, data enable, horizont al-sync and vertical-sync. internal memory resource of the pxd10 allows to ea sily handle complex graphi cs contents (pictures, icons, languages, fonts) on a color tft panel in up to wide quarter video graphics array (wqvga) sizes. all the data fetches from inte rnal and/or external memory are pe rformed by the internal four-channel dma of the dcu providing a high speed/low latency access to the system backbone. control descriptors (cds) associated with each layer enable effective merging of different resolutions into one plane to optimize use of internal memory buffers. a layer may be constructed from graphic content of various resolutions including 1bpp, 2bpp, 4bpp, 8bpp, 16bpp, 24bpp and 24bpp+alpha. the ability of the dcu to handle input data in resolutions as low as 1bpp, 2bpp and 4bpp enables a highly efficient use of internal memory resources of the pxd10. a special tiled mode can be enabled on any of the 16 layers to repeat a pattern optimizi ng graphic memory usage. a hardware cursor can be managed independently of the layers at bl ending level increasing the efficient use of the internal dcu resources. to secure the content of all critical information to be displayed, a safety mode can be activated to check the integrity of critical data along the whole system data path from the memory to the tft pads. the dcu features the following: ? display color depth: up to 24 bpp ? generation of all rgb and control signals for tft ? four-plane blending ? maximum number of input layers: 16 (fixed priority) ? dynamic look-up table (c olor and gamma look-up) ? ?? blending range: as many as 256 levels ? transparency mode ? gamma correction ? tiled mode on all the layers ? hardware cursor ? critical display content integrity m onitoring for functional safety support ? internal direct memory access (d ma) module to transfer data from internal and/or external memory.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-13 preliminary?subject to change without notice 1.5.4 parallel data interface (pdi) the pdi is a digital interface used to receive external digital video or graphic content into the dcu. the pdi input is directly injected into the dcu ba ckground plane fifo. when the pdi is activated, all the dcu synchronization is extracted from the external video stream to guarant ee the synchronization of the two video sources. the pdi can be used to: ? connect a video camera output directly to the pdi ? connect a secondary display driver as slave with a minimum of extra cost ? connect a device gathering various video sources ? provide flexibility to allow the dcu to be used in slave mode (e xternal synchronization) the pdi features the following: ? supported color modes: ? 8-bit mono ? 8-bit color multiplexed ? rgb565 ? 16-bit/18-bit raw color ? supported synchronization modes: ? embedded itu-r bt.656-4 (rgb565 mode 2) ? hsync, vsync ? data enable ? direct interface with dcu background plane fifo ? synchronization generation for the dcu 1.5.5 liquid crystal display (lcd) driver the lcd driver module has two configurations allowing a maximum of 160 or 228 lcd segments: ? as many as 40 frontplane driver s and four backplane drivers ? as many as 38 frontplane drivers and six backplane drivers each segment is controlled and can be masked by a corresponding bit in the lcd ram. four to six multiplex modes (1/1, 1/2, 1/3, 1/4, 1/5, 1/ 6 duty), and three bias (1/1, 1/2, 1/3) methods are available. all frontplane and backplane pins can be multiplexed with other port functions. the lcd driver module fe atures the following: ? programmable frame clock generato r from different clock sources: ? system clock ? internal rc oscillator ? programmable bias vol tage level selector
pxd10 microcontroller reference manual, rev. 1 1-14 freescale semiconductor preliminary?subject to change without notice ? on-chip generation of all output voltage levels ? lcd voltage reference ta ken from main 5v supply ? lcd ram ? contains the data to be displayed on the lcd ? data can be read from or writte n to the display ram at any time ? end of frame interrupt ? optimizes the refresh of the data without visual artefact ? provides selectable number of frames between each interrupt ? contrast adjustment using program mable internal voltage reference ? remapping capability of four or six backplanes with frontplanes ? increase pin selection flexibility ? in low power modes, the lcd operation can be suspended under software control. the lcd can also operate in low power modes, clocked by the internal 128 khz irc or external 32 khz crystal oscillator ? selectable output current boost during transitions 1.5.6 stepper motor controller (smc) the smc module is a pwm motor controller suitable to drive loads requiring a pwm signal. the motor controller has twelve pwm cha nnels associated with two pi ns each (24 pins in total). the smc module includes the following features: ? 10/11-bit pwm counter ? 11-bit resolution with select able pwm dithering function ? left, right, or center aligned pwm ? output slew rate control ? output short circuit detection this module is suited for, but not limited to, dr iving small stepper and ai r core motors used in instrumentation applications . this module can be used for other motor control or pwm applications that match the frequency, resolution, and out put drive capabilities of the module. 1.5.7 stepper stall detector (ssd) the stepper stall detector (ssd) m odule provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full st eps when the gauge pointer is returning to zero (rtz). the ssd module features the following: ? programmable full step state ? programmable integration polarity ? blanking (recirculation) state ? 16-bit integration accumulator register
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-15 preliminary?subject to change without notice ? 16-bit modulus down counter with interrupt 1.5.8 flash memory the pxd10 microcontroller has the fo llowing flash memory features: ? as much as 1 mb of burst flash memory ? typical flash memory access time: 0 wait-state for buffer hits, 2 wait-states for page buffer miss at 64 mhz ? two 4 128-bit page buffers with programmable prefetch control ? one set of page buffers can be allocated for c ode-only, fixed partitions of code and data, all available for any access ? one set of page buffers allocated to display controller unit and the edma ? 64-bit ecc with single-bit correction, double-bit detection for data integrity ? 64 kb data flash memory ? separate 4 ? 16 kb flash block for eeprom emulation with prefetch buffer and 128-bit data access port ? small block flash memory arrangement to suppor t features such as boot block, operating system block ? hardware managed flash memory wr ites, erase and verify sequence ? censorship protection scheme to prev ent flash memory content visibility ? separate dedicated 64 kb data flash memory for eeprom emulation ? four erase sectors each c ontaining 16 kb of memory ? offers read-while-write functi onality from main program space ? same data retention and program erase specification as main program flash memory array 1.5.9 static random-access memory (sram) the pxd10 microcontrollers have as much as 48 kb general-purpos e on-chip sram with the following features: ? typical sram access time: 0 wait-s tate for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back with a read to same memory block ? 32-bit ecc with single-bit correction, double bit detection for data integrity ? supports byte (8-bit), half word (16-bit), and wo rd (32-bit) writes for optimal use of memory ? user transparent ecc encoding and decoding for byte, half word, and word accesses ? separate internal power domain applied to full sram block, 8 kb sram block during standby modes to retain cont ents during low power mode. 1.5.10 on-chip graphics sram the pxd10 microcontroller has 160 kb on-chip gr aphics sram with th e following features: ? usable as general purpose sram ? typical sram access tim e: 0 wait-state for r eads and 32-bit writes
pxd10 microcontroller reference manual, rev. 1 1-16 freescale semiconductor preliminary?subject to change without notice ? supports byte (8-bit), half word (16-bit), and wo rd (32-bit) writes for optimal use of memory 1.5.11 quadspi serial flash controller the quadspi module enables use of external seri al flash memories supporting single, dual and quad modes of operation. it features the following: ? memory mapping of external serial flash ? automatic serial flash read command generation by cpu, dma or dcu r ead access on ahb bus ? supports single, dual and quad serial flash read commands ? flexible buffering scheme to maximi ze read bandwidth of serial flash ? ?legacy? mode allowing quadspi to be used as a standard spi (no dsi or csi mode) 1.5.12 analog-to-digital converter (adc) the adc features the following: ? 10-bit a/d resolution ? 0 to 5 v common mode conversion range ? supports conversions speeds of as fast as 1 s ? 16 internal and 8 external channels support ? as many as 16 single-ended inputs channels ? all channels configured to have alternat e function as general purpose input/output pins ? 10-bit 3 counts accuracy (tue) ? external multiplexer support to in crease as many as 23 channels ? automatic 1 8 mu ltiplexer control ? external multiplexer connected to a dedicated input channel ? shared register between the 8 external channels ? result register available fo r every non-multiplexed channel ? configurable left- or right-aligned result format ? supports for one-shot, scan and injection conversion modes ? injection mode status bit implemented on adjacent 16-bit register for each result ? supports access to result and inject ion status with single 32-bit read ? independently enabling of function for channels: ? pre-sampling ? offset error cancellation ?offset refresh ? conversion triggering support ? internal conversion triggering from periodic interrupt timer (pit) ? four configurable analog comparator channels offering range comparison with triggered alarm ? greater than
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-17 preliminary?subject to change without notice ?less than ? out of range ? all unused analog inputs can be used as general purpose input and output pins ? power down mode ? optional support for dma transfer of results 1.5.13 sound generation logic (sgl) module the sgl module has two modes of operation: ? amplitude modulated pwm mode for low co st buzzers using any two emios channels ? monophonic signal with amplitude control ? 8-bit amplitude resolution ? ability to mix any two emios channels. ? requires simple external rc lowpass filter ? digital sample mode for higher quality sound using one emios channel and edma ? up to 10-bit audio amplitude resolution ? polyphonic sound synthesis ? playback of sample based waveforms ? text-to-speech possibility ? requires external lowpass filter 1.5.14 serial communication interface module (uart) the pxd10 devices include as many as two uart modules and support uart master mode, uart slave mode and uart mode. the modules are uart state machine compliant to the uart 1.3 and 2.0 and 2.1 specifications and handle uart frame tran smission and reception without cpu intervention. the serial communication interf ace module offers the following: ? uart features: ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt driven operation wi th four interrupts sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate modul us counter and 16-bit fractional ? two receiver wake-up methods ? lin features:
pxd10 microcontroller reference manual, rev. 1 1-18 freescale semiconductor preliminary?subject to change without notice ? autonomous lin frame handling ? message buffer to stor e identifier and as many as 8 data bytes ? supports message length of as long as 64 bytes ? detection and flagging of lin errors ? sync field; delimiter; id parity; bit, framing; checksum and timeout errors ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features ? loop back ?self test ? lin bus stuck dominant detection ? interrupt driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? discarding of irrelevant lin responses using as many as 16 id filters 1.5.15 serial peripheral interface (spi) module the spi modules provide a synchronous serial inte rface for communication betw een the pxd10 mcu and external devices. the spi features the following: ? as many as two spi modules ? full duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate ? programmable data frames from four to 16 bits ? as many as six chip select lines available, depending on packag e and pin multiplexing, enable 64 external devices to be selected us ing external muxing from a single spi ? eight clock and transfer attributes registers ? chip select strobe available as alternate functi on on one of the chip select pins for deglitching ? fifos for buffering as many as four tr ansfers on the transmit and receive side ? general purpose i/o functionality on pins when not used for spi ? queueing operation possible through use of edma
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-19 preliminary?subject to change without notice 1.5.16 controller area ne twork (can) module the pxd10 contains two can modules that offer the following features: ? compliant with can protocol specification, version 2.0b active ? 64 mailboxes, each configurab le as transmit or receive ? mailboxes configurable while modul e remains synchronized to can bus ? transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to me ssage id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort proce dure and notification ? receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a 6-entry receive fifo ? 8 programmable acceptance filters for receive fifo ? programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter ? listen only mode capabilities ?can sampler ? can catch the first message sent on the can network while the pxd10 is stopped. this guarantees a clean startup of the system without missing message s on the can network. ? the can sampler is connected to one of the can rx pins. 1.5.17 inter-ic communications (i 2 c) module the i 2 c module features the following: ? as many as four i 2 c modules supported ? two-wire bi-directional serial bus for on-board communications ? compatibility with i 2 c bus standard ? multimaster operation ? software-programmable for one of 256 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection
pxd10 microcontroller reference manual, rev. 1 1-20 freescale semiconductor preliminary?subject to change without notice ? bus-busy detection 1.5.18 real time counter (rtc) the real timer counter supports wake-up from lo w power modes or real time clock generation ? configurable resolution for different timeout periods ? 1 s resolution for >1 hour period ? 1 ms resolution for 2 second period ? selectable clock sources from external 32 khz crystal, extern al 4?16 mhz crystal, internal 128 khz rc oscillator or divide d internal 16 mhz rc oscillator 1.5.19 enhanced modular input/ output system (timers, pwm) pxd10 microcontrollers have two emios modules ?one with 16 channels and one with 8?with input/output channels supporting a range of 16-bit input capture, out put compare, and pulse width modulation functions. the modules are configurable and can implement 8-channel, 16-bit input capture/output compare or 16-channel, 16-bit output pulse wi dth modulation/input compare/output compare. as many as five additional channels are confi gurable as modulus counters. emios features include: ? selectable clock source from main fmpll, a uxiliary fmpll, external 4?16 mhz oscillator or 16 mhz internal rc oscillator ? timed i/o channels with 16-bit counter resolution ? buffered updates ? support for shifted pwm outputs to mini mize occurrence of concurrent edges ? edge aligned output pulse width modulation ? programmable pulse pe riod and duty cycle ? supports 0% and 100% duty cycle ? shared or independent time bases ? programmable phase sh ift between channels ? selectable combination of pairs of emios outputs to support sound generation ? dma transfer support ? selectable clock source from the primary fmpll, auxiliar y fmpll, external 4?16 mhz oscillator or the 16 mhz internal rc oscillator. the channel configuration options for the 16-channel emios module are summarized in table 5 .
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-21 preliminary?subject to change without notice the channel configuration options for the 8-channel emios module are summarized in table 6 . 1.5.20 periodic interrupt timer (pit) module the pit features the following: ? four general purpos e interrupt timers ? as many as two dedicated interrupt timers for triggering adc conversions ? 32-bit counter resolution ? clocked by system clock frequency ? 32-bit counter for real time interrupt, clocked from main external oscillator table 5. 16-channel emios module channel configuration channel mode channel number 8 ic/oc counter 9?15 ic/oc 16 pwm counter 17?22 pwm 23 pwm counter general purpose input/output x xxxx single action input capture x xxxx single action output compare xxxxx modulus counter buffered 1 1 modulus up and down counters to support driving local and global counter busses xxx output pulse width and frequency modulation buffered x x x output pulse width modulation buffered x x x table 6. 8-channel emios module channel configuration channel mode channel number 16 pwm counter 17?22 pwm 23 pwm counter general purpose input/output x x x single action input capture x x x single action output compare x x x modulus counter buffered 1 1 modulus up and down counters to support driving local and global counter busses xx output pulse width and frequency modulation buffered x x x output pulse width modulation buffered x x x
pxd10 microcontroller reference manual, rev. 1 1-22 freescale semiconductor preliminary?subject to change without notice 1.5.21 system timer module (stm) the stm is a 32-bit timer that supports commonly required system and application software timing functions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 1.5.22 software watchdog timer (swt) the swt features the following: ? watchdog supporting software acti vation or enabled out of reset ? supports normal or windowed mode ? watchdog timer value wr itable once after reset ? watchdog supports optional ha lting during low power modes ? configurable response on timeout: reset, in terrupt, or interrupt followed by reset ? selectable clock source for main system cl ock or internal 16 mhz rc oscillator clock 1.5.23 interrupt controller (intc) the intc provides priority-based preemptive scheduli ng of interrupt requests, suitable for statically scheduled hard real-time systems. for high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executi ng the interrupt service routine (i sr) has been minimized. the intc provides a unique vector for each inte rrupt request source for quick dete rmination of which isr needs to be executed. it also provides an ample number of prior ities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropria te priorities for each s ource of interrupt request, the priority of each interrupt re quest is software configurable. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providi ng a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. multiple processors can assert interrupt requests to each other through software settable interrupt requests. these same software settable interrupt requests also ca n be used to break the work involved in servicing an interrupt request into a high priority po rtion and a low priority portion. the high priority porti on is initiated by a peripheral interrupt request, but then the isr asserts a so ftware settable interrupt reque st to finish the servicing in a lower priority isr. therefore these software settable interrupt requests can be used instead of the peripheral isr scheduling a task through the rtos. the intc provides the following features: ? unique 9-bit vector for each of the po ssible 128 separate interrupt sources
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-23 preliminary?subject to change without notice ? eight software-triggerable interrupt sources ? 16 priority levels with fixed hardware arbitrati on within priority levels for each interrupt source ? ability to modify the isr or task priority. ? modifying the priority can be used to implem ent the priority ceiling protocol for accessing shared resources. ? external non-maskable in terrupt directly accessing the main core cri tical interrupt mechanism ? 32 external interrupts 1.5.24 system integration unit (siu) the siu controls mcu reset confi guration, pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiple xing, and the system reset operation. the gpio features the following: ? as many as four levels of internal pin mul tiplexing, allowing exceptional flexibility in the allocation of device functions for each package ? centralized general purpose input output (gpio) control of as many as 132 input/output pins (package dependent) ? all gpio pins can be independently conf igured to support pul l-up, pull down, or no pull ? reading and writing to gpio supported both as individual pins and 16-bit wide ports ? all peripheral pins can be alte rnatively configured as both gene ral purpose input or output pins except adc channels which support alternative configurat ion as general purpose inputs ? direct readback of the pin value supported on all digita l output pins through the siu ? configurable digital input filter that can be applied to as many as 14 general purpose input pins for noise elimination on external interrupts ? register configuration protected ag ainst change with soft lock for temporary guard or hard lock to prevent modification until next reset. 1.5.25 system clocks and clock generation modules the system clock on the pxd10 can be derived from an external oscillator, an on-chip fmpll, or the internal 16 mhz oscillator. ? the source system clock freque ncy can be changed via an on-ch ip programmable clock divider ( ? 1 to ?? 2). ? additional programmabl e peripheral bus cl ock divider ratio ( ? 1 to ? 16) ? the pxd10 has two on-chip fmplls?the primary module and an auxiliary module. ? each features the following: ? input clock frequency from 4 mhz to 16 mhz ? lock detect circuitry conti nuously monitors lock status ? loss of clock (loc) detection fo r reference and feedback clocks
pxd10 microcontroller reference manual, rev. 1 1-24 freescale semiconductor preliminary?subject to change without notice ? on-chip loop filter (for impr oved electromagnetic interfer ence performance and reduction of number of external components required) ? support for frequency ramping from pll ? the primary fmpll module is for use as a system clock s ource. the auxiliary fmpll is available for use as an altern ate, modulated or non-modulated clock source to emios modules and as alternate clock to the dcu for pixel clock generation. ? the main oscillator provides the following features: ? input frequency range 4?16 mhz ? square-wave input mode ? oscillator input mode 3.3 v (5.0 v) ? automatic level control ? pll reference ? pxd10 includes a 32 khz low power external oscillator for slow execution, low power, and real time clock ? dedicated internal 128 khz rc oscillator fo r low power mode operation and self wake-up ? 10% accuracy across vol tage and temperature (a fter factory trimming) ? trimming registers to suppor t improved accuracy with in-application calibration ? dedicated 16 mhz inte rnal rc oscillator ? used as default clock source out of reset ? provides a clock for rapid st art-up from low power modes ? provides a back-up clock in the event of pll or external oscillator clock failure ? offers an independent clock source for the watchdog timer ? 5% accuracy across voltage and te mperature (after factory trimming) ? trimming registers to support frequency ad justment with in-appl ication calibration 1.5.26 crossbar switch (xbar) the xbar multi-port crossbar switch supports simultaneous connections between four master ports and four slave ports. the crossbar supports a 32-bi t address bus width and a 32-bit data bus width. the crossbar allows four concurrent transactions to occur from any ma ster port to any slave port but one of those transfers must be an inst ruction fetch from internal flash. if a slave port is simultaneously requested by more than one master por t, arbitration logic selects the highe r priority master and grants it ownership of the slave port. all other masters requesting that slave port are stalled until the higher priority master completes its transactions. requesting masters having equal priori ty are granted access to a slave port in round-robin fashion, based upon the id of the last master to be granted access. the crossbar provides the following features: ? four master ports ? e200z0h core instruction port ? e200z0h core complex load/store data port
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-25 preliminary?subject to change without notice ? edma controller ? display control unit ? four slave ports ? one flash port dedicated to the cpu ? platform sram ? quadspi serial flash controller ? one slave port combining: ? flash port dedicated to the disp lay control unit and edma module ? graphics sram ? peripheral bridge ? 32-bit internal address bus , 32-bit internal data bus 1.5.27 enhanced direct memory access (edma) the edma module is a controller capable of performing complex da ta movements via 16 programmable channels, with minimal intervention from the host processor. the hardware micro architecture includes a dma engine which performs source and destination address calculations , and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. this implementation is utilized to minimize the overall bl ock size. the edma module provides the following features: ? 16 channels support independent 8-, 16- or 32-bit single value or block transfers ? supports variable sized que ues and circular queues ? source and destination address regi sters are independently configured to post-increment or remain constant ? each transfer is initiated by a peripheral, cpu, periodic timer interrupt or edma channel request ? each dma channel can optionally send an interrupt request to th e cpu on completion of a single value or block transfer ? dma transfers possible between sy stem memories, quadspi, spis, i 2 c, adc, emios and general purpose i/os (gpios) ? programmable dma channel mux allows assignm ent of any dma source to any available dma channel with a total of as many as 64 potential request sources. 1.5.28 memory protection unit (mpu) the mpu features the following: ? 12 region descriptors for per-master protection ? start and end address defi ned with 32-byte granularity ? overlapping regions supported ? protection attributes can optionally include process id ? protection offered for 3 concurrent read ports
pxd10 microcontroller reference manual, rev. 1 1-26 freescale semiconductor preliminary?subject to change without notice ? read and write attri butes for all masters ? execute and supervisor/user mode attributes for processor masters 1.5.29 boot assist module (bam) the bam is a block of read-only memory that is programmed once by freescale. the bam program is executed every time the mcu is powered-on or reset in normal mode. the bam s upports different modes of booting. they are: ? booting from internal flash memory ? serial boot loading (a program is downloaded into ram via can or uart and then executed) ? booting from external memory additionally, the bam: ? enables and manages the transition of the mcu from reset to user code execution ? configures device for serial bootload ? enables multiple bootcode starting locations out of reset through implem entation of search for valid reset configuration halfword ? enables or disables software watchdog timer out of reset through ba m read of the reset configuration halfword option bit 1.5.30 ieee 1149.1 jtag controller (jtagc) jtagc features the following: ? backward compatible to standard jtag ie ee 1149.1-2001 test access port (tap) interface ? support for boundary scan testing 1.5.31 nexus development interface (ndi) nexus features the following: ? per ieee-isto 5001-2003 ? nexus 2 plus features supported ? static debug ? watchpoint messaging ? ownership trace messaging ? program trace messaging ? real time read/write of any internally memory mapped resources through jtag pins ? overrun control, which selects whether to stal l before nexus overruns or keep executing and allow overwrite of information ? watchpoint triggering, watchpoint triggers program tracing ? configured via the ieee 1149.1 (jtag) port ? nexus auxiliary port supported on the 176 lqfp package for development only
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-27 preliminary?subject to change without notice ? narrow auxiliary nexus port supporti ng support trace, with two mdo pins ? wide auxiliary nexus port supporting higher bandwidth trace, with four mdo pins 1.6 developer environment the pxd10 mcu family uses tools and third-party developers which offer a widespread, established network of tool and software vendors. it also features a high-performance nexus debug interface. the following development support is available: ? evaluation boards (evb) featuring displa y capability and serial interfaces ? compilers ? debuggers ? jtag and nexus interfaces 1.7 how to use the pxd10 documents this section: ? describes how the pxd10 documents pr ovide information on the microcontroller ? makes recommendations on how to us e the documents in a system design 1.7.1 the pxd10 document set the pxd10 document set comprises: ? this reference manual (provides in formation on the features of the logical blocks on the device and how they are integrated with each other) ? the device data sheet (specifies the el ectrical characteristics of the device) ? the device product brief the following reference documents (available online at www.freescale.com) are also available to support the cpu on this device: ? programmer?s reference manual for freescale embedded processors ? e200z0 power architectur e core reference manual ? variable-length encoding (vle) programming environments manual the aforementioned documents describe all of the f unctional and electrical char acteristics of the pxd10 microcontroller. depending on your task, you may need to refer to multiple documents to make design decisions. however, in general the use of the documents can be divided up as follows: ? use the reference manual (this document) dur ing software development and when allocating functions during system design. ? use the data sheet when designing hard ware and optimizing power consumption.
pxd10 microcontroller reference manual, rev. 1 1-28 freescale semiconductor preliminary?subject to change without notice ? use the cpu reference documen ts when doing detailed softwa re development in assembly language or debugging comple x software interactions. 1.7.2 reference manual content the content in this document focuses on the functi onality of the microcontroller rather than its performance. most chapters describe the functionality of a particular on-chip module, such as a can controller or timer. the remaining chapters describe how these modules are integrated into the memory map, how they are powered and clocked, and the pin-out of the device. in general, when an individual modul e is enabled for use all of the detail required to configure and operate it is contained in the dedicated chap ter. in some cases ther e are multiple implementa tions of this module, however, there is only one chapter for each type of mo dule in use. for this reas on, the address of registers in each module is normally provide d as an offset from a base address which can be found in chapter 2, memory map . the benefit of this approach is that software developed for a pa rticular module can be easily reused on this device and on other rela ted devices that use the same modules. the steps to enable a module for use varies but typi cally these require configur ation of the integration features of the microcontroller. the module will normally have to be power ed and enabled at system level, then a clock may have to be explicitly chosen and finally if required the input and output connections to the external system must be configured. the primary integration chapters of the reference manual contain most of the information required to enable the modules. there are specia l cases where a chapter may describe module functionality and some integration features for convenience ? for example, the microcontroller input /output (siul) module. integration and functional content is provided in the manual as shown in table 1-7 . table 1-7. reference manual integration and functional content chapter integration content functional content overview ? the main features on chip ? a summary of the functions provided by each module ? memory map how the memo ry map is allocated, including: ? internal ram ? flash memory ? external memory-mapped resources and the location of the registers used by the peripherals 1 ? signal description how the signals from each of the modules are combined and brought to a particular pin on a package ? boot assist module cpu boot sequence from re set implementation of the boot options if internal flash memory is not used clock description clocking architecture of the device (which clock is available for the system and each peripheral) description of operation of different clock sources
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-29 preliminary?subject to change without notice 1.8 using the pxd10 there are many different approaches to designing a system using the pxd10 so the guidance in this section is provided as an example of how the doc uments can be applied in this task. familiarity with the pxd10 m odules can help ensure that its features are being optimally used in a system design. therefore, the current chapte r is a good starting point. further info rmation on the detailed features of a module are provided within the module chapters. these, combined wi th the current chapter, should provide a good introduction to the functions available on the mcu. 1.8.1 hardware design the pxd10 requires that certain pi ns are connected to particular pow er supplies, system functions and other voltage leve ls for operation. the pxd10 internal logic operates from 1.2 v (nom inal) supplies that are normally supplied by the on-chip voltage regulator from a 5 v or 3.3 v supply. the 5 v and 3.3 v supplies are also used to supply the input/output pins on the mcu. this means that di fferent input/output ports can operate at different voltages simultaneously. chapter 3, signal description, describes the power supply pin names, numbers and their purpose. for more detail on the voltage supply of each pin, see chapter 40, voltage regulators and power supplies ; that chapter also describes the use of th e required external ballast transistor to generate the 1.2v. for specifications of the voltage ranges and limits and decoupling of the power supplies see the pxd10 data sheet. certain pins have dedicated functions that affect the behavior of the mc u after reset. these include pins to force test or alternate boot conditions and debug features. these are described in chapter 3, signal description, and a hardware designer should take care that these pins are connected to allow correct operation. beyond power supply and pins that have special functions there are also pins that have special system purposes such as oscillat or and reset pins. these are also described in chapter 3, signal description . the dma channel mux source values for module dma channels how to connect a module dma channel to the edma module interrupt controller interrupt vector table operation of the module mode entry module module numbering for cont rol and status operation of operating modes system integration unit lite how input signals are mapped to individual modules including external interrupt pins operation of gpio voltage regulators and power supplies power distribution to the mcu and in particular to different i/o banks ? wakeup unit allocation of inputs to the wakeup unit operation of the wakeup feature 1 to find the address of a register in a particular module ta ke the start address of the module given in the memory map and add the offset for the register given in the module chapter. table 1-7. reference manual integration and functional content (continued) chapter integration content functional content
pxd10 microcontroller reference manual, rev. 1 1-30 freescale semiconductor preliminary?subject to change without notice reset pin is bidirectional and its function is closely tied to the reset generation module (see chapter 32, reset generation module (mc_rgm) ). the crystal oscillator pins are dedicated to this function but the oscillator is not started automatically after reset. the oscillator module is described in chapter 8, clock description, along with the internal clock architecture and the other oscillator sources on chip. 1.8.2 input/output pins the majority of the pins on the mcu are input/output pins which may either operate as general purpose pins or be connected to a particul ar on-chip module. the arrangement al lows a function to be available on several pins. the system designer s hould allocate the function for the pi n before connecting to external hardware. the software should then choose the co rrect function to match the hardware. the pad characteristics can vary dependi ng on the functions on the pad. chapter 3, signal description, describes each pad type (for example, slow , m1, or smd). two pads may be ab le to carry the same function but have different pad types. the electr ical specification of the pads is de scribed in the data sheet dependent on the function enabled and the pad type. there are four modules that confi gure the various fu nctions available: ? system integration unit lite (siul) ? wakeup unit (wkpu) ?lcd ? 32 khz oscillator (sxosc) the siul configures the di gital pin functions. each pin has a regi ster (pcr) in the module that allows selection of the output func tions that is connected to the pin. th e available settings for the pcr are described in section 3.8, functional ports. inputs are selected using the psm i registers; these are described in chapter 37, system integration unit lite (siul) . (psmi registers connect a module to one of several pins, whereas the pcr registers connect a pin to one of several modules). the wkpu provides the ability to cause interr upts and wake the mcu from low power modes and operates independently from the siul. in addition to digital i/o functions there are "special functions" that provide analog functionality. these are listed in section 3.8, functional ports . the special functions are enable d independently from the digital i/o which means that the digital function on the pin must be disabled when the special function is active. the lcd module and the sxosc oscillator are enable d in the modules. the adc functions are enabled using the pcrs. 1.8.3 software design certain modules provide system inte gration functions, and ot her modules (such as ti mers) provide specific functions. from reset, the modules involved in configur ing the system for application software are: ? boot assist module (bam) ? determines the selected boot source ? reset generation module (mc_rgm) ? determines the behavior of the mcu when various reset sources are triggered and reports the source of the reset
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 1-31 preliminary?subject to change without notice ? mode entry module (mc_me) ? controls which op erating mode the mcu is in and configures the peripherals and clocks and power supplies for each of the modes ? power control unit (mc_pcu) ? de termines which power domains (see chapter 40, voltage regulators and power supplies ) are active ? clock generation module (mc_cgm) ? chooses the clock source for the system and many peripherals after reset, the mcu will automatical ly select the appropriate reset so urce and begin to execute code. at this point the system clock is the 16 mhz firc osci llator, the cpu is in supervisor mode and all the memory is available. initialization is required before most peripherals may be used and before the sram can be read (since the sram is pr otected by ecc, the syndrome will ge nerally be uninitialized after reset and reads would fail the check). accessing disabled features causes error conditions or interrupts. a typical startup routine would invol ve initializing the soft ware environment including stacks, heaps, variable initialization and so on and c onfiguring the mcu for the application. the mc_me module enables the modules and other features like clocks. it is therefore an essential part of the initialization and operation so ftware. in general, the software will configure an mc_me mode to make certain peripherals, clocks, and memory active and then switch to that mode. chapter 8, clock description, includes a graphic of the clock archit ecture of the mcu. this can be used to determine how to configure the mc_cgm module. in general software will configure the module to enable the required clocks and plls and route these to the active modules. after these steps are complete it is possible to c onfigure the input/output pins and the modules for the application. 1.8.4 other features the mc_me module manages low power m odes and so it is likely that it will be used to switch into different configurations (module sets, cloc ks) depending on the application requirements. the mcu includes two other f eatures (both described in chapter 4, safety ) to improve the integrity of the application: ? it is possible to enable a software watchdog (swt ) immediately at reset or afterwards to help detect code runaway. ? individual register settings can be protected fr om unintended writes using the features of the register protection module. the pr otected registers are shown in appendix a, registers under protection . other integration f unctionality is provided by the system status and configur ation module (sscm).
pxd10 microcontroller reference manual, rev. 1 1-32 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 2-1 preliminary?subject to change without notice chapter 2 memory map table 2-1 shows the system memory map for the pxd 10. all addresses on the pxd10, including those that are reserved, are identified in the table. the addresses represent the physi cal addresses assigned to each ip block. table 2-1. pxd10 system memory map ap size [kb] pxd1005 pxd1010 region 1 start address end address on chip flash memories (code flash) 0x00000000 0x00007fff 32 yes yes 2 code flash array 0 0x00008000 0x0000bfff 16 yes yes 2 code flash array 0 0x0000c000 0x0000ffff 16 yes yes 2 code flash array 0 0x00010000 0x00017fff 32 yes yes 2 code flash array 0 0x00018000 0x0001ffff 32 yes yes 2 code flash array 0 0x00020000 0x0003ffff 128 yes yes 2 code flash array 0 0x00040000 0x0005ffff 128 yes yes 2 code flash array 0 0x00060000 0x0007ffff 128 yes yes 2 code flash array 0 0x00080000 0x0009ffff 128 no yes 2 code flash array 1 0x000a0000 0x000bffff 128 no yes 2 code flash array 1 0x000c0000 0x000dffff 128 no yes 2 code flash array 1 0x000e0000 0x000fffff 128 no yes 2 code flash array 1 0x00100000 0x001fffff 1024 ? ? reserved on chip flash memories (shadow for code flash) 0x00200000 0x00203fff 16 yes yes code flash array 0 shadow sector 0x00204000 0x003fffff 2032 ? ? reserved on chip flash memories (test for code flash) 0x00400000 0x00403fff 16 yes yes code flash array 0 test sector 0x00404000 0x0047ffff 496 ? ? reserved 0x00480000 0x00483fff 16 no yes code flash array 1 test sector 0x00484000 0x007fffff 3568 ? ? reserved
pxd10 microcontroller reference manual, rev. 1 2-2 freescale semiconductor preliminary?subject to change without notice on chip flash memories (data flash) 0x00800000 0x00803fff 16 yes yes data flash array 0 0x00804000 0x00807fff 16 yes yes data flash array 0 0x00808000 0x0080bfff 16 yes yes data flash array 0 0x0080c000 0x0080ffff 16 yes yes data flash array 0 0x00810000 0x00bfffff 4032 ? ? reserved on chip flash memories (test for data flash) 0x00c00000 0x00c03fff 16 yes yes data flash array 0 test sector 0x00c04000 0x00ffffff 2032 ? ? reserved emulation mapping 0x01000000 0x1fffffff 507904 yes yes flash emulation mapping 0x20000000 0x3fffffff 524288 ? ? reserved sram 0x40000000 0x40001fff 8 yes yes sram (ecc protection, standby support) 0x40002000 0x40005fff 16 yes yes sram (ecc protection, in pd2) 0x40006000 0x4000bfff 24 yes yes sram (ecc protection, in pd2) 0x4000c000 0x5fffffff 524240 ? ? reserved 0x60000000 0x60027fff 160 no yes graphics sram (no ecc protection, no standby support) 0x60028000 0x7fffffff 524128 ? ? reserved external, memory mapped serial flash (supports one [quad]spi serial flash) 0x80000000 0x87ffffff 131072 no yes external serial flash memory 0 0x88000000 0xbfffffff 917504 ? ? reserved aips(1) - off platform peripher als (mirrored to aips(0) memory range 0xffe80000-0xffefffff) 0xc3f80000 0xc3f87fff 32 ? ? reserved 0xc3f88000 0xc3f8bfff 16 yes yes code flash 0 configuration (cflash0) table 2-1. pxd10 system memory map (continued) ap size [kb] pxd1005 pxd1010 region 1 start address end address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 2-3 preliminary?subject to change without notice 0xc3f8c000 0xc3f8ffff 16 yes yes data flash 0 configuration (dflash0) 0xc3f90000 0xc3f93fff 16 yes yes system integration unit lite (siul) 0xc3f94000 0xc3f97fff 16 yes yes wakeup unit (wkup) 0xc3f98000 0xc3f9ffff 32 ? ? reserved 0xc3fa0000 0xc3fa3fff 16 yes yes enh anced modular i/o subsystem 0 (emios0) 0xc3fa4000 0xc3fa7fff 16 yes yes enh anced modular i/o subsystem 1 (emios1) 0xc3fa8000 0xc3faffff 32 ? ? reserved 0xc3fb0000 0xc3fb3fff 16 no yes code flash 1 configuration (cflash1) 0xc3fb4000 0xc3fd7fff 144 ? ? reserved 0xc3fd8000 0xc3fdbfff 16 yes yes system status and configuration module (sscm) 0xc3fdc000 0xc3fdffff 16 yes yes mode entry module (mc_me) 0xc3fe0000 0xc3fe3fff 16 yes yes clock generation module (mc_cgm, xosc, ircosc, fmpll_0, fmpll_1, cmu0, cmu1) 0xc3fe4000 0xc3fe7fff 16 yes yes reset generation module (mc_rgm) 0xc3fe8000 0xc3febfff 16 yes yes power control unit (mc_pcu) 0xc3fec000 0xc3feffff 16 yes yes real time counter (rtc/api) 0xc3ff0000 0xc3ff3fff 16 yes yes periodic interrupt timer (pit/rti) 0xc3ff4000 0xc3ffffff 48 ? ? reserved aips(0) - off platform peripherals (new range) 0xffe00000 0xffe03fff 16 yes yes analog to digital converter 0 (adc0) 0xffe04000 0xffe2ffff 176 o reserved 0xffe30000 0xffe33fff 16 yes yes inte r-ic bus interface controller 0 (i 2 c0) 0xffe34000 0xffe37fff 16 yes yes inte r-ic bus interface controller 1 (i 2 c1) table 2-1. pxd10 system memory map (continued) ap size [kb] pxd1005 pxd1010 region 1 start address end address
pxd10 microcontroller reference manual, rev. 1 2-4 freescale semiconductor preliminary?subject to change without notice 0xffe38000 0xffe3bfff 16 no yes inte r-ic bus interface controller 2 (i 2 c2) 0xffe3c000 0xffe3ffff 16 no yes inte r-ic bus interface controller 3 (i 2 c3) 0xffe40000 0xffe43fff 16 yes yes linflex 0 0xffe44000 0xffe47fff 16 yes yes linflex 1 0xffe48000 0xffe5ffff 96 ? ? reserved 0xffe60000 0xffe60fff 4 yes yes stepper motor control (smc) 0xffe61000 0xffe617ff 2 yes yes stepper stall detect (ssd0) 0xffe61800 0xffe61fff 2 yes yes stepper stall detect (ssd1) 0xffe62000 0xffe627ff 2 yes yes stepper stall detect (ssd2) 0xffe62800 0xffe62fff 2 yes yes stepper stall detect (ssd3) 0xffe63000 0xffe637ff 2 yes yes stepper stall detect (ssd4) 0xffe63800 0xffe63fff 2 yes yes stepper stall detect (ssd5) 0xffe64000 0xffe6ffff 48 ? ? reserved 0xffe70000 0xffe73fff 16 ye s yes can sampler (cansp) 0xffe74000 0xffe77fff 16 yes yes lcd controller 0 (lcd0) 0xffe78000 0xffe7bfff 16 ye s ye s sound generation logic (sgl) 0xffe7c000 0xffe7ffff 16 yes yes display control unit 0 (dcu0) aips(0) - off platform mirror from aips( 1) (mirrored range from aips(1) range 0xc3f80000-0xc3ffff ff) (new range) 0xffe80000 0xffefffff 512 yes yes reserved aips(0) - on platform peripherals (existing esys range) 0xfff00000 0xfff03fff 16 yes yes aips0 0xfff04000 0xfff07fff 16 yes yes axbs 0xfff08000 0xfff0ffff 16 - - reserved 0xfff10000 0xfff13fff 16 yes yes me mory protection unit (mpu) 0xfff14000 0xfff37fff 144 ? ? reserved table 2-1. pxd10 system memory map (continued) ap size [kb] pxd1005 pxd1010 region 1 start address end address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 2-5 preliminary?subject to change without notice 0xfff38000 0xfff3bfff 16 yes yes software watchdog (swt0) 0xfff3c000 0xfff3ffff 16 yes yes system timer module (stm0) 0xfff40000 0xfff43fff 16 yes yes e rror correction status module 0xfff44000 0xfff47fff 16 yes yes direct memory access controller 2 (dma2x) 0xfff48000 0xfff4bfff 16 yes yes interrupt controller (intc) 0xfff4c000 0xfff8ffff 272 ? ? reserved 0xfff90000 0xfff93fff 16 yes yes dspi 0 0xfff94000 0xfff97fff 16 yes yes dspi 1 0xfff98000 0xfffa7fff 64 ? ? reserved 0xfffa8000 0xfffabfff 16 no yes quadspi 0 0xfff9c000 0xfffbffff 144 ? ? reserved 0xfffc0000 0xfffc3fff 16 yes yes flexcan 0 (can0) 0xfffc4000 0xfffc7fff 16 yes yes flexcan 1 (can1) 0xfffc8000 0xfffdbfff 80 ? ? reserved 0xfffdc000 0xfffdffff 16 yes yes dma channel multiplexer (dma_mux) 0xfffe0000 0xffffbfff 112 ? ? reserved 0xffffc000 0xffffffff 16 yes yes boot assist module (bam) 1 the contents of memory addresses marked as reserved and individual bits within a memory address that are marked as reserved may return any value when read unless otherwise indicated. 2 flash sector can be accessed via both slave ports. arbitration logic required in case two different masters do access the same address at the same time. table 2-1. pxd10 system memory map (continued) ap size [kb] pxd1005 pxd1010 region 1 start address end address
pxd10 microcontroller reference manual, rev. 1 2-6 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 3-1 preliminary?subject to change without notice chapter 3 signal description 3.1 introduction the following sections provide signa l descriptions and related inform ation about the f unctionality and configuration.
pxd10 microcontroller reference manual, rev. 1 3-2 freescale semiconductor preliminary?subject to change without notice 3.2 package pinouts the 144- and 176-pin lqfp pinouts and the 208 mapbga ball map are provided in the following figures. figure 3-1. lqfp 144-pin configuration (top view) 1 1. availability of port pin alternate functions depends on product selection 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144-pin lqfp 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 nmi/gpio[72]/pf2 vdde_b vsse_b pcs2_0/emiosb19/rxd_1/gpio[28]/pb12 pcs1_0/emiosb18/txd_1/gpio[29]/pb13 vdd12 vss12 emiosb20/sck_0/gpio[25]/pb9 emiosb21/sout_0/gpio[24]/pb8 emiosb22/sin_0/gpio[23]/pb7 clkout/emiosb16/pcs0_0/gpio[103]/ph4 ma0/sck_1/gpio[20]/pb4 fabm/ma1/sout_1/gpio[21]/pb5 abs[0]/ma2/sin_1/gpio[22]/pb6 vdd12 vss12 vdda vssa xtal32/ans15/gpio[45]/pc15 extal32/ans14/gpio[44]/pc14 pcs0_1/ma2/ans13/gpio[43]/pc13 pcs1_1/ma1/ans12/gpio[42]/pc12 pcs2_1/ma0/ans11/gpio[41]/pc11 sound/ans10(mux)/gpio[40]/pc10 ans9/gpio[39]/pc9 ans8/gpio[38]/pc8 vdde_c vsse_c ans7/gpio[37]/pc7 ans6/gpio[36]/pc6 ans5/gpio[35]/pc5 ans4/gpio[34]/pc4 ans3/gpio[33]/pc3 ans2/gpio[32]/pc2 ans1/gpio[31]/pc1 ans0/gpio[30]/pc0 pa9/gpio[9]/dcu_g1/emiosb18/sda_2/fp14 pa8/gpio[8]/dcu_g0/emiosb23/scl_2/fp15 pa7/gpio[7]/dcu_r7/emiosa16/fp16 pa6/gpio[6]/dcu_r6/emiosa15/fp17 pa5/gpio[5]/dcu_r5/emiosa17/fp18 pa4/gpio[4]/dcu_r4/emiosa18/fp19 pa3/gpio[3]/dcu_r3/emiosa19/fp20 pa2/gpio[2]/dcu_r2/emiosa20/fp21 pa1/gpio[1]/dcu_r1/emiosa21/fp22 pa0/gpio[0]/dcu_r0/emiosa22/sound/fp23 vss12 vdd12 pf15/gpio[85]/sck_2/fp24 pf14/gpio[84]/sout_2/cantx_1/fp25 pf13/gpio[83]/sin_2/canrx_1/fp26 pf12/gpio[82]/emiosb16/pcs2_2/fp27 pf11/gpio[81]/emiosb23/pcs1_2/fp28 pf10/gpio[80]/emiosa16/pcs0_2/fp29 pg12/gpio[98]/emiosa23/sound/emiosa8/fp30 vsse_a vdde_a pf9/gpio[79]/scl_1/pcs_b0/txd_1/fp31 pf8/gpio[78]/sda_1/pcs_b1/rxd_1/fp32 pf7/gpio[77]/scl_0/pcs2_1/fp33 pf6/gpio[76]/sda_0/fp34 vss12 vdd12 pf5/gpio[75]/emiosa9/dcu_tag/fp35 pf4/gpio[74]/emiosa10/pdi7/fp36 pf3/gpio[73]/emiosa11/pdi6/fp37 pf1/gpio[71]/emiosa12/pdi5/emiosa21/fp38 pf0/gpio[70]/emiosa13/pdi4/emiosa22/fp39 pb2/gpio[18]/txd_0 pb3/gpio[19]/rxd_0 vsse_e vdde_e pb11/gpio[27]/cantx_1/pdi3/emiosa16 pb10gpio[26]//canrx_1/pdi2/emiosa23 pb0/gpio[16]/cantx_0/pdi1 pb1/gpio[17]/canrx_0/pdi0 vss12 vdd12 pe7/gpio[69]/m5c1p/ssd5_3/emiosa8 pe6/gpio[68]/m5c1m/ssd5_2/emiosa9 pe5/gpio[67]/m5c0p/ssd5_1/emiosa10 pe4/gpio[66]/m5c0m/ssd5_0/emiosa11 vssmc vddmc pe3/gpio[65]/m4c1p/ssd4_3/emiosa12 pe2/gpio[64]/m4c1m/ssd4_2/emiosa13 pe1/gpio[63]/m4c0p/ssd4_1/emiosa14 pe0/gpio[62]/m4c0m/ssd4_0/emiosa15 pd15/gpio[61]/m3c1p/ssd3_3 pd14/gpio[60]/m3c1m/ssd3_2 pd13/gpio[59]/m3c0p/ssd3_1 pd12/gpio[58/m3c0m/ssd3_0 vssmb vddmb pd11/gpio[57]/m2c1p/ssd2_3 pd10/gpio[56]/m2c1m/ssd2_2 pd9/gpio[55]/m2c0p/ssd2_1 pd8/gpio[54]/m2c0m/ssd2_0 pd7/gpio[53]/m1c1p/ssd1_3/emiosb16 pd6/gpio[52]/m1c1m/ssd1_2/emiosb17 pd5/gpio[51]/m1c0p/ssd1_1/emiosb18 pd4/gpio[50]/m1c0m/ssd1_0/emiosb19 vssma vddma pd3/gpio[49]/m0c1p/ssd0_3/emiosb20 pd2/gpio[48]/m0c1m/ssd0_2/emiosb21 pd1/gpio[47]/m0c0p/ssd0_1/emiosb22 pd0/gpio[46]/m0c0m/ssd0_0/emiosb23 (see detail inset) pa10 (see detail inset) pa11 (see detail inset) pa12 (see detail inset) pa13 (see detail inset) pa14 (see detail inset) pa15 vdde_a vsse_a (see detail inset) pg0 fp6/sda_3/dcu_b1/gpio[87]/pg1 (see detail inset) pg2 (see detail inset) pg3 (see detail inset) pg4 fp2/emiosa8/dcu_b5/gpio[91]/pg5 fp1/dcu_b6/gpio[92]/pg6 fp0/dcu_b7/gpio[93]/pg7 bp0/dcu_vsync/gpio[94]/pg8 bp1/dcu_hsync/gpio[95]/pg9 bp2/dcu_de/gpio[96]/pg10 bp3/dcu_pclk/gpio[97]/pg11 vlcd/gpio[104]/ph5 vddr vssr reset vrc_ctrl vpp xtal vssosc extal vsspll vddpll vreg_bypass tdi/gpio[100]/ph1 tdo/gpio[101]/ph2 tms/gpio[102]/ph3 tck/gpio[99]/ph0 detail: fp13/emiosb20/dcu_g2/gpio[10]/pa10 ? fp12/emiosa13/dcu_g3/gpio[11]/pa11 ? fp11/emiosa12/dcu_g4/gpio[12]/pa12 ? fp10/emiosa11/dcu_g5/gpio[13]/pa13 ? fp9/emiosa10/dcu_g6/gpio[14]/pa14 ? fp8/emiosa9/dcu_g7/gpio[15]/pa15 ? fp7/sound/scl_3/dcu_b0/gpio[86]/pg0 ? fp5/emiosb19/dcu_b2/gpio[88]/pg2 ? fp4/emiosb21/dcu_b3/gpio[89]/pg3 ? fp3/emiosb17/dcu_b4/gpio[90]/pg4 ?
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 3-3 preliminary?subject to change without notice figure 3-2. lqfp 176-pin configuration (top view) 1 1. availability of port pin alternate functions depends on product selection 176-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pa9/gpio[9]/dcu_g1/emiosb18/sda_2/fp14 pa8/gpio[8]/dcu_g0/emiosb23/scl_2/fp15 pa7/gpio[7]/dcu_r7/emiosa16/fp16 pa6/gpio[6]/dcu_r6/emiosa15/fp17 pa5/gpio[5]/dcu_r5/emiosa17/fp18 vsse_a vdde_a pa4/gpio[4]/dcu_r4/emiosa18/fp19 pa3/gpio[3]/dcu_r3/emiosa19/fp20 pa2/gpio[2]/dcu_r2/emiosa20/fp21 pa1/gpio[1]/dcu_r1/emiosa21/fp22 pa0/gpio[0]/dcu_r0/emiosa22/sound/fp23 vss12 vdd12 pf15/gpio[85]/sck_2/fp24 pf14/gpio[84]/sout_2/cantx_1/fp25 pf13/gpio[83]/sin_2/canrx_1/fp26 pf12/gpio[82]/emiosb16/pcs2_2/fp27 pf11/gpio[81]/emiosb23/pcs1_2/fp28 pf10/gpio[80]/emiosa16/pcs0_2/fp29 pg12/gpio[98]/emiosa23/sound/emiosa8/fp30 vsse_a vdde_a pf9/gpio[79]/scl_1/pcs_b0/txd_1/fp31 pf8/gpio[78]/sda_1/pcs_b1/rxd_1/fp32 pf7/gpio[77]/scl_0/pcs2_1/fp33 pf6/gpio[76]/sda_0/fp34 vss12 vdd12 pf5/gpio[75]/emiosa9/dcu_tag/fp35 pf4/gpio[74]/emiosa10/pdi7/fp36 pf3/gpio[73]/emiosa11/pdi6/fp37 pf1/gpio[71]/emiosa12/pdi5/emiosa21/fp38 pf0/gpio[70]/emiosa13/pdi4/emiosa22/fp39 pk1/gpio[122]/pdi13/emiosa17 pk0/gpio[121]/pdi12/emiosa18/dcu_tag pb2/gpio[18]/txd_0 pb3/gpio[19]/rxd_0 pj15/gpio[120]/pdi11/emiosa19 pj14/gpio[119]/pdi10/emiosa20 pj13/gpio[118]/pdi9/emiosb20 pj12/gpio[117]/pdi8/emiosb17 vsse_e vdde_e nmi/gpio[72]/pf2 vdde_b vsse_b pcs2_0/emiosb19/rxd_1/gpio[28]/pb12 pcs1_0/emiosb18/txd_1/gpio[29]/pb13 vdd12 vss12 emiosa15/sda_1/gpio[131]/pk10 emiosa14/scl_1/gpio[132]/pk11 emiosb20/sck_0/gpio[25]/pb9 emiosb21/sout_0/gpio[24]/pb8 emiosb22/sin_0/gpio[23]/pb7 canrx_0/pdi0/gpio[109]/pj4 cantx_0/pdi1/gpio[110]/pj5 emiosa22/canrx_1/pdi2/gpio[111]/pj6 emiosa21/cantx_1/pdi3/gpio[112]/pj7 clkout/emiosb16/pcs0_0/gpio[103]/ph4 ma0/sck_1/gpio[20]/pb4 fabm/ma1/sout_1/gpio[21]/pb5 vdde_b vsse_b abs[0]/ma2/sin_1/gpio[22]/pb6 vdd12 vss12 vdda vssa xtal32/ans15/gpio[45]/pc15 extal32/ans14/gpio[44]/pc14 pcs0_1/ma2/ans13/gpio[43]/pc13 pcs1_1/ma1/ans12/gpio[42]/pc12 pcs2_1/ma0/ans11/gpio[41]/pc11 sound/ans10(mux)/gpio[40]/pc10 ans9/gpio[39]/pc9 ans8/gpio[38]/pc8 vdde_c vsse_c ans7/gpio[37]/pc7 ans6/gpio[36]/pc6 ans5/gpio[35]/pc5 ans4/gpio[34]/pc4 ans3/gpio[33]/pc3 ans2/gpio[32]/pc2 ans1/gpio[31]/pc1 ans0/gpio[30]/pc0 pb11/gpio[27]/cantx_1/pdi3/emiosa16 pb10/gpio[26]/canrx_1/pdi2/emiosa23 pb0/gpio[16]/cantx_0/pdi1 pb1/gpio[17]/canrx_0/pdi0 pj11/gpio[116]/pdi7 pj10/gpio[115]/pdi6 pj9/gpio[114]/pdi5 pj8/gpio[113]/pdi4 vss12 vdd12 pj3/gpio[108]/pdi_pclk pj2/gpio[107]/pdi_vsync pj1/gpio[106]/pdi_hsync pj0/gpio[105]/pdi_de pe7/gpio[69]/m5c1p/ssd5_3/emiosa8 pe6/gpio[68]/m5c1m/ssd5_2/emiosa9 pe5/gpio[67]/m5c0p/ssd5_1/emiosa10 pe4/gpio[66]/m5c0m/ssd5_0/emiosa11 vssmc vddmc pe3/gpio[65]/m4c1p/ssd4_3/emiosa12 pe2/gpio[64]/m4c1m/ssd4_2/emiosa13 pe1/gpio[63]/m4c0p/ssd4_1/emiosa14 pe0/gpio[62]/m4c0m/ssd4_0/emiosa15 pd15/gpio[61]/m3c1p/ssd3_3 pd14/gpio[60]/m3c1m/ssd3_2 pd13/gpio[59]/m3c0p/ssd3_1 pd12/gpio[58]/m3c0m/ssd3_0 vssmb vddmb pd11/gpio[57]/m2c1p/ssd2_3 pd10/gpio[56]/m2c1m/ssd2_2 pd9/gpio[55]/m2c0p/ssd2_1 pd8/gpio[54]/m2c0m/ssd2_0 pd7/gpio[53]/m1c1p/ssd1_3/emiosb16 pd6/gpio[52]/m1c1m/ssd1_2/emiosb17 pd5/gpio[51]/m1c0p/ssd1_1/emiosb18 pd4/gpio[50]/m1c0m/ssd1_0/emiosb19 vssma vddma pd3/gpio[49]/m0c1p/ssd0_3/emiosb20 pd2/gpio[48]/m0c1m/ssd0_2/emiosb21 pd1/gpio[47]/m0c0p/ssd0_1/emiosb22 pd0/gpio[46]/m0c0m/ssd0_0/emiosb23 (see detail inset) pa10 (see detail inset) pa11 (see detail inset) pa12 (see detail inset) pa13 (see detail inset) pa14 (see detail inset) pa15 vdde_a vsse_a (see detail inset) pg0 (see detail inset) pg1 (see detail inset) pg2 (see detail inset) pg3 (see detail inset) pg4 (see detail inset) pg5 fp1/dcu_b6/gpio[92]/pg6 fp0/dcu_b7/gpio[93]/pg7 (see detail inset) pg8 (see detail inset) pg9 bp2/dcu_de/gpio[96]/pg10 (see detail inset) pg11 vlcd/gpio[104]/ph5 vddr vssr reset vrc_ctrl vpp xtal vssosc extal vsspll vddpll vreg_bypass pdi10/mcko/gpio[123]/pk2 pdi11/mseo/gpio[124]/pk3 pdi12/evto/gpio[125]/pk4 tdi/gpio[100]/ph1 pdi13/evti/gpio[126]/pk5 pdi14/mdo0/gpio[127]/pk6 tdo/gpio[101]/ph2 pdi15/mdo1/gpio[128]/pk7 tms/gpio[102]/ph3 pdi16/mdo2/gpio[129]/pk8 tck/gpio[99]/ph0 pdi17/mdo3/gpio[130]/pk9 detail: fp13/emiosb20/dcu_g2/gpio[10]/pa10 ? fp12/emiosa13/dcu_g3/gpio[11]/pa11 ? fp11/emiosa12/dcu_g4/gpio[12]/pa12 ? fp10/emiosa11/dcu_g5/gpio[13]/pa13 ? fp9/emiosa10/dcu_g6/gpio[14]/pa14 ? fp8/emiosa9/dcu_g7/gpio[15]/pa15 ? fp7/sound/scl_3/dcu_b0/gpio[86]/pg0 ? fp6/sda_3/dcu_b1/gpio[87]/pg1 ? fp5/emiosb19/dcu_b2/gpio[88]/pg2 ? fp4/emiosb21/dcu_b3/gpio[89]/pg3 ? fp3/emiosb17/dcu_b4/gpio[90]/pg4 ? fp2/emiosa8/dcu_b5/gpio[91]/pg5 ? bp0/dcu_vsync/gpio[94]/pg8 ? bp1/dcu_hsync/gpio[95]/pg9 ? bp3/dcu_pclk/gpio[97]/pg11 ?
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-4 figure 3-3. 208 mapbga configuration 1 2 1 2 3 4 5 6 7 8 9 1011121314 1516 a pa0 pj0 pj1 pj3 pj5 pj7 pj14 pf0 pf5 pk9 pk5 nc nc pf10 pf11 pf12 b pa1 vdde_a pj2 pj4 pj6 pj8 pj15 pf1 pf6 nc pk6 pk2 nc nc vdde_e pf13 c pa2 pa3 vdde_a pj9 pj10 pj12 pk0 pf3 pf7 nc pk7 pk3 nc vdde_e nc pf14 d pa4 pa5 pg0 vdd12 pj11 pj13 pk1 pf4 vdd12 pg12 pk8 pk4 vdd12 nc nc pf15 e pa 6 pa 7 p g 1 p g 2 nc nc nc nc f pa 8 pa 9 p g 3 p g 4 nc nc nc nc g pa10 pa11 pg5 pg6 vss vss vss vss nc pe7 pe1 nc h pa12 pa13 pa15 pg7 vss vss vss vss pe5 pe6 vddmc vssmc j reset pa14 pg8 pg10 vss vss vss vss pe4 pe2 pe0 pd8 k extal vdde_a pg9 pg11 vss vss vss vss pe3 pd13 pd9 pd7 l vsspll vddpll nmi/pf2 mdo3 pd15 pd12 vddmb vssmb m xtal vpp ph3 vreg bypass pd14 pd11 pd5 pd6 n vddr vlcd ph2 vdd12 pk11 pk10 pb8 pb5 pc13 pc9 pc6 pb11 vddma pd10 pd4 pd3 p vrc_ ctrl ph1 vdde_b mdo2 mdo1 pb13 pb7 pb4 pc12 pc8 pc5 pc3 pb10 nc pd2 pd1 r ph0 vdde_b evto pf9 ph4 pb12 pb6 pc15 pc11 pc7 pc4 pc2 pb3 pb2 vdde_b pd0 t mcko mseo evti pf8 mdo0 pb9 vdde_c pc14 pc10 vssa vdda pc1 pc0 pb1 pb0 vssma 1. nc = not connected 2. 208 mapbga available only as development package for nexus2+
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 3-5 preliminary?subject to change without notice 3.3 pad configuration during reset phases all pads have a fixed c onfiguration under reset. during the power-up phase, all pa ds are forced to tristate. after power-up phase, all pads are fl oating with the following exceptions: ? pb[5] (fab) is pull-down. without external str ong pull-up the device starts fetching from flash. ? reset pad is driven low. this is re leased only after phase2 reset completion. ? main oscillator pads (extal, xtal) are tristate. ? nexus output pads (mdo[n], mcko, evto, mseo) are forced to output. ? the following pads are pull-up: ?pb[6] ?ph[0] ?ph[1] ?ph[3] ?evti 3.4 voltage supply pins voltage supply pins are used to provide power to the device. two dedicated pins are used for 1.2 v regulator stabilization. there is a preferred power-up sequen ce for devices in the pxd10 family . that sequence is described in the following paragraphs. broadly, the supply voltages can be grouped as follows: ? vreg hv supply (v ddr ) ? generic io supply or noise free supply ?v dda ?v dde_a ?v dde_b ?v dde_c ?v dde_e ?v ddma ?v ddmb ?v ddmc ?v ddpll ? lv supply (v dd12 ) the preferred order of ramp up is as follows: 1. generic io supply or noise free supply
pxd10 microcontroller reference manual, rev. 1 3-6 freescale semiconductor preliminary?subject to change without notice 2. vreg hv supply (v ddr - should be the last hv supply to ramp up. it is also ok if all hv supplies including v ddr ramp up together) 3. lv supply the reason for following this sequence is to ensure that when vreg releases its lvds, the i/o and other hv segments are powered properly. this is importa nt because the pxd10 does not monitor lvds on i/o hv supplies. 3.5 pad types the pads available for system pins a nd functional port pins are described in: table 3-1. voltage supply pin descriptions supply pin function pin number 144 lqfp 176 lqfp vdd12 1 1 decoupling capacitors must be connected between these pins and the nearest v ss12 pin. 1.2 v core supply 42, 51, 103, 118 , 133 50, 67, 123, 148, 163 vdda 3.3 v/5 v adc supply source 53 69 vdde_a 3.3 v/5 v i/o supp ly 7, 124 7, 154, 170 vdde_b 3.3 v/5 v i/o supply 38 46, 64 vdde_c 3.3 v/5 v i/o supply 63 79 vdde_e 3.3 v/5 v i/o supply 109 133 vddma 2 2 all stepper motor supplies need to be at same level (3.3 v or 5 v). motor pads 5 v supply 77 93 vddmb 2 motor pads 5 v supply 87 103 vddmc 2 motor pads 5 v supply 97 113 vddpll 1.2 v pll supply 31 31 vddr vreg reg supply 22 22 vpp 3 3 this signal needs to be connected to ground during normal operation. 9 v - 12 v flash test analog write signal 26 26 vss digital ground 8, 23, 39, 43, 52, 64, 104, 110, 119, 125, 134 8, 23, 47, 51, 68, 80, 124, 134, 149, 155, 164, 65, 171 vssa adc ground 54 70 vssma stepper motor ground 78 94 vssmb stepper motor ground 88 104 vssmc stepper motor ground 98 114 vssosc mhz oscillator ground 28 28 vsspll pll ground 30 30
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 3-7 preliminary?subject to change without notice ? the port pin summary table ? the pad type descriptions ? the description of the pad conf iguration registers in the siul chapter of the device reference manual ? the device data sheet 3.6 system pins the system pins are listed in table 3-2 . 3.7 debug pins the debug pins are listed in table 3-3 . table 3-2. system pin descriptions system pin function i/o direction pad type reset config pin no. 144 lqfp 176 lqfp 208 mapb ga reset bidirectional reset with schmitt-trigger characteristics and noise filter. i/o m input, weak pull up 24 24 j1 extal analog output of the oscillator amplifier circuit. input for the clock generator in bypass mode. x ? 29 29 k1 xtal analog input of the oscillator amplifier circuit. needs to be grounded if oscillator bypass mode is used. ix ? 27 27 m1 vrc_ctrl vreg ballast control gain 25 25 p1 vreg_ bypass 1 1 vreg_bypass should be pulled down externally. pin used for factory testing i x ? 32 32 m1 table 3-3. debug pin descriptions debug pin function pad type i/o direction reset config pin number 144 lqfp 176 lqfp 1 208 map bga evti nexus event input m i/o input, pull up ? 37 t3 evto nexus event output m i/o input, pull up ? 35 r3 mcko nexus message clock output f i/o input, pull up ? 33 t1
pxd10 microcontroller reference manual, rev. 1 3-8 freescale semiconductor preliminary?subject to change without notice mdo0 nexus message clock output m i/o input, pull up ? 38 t5 mdo1 nexus message clock output m i/o input, pull up ? 40 p5 mdo2 nexus message clock output m i/o input, pull up ? 42 p4 mdo3 nexus message clock output m i/o input, pull up ? 44 l4 mseo nexus message clock output m i/o input, pull up ? 34 t2 1 on the 176-pin package, the debug pins are multiplexed with other pins. the multiplexing is described in the port pin summary table. table 3-3. debug pin descriptions (continued) debug pin function pad type i/o direction reset config pin number 144 lqfp 176 lqfp 1 208 map bga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-9 3.8 functional ports the functional port pins are listed in table 3-4 . table 3-4. port pin summary port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga pa[0] pcr[0] option 0 option 1 option 2 option 3 gpio[0] dcu_r0 emiosa[22] sound fp23 siul dcu pwm/timer sound i/o m1 none, none 135 165 a1 pa[1] pcr[1] option 0 option 1 option 2 option 3 gpio[1] dcu_r1 emiosa[21] ? fp22 siul dcu pwm/timer ? i/o m1 none, none 136 166 b1 pa[2] pcr[2] option 0 option 1 option 2 option 3 gpio[2] dcu_r2 emiosa[20] ? fp21 siul dcu pwm/timer ? i/o m1 none, none 137 167 c1 pa[3] pcr[3] option 0 option 1 option 2 option 3 gpio[3] dcu_r3 emiosa[19] ? fp20 siul dcu pwm/timer ? i/o m1 none, none 138 168 c2 pa[4] pcr[4] option 0 option 1 option 2 option 3 gpio[4] dcu_r4 emiosa[18] ? fp19 siul dcu pwm/timer ? i/o m1 none, none 139 169 d1 pa[5] pcr[5] option 0 option 1 option 2 option 3 gpio[5] dcu_r5 emiosa[17] ? fp18 siul dcu pwm/timer ? i/o m1 none, none 140 172 d2 pa[6] pcr[6] option 0 option 1 option 2 option 3 gpio[6] dcu_r6 emiosa[15] ? fp17 siul dcu pwm/timer ? i/o m1 none, none 141 173 e1
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-10 pa[7] pcr[7] option 0 option 1 option 2 option 3 gpio[7] dcu_r7 emiosa[16] ? fp16 siul dcu pwm/timer ? i/o m1 none, none 142 174 e2 pa[8] pcr[8] option 0 option 1 option 2 option 3 gpio[8] dcu_g0 emiosb[23] scl_2 fp15 siul dcu pwm/timer i 2 c_2 i/o m1 none, none 143 175 f1 pa[9] pcr[9] option 0 option 1 option 2 option 3 gpio[9] dcu_g1 emiosb[18] sda_2 fp14 siul dcu pwm/timer i 2 c_2 i/o m1 none, none 144 176 f2 pa[10] pcr[10] option 0 option 1 option 2 option 3 gpio[10] dcu_g2 emiosb[20] ? fp13 siul dcu pwm/timer ? i/o m1 none, none 11g1 pa[11] pcr[11] option 0 option 1 option 2 option 3 gpio[11] dcu_g3 emiosa[13] ? fp12 siul dcu pwm/timer ? i/o m1 none, none 22g2 pa[12] pcr[12] option 0 option 1 option 2 option 3 gpio[12] dcu_g4 emiosa[12] ? fp11 siul dcu pwm/timer ? i/o m1 none, none 33h1 pa[13] pcr[13] option 0 option 1 option 2 option 3 gpio[13] dcu_g5 emiosa[11] ? fp10 siul dcu pwm/timer ? i/o m1 none, none 44h2 pa[14] pcr[14] option 0 option 1 option 2 option 3 gpio[14] dcu_g6 emiosa[10] ? fp9 siul dcu pwm/timer ? i/o m2 none, none 55j2 table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-11 pa[15] pcr[15] option 0 option 1 option 2 option 3 gpio[15] dcu_g7 emiosa[9] ? fp8 siul dcu pwm/timer ? i/o m1 none, none 66h3 pb[0] pcr[16] option 0 option 1 option 2 option 3 gpio[16] cantx_0 pdi1 ? ?siul flexcan_0 pdi ? i/o m1 none, none 106 130 t15 pb[1] pcr[17] option 0 option 1 option 2 option3 gpio[17] canrx_0 pdi0 ? ?siul flexcan_0 pdi ? i/o s none, none 105 129 t14 pb[2] pcr[18] option 0 option 1 option 2 option3 gpio[18] txd_0 ? ? ?siul linflex_0 ? ? i/o s none, none 112 140 r14 pb[3] pcr[19] option 0 option 1 option 2 option3 gpio[19] rxd_0 ? ? ?siul linflex_0 ? ? i/o s none, none 111 139 r13 pb[4] pcr[20] option 0 option 1 option 2 option 3 gpio[20] sck_1 ma0 ? ?siul dspi_1 adc ? i/o m1 none, none 48 62 p8 pb[5] pcr[21] option 0 option 1 option 2 option 3 gpio[21] sout_1 ma1 fabm ?siul dspi_1 adc control i/o m1 input, pull-do wn 49 63 n8 pb[6] pcr[22] option 0 option 1 option 2 option 3 gpio[22] sin_1 ma2 abs[0] ?siul dspi_1 adc control i/o s input, pull-up 50 66 r7 table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-12 pb[7] pcr[23] option 0 option 1 option 2 option 3 gpio[23] sin_0 emiosb[22] ? ?siul dspi_0 pwm/timer ? i/o s none, none 46 56 p7 pb[8] pcr[24] option 0 option 1 option 2 option 3 gpio[24] sout_0 emiosb[21] ? ?siul dspi_0 pwm/timer ? i/o m1 none, none 45 55 n7 pb[9] pcr[25] option 0 option 1 option 2 option 3 gpio[25] sck_0 emiosb[20] ? ?siul dspi_0 pwm/timer ? i/o m1 none, none 44 54 t6 pb[10] pcr[26] option 0 option 1 option 2 option 3 gpio[26] canrx_1 pdi2 emiosa[23] ?siul flexcan_1 pdi pwm/timer i/o s none, none 107 131 p13 pb[11] pcr[27] option 0 option 1 option 2 option 3 gpio[27] cantx_1 pdi3 emiosa[16] ?siul flexcan_1 pdi pwm/timer i/o m1 none, none 108 132 n12 pb[12] pcr[28] option 0 option 1 option 2 option 3 gpio[28] rxd_1 emiosb[19] pcs2_0 ?siul linflex_1 pwm/timer dspi_0 i/o s none, none 40 48 r6 pb[13] pcr[29] option 0 option 1 option 2 option 3 gpio[29] txd_1 emiosb[18] pcs1_0 ?siul linflex_1 pwm/timer dspi_0 i/o s none, none 41 49 p6 pb[14] ? ? reserved ? ? ? ? ? ? ? ? pb[15] ? ? reserved ? ? ? ? ? ? ? ? table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-13 pc[0] pcr[30] option 0 option 1 option 2 option 3 gpio[30] ? ? ? ans[0] siul ? ? ? i/o j none, none 72 88 t13 pc[1] pcr[31] option 0 option 1 option 2 option 3 gpio[31] ? ? ? ans[1] siul ? ? ? i/o j none, none 71 87 t12 pc[2] pcr[32] option 0 option 1 option 2 option 3 gpio[32] ? ? ? ans[2] siul ? ? ? i/o j none, none 70 86 r12 pc[3] pcr[33] option 0 option 1 option 2 option 3 gpio[33] ? ? ? ans[3] siul ? ? ? i/o j none, none 69 85 p12 pc[4] pcr[34] option 0 option 1 option 2 option 3 gpio[34] ? ? ? ans[4] siul ? ? ? i/o j none, none 68 84 r11 pc[5] pcr[35] option 0 option 1 option 2 option 3 gpio[35] ? ? ? ans[5] siul ? ? ? i/o j none, none 67 83 p11 pc[6] pcr[36] option 0 option 1 option 2 option 3 gpio[36] ? ? ? ans[6] siul ? ? ? i/o j none, none 66 82 n11 pc[7] pcr[37] option 0 option 1 option 2 option 3 gpio[37] ? ? ? ans[7] siul ? ? ? i/o j none, none 65 81 r10 table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-14 pc[8] pcr[38] option 0 option 1 option 2 option 3 gpio[38] ? ? ? ans[8] siul ? ? ? i/o j none, none 62 78 p10 pc[9] pcr[39] option 0 option 1 option 2 option 3 gpio[39] ? ? ? ans[9] siul ? ? ? i/o j none, none 61 77 n10 pc[10] pcr[40] option 0 option 1 option 2 option 3 gpio[40] ? sound ? ans[10] siul ? sgl ? i/o j none, none 60 76 t9 pc[11] pcr[41] option 0 option 1 option 2 option 3 gpio[41] ? ma0 pcs2_1 ans[11] siul ? adc dspi_1 i/o j none, none 59 75 r9 pc[12] pcr[42] option 0 option 1 option 2 option 3 gpio[42] ? ma1 pcs1_1 ans[12] siul ? adc dspi_1 i/o j none, none 58 74 p9 pc[13] pcr[43] option 0 option 1 option 2 option 3 gpio[43] ? ma2 pcs0_1 ans[13] siul ? adc dspi_1 i/o j none, none 57 73 n9 pc[14] pcr[44] option 0 option 1 option 2 option 3 gpio[44] ? ? ? ans[14] extal32 siul ? ? ? i/o j none, none 56 72 t8 pc[15] pcr[45] option 0 option 1 option 2 option 3 gpio[45] ? ? ? ans[15] xtal32 siul ? ? ? i/o j none, none 55 71 r8 table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-15 pd[0] pcr[46] option 0 option 1 option 2 option 3 gpio[46] m0c0m ssd0_0 emiosb[23] ?siul smc ssd pwm/timer i/o smd none, none 73 89 r16 pd[1] pcr[47] option 0 option 1 option 2 option 3 gpio[47] m0c0p ssd0_1 emiosb[22] ?siul smc ssd pwm/timer i/o smd none, none 74 90 p16 pd[2] pcr[48] option 0 option 1 option 2 option 3 gpio[48] m0c1m ssd0_2 emiosb[21] ?siul smc ssd pwm/timer i/o smd none, none 75 91 p15 pd[3] pcr[49] option 0 option 1 option 2 option 3 gpio[49] m0c1p ssd0_3 emiosb[20] ?siul smc ssd pwm/timer i/o smd none, none 76 92 n16 pd[4] pcr[50] option 0 option 1 option 2 option 3 gpio[50] m1c0m ssd1_0 emiosb[19] ?siul smc ssd pwm/timer i/o smd none, none 79 95 n15 pd[5] pcr[51] option 0 option 1 option 2 option 3 gpio[51] m1c0p ssd1_1 emiosb[18] ?siul smc ssd pwm/timer i/o smd none, none 80 96 m15 pd[6] pcr[52] option 0 option 1 option 2 option 3 gpio[52] m1c1m ssd1_2 emiosb[17] ?siul smc ssd pwm/timer i/o smd none, none 81 97 m16 pd[7] pcr[53] option 0 option 1 option 2 option 3 gpio[53] m1c1p ssd1_3 emiosb[16] ?siul smc ssd pwm/timer i/o smd none, none 82 98 k16 table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-16 pd[8] pcr[54] option 0 option 1 option 2 option 3 gpio[54] m2c0m ssd2_0 ? ?siul smc ssd ? i/o smd none, none 83 99 j16 pd[9] pcr[55] option 0 option 1 option 2 option 3 gpio[55] m2c0p ssd2_1 ? ?siul smc ssd ? i/o smd none, none 84 100 k15 pd[10] pcr[56] option 0 option 1 option 2 option 3 gpio[56] m2c1m ssd2_2 ? ?siul smc ssd ? i/o smd none, none 85 101 n14 pd[11] pcr[57] option 0 option 1 option 2 option 3 gpio[57] m2c1p ssd2_3 ? ?siul smc ssd ? i/o smd none, none 86 102 m14 pd[12] pcr[58] option 0 option 1 option 2 option 3 gpio[58] m3c0m ssd3_0 ? ?siul smc ssd ? i/o smd none, none 89 105 l14 pd[13] pcr[59] option 0 option 1 option 2 option 3 gpio[59] m3c0p ssd3_1 ? ?siul smc ssd ? i/o smd none, none 90 106 k14 pd[14] pcr[60] option 0 option 1 option 2 option 3 gpio[60] m3c1m ssd3_2 ? ?siul smc ssd ? i/o smd none, none 91 107 m13 pd[15] pcr[61] option 0 option 1 option 2 option 3 gpio[61] m3c1p ssd3_3 ? ?siul smc ssd ? i/o smd none, none 92 108 l13 table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-17 pe[0] pcr[62] option 0 option 1 option 2 option 3 gpio[62] m4c0m ssd4_0 emiosa[15] ?siul smc ssd pwm/timer i/o smd none, none 93 109 j15 pe[1] pcr[63] option 0 option 1 option 2 option 3 gpio[63] m4c0p ssd4_1 emiosa[14] ?siul smc ssd pwm/timer i/o smd none, none 94 110 g15 pe[2] pcr[64] option 0 option 1 option 2 option 3 gpio[64] m4c1m ssd4_2 emiosa[13] ?siul smc ssd pwm/timer i/o smd none, none 95 111 j14 pe[3] pcr[65] option 0 option 1 option 2 option 3 gpio[65] m4c1p ssd4_3 emiosa[12] ?siul smc ssd pwm/timer i/o smd none, none 96 112 k13 pe[4] pcr[66] option 0 option 1 option 2 option 3 gpio[66] m5c0m ssd5_0 emiosa[11] ?siul smc ssd pwm/timer i/o smd none, none 99 115 j13 pe[5] pcr[67] option 0 option 1 option 2 option 3 gpio[67] m5c0p ssd5_1 emiosa[10] ?siul smc ssd pwm/timer i/o smd none, none 100 116 h13 pe[6] pcr[68] option 0 option 1 option 2 option 3 gpio[68] m5c1m ssd5_2 emiosa[9] ?siul smc ssd pwm/timer i/o smd none, none 101 117 h14 pe[7] pcr[69] option 0 option 1 option 2 option 3 gpio[69] m5c1p ssd5_3 emiosa[8] ?siul smc ssd pwm/timer i/o smd none, none 102 118 g14 pe[8] ? ? reserved ? ? ? ? ? ? ? ? table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-18 pe[9] ? ? reserved ? ? ? ? ? ? ? ? pe[10] ? ? reserved ? ? ? ? ? ? ? ? pe[11] ? ? reserved ? ? ? ? ? ? ? ? pe[12] ? ? reserved ? ? ? ? ? ? ? ? pe[13] ? ? reserved ? ? ? ? ? ? ? ? pe[14] ? ? reserved ? ? ? ? ? ? ? ? pe[15] ? ? reserved ? ? ? ? ? ? ? ? pf[0] pcr[70] option 0 option 1 option 2 option 3 gpio[70] emiosa[13] pdi4 emiosa[22] fp39 siul pwm/timer pdi pwm/timer i/o s none, none 113 143 a8 pf[1] pcr[71] option 0 option 1 option 2 option 3 gpio[71] emiosa[12] pdi5 emiosa[21] fp38 siul pwm/timer pdi pwm/timer i/o s none, none 114 144 b8 pf[2] pcr[72] option 0 option 1 option 2 option 3 gpio[72] nmi ? ? ?siul nmi ? ? i/o s none, none 37 45 l3 pf[3] pcr[73] option 0 option 1 option 2 option 3 gpio[73] emiosa[11] pdi6 ? fp37 siul pwm/timer pdi ? i/o m1 none, none 115 145 c8 pf[4] pcr[74] option 0 option 1 option 2 option 3 gpio[74] emiosa[10] pdi7 ? fp36 siul pwm/timer pdi ? i/o m1 none, none 116 146 d8 pf[5] pcr[75] option 0 option 1 option 2 option 3 gpio[75] emiosa[9] dcu_tag ? fp35 siul pwm/timer dcu ? i/o m1 none, none 117 147 a9 table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-19 pf[6] pcr[76] option 0 option 1 option 2 option 3 gpio[76] sda_0 ? ? fp34 siul i 2 c_0 ? ? i/o s none, none 120 150 b9 pf[7] pcr[77] option 0 option 1 option 2 option 3 gpio[77] scl_0 pcs2_1 ? fp33 siul i 2 c_0 dspi_1 ? i/o s none, none 121 151 c9 pf[8] pcr[78] option 0 option 1 option 2 option 3 gpio[78] sda_1 pcs1_1 rxd_1 fp32 siul i 2 c_1 dspi_1 linflex_1 i/o s none, none 122 152 t4 pf[9] pcr[79] option 0 option 1 option 2 option 3 gpio[79] scl_1 pcs0_1 txd_1 fp31 siul i 2 c_1 dspi_1 linflex_1 i/o s none, none 123 153 r4 pf[10] pcr[80] option 0 option 1 option 2 option 3 gpio[80] emiosa[16] pcs0_2 ? fp29 siul pwm/timer quadspi ? i/o m1 none, none 127 157 a14 pf[11] pcr[81] option 0 option 1 option 2 option 3 gpio[81] emiosb[23] io2/pcs1_2 6 ? fp28 siul pwm/timer quadspi ? i/o m1 none, none 128 158 a15 pf[12] pcr[82] option 0 option 1 option 2 option 3 gpio[82] emiosb[16] io3/pcs2_2 6 ? fp27 siul pwm/timer quadspi ? i/o m1 none, none 129 159 a16 pf[13] pcr[83] option 0 option 1 option 2 option 3 gpio[83] io0/sin_2 6 canrx_1 ? fp26 siul quadspi flexcan_1 ? i/o m1 none, none 130 160 b16 table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-20 pf[14] pcr[84] option 0 option 1 option 2 option 3 gpio[84] io1/sout_2 6 cantx_1 ? fp25 siul quadspi flexcan_1 ? i/o m1 none, none 131 161 c16 pf[15] pcr[85] option 0 option 1 option 2 option 3 gpio[85] sck_2 ? ? fp24 siul quadspi ? ? i/o f none, none 132 162 d16 pg[0] pcr[86] option 0 option 1 option 2 option 3 gpio[86] dcu_b0 scl_3 sound fp7 siul dcu i 2 c_3 sgl i/o m2 none, none 99d3 pg[1] pcr[87] option 0 option 1 option 2 option 3 gpio[87] dcu_b1 sda_3 ? fp6 siul dcu i 2 c_3 ? i/o m1 none, none 10 10 e3 pg[2] pcr[88] option 0 option 1 option 2 option 3 gpio[88] dcu_b2 emiosb[19] ? fp5 siul dcu pwm/timer ? i/o m2 none, none 11 11 e4 pg[3] pcr[89] option 0 option 1 option 2 option 3 gpio[89] dcu_b3 emiosb[21] ? fp4 siul dcu pwm/timer ? i/o m1 none, none 12 12 f3 pg[4] pcr[90] option 0 option 1 option 2 option 3 gpio[90] dcu_b4 emiosb[17] ? fp3 siul dcu pwm/timer ? i/o m2 none, none 13 13 f4 pg[5] pcr[91] option 0 option 1 option 2 option 3 gpio[91] dcu_b5 emiosa[8] ? fp2 siul dcu pwm/timer ? i/o m1 none, none 14 14 g3 table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-21 pg[6] pcr[92] option 0 option 1 option 2 option 3 gpio[92] dcu_b6 ? ? fp1 siul dcu ? ? i/o m2 none, none 15 15 g4 pg[7] pcr[93] option 0 option 1 option 2 option 3 gpio[93] dcu_b7 ? ? fp0 siul dcu ? ? i/o m1 none, none 16 16 h4 pg[8] pcr[94] option 0 option 1 option 2 option 3 gpio[94] dcu_vsync ? ? bp0 siul dcu ? ? i/o m2 input, none 17 17 j3 pg[9] pcr[95] option 0 option 1 option 2 option 3 gpio[95] dcu_hsync ? ? bp1 siul dcu ? ? i/o m1 input, none 18 18 k3 pg[10] pcr[96] option 0 option 1 option 2 option 3 gpio[96] dcu_de ? ? bp2 siul dcu ? ? i/o m2 none, none 19 19 j4 pg[11] pcr[97] option 0 option 1 option 2 option 3 gpio[97] dcu_pclk ? ? bp3 siul dcu ? ? i/o m1 none, none 20 20 k4 pg[12] pcr[98] option 0 option 1 option 2 option 3 gpio[98] emiosa[23] sound emiosa[8] fp30 siul pwm/timer sgl pwm/timer i/o s none, none 126 156 d10 pg[13]??reserved ???????? pg[14]??reserved ???????? pg[15]??reserved ???????? table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-22 ph[0] 7 pcr[99] option 0 option 1 option 2 option 3 gpio[99] tck ? ? ?siul jtag ? ? i/o s input, pull-up 36 43 r1 ph[1] 7 pcr[100 ] option 0 option 1 option 2 option 3 gpio[100] tdi ? ? ?siul jtag ? ? i/o s input, pull-up 33 36 p2 ph[2] 7 pcr[101 ] option 0 option 1 option 2 option 3 gpio[101] tdo ? ? ?siul jtag ? ? i/o m1 output, none 34 39 n3 ph[3] 7 pcr[102 ] option 0 option 1 option 2 option 3 gpio[102] tms ? ? ?siul jtag ? ? i/o s input, pull-up 35 41 m3 ph[4] pcr[103 ] option 0 option 1 option 2 option 3 gpio[103] pcs0_0 emiosb[16] clkout ?siul dspi_0 pwm/timer control i/o f none, none 47 61 r5 ph[5] pcr[104 ] option 0 option 1 option 2 option 3 gpio[104] vlcd 8 ? ? ?siul lcd ? ? i/o s none, none 21 21 n2 ph[6]??reserved ???????? ph[7]??reserved ???????? ph[8]??reserved ???????? ph[9]??reserved ???????? ph[10] ? ? reserved ? ? ? ? ? ? ? ? ph[11] ? ? reserved ? ? ? ? ? ? ? ? ph[12] ? ? reserved ? ? ? ? ? ? ? ? table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-23 ph[13] ? ? reserved ? ? ? ? ? ? ? ? ph[14] ? ? reserved ? ? ? ? ? ? ? ? ph[15] ? ? reserved ? ? ? ? ? ? ? ? pj[0] pcr[105 ] option 0 option 1 option 2 option 3 gpio[105] pdi_de ? ? ?siul pdi ? ? i/o s none, none ?119a2 pj[1] pcr[106 ] option 0 option 1 option 2 option 3 gpio[106] pdi_hsync ? ? ?siul pdi ? ? i/o s none, none ?120a3 pj[2] pcr[107 ] option 0 option 1 option 2 option 3 gpio[107] pdi_vsync ? ? ?siul pdi ? ? i/o s none, none ?121b3 pj[3] pcr[108 ] option 0 option 1 option 2 option 3 gpio[108] pdi_pclk ? ? ?siul pdi ? ? i/o m1 none, none ?122a4 pj[4] pcr[109 ] option 0 option 1 option 2 option 3 gpio[109] pdi[0] canrx_0 ? ?siul pdi flexcan_0 ? i/o s none, none ?57b4 pj[5] pcr[110 ] option 0 option 1 option 2 option 3 gpio[110] pdi[1] cantx_0 ? ?siul pdi flexcan_0 ? i/o m1 none, none ?58a5 pj[6] pcr[111 ] option 0 option 1 option 2 option 3 gpio[111] pdi[2] canrx_1 emiosa[22] ?siul pdi flexcan_1 pwm/timer i/o s none, none ?59b5 table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-24 pj[7] pcr[112 ] option 0 option 1 option 2 option 3 gpio[112] pdi[3] cantx_1 emiosa[21] ?siul pdi flexcan_1 pwm/timer i/o m1 none, none ?60a6 pj[8] pcr[113 ] option 0 option 1 option 2 option 3 gpio[113] pdi[4] ? ? ?siul pdi ? ? i/o s none, none ?125b6 pj[9] pcr[114 ] option 0 option 1 option 2 option 3 gpio[114] pdi[5] ? ? ?siul pdi ? ? i/o s none, none ?126c4 pj[10] pcr[115 ] option 0 option 1 option 2 option 3 gpio[115] pdi[6] ? ? ?siul pdi ? ? i/o s none, none ?127c5 pj[11] pcr[116 ] option 0 option 1 option 2 option 3 gpio[116] pdi[7] ? ? ?siul pdi ? ? i/o s none, none ?128d5 pj[12] pcr[117 ] option 0 option 1 option 2 option 3 gpio[117] pdi[8] emiosb[17] ? ?siul pdi pwm/timer ? i/o m1 none, none ?135c6 pj[13] pcr[118 ] option 0 option 1 option 2 option 3 gpio[118] pdi[9] emiosb[20] ? ?siul pdi pwm/timer ? i/o m1 none, none ?136d6 pj[14] pcr[119 ] option 0 option 1 option 2 option 3 gpio[119] pdi[10] emiosa[20] ? ?siul pdi pwm/timer ? i/o m1 none, none ?137a7 table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-25 pj[15] pcr[120 ] option 0 option 1 option 2 option 3 gpio[120] pdi[11] emiosa[19] ? ?siul pdi pwm/timer ? i/o m1 none, none ?138b7 pk[0] pcr[121 ] option 0 option 1 option 2 option 3 gpio[121] pdi[12] emiosa[18] dcu_tag ?siul pdi pwm/timer dcu i/o m1 none, none ?141c7 pk[1] pcr[122 ] option 0 option 1 option 2 option 3 gpio[122] pdi[13] emiosa[17] ? ?siul pdi pwm/timer ? i/o m1 none, none ?142d7 pk[2] pcr[123 ] option 0 option 1 option 2 option 3 gpio[123] mcko pdi[10] ? ?siul nexus pdi ? i/o f none, none ?33b12 pk[3] pcr[124 ] option 0 option 1 option 2 option 3 gpio[124] mseo pdi[11] ? ?siul nexus pdi ? i/o m1 none, none ?34c12 pk[4] pcr[125 ] option 0 option 1 option 2 option 3 gpio[125] evto pdi[12] ? ?siul nexus pdi ? i/o m1 none, none ?35d12 pk[5] pcr[126 ] option 0 option 1 option 2 option 3 gpio[126] evti pdi[13] ? ?siul nexus pdi ? i/o m1 none, none ?37a11 pk[6] pcr[127 ] option 0 option 1 option 2 option 3 gpio[127] mdo0 pdi[14] ? ?siul nexus pdi ? i/o m1 none, none ?38b11 table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-26 pk[7] pcr[128 ] option 0 option 1 option 2 option 3 gpio[128] mdo1 pdi[15] ? ?siul nexus pdi ? i/o m1 none, none ?40c11 pk[8] pcr[129 ] option 0 option 1 option 2 option 3 gpio[129] mdo2 pdi[16] ? ?siul nexus pdi ? i/o m1 none, none ?42d11 pk[9] pcr[130 ] option 0 option 1 option 2 option 3 gpio[130] mdo3 pdi[17] ? ?siul nexus pdi ? i/o m1 none, none ?44a10 pk[10] pcr[131 ] option 0 option 1 option 2 option 3 gpio[131] sda_1 emiosa[15] ? ?siul i 2 c_1 pwm/timer ? i/o s none, none ?52n6 pk[11] pcr[132 ] option 0 option 1 option 2 option 3 gpio[132] scl_1 emiosa[14] ? ?siul i 2 c_1 pwm/timer ? i/o s none, none ?53n5 pk[12] ? ? reserved ? ? ? ? ? ? ? ? pk[13] ? ? reserved ? ? ? ? ? ? ? ? pk[14] ? ? reserved ? ? ? ? ? ? ? ? pk[15] ? ? reserved ? ? ? ? ? ? ? ? 1 alternate functions are chosen by setting the values of the pcr[n ].pa bitfields inside the siul module. pcr[n].pa = 00 -> optio n 0; pcr[n].pa = 01 -> option 1; pcr[n].pa = 10 -> option 2; pcr[n].pa = 11-> option 3. this is intended to select t he output functions; to use one of the input functions, the pcr[n].ibe bit must be written to ?1?, regardless of the values selected in the pcr[n].pa bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2 special functions are enabled independently from the standard digi tal pin functions. enabling standard i/o functions in the pcr registers may interfere with their functionality. adc functions are enabled using the p cr[apc] bit; other functions are enabled by enabling the respect ive module. 3 using the psmi registers in the sy stem integration unit lite (siul), different pads can be multiplexed to the same peripheral i nput. please see the siul chapter of the pxd10 reference manual for details. table 3-4. port pin summary (continued) port pin pcr register alternate function 1 function special function 2 peripheral 3 i/o directio n pad type 4 reset config. 5 pin number 144 lqfp 176 lqfp 208 mapb ga
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 3-27 3.9 signal details 4 see ta b l e 3 - 5 . 5 reset configuration is given as i/o di rection and pull, e.g., ?input, pullup?. 6 this option on this pin has alternate functions that depend on whet her the quadspi is in spi mode or in serial flash mode (sfm) . 7 out of reset pins ph[0:3] are available as jtag pins (tck, tdi, tdo and tms respectively). it is up to the user to configure pi ns ph[0:3] when needed. 8 this pin can be used for lcd supply pin vlcd. refer to the voltage supply pin descriptions in the pxd10 data sheet for details. table 3-5. pad type descriptions abbreviation 1 1 the pad descriptions refer to the different pad config uration register (pcr) types. refer to the siul chapter in the device reference manual for the features available for each pad type. description f fast (with gpio and digital alternate function) j fast/medium/slow i/o pad with analog fe ature (gpio and a nalog functionality) m1 medium (with gpio and digital alternate function) m2 medium (with slew rate control) s slow (with gpio and digital alternate function) smd stepper motor driver (with slew rate control) x oscillator table 3-6. signal details signal peripheral description abs[0] bam alternate boot select. gives an option to boot by downloading code via can or lin. ans[0:15] adc inputs used to bring into t he device sensor-based signals for a/d conversion. ans[0:15] connec t to atd channels [32:47]. ma[0:2] adc these three control bits are output to enable the selection for an external analog mux for expansion channels. the available 8 multiplexed channels connect to atd channels [64:71]. fabm force alternate boot mode. forc es the device to boot from the external bus (can or lin). if not asserted, the device boots up from the lowest flash sector containing a valid boot signature.
pxd10 microcontroller reference manual, rev. 1 3-28 freescale semiconductor preliminary?subject to change without notice dcu_de dcu indicates that valid pixels are present. dcu_hsync dcu horizontal sync pulse for tft-lcd display dcu_pclk dcu output pixel clock for tft-lcd display dcu_r[0:7], dcu_g[0:7], dcu_b[0:7] dcu red, green and blue color 8-bit pixel values for tft-lcd displays dcu_tag dcu indicates when a tagged pixel is present in safety mode dcu_vsync dcu vertical sync pulse for tft-lcd display pcs[0..2]_0, pcs[0..2]_1 dspi peripheral chip selects when device is in master mode; not used in slave modes. sck_0, sck_1 dspi spi clock signal?bidirectional sin_0, sin_1 dspi spi data input signal sout_0, sout_1 dspi spi data output signal pcs0_2 quadspi peripheral chip select for serial flash mode or chip select 0 for spi master mode io2/pcs1_2 quadspi chip select 1 for spi master mode and bidirectional io2 for serial flash mode io3/pcs2_2 quadspi chip select 2 for spi master mode and bidirectional io3 for serial flash mode io0/sin_2 quadspi data input signal for spi master and slave modes and bidirectional io0 for serial flash mode io1/sout_2 quadspi data output signal for spi master and slave modes and bidirectional io1 for serial flash mode sck_2 quadspi clock output signal for spi master and serial flash modes and clock input signal for spi slave mode emiosa[8:23], emiosb[16:23] emios enhanced modular input output system. 16+8 channel emios for timed input or output functions. canrx_0, canrx_1 flexcan receive (rx) pins for the can bus transceiver cantx_0, cantx_1 flexcan transmit (tx) pins for the can bus transceiver scl_0, scl_1, scl_2, scl_3 i 2 c bidirectional serial clock compatible with i 2 c specifications table 3-6. signal details (continued) signal peripheral description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 3-29 preliminary?subject to change without notice sda_0, sda_1, sda_2, sda_3 i 2 c bidirectional serial data compatible with i 2 c specifications tck jtag debug port serial clock as per jtag specifications tdi jtag debug port serial data input port as per jtag standards specifications tdo jtag debug port serial data output port as per jtag standards specifications tms jtag debug port test mode select signal for the jtag tap controller state machine and indicates various state transitions for the tap controller in the device bp[0:3] lcd backplane signals from the lcd controlling the backplane reference voltage for the lcd display fp[0:39] lcd frontplane signals for lcd segments evti nexus nexus2+ event input trigger evto nexus nexus2+ event output trigger mcko nexus output clock for the development tool mdo[0:3] nexus message output port pins that send information bits to the development tools for messages such as branch trace message (btm), ownership trace message (otm), data trace message (dtm). only available in reduced port mode. mseo nexus output pin?indicates the start or end of the variable length message on the mdo pins pdi[0:17] dcu (pdi) video/graphic data in various rgb modes input to the dcu pdi_de dcu (pdi) input signal indicates the validity of pixel data on the input pdi data bus. pdi_hsync dcu (pdi) input indicates the timing reference for the start of each frame line for the pdi input data. pdi_pclk dcu (pdi) input pixel clock from pdi pdi_vsync dcu (pdi) input indicate s the timing reference for the start of a frame for the pdi input data. rxd_0 linflex sci/lin receive data signal?t his port is used to download the code for the bam boot sequence. rxd_1 linflex sci/lin receive data signal. input pad for the lin sci module. connects to the internal lin second port. txd_0 linflex sci/lin transmit data signal. this port is used to download the code for the bam boot sequence. txd_1 linflex sci/lin transmit data sign al?transmit (output) port for the second lin module in the chip table 3-6. signal details (continued) signal peripheral description
pxd10 microcontroller reference manual, rev. 1 3-30 freescale semiconductor preliminary?subject to change without notice sound sgl sound signal to the speaker/buzzer ssd[0:5]_0 ssd[0:5]_1 ssd[0:5]_2 ssd[0:5]_3 ssd bidirectional control of stepper motors using stall detection module m[0:5]c0m m[0:5]c0p m[0:5]c1m m[0:5]c1p smc controls stepper motors in various configuration clkout mc_cgm output clock?it can be select ed from several internal clocks of the device from the clock generation module. table 3-6. signal details (continued) signal peripheral description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 4-1 preliminary?subject to change without notice chapter 4 safety 4.1 register protection 4.1.1 introduction 4.1.1.1 overview the register protection m odule offers a mechanism to protect de fined memory-mapped address locations in a module under protection from being written. the registers that are prot ected on this device are listed in appendix a, registers under protection . the protection module is located be tween the module under protection and the pbridge. this is shown in figure 4-1 . figure 4-1. register protection block diagram 4.1.1.2 features the register protection include s these distinctive features: ? restrict write accesses for the module unde r protection to supervisor mode only ? lock registers for first 6 kb of memory-mapped address space ? address mirror automatically sets corresponding lock bit pbridge / apb supervisor access / lock registers module under protection protection module write data address / access size uaa hlb gcr access allowed? peripheral enable other control signals peripheral enable
pxd10 microcontroller reference manual, rev. 1 4-2 freescale semiconductor preliminary?subject to change without notice ? once configured lock bits can be protected from changes 4.1.1.3 modes of operation the register protection module is operable when the mo dule under protection is operable. for further details about the availabili ty please see the module?s chapter in this document. 4.1.2 external signal description there are no external signals. 4.1.3 memory map and register description this section provides a detailed de scription of the memory map of a module usi ng the register protection. the original 16 kb module memory space is divided into five areas as shown in figure 4-2 . figure 4-2. register protection memory diagram area 1 is 6 kb large and hol ds the normal functional m odule registers and is transp arent for all read/write operations. area 2 is 2 kb starting at address 0x1800 is a reserved area, which shall not be accessed. area 3 is 6 kb large, starting at address 0x2000 and is a mirror of area 1. a r ead/write access to these 0x2000+x addresses will read/write the register at address x. as a side effect, a write access to address 0x2000+x will set the optional soft lock bits for this address x in the same cycle as th e register at address x is written. not all registers in ar ea 1 need to have protection defined by associated soft lock bits. for module register space base + 0x0000 6kb 2 kb reserved mirror module register space 6kb 1.5 kb lock bits with user defined base + 0x1800 base + 0x2000 base + 0x3800 soft locking function 512 bytes configuration base + 0x3e00 base + 0x3fff area 1 area 2 area 3 area 4 area 5
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 4-3 preliminary?subject to change without notice unprotected registers at address y, accesses to address 0x2000+y will be identical to accesses at address y. only for registers implemented in area 1 and defined as protectable soft lock bits will be available in area 4. area 4 is 1.5 kb large and holds the soft lock bits, one bit per byte in area 1. th e four soft lock bits associated with one module regist er word are arranged at byte boundaries in the memory map. the soft lock bit registers can be dir ectly written using a bit mask. area 5 is 512 bytes large and holds the configurat ion bits of the protection mode. there is one configuration hard lock bit per module that prevents all furthe r modifications to the so ft lock bits and can only be cleared by a system reset once set. the other bi ts, if set, will allow us er access to the protected module. if any locked byte is accessed with a write transaction, a transf er error will be issued to the system and the write transaction will not be ex ecuted. this is true even if not all accessed bytes are locked. accessing unimplemented 32-bit regi sters in areas 4 and 5 will result in a transfer error. 4.1.3.1 memory map table 4-1 gives an overview on the register protection registers implemented. note reserved registers in area #2 will be handled according to the protected ip (module under protection). table 4-1. register protection memory map address offset use location 0x0000 module register 0 (mr0) on page 4 0x0001 module register 1 (mr1) on page 4 0x0002 module register 2 (mr2) on page 4 0x0003 - 0x17ff module register 3 (mr3) - module register 6143(mr6143) on page 4 0x1800 - 0x1fff reserved 0x2000 module register 0 (mr0) + set soft lock bit 0 (lmr0) on page 4 0x2001 module register 1 (mr1) + set soft lock bit 1 (lmr1) on page 4 0x2002 - 0x37ff module register 2 (mr2) + set soft lock bit 2 (lmr2) - module register 6143 (mr6143) + set soft lock bit 6143 (lmr6143) on page 4 0x3800 soft lock bit register 0 (slbr0): soft lock bits 0-3 on page 4 0x3801 soft lock bit register 1 (slbr1): soft lock bits 4-7 on page 4 0x3802 - 0x3dff soft lock bit register 2 (slbr2): soft lock bits 8-11 - soft lock bit register 1535 (slbr1535): soft lock bits 6140-6143 on page 4 0x3e00 - 0x3ffb reserved 0x3ffc global configuration register (gcr) on page 5
pxd10 microcontroller reference manual, rev. 1 4-4 freescale semiconductor preliminary?subject to change without notice 4.1.3.2 register description this section describes in address order all the regist er protection registers. each description includes a standard register diagram with an associated figure num ber. details of register bi t and field function follow the register diagrams, in bit order. 4.1.3.2.1 module re gisters (mr0-6143) this is the lower 6k module memory space which hold s all the functional registers of the module that is protected by the regi ster protection module. 4.1.3.2.2 module re gister and set soft lock bit (lmr0-6143) this is memory area #3 that provides mirrored acce ss to the mr0-6143 registers with the side effect of setting soft lock bits in case of a write access to a mr that is defined as protectable by the locking mechanism. each mr is protectable by one associated bit in a slbr n .slb m , according to the mapping described in table 4-2 . 4.1.3.2.3 soft lock bit register (slbr0-1535) these registers hold the soft lock bits fo r the protected registers in memory area #1. figure 4-3. key to register fields always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit address 0x3800-0x3dff access: read always supervisor write 01234567 r0000 slb0 slb1 slb2 slb3 w we0 we1 we2 we3 reset00000000 figure 4-4. soft lock bit register (slbr n )
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 4-5 preliminary?subject to change without notice table 4-3 gives some examples of how slbr n .slb and mr n go together: 4.1.3.2.4 global configur ation register (gcr) this register is used to make global confi gurations related with the register protection. table 4-2. slbr n field descriptions field description we0 we1 we2 we3 write enable bits for soft lock bits (slb): we0 enables writing to slb0 we1 enables writing to slb1 we2 enables writing to slb2 we3 enables writing to slb3 1 value is written to slb 0 slb is not modified slb0 slb1 slb2 slb3 soft lock bits for one mr n register: slb0 can block accesses to mr[ n *4 + 0] slb1 can block accesses to mr[ n *4 + 1] slb2 can block accesses to mr[ n *4 + 2] slb3 can block accesses to mr[ n *4 + 3] 1 associated mr n byte is locked against write accesses 0 associated mr n byte is unprotected and writeable table 4-3. soft lock bits vs. protected address soft lock bit protected address slbr0.slb0 mr0 slbr0.slb1 mr1 slbr0.slb2 mr2 slbr0.slb3 mr3 slbr1.slb0 mr4 slbr1.slb1 mr5 slbr1.slb2 mr6 slbr1.slb3 mr7 slbr2.slb0 mr8 ... ...
pxd10 microcontroller reference manual, rev. 1 4-6 freescale semiconductor preliminary?subject to change without notice note the gcr.uaa bit has no effect on the allowed access modes for the registers in the register protection module. 4.1.4 functional description 4.1.4.1 general this module provides a generic regist er (address) write-prot ection mechanism. the protection size can be: ? 32-bit (address == multiples of 4) ? 16-bit (address == multiples of 2) ? 8-bit (address == multiples of 1) ? unprotected (address == multiples of 1) which addresses are protected and the protection size depend on the soc and/or module. therefore this section can just give examples fo r various protecti on configurations. for all addresses that are protected there are slbr n .slb m bits that specify whether the address is locked. when an address is locked it can only be read but not written in any mode (s upervisor/normal). if an address is unprotected the corresponding slbr n .slb m bit is always 0b0 no matt er what software is writing to. address: 0x3ffc access: read always supervisor write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hl b 0000000u a a 00000000000000000000000 w reset 00000000000000000000000000000000 figure 4-5. global configuration register (gcr) table 4-4. gcr field descriptions field description hlb hard lock bit. this register can not be cleared once it is set by software. it can only be cleared by a system reset. 1 all slb bits are write prot ected and can not be modified 0 all slb bits are accessible and can be modified. uaa user access allowed. 1 the registers in the module under protection can be accessed in the user mode without any additional restrictions. 0 the registers in the module under protection can only be written in supervisor mode. all write accesses in non-supervisor mode are not execut ed and a transfer error is issued. this access restriction is in addition to any access restrictions imposed by the protected ip module.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 4-7 preliminary?subject to change without notice 4.1.4.2 change lock settings to change the setting whether an address is locked or unlocked the corresponding slbr n .slb m bit needs to be changed. this can be done using the following methods: ? modify the slbr n .slb m directly by writing to area #4 ? set the slbr n .slb m bit(s) by writing to the mirror module space (area #3) both methods are explained in the following sections. 4.1.4.2.1 change lock sett ings directly via area #4 in memory area #4 the lock bits are located. they can be modified by wr iting to them. each slbr n .slb m bit has a mask bit slbr n .we m which protects it from being modified. this masking makes clear-modify-write op erations unnecessary. figure 4-6 shows two modification examples . in the left example there is a write access to the slbr n register specifying a mask value wh ich allows modifi cation of all slbr n .slb m bits. the example on the right specifies a mask which only al lows modification of the bits slbr n .slb[3:1]. figure 4-6. change lock settings directly via area #4 figure 4-6 showed four registers that ca n be protected 8-bit wise. in figure 4-7 registers with 16-bit protection and in figure 4-8 registers with 32-bi t protection are shown: figure 4-7. change lock settings for 16-bit protected addresses on the right side of figure 4-7 it is shown that the data written to slbr n .slb[0] is automatically written to slbr n .slb[1] also. this is done as the address reflected by slbr n .slb[0] is protected 16-bit wise. 1 slb3 slb2 slb1 slb0 slbr n .we[3:0] slbr n .slb[3:0] slb3 slb2 slb1 slb0 slbr n .slb[3:0] change allowed to slb3 write data to slb2 to slb1 to slb0 1 1 1 1slbr n .we[3:0] to slb3 write data to slb2 to slb1 to slb0 1 1 0 change allowed slb0 slb1 slb2 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 x1x slb0 slb1 slb2 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 x00
pxd10 microcontroller reference manual, rev. 1 4-8 freescale semiconductor preliminary?subject to change without notice note that in this case the write enable slbr n .we[0] must be set while slbr n .we[1] does not matter. as the enable bits slbr n .we[3:2] are cleared the lock bits slbr n .slb[3:2] remain unchanged. in the example on the left side of figure 4-7 the data written to slbr n .slb[0] is mirrored to slbr n .slb[1] and the data written to slbr n .slb[2] is mirrored to slbr n .slb[3] as for both registers the write enables are set. in figure 4-8 a 32-bit wise protected re gister is shown. when slbr n .we[0] is set the data written to slbr n .slb[0] is automatically written to slbr n .slb[3:1] also. otherwise slbr n .slb[3:0] remains unchanged. figure 4-8. change lock settings for 32-bit protected addresses in figure 4-9 an example is shown which has a mixed protection size configuration: figure 4-9. change lock settings for mixed protection the data written to slbr n .slb[0] is mirrored to slbr n .slb[1] as the corresponding register is 16-bit protected. the data written to slbr n .slb[2] is blocked as the corresponding regist er is unprotected. the data written to slbr n .slb[3] is written to slbr n .slb[3]. 4.1.4.2.2 enable locking via mirror module space (area #3) it is possible to enable locking for a register after writing to it. to do so the mirrored module address space must be used. figure 4-10 shows one example: 1 slb0 slb1 slb2 slb3 slbr n .we[3:0] slbr.slb[3:0] update lock bits to slb0 write data to slb1 to slb2 to slb3 xxx slb0 slb1 0 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 xx1
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 4-9 preliminary?subject to change without notice figure 4-10. enable locking via mirror module space (area #3) when writing to address 0x0008 the registers mr9 and mr8 in the protected module are updated. the corresponding lock bits rema in unchanged (left part of figure 4-7 ). when writing to address 0x2008 the registers mr9 and mr8 in the protected module are updated. the corresponding lock bits slbr2.slb[1 :0] are set while the lock bits slbr2.slb[3:2] remain unchanged (right part of figure 4-7 ). figure 4-11 shows an example where some addres ses are protected and some are not: figure 4-11. enable locking for protected and unprotected addresses in the example in figure 4-11 addresses 0x0c and 0x0d are unprotect ed. therefore their corresponding lock bits slbr3.slb[1:0] are always 0b0 (shown in bold). when doing a 32-bit write access to address 0x200c only lock bits slbr3.slb[3:2] are set while bits slbr3.slb[1:0] stay 0b0. note lock bits can only be set via writes to the mirror module space. reads from the mirror module space will not change the lock bits. 4.1.4.2.3 write protect ion for locking bits changing the locking bits through any of the procedures mentioned in section 4.1.4.2.1, change lock settings directly via area #4 , and section 4.1.4.2.2, enable locking via mirror module space (area #3) , is only possible as long as the bit gcr.hlb is cleared. once this bit is set the locking bits can no longer be modified until there was a system reset. 4.1.4.3 access errors the protection module generates tran sfer errors under several circumst ances. for the area definition refer to figure 4-2 . 1. if accessing area #1 or area #3, the protection m odule will pass on any access error from the underlying module under protection. slbr 2 we[3:0] 00000000 slb[3:0] 16-bit write to address 0x0008 no change write to mr[9:8] slbr 2 we[3:0] 00001100 slb[3:0] 16-bit write to address 0x2008 set lock bits write to mr[9:8] slbr 3 we[3:0] 0000 00 00 slb[3:0] before write access slbr 3 we[3:0] 0000 00 11 slb[3:0] 32-bit write to address 0x200c set lock bits write to mr[15:12] after write access
pxd10 microcontroller reference manual, rev. 1 4-10 freescale semiconductor preliminary?subject to change without notice 2. if user mode is not allowed, user writes to all ar eas will assert a transfer error and the writes will be blocked. 3. if accessing the reserved area #2, a transfer error will be asserted. 4. if accessing unimplemented 32-bit registers in area #4 and area #5 a tr ansfer error will be asserted. 5. if writing to a register in area #1 and area #3 with soft lock bit set for any of the affected bytes a transfer error is asserted and the write will be blocked. also the comp lete write operation to non-protected bytes in th is word is ignored. 6. if writing to a soft lock register in area #4 with the hard lock bit being set a transfer error is asserted. 7. any write operation in any access mode to area #3 while hard lock bit gcr.hlb is set 4.1.5 reset the reset state of each individu al bit is shown within the regi ster descripti on section (see section 4.1.3.2, register description ?). in summary, after reset, locking for all mr n registers is disabled. the registers can be accessed in supervisor mode only. 4.2 software watchdog timer (swt) 4.2.1 overview the software watchdog timer (swt) is a peripheral module that can prev ent system lockup in situations such as software getting trapped in a loop or if a bus transa ction fails to terminate. when enabled, the swt requires periodic execution of a watchdog servicing sequ ence. writing the sequence resets the timer to a specified time-out period. if this servicing action does not occur be fore the timer expires the swt generates an interrupt or ha rdware reset. the swt can be configured to generate a reset or interrupt on an initial time-out, a reset is always ge nerated on a second consecutive time-out. the swt provides a window functionality. when this functionality is program med, the servicing action should take place within the defined window. when occuring outside the defined period, the swt will generate a reset. 4.2.2 features the swt has the following features: ? 32-bit time-out register to set the time-out period ? the unique swt counter clock is the undivided low power internal oscillator (irc 128 khz), no other clock source can be selected ? programmable selection of window mode or regular servicing ? programmable selection of reset or interrupt on an initial time-out ? master access protection ? hard and soft configuration lock bits
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 4-11 preliminary?subject to change without notice ? the swt is started on phase1 exit and counts unconditionally dur ing phase2 to monitor flash boot sequence. swt is held in reset during phase3 but can star t again at phase3 exit depending on the value of the shadow flash c onfiguration bit nvusr0[watchdog_en]. 4.2.3 modes of operation when enabled, the swt is always active in all modes except standby when it is always disabled and stop when it may be disabled by the swt_cr[stp] bi t. if the stp bit is set, the counter is stopped in stop mode, otherwise it continues to run. on exit from stop mode, th e swt will continue from the state it was before entering stop mode. to simplify software development it is possible to temporarily suspend the swt counter while the mcu is stopped by a debugger. while the mcu is running th e swt counter runs normally. this feature is enabled by setting the swt_cr[frz] bit and is only available when the cpu ha s debug mode active (see the cpu reference manual for more in formation on debug mode and support). software watchdog is not availabl e in standby mode. as soon as out of standby mode, the swt behaves as in a usual ?out of reset? situation. figure 4-12 shows the operation timi ng diagram of the swt. table 4-5 describes the swt operation after reset. figure 4-12. swt operation timing diagram table 4-5. swt operation after reset swt_cr [wen] mcu mode cpu debug active swt_cr [frz] swt_cr [stp] swt operation 0 ? no 0 or 1 0 or 1 off mc_me mode reset phases swt status swt_cr[wen] reset drun drun idle phase0 phase1 phase2 phase3 disabled enabled disabled enabled if wen = 1 (see note 1) see note 2 notes: 1) the swt is started on phase1 exit and counts unconditionally during phase2 to monitor the flash memory boot sequence. 2) value copied from configuration bit nvusr0[watchdog_en] in the shadow flash memory (software can modify it later)
pxd10 microcontroller reference manual, rev. 1 4-12 freescale semiconductor preliminary?subject to change without notice 4.2.4 external signal description the swt module does not have a ny external interface signals. 4.2.5 memory map and register description the swt programming model has six 32-bit register s. the programming model can only be accessed using 32-bit (word) accesses. references using a differ ent size are invalid. other types of invalid accesses include: writes to read only regist ers, incorrect values written to the service register when enabled, accesses to reserved addr esses and accesses by master s without permission. if th e ria bit in the swt_cr is set then the swt generates a system reset on an invalid access otherwise a bus error is generated. if either the hlk or slk bits in the swt_cr are set then the swt_ cr, swt_to and swt_wn registers are read only. 4.2.5.1 memory map the swt memory map is shown in table 4-6 . 1 normal (mc_me modes drun, run0:3, halt, safe) no 0 or 1 0 or 1 running debug 1 (mc_me modes drun, run0:3, halt, safe) yes 0 0 or 1 running yes 1 0 or 1 halted stop (mc_me mode stop) no 0 or 1 0 running no 0 or 1 1 halted 0 or 1 standby no no no off 1 swt debug mode occurs when the processor is stopped due to user specified debug criteria such as breakpoint. table 4-6. swt memory map address offset register name register description size (bits) access 0x0000 swt_cr swt control register 32 r/w 0x0004 swt_ir swt interrupt register 32 r/w 0x0008 swt_to swt time-out register 32 r/w 0x000c swt_wn swt window register 32 r/w 0x0010 swt_sr swt service register 32 r/w 0x0014 swt_co swt counter output register 32 r 0x0018- 0x3fff -reserved -- table 4-5. swt operation after reset (continued) swt_cr [wen] mcu mode cpu debug active swt_cr [frz] swt_cr [stp] swt operation
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 4-13 preliminary?subject to change without notice 4.2.5.2 swt control register (swt_cr) the swt_cr contains fields for configuring and controlli ng the swt. this register is read only if either the swt_cr.hlk or swt_cr.slk bits are set. the swt_cr reset value is 0x8000_011a or 0x800 0_011b, corresponding to map0 = 1 (only cpu access allowed), ria = 1 (reset on invalid swt access) , slk = 1 (soft lock), csl = 1 (irc clock source for counter), frz = 1 (freeze available while debuggi ng), wen = 0 or 1 (copied from configuration bit nvusr0[watchdog_en]). offset 0x0000 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r map 0 map 1 map 2 map 3 000000000 0 00 w reset 1000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 000000 ria wnd itr hlk slk csl stp frz wen w reset 0000000100011 0 1see note note: swt_cr[wen] value is copied from configur ation bit nvusr0[watchdog_en] during reset figure 4-13. swt control register (swt_cr) table 4-7. swt_cr field descriptions field description mapn master access protection for ma ster n. the platform bus master assignments are device specific. 0 = access for the master is not enabled 1 = access for the master is enabled ria reset on invalid access. 0 = invalid access to the swt generates a bus error 1 = invalid access to the swt causes a system reset if wen=1 wnd window mode. 0 = regular mode, service sequence can be done at any time 1 = windowed mode, the service sequence is only valid when the down counter is less than the value in the swt_wn register. itr interrupt then reset. 0 = generate a reset on a time-out 1 = generate an interrupt on an initial time-out, reset on a second consecutive time-out hlk hard lock. this bit is only cleared at reset. 0 = swt_cr, swt_to and swt_wn are read/write registers if slk=0 1 = swt_cr, swt_to and swt_wn are read only registers
pxd10 microcontroller reference manual, rev. 1 4-14 freescale semiconductor preliminary?subject to change without notice 4.2.5.3 swt interrupt register (swt_ir) the swt_ir contains the time-out interrupt flag. slk soft lock. this bit is cleared by writing the unlock sequence to the service register. 0 = swt_cr, swt_to and swt_wn are read/write registers if hlk=0 1 = swt_cr, swt_to and swt_wn are read only registers csl clock selection. selects the lp irc 128 khz oscillator clock that drives the internal timer. csl bit can be written.the status of the bit has no effect on counter clock selection on this device. 0 = system clock. (not applicable on this device) 1 = oscillator clock. stp stop mode control. allows the watchdog timer to be stopped when the device enters stop mode. 0 = swt counter continues to run in stop mode 1 = swt counter is stopped in stop mode frz freeze available during debug. this function is only operational when the cpu is in an active debug mode. 0 = swt counter continues to run independent of the cpu status 1 = swt counter is stopped when the cpu is stopped by a debugger wen watchdog enabled. 0 = swt is disabled 1 = swt is enabled offset 0x0004 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0000000000000 0 00 w reset 0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0000000 00 00000 tif w reset 0000000000000 0 00 figure 4-14. swt interrupt register (swt_ir) table 4-8. swt_ir field descriptions field description tif time-out interrupt flag. the flag and interrupt are cleared by writing a 1 to this bit. writing a 0 has no effect. 0 = no interrupt request. 1 = interrupt request due to an initial time-out. table 4-7. swt_cr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 4-15 preliminary?subject to change without notice 4.2.5.4 swt time-out register (swt_to) the swt time-out (swt_to) register contains the 32-bi t time-out period. this re gister is read only if either the swt_cr.hlk or swt_cr.slk bits are set. figure 4-15. swt time-out register (swt_to) the default counter value (swt_t o_rst) is 1280 (0x500 he xadecimal) which correspond to 10 ms with a 128 khz clock. 4.2.5.4.1 swt window register (swt_wn) the swt window (swt_wn) register c ontains the 32-bit window start valu e. this register is cleared on reset. this register is read only if either the swt_cr.hlk or swt_cr.slk bits are set. offset 0x008 access: read/write 012345678910111213141516171 8 19 20 21 22 23 24 25 26 27 28 29 30 31 r wto w reset 00000000000000000000010100000000 table 4-9. swt_to register field descriptions field description wto watchdog time-out period in clock cycles. an internal 32-bit down counter is loaded with this value or 0x100 which ever is greater when the service sequ ence is written or when the swt is enabled. offset 0x00c access: read/write 012345678910111213141516171 8 19 20 21 22 23 24 25 26 27 28 29 30 31 r wst w reset 00000000000000000000000000000000 figure 4-16. swt window register (swt_wn) table 4-10. swt_wn regi ster field descriptions field description wst window start value. when window mode is enabled, the service sequence can only be written when the internal down counter is less than this value.
pxd10 microcontroller reference manual, rev. 1 4-16 freescale semiconductor preliminary?subject to change without notice 4.2.5.4.2 swt servi ce register (swt_sr) the swt time-out (swt_sr) service register is the target for servic e sequence writes used to reset the watchdog timer. 4.2.5.4.3 swt counter ou tput register (swt_co) the swt counter output (swt_co) regi ster is a read only register that shows the value of the internal down counter when the swt is disabled. offset 0x010 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000000000000 00000000 00 0 0 00 w wsc reset 00000000000000000000000000000000 figure 4-17. swt service register (swt_sr) table 4-11. swt_sr field descriptions field description wsc watchdog service code.this field is used to service the watchdog and to clear the soft lock bit (swt_cr.slk). to service the watchdog, the value 0xa602 followed by 0xb480 is written to the wsc field. to clear the soft lock bit (swt_cr.slkswt_cr.), the value 0xc520 followed by 0xd928 is written to the wsc field. offset 0x014 access: read only 012345678910111213141516171 8 19 20 21 22 23 24 25 26 27 28 29 30 31 r cnt w reset 00000000000000000000000000000000 figure 4-18. swt counter output register (swt_co) table 4-12. swt_co register field descriptions field description cnt watchdog count. when the watchdog is disabled (s wt_cr.wenswt_cr.=0) this field shows the value of the internal down counter. when the watchdog is enabled the value of this field is 0x0000_0000. values in this field can lag behind the inte rnal counter value for up to six s ystem plus eight counter clock cycles. therefore, the value read from this field immediately after disabling the watchdog may be higher than the actual value of the internal counter.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 4-17 preliminary?subject to change without notice 4.2.6 functional description the swt is a 32-bit timer desi gned to enable the system to recover in situations such as software getting trapped in a loop or if a bus transact ion fails to terminate. it includes a a control register (swt_cr), an interrupt register (swt_ir), time -out register (swt_to), a window register (swt_wn), a service register (swt_sr) and a counter output regist er (swt_co). the swt_cr includes bits to enable the timer, set c onfiguration options and lo ck configuration of the module. the watchdog is enabled by setting th e swt_cr.wen bit. the reset value of the swt_cr.wen bit is 0 when exiting reset mode if the flash user option bit 31 (watchdog_en) is `0'. if the reset value of watchdog_en is 1, the swt_cr.wen bit is set and the watchdog starts operation automatically after reset is released. the swt_to register holds the watc hdog time-out period in clock cycles unless the value is less than 0x100 in which case the time-out period is set to 0x100. th is time-out period is loaded into an internal 32-bit down counter when the swt is enabled and e ach time a valid service sequence is written. the swt_cr.csl bit selects which clock (system or os cillator) is used to drive the down counter. the configuration of the swt can be lo cked through use of either a soft lock or a hard lock. in either case, when locked the swt_cr, swt_to and swt_wn regist ers are read only. the hard lock is enabled by setting the swt_cr.hlk bit which can only be cleared by a reset. th e soft lock is enabled by setting the swt_cr.slk bit and is cleared by writing the unloc k sequence to the service register. the unlock sequence is a write of 0xc520 followed by a write of 0xd928 to the swt_sr.wsc field. there is no timing requirement between the two writes. the unlock sequence logic ignores service sequence writes and recognizes the 0xc520, 0xd928 seque nce regardless of previous writ es. the unlock sequence can be written at any time and does not requi re the swt_cr.wen bit to be set. when enabled, the swt requires periodic execution of the watchdog servicing sequence. the service sequence is a write of 0xa602 followed by a write of 0xb480 to the swt_sr.wsc field. writing the service sequence loads the internal down counter with the time-out pe riod. there is no timing requirement between the two writes. the servic e sequence logic ignores unlock se quence writes and recognizes the 0xa602, 0xb480 sequence regardless of previous writ es. accesses to swt registers occur with no peripheral bus wait states. (the peri pheral bus bridge may add one or more system wait states.) however, due to synchronization logic in the swt design, rec ognition of the service se quence or configuration changes may require up to three system plus seven counter clock cycles. if window mode is enabled (swt_cr. wnd bit is set), the se rvice sequence must be performed in the last part of the time-out period define d by the window register. the window is open when the down counter is less than the value in the swt_wn register. outside of this window, service se quence writes are invalid accesses and generate a bus error or reset depending on the value of the swt_cr.ria bit. for example, if the swt_to register is set to 5000 and swt_wn register is set to 1000 then th e service sequence must be performed in the last 20% of the time-out period. there is a short lag in the time it takes for the window to open due to synchronization logic in the watchdog design. this delay c ould be up to three system plus four counter clock cycles. the interrupt then reset bit (swt_cr.itr) controls the action taken when a time-out occurs. if the swt_cr.itr bit is not set, a reset is generated immediately on a time-out. if the sw t_cr.itr bit is set, an initial time-out causes the swt to generate an interrupt a nd load the down counter with the time-out
pxd10 microcontroller reference manual, rev. 1 4-18 freescale semiconductor preliminary?subject to change without notice period. if the service sequen ce is not written before the second c onsecutive time-out, the swt generates a system reset. the interrupt is indicated by the time-out interrupt flag (s wt_ir.tif). the interrupt request is cleared by writing a one to the swt_ir.tif bit. the swt_co register shows the va lue of the down counter when the watchdog is disabled. when the watchdog is enabled this register is cleared. the value shown in this register can lag behind the value in the internal counter for up to six syst em plus eight counter clock cycles. the swt_co can be used during a so ftware self test of the swt. fo r example, the swt can be enabled and not serviced for a fixed period of time less than the time-out value. then the swt can be disabled (swt_cr.wen cleared) and the value of the swt_co re ad to determine if the internal down counter is working properly.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-1 preliminary?subject to change without notice chapter 5 analog-to-digital converter (adc) 5.1 overview 5.1.1 device-specific features ? 10-bit resolution ? as many as 16 channels, expandable to 23 channels via external multiplexing ? minimum conversion time of 1 s ? conversion triggering sources: ? software ? pit channel 2 (for normal conversion trigger only) ? 2 different sampling and conversi on time registers ctr[1:2] (exte nded internal chan nels, external channels) ? as many as 23 data registers for storing converted data. conversion information, such as mode of operation (normal, injected), is associated to data value. ? conversions on external channels managed in th e same way as internal channels, making it transparent to the application ? external decode signals (3 bits) to control the external analog multiplexers ? one shot/scan modes ? chain injection mode ? hardware-triggered dma transfer requests ? power-down mode ? 2 different abort functions allow to abort eith er single-channel convers ion or chain conversion ? 4 programmable analog watc hdogs with interrupt capability ? allows continuous hardware monitoring of as many as 4 analog input channels ? alternate analog thresholds ? auto-clock-off
pxd10 microcontroller reference manual, rev. 1 5-2 freescale semiconductor preliminary?subject to change without notice 5.1.2 device-specific implementation figure 5-1. adc implementation 5.2 introduction the analog-to-digital converter (adc ) block provides accurate and fast conversions for a wide range of applications. an adc analog part has it s corresponding digital interface (adcdig). the adc digital interface c ontains advanced features for normal or injected conversion. a conversion can be triggered by software or hardware (pit3). there are several type s of input channels: ? internal extended, ans (internally mult iplexed standard accuracy channels) ? external, anx (externally multipl exed standard accuracy channels) the mask registers present within the adcdig can be programmed to co nfigure which channel has to be converted. several external decode si gnals ma[2:0] (multiplexer address) are provided for external channel selection and are available as alternate functions on gpio. a conversion timing register for configuring different sampling and c onversion times is as sociated to each channel type. analog watchdogs allow conti nuous hardware monitoring. 16 channels up to 8 extended channels through external mux ch 47 (ans15) ch 42 (ans10) ch 32 (ans0) pit3 ma [2:0] 3 single-ended interrupts eoc, watchdog, ech mux 8 3 digital interface analog switch pit intc d a mux 16 adc system . . . . . . injected and normal trigger /2 adclksel acko system clock
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-3 preliminary?subject to change without notice 5.3 functional description 5.3.1 analog channel conversion two conversion modes are available within the adcdig: ? normal conversion ? injected conversion 5.3.1.1 normal conversion this is the normal conversion that the user program s by configuring the normal conversion mask registers (ncmr). each channel can be individually enabled by setting ?1? in the corresponding field of ncmr registers. mask registers must be programmed before starting the conve rsion and cannot be changed until the conversion of all the sel ected channels ends (nstart bit in the main status register (msr) is reset). 5.3.1.2 start of normal conversion by programming the configuration bits in the main configuration register (m cr), the normal conversion can be started in two ways: ? by software (trgen reset)?if the external trigger enable bit is reset, the c onversion chain starts when the nstart bit in the mcr is set. ? by trigger (trgen set)?an on-chip internal signal triggers an adc conversion. the settings in the mcr select how conversions are tri ggered based on these internal signals: ? if the edglev (edge/level selection) bit in th e mcr is cleared, then aa rising/falling edge (depending on the edge bit in m cr) detected in the signal sets the nstart bit in the msr and starts the programmed conversion. edge = 0 selects a falling edge. edge = 1 selects a rising edge. ? if the edglev bit in the mcr is set, tthe conve rsion is started if and only if the nstart bit in the mcr is set and the programmed level on th e trigger signal is detected. the level is selected using the edge bit in the mcr. ed ge = 0 means that the start of conversion is enabled if the signal is low. if edge = 1, the start of conversion is enabled when the signal is high.
pxd10 microcontroller reference manual, rev. 1 5-4 freescale semiconductor preliminary?subject to change without notice the nstart status bit in the msr is automatically set when the normal conversion starts. at the same time the nstart bit in the mcr is reset, allowing the software to pr ogram a new start of conversion. in that case the new requested conversion star ts after the running conversion is completed. if the content of all the normal conversion mask regi sters is zero (that is, no channel is selected) the conversion operation is considered completed and the interrupt ech (see further) is immediately issued after the start of conversion. 5.3.1.3 normal conversion operating modes two operating modes are available for the normal conversion: ? one shot ?scan to enter one of these modes, it is necessary to program the mode bit in the mcr. the first phase of the conversion process involves sampling the analog channel and the next phase involves the conversion phase when the sampled analog value is c onverted to digital as shown in figure 5-2 . figure 5-2. normal conversion flow in one shot mode (mode = 0) a sequential conversion specified in the ncmr registers is performed only once. at the end of ea ch conversion, the digital re sult of the conversion is stored in the corresponding data register. table 5-1. configurations for starting normal conversion type of conversion start mcr msr result trgen nstar t edgle v edge nstar t software 0 1 ? ? 1 conversion chain starts trigger 1 ? 0 0 1 a falling edge detected in a trigger signal sets the nstart bit in the msr and starts the programmed conversion. 1 a rising edge detected in a trigger signal sets the nstart bit in the msr and starts the programmed conversion. trigger11101the conversion is started if the programmed level on the trigger signal is detected: the start of conversion is enabled if the external pin is low. 1 1 the conversion is started if the programmed level on the trigger signal is detected: the start of conversion is enabled if the external pin is high. sample b convert b sample c sample d convert d sample e convert e convert c
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-5 preliminary?subject to change without notice example 5-1. one shot mode (mode = 0) channels a-b-c-d-e-f-g-h are present in the devi ce where channels b-d-e are to be converted in the one shot mode. mode = 0 is set for one s hot mode. conversion star ts from the channel b followed by conversion of channels d-e. at the end of conversion of ch annel e the scanning of channels stops. the nstart status bit in the msr is automatically set when the normal convers ion starts. at the same time the nstart bit in the mcr is reset, allowing the software to pr ogram a new start of conversion. in that case the new requested conversion star ts after the running conversion is completed. in scan mode (mode = 1), a sequential conversion of n cha nnels specified in the ncmr registers is continuously performed. as in the pr evious case, at the end of each c onversion the digital result of the conversion is stored into th e corresponding data register. the nstart status bit in the msr is automatically set when the normal conve rsion starts. unlike one shot mode, the nstart bit in the mcr is not reset. it can be reset by software when the user needs to stop scan mode. in that case, the adc completes the current scan conversion and, after the last conversion, also resets the nstart bit in the msr. example 5-2. scan mode (mode = 1) channels a-b-c-d-e-f-g-h are present in the devi ce where channels b-d-e are to be converted in the scan mode. mode = 1 is se t for scan mode. conversion starts from the channel b followed by conversion of the channels d-e. at the end of conversion of ch annel e the scanning of channel b starts followed by conversion of the channels d-e. this sequence repeats itself till the nstart bit in the mcr is reset by software. if the conversion is started by an ex ternal trigger and edglev is ?0?, the nstart bit in the mcr is not set. as a consequence, once started the only way to st op scan mode conversion is to set the mode bit to ?0?. at the end of each conversion an end of conversion interr upt is issued (if enab led by the corresponding mask bit) and at the end of the co nversion sequence an end of chain inte rrupt is issued (if enabled by the corresponding mask bit). 5.3.1.4 injected channel conversion a conversion chain can be injected into the ongoi ng normal conversion by configuring the injected conversion mask registers (jcmr). as normal conversion, each channe l can be individually selected. this injected conversion can only occur in one shot mode and interrupts the normal conversion. when an injected conversion is inserted, ongoi ng channel conversion is aborted and the injected channel request is processed. after the last channel in the injected ch ain is converted, normal conversion resumes from the channel at which the normal co nversion was stopped as shown in figure 5-3 .
pxd10 microcontroller reference manual, rev. 1 5-6 freescale semiconductor preliminary?subject to change without notice figure 5-3. injected sample/conversion sequence the injected conversion can be star ted by software setting the jsta rt bit in the mcr; the current conversion is suspended and th e injected chain is convert ed. at the end of the chain, the jstart bit in the msr is reset and the normal chain conversion is resumed. the jstart status bit in the msr is automatically se t when the injected conversion starts. at the same time the jstart bit in the mcr is reset, allowing th e software to program a new start of conversion. in that case the new requested conversion starts af ter the running injected conversion is completed. at the end of each injected conversion, an end of in jected conversion (jeoc) interrupt is issued (if enabled by the corresponding mask bit) and at the end of the sequence an end of injected chain (jech) interrupt is issued (if enabled by the corresponding mask bit). if the content of all the injected conversion mask registers is zero (t hat is, no channel is selected) the interrupt jech is immediately issu ed after the start of conversion. once started, injected chain conversion cannot be interrupted by any other conversion type (it can, however, be aborted; see section 5.3.1.5, abort conversion ). 5.3.1.5 abort conversion two different abort functions are provided. ? the user can abort the ongoing conversion by setting the abort bit in the mcr. the current conversion is aborted and the conve rsion of the next channel of th e chain is immediately started (generating a new start pulse to the analog adc). in the case of an abort operation, the nstart/jstart bit remains set and the abort bi t is reset after the conversion of the next channel starts. the eoc corresponding to the aborte d channel is not generated. this behavior is true for normal or triggered/inject ed conversion modes. if the last channel of a chai n is aborted, the end of chain is reported generating an ech interrupt. ? it is also possible to abort the current chain conversion by setting the abortchain bit in the mcr. in that case the behavior of the adc depends on the mode bit. in fact, if scan mode is disabled, the nstart bit is automatically reset together with the abor tchain bit. otherwise, if the mode bit is set to ?1?, a new chain conve rsion is started. the eoc of the current aborted conversion is not generated but an ech interrupt is generated to signal the end of the chain. the ongoing channel conversion is interrupted and the injected conversion chain is processed first, after the injected chain is converted the normal chain conversion resumes from the channel at which normal conversion was aborted. injected conversion of channels i and j normal conversion resumes from the last aborted channel. sample b convert b sample c sample d convert d sample e convert e convert c sample c abort c sample i sample j convert j sample c convert c convert i
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-7 preliminary?subject to change without notice when a chain conversion abort is requested (a bortchain bit is set) while an injected conversion is running over a suspended normal conversion, both injected chain and normal conversion chain are aborted (both the nsta rt and jstart bits are also reset). 5.3.2 analog clock generator and conversion timings the clock frequency can be select ed by programming the adclksel bit in the mcr. when this bit is set to ?1? the adc clock has the same frequency as the system clock. othe rwise, the adc clock is half of the system clock frequency. the adclksel bi t can be written only in power-down mode. when the internal divider is not enabled (adcclksel = 1), it is important th at the associated clock divider in the clock generation module is ?1?. th is is needed to ensure 50% clock duty cycle. the direct clock should basically be used only in low power mode when the device is using only the 16 mhz fast internal rc oscillator, but the conversi on still requires a 16 mhz clock (an 8 mhz clock is not fast enough). in all other cases, the adc should us e the clock divided by two internally. 5.3.3 adc sampling and conversion timing in order to support different loading and switching times, several different conversion timing registers (ctr) are present. there is one register per cha nnel type. inplatch and in pcmp configurations are limited when the system clock fr equency is greater than 20 mhz. when a conversion is started, the adc connects the in ternal sampling capacitor to the respective analog input pin, allowing the capac itance to charge up to the input voltage value. the time to load the capacitor is referred to as sampling time. after completion of the sampling phase, the evalua tion phase starts and all the bits corresponding to the resolution of the adc are estimated to provide the conversion result. the conversion times are pr ogrammed via the bit fields of the ct r. bit fields inplatch, inpcmp and inpsamp are used to define the total conversion duration (t conv ) and in particular the partition between sampling phase duration (t sample ) and total evaluation phase duration (t eval ). the sampling phase duration is: where ndelay is equal to 0.5 if inpsamp is less than or equal to 06h, otherwise it is 1. inpsamp must be greater than or equal to 3 (hardware requirement). the total evaluation phase duration is: t sample inpsamp ndelay ? ?? t ck ? = inpsamp 3 ? ? 10 inpcmp t ck ? ?? ? == inpcmp 1 ? ?? and inplatch inpcmp ? ??
pxd10 microcontroller reference manual, rev. 1 5-8 freescale semiconductor preliminary?subject to change without notice inpcmp must be greater than or equal to 1 and inplatch must be less than incmp (hardware requirements). the total conversion duration is (not including external multiplexing): the timings refer to the unit t ck , where f ck = (1/2 x adc peripheral se t clock). the maximum clock frequency is specified in table 5-2 . table 5-3 lists the possible combinations by configuring the ad_clk at 60 mhz. table 5-2. max ad_clk frequency and related configuration settings inplatch inpcmp inpsamp ad_clk f max (mhz) t sample min. (ns) 01h3h20125 0 1h 4h 20 + 4% 168 1 2h 4h 20 + 4% 168 1 2h 5h 20 + 4% 135 1 3h 7h 32 + 4% 132 1 3h 7h 40 + 4% 128 1 3h 8h 50 + 4% 134 1 3h 9h 60 + 4% 128 table 5-3. adc sampling and conversion timing inplatch inpcmp inpsamp t sample 1 1 represents the number of clock cycl es that this operation will last t eval ndelay t conv 1 11 0000 1001 8 * tck 30 * tck 1 * tck 39 * tck 2 2 the adc minimum conversion time at 60 mhz frequency is 39 * tck; that corresponds to 650 ns. 1 11 0000 1010 9 * tck 30 * tck 1 * tck 40 * tck 1 11 0000 1011 10 * tck 30 * tck 1 * tck 41 * tck 1 11 0000 1100 11 * tck 30 * tck 1 * tck 42 * tck 1 11 0000 1101 12 * tck 30 * tck 1 * tck 43 * tck 1 11 0000 1110 13 * tck 30 * tck 1 * tck 44 * tck 1 11 0000 1111 14 * tck 30 * tck 1 * tck 45 * tck ... ... ... ... ... ... ... 1 11 1111 1100 251 * tck 30 * tck 1 * tck 282 * tck 1 11 1111 1101 252 * tck 30 * tck 1 * tck 283 * tck 1 11 1111 1110 253 * tck 30 * tck 1 * tck 284 * tck 1 11 1111 1111 254 * tck 30 * tck 1 * tck 285 * tck t conv t sample t eval ndelay t ck ? ?? ++ =
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-9 preliminary?subject to change without notice 5.3.4 programmable analog watchdog 5.3.4.1 introduction the analog watchdogs are used for determining whether the result of a channel conversion lies within a given guarded area (as shown in figure 5-4 ) specified by an upper and a lower threshold value named thrh and thrl respectively. figure 5-4. guarded area after the conversion of the selected channel, a comparison is perfor med between the converted value and the threshold values. if the converted value lies outside that guarded area then corresponding threshold violation interrupts are generated. the comparison resu lt is stored as wdgxh and wdgxl bits in the wtisr as explained in table 5-4 . depending on the mask bits mskwdgxl and mskwdgxh in the wtimr, an interrupt is gene rated on threshold violation. the channel on which the analog watchdog is to be a pplied is selected by the thrch field in the trc registers. the analog watchdog is enabled by setting the corresponding thren bit in the same register. the lower and higher threshold values for the analog watchdog are programme d using the registers thrhlr. for example, if channel num ber 3 is to be monitored with threshold values in thrhlr1, then the thrch field is programmed in the trc1 re gister to select channel number 3. a set of threshold register s (thrhlrx and trcx) can be linked only to a single channel for a particular thrch value. if another channel is to be monitore d with same threshold values, then the thrch field in the trcx register ha s to be programmed again. table 5-4. values of wdgxh and wdgxl fields wdgxh wdgxl converted data 1 0 converted data > thrh 0 1 converted data < thrl 0 0 thrl <= converted data <= thrh thrh thrl analog voltage upper threshold lower threshold guarded area
pxd10 microcontroller reference manual, rev. 1 5-10 freescale semiconductor preliminary?subject to change without notice note if the higher threshold for the anal og watchdog is programmed lower than the lower threshold and the converted value is less than the lower threshold, then the wdgxl interrupt for the low thre shold violation is set, else if the converted value is greater than the lower threshold (consequently also greater than the higher threshold) then the interrupt wdgxh for high threshold violation is set. thus, the us er should avoid that situation as it could lead to misinterpretati on of the watchdog interrupts. 5.3.5 dma functionality a dma request can be programmed after the convers ion of every channel by setting the respective masking bit in the dmar register s. the dmar masking registers mu st be programmed before starting any conversion. there is one dmar per channel type. the dma transfers can be enabled using the dmaen bit of dmae register. when the dclr bit of dmae register is set then the dma request is clea red on the reading of the register for which dma transfer has been enabled. 5.3.6 interrupts the adc generates the followi ng maskable interrupt signals: ? adc_eoc interrupt requests ? eoc (end of conversion) ? ech (end of chain) ? jeoc (end of injected conversion) ? jech (end of injected chain) ? wdgxl and wdgxh (watchdog threshold) interrupt requests interrupts are generated during the conversion process to signal events such as end of conversion as explained in register descript ion for ceocfr. two 7-bit regist ers named ceocfr (channel pending registers) and imr (interrupt mask register) are provided in order to check and enable the interrupt request to eic module. interrupts can be individually en abled on a channel by channel base by programming the cimr (channel interrupt mask register). several channel interrupt pending registers are also provided in or der to signal which of the channels? measurement has been completed. the analog watchdog interrupts are ha ndled by two 8-bit registers wtis r (watchdog threshold interrupt status register) and wtimr (watchdog threshold interrupt mask registe r) in order to check and enable the interrupt request to the eic module. the watchdog inte rrupt source sets two pending bits wdgxh and wdgxl in the wtisr for each of th e four channels being monitored.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-11 preliminary?subject to change without notice the ceocfr contains the in terrupt pending request status . if the user wants to cl ear a particular interrupt event status, then writing a ?1? to th e corresponding status bit clears the pending interrupt flag (at this write operation all the other bits of the ce ocfr must be maintained at ?0?). 5.3.7 external decode signals delay the adc provides several external decode signals to select which external channel has to be converted. in order to take into account the control switchi ng time of the external an alog multiplexer, a decode signals delay register (dsd r) is provided. the delay between the decoding signal selection and the actual start of conversion can be program med by writing the field dsd[0:7]. 5.3.8 power-down mode the analog part of the adc can be put in low power mode by setting the pwdn bit in the mcr. after releasing the reset signal the adc an alog module is kept in power-down mode by default, so this state must be exited before starti ng any operation by resetting th e appropriate bit in the mcr. the power-down mode can be requested at any time by setti ng the pwdn bit in the mcr. if a conversion is ongoing, the adc hard macrocell cannot immediatel y enter the power-down mode. in fact, the adc enters power-down mode only afte r completing the ongoing conversion. otherwise, the ongoing operation should be aborted manually by resetting the nstart bit and using the abortchain bit. bit adcstatus[0] in the msr is set on ly when adc enters power-down mode. after the power-down phase is completed the proc ess ongoing before the power-down phase must be restarted manually (by setting the appropriate start bit). resetting pwdn bit and setting nstart or jsta rt bit during the same cycle is forbidden. 5.3.9 auto-clock-off mode to reduce power consumption during the idle mode of operation (without going into power-down mode), an ?auto-clock-off? feature can be enabled by setti ng the acko bit in the mcr. when enabled, the analog clock is automatically switched off when no opera tion is ongoing, that is, no conversion is programmed by the user. 5.4 register descriptions 5.4.1 introduction table 5-5 lists the adc registers with thei r address offsets and reset values. table 5-5. adc digital registers register name address offset (hex.) reset value main configuration register (mcr) 000 0x0000_0001 main status register (msr) 004 0x0000_0001
pxd10 microcontroller reference manual, rev. 1 5-12 freescale semiconductor preliminary?subject to change without notice reserved 008 .. 00c ? interrupt status regi ster (isr) 010 0x0000_0000 reserved 014 ? channel pending register (ceocfr1) 018 0x0000_0000 channel pending register (ceocfr2) 01c 0x0000_0000 interrupt mask register (imr) 020 0x0000_0000 reserved 024 ? channel interrupt mask register (cimr1) 028 0x0000_0000 channel interrupt mask register (cimr2) 02c 0x0000_0000 watchdog threshold interrupt stat us register (wtisr) 030 0x0000_0000 watchdog threshold interrupt mask register (wtimr) 034 0x0000_0000 reserved 038 .. 03c ? dma enable register (dmae) 040 0x0000_0000 reserved 044 ? dma channel select register 1 (dmar1) 048 0x0000_0000 dma channel select register 2 (dmar2) 04c 0x0000_0000 threshold control register 0 (trc0) 050 0x0000_0000 threshold control register 1 (trc1) 054 0x0000_0000 threshold control register 2 (trc2) 058 0x0000_0000 threshold control register 3 (trc3) 05c 0x0000_0000 threshold register 0 (thrhlr0) 060 0x03ff_0000 threshold register 1 (thrhlr1) 064 0x03ff_0000 threshold register 2 (thrhlr2) 068 0x03ff_0000 threshold register 3 (thrhlr3) 06c 0x03ff_0000 reserved 070 .. 094 ? conversion timing register 1 (ctr1) 098 0x0000_0203 conversion timing register 2 (ctr2) 09c 0x0000_0203 reserved 0a0 .. 0a4 ? normal conversion mask register 1 (ncmr1) 0a8 0x0000_0000 normal conversion mask register 2 (ncmr2) 0ac 0x0000_0000 reserved 0b0 .. 0b4 ? injected conversion mask register 1 (jcmr1) 0b8 0x0000_0000 injected conversion mask register 2 (jcmr2) 0bc 0x0000_0000 table 5-5. adc digital registers (continued) register name address offset (hex.) reset value
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-13 preliminary?subject to change without notice reserved 0c0 ? decode signals delay register (dsdr) 0c4 0x0000_0000 power-down exit delay register (pdedr) 0c8 0x0000_0000 reserved 0cc .. 17c ? channel 32 data register (cdr32) 180 0x0000_0000 channel 33 data register (cdr33) 184 0x0000_0000 channel 34 data register (cdr34) 188 0x0000_0000 channel 35 data register (cdr35) 18c 0x0000_0000 channel 36 data register (cdr36) 190 0x0000_0000 channel 37 data register (cdr37) 194 0x0000_0000 channel 38 data register (cdr38) 198 0x0000_0000 channel 39 data register (cdr39) 19c 0x0000_0000 channel 40 data register (cdr40) 1a0 0x0000_0000 channel 41 data register (cdr41) 1a4 0x0000_0000 channel 43 data register (cdr43) 1ac 0x0000_0000 channel 44 data register (cdr44) 1b0 0x0000_0000 channel 45 data register (cdr45) 1b4 0x0000_0000 channel 46 data register (cdr46) 1b8 0x0000_0000 channel 47 data register (cdr47) 1bc 0x0000_0000 channel 48 data register (cdr48) 1c0 0x0000_0000 reserved 1c4 .. 1fc ? channel 64 data register (cdr64) 200 0x0000_0000 channel 65 data register (cdr65) 204 0x0000_0000 channel 66 data register (cdr66) 208 0x0000_0000 channel 67 data register (cdr67) 20c 0x0000_0000 channel 68 data register (cdr68) 210 0x0000_0000 channel 69 data register (cdr69) 214 0x0000_0000 channel 70 data register (cdr70) 218 0x0000_0000 channel 71 data register (cdr71) 21c 0x0000_0000 reserved 220 .. 2fc ? table 5-5. adc digital registers (continued) register name address offset (hex.) reset value
pxd10 microcontroller reference manual, rev. 1 5-14 freescale semiconductor preliminary?subject to change without notice table 5-6. bit access descriptions access type description read/write (rw) software can read and write to these bits. read-only (r) software can only read these bits. write-only (w) software can only write to these bits. write 1 to clear (w1c) software can clear bits by writing ?1?.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-15 preliminary?subject to change without notice 5.4.2 control logic registers 5.4.2.1 main configuration register (mcr) the main configuration register (mcr) pr ovides configuration settings for the adc. address: base + 0x0000 access: user read/write 0123456789101112131415 r owren wlside mode edglev trgen edge 0 nstart 0 jtrgen jedge jstart 0000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 adclk sel abort chain abort acko 0000 pwdn w reset00000000 00000001 figure 5-5. main configuration register (mcr) table 5-7. main configuration register (mcr) field descriptions bit description 0 owren: overwrite enable this bit enables or disables the functionality to overwrite unread converted data. 0 prevents overwrite of unread converted data; new result is discarded 1 enables converted data to be overwritten by a new conversion 1 wlside: write left/right-aligned 0 the conversion data is written right-aligned. 1 data is left-aligned (from 15 to (15 ? resolution + 1)). 2 mode: one shot/scan 0 one shot mode?configures the normal conversion of one chain. 1 scan mode?configures continuous chain conversion mode; when the programmed chain conversion is finished it restarts immediately. 3 edglev: edge or level selection for external start trigger 0 edge configuration for external trigger usage. 1 level configuration for external trigger usage. 4 trgen: external trigger enable. this bit must be set to use external triggering to start a conversion. 0 an external trigger cannot be used to start a conversion. 1 an external trigger can start a conversion.
pxd10 microcontroller reference manual, rev. 1 5-16 freescale semiconductor preliminary?subject to change without notice 5 start trigger edge/ level detection. the following table shows the interaction between the edge bit and the trgen and edglev bits. 6reserved must be kept at 0. 7 nstart: normal start conversion setting this bit starts the chain or scan conversion. resetting this bit during scan mode causes the current chain conversion to finish, then stops the operation. this bit stays high while the conversion is ongoing (or pending during injection mode). 0 causes the current chain conversion to finish and stops the operation 1 starts the chain or scan conversion 8reserved write of any value has no effect, read value is always 0. 9 jtrgen: injection external trigger enable 0 external trigger disabled for channel injection (injected conversion cannot be started using an external signal) 1 external trigger enabled for channel injection 10 jedge: injection trigger edge selection edge selection for external trigger, if jtrgen = 1. 0 selects falling edge for the external trigger 1 selects rising edge for the external trigger 11 jstart: injection start setting this bit will start the configured injected ana log channels to be converted by software. resetting this bit has no effect, as the injected chain conversion cannot be interrupted. 12:13 reserved write of any value has no effect, read value is always 0. 14 reserved must be kept at 0. 15:22 reserved write of any value has no effect, read value is always 0. 23 adclksel: analog cloc k frequency selector if this bit is set the ad_clk frequency is equal to ipg_clk frequency. otherwise, it is half of ipg_clk frequency. this bit can be written in power-down only. table 5-7. main configuration register (mcr) field descriptions (continued) bit description trgen edglev edge trigger detection 0 nn external triggering disabled 1 0 0 external trigger on falling edge of trigger 1 0 1 external trigger on rising edge of trigger 1 1 0 external trigger on low edge of trigger 1 1 1 external trigger on high edge of trigger
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-17 preliminary?subject to change without notice 24 abortchain: abort chain when this bit is set, the ongoing chain conversion is aborted. this bit is reset by hardware as soon as a new conversion is requested. 0 conversion is not affected 1 aborts the ongoing chain conversion 25 abort: abort conversion when this bit is set, the ongoing conversion is aborted and a new conversion is invoked. this bit is reset by hardware as soon as a new conversion is invoked. 0 conversion is not affected 1 aborts the ongoing conversion 26 acko: auto-clock-off enable if set, this bit enables the auto clock off feature. 0 auto clock off disabled 1 auto clock off enabled 27:28 reserved must be kept at 0. 29:30 reserved write of any value has no effect, read value is always 0. 31 pwdn: power-down enable when this bit is set, the analog module is requeste d to enter power down mode. when adc status is pwdn, resetting this bit starts adc transition to idle mode. 0 adc is in normal mode 1 adc has been requested to power down table 5-7. main configuration register (mcr) field descriptions (continued) bit description
pxd10 microcontroller reference manual, rev. 1 5-18 freescale semiconductor preliminary?subject to change without notice 5.4.2.2 main status register (msr) the main status register (msr) pr ovides status bits for the adc. address: base + 0x0004 access: user read-only 0123456789101112131415 r 0000000 n start j abort 00 j start 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r chaddr[0:6] 0 00 ack0 0 0 adcstatus[0:2] w reset00000000 00000001 figure 5-6. main status register (msr) table 5-8. main status register (msr) field descriptions field description 0:6 reserved write of any value has no effect, read value is always 0. 7 nstart this status bit is used to signal that a normal conversion is ongoing. 8 jabort this status bit is used to signal that an injected conversion has been aborted. this bit is reset when a new injected conversion starts. 9:10 reserved write of any value has no effect, read value is always 0. 11 jstart this status bit is used to signal that an injected conversion is ongoing. 12:14 reserved write of any value has no effect, read value is always 0. 15 reserved write of any value has no effect, read value is always 0. 16:22 chaddr[0:6]: channel under measure address this status bit is used to signal which channel is under measure. 23:25 reserved write of any value has no effect, read value is always 0. 26 acko: auto-clock-off enable this status bit is used to signal if the auto-clock-off feature is on.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-19 preliminary?subject to change without notice 5.4.3 interrupt registers 5.4.3.1 interrupt status register (isr) the interrupt status register (isr) cont ains interrupt status bits for the adc. 27:28 reserved write of any value has no effect, read value is always 0. 29:31 adcstatus[0:2] the value of this parameter depends on adc status: 000 idle 001 power-down 010 wait state 011 ? 100 sample 101 ? 110 conversion 111 ? address: base + 0x0010 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 0000 jeoc jech eoc ech w w1c w1c w1c w1c reset00000000 00000000 figure 5-7. interrupt status register (isr) table 5-9. interrupt status register (isr) field descriptions field description 0:24 reserved write of any value has no effect, read value is always 0. 25:26 reserved write of any value has no effect, read value is always 0. 27 reserved write of any value has no effect, read value is always 0 table 5-8. main status register (m sr) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 5-20 freescale semiconductor preliminary?subject to change without notice 5.4.3.2 channel pending registers (ceocfr[1..2]) the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-5 . ceocfr1 = end of conversion pending interrupt for channel 32 to 63 (extended internal channels) ceocfr2 = end of conversion pending interrupt for channel 64 to 95 (external channels) 28 end of injected channel conversion interrupt (jeoc) flag it is the interrupt of the digital end of conversion fo r the injected channel; active when set. when this bit is set, a jeoc interrupt has occurred. 29 end of injected chain conversion interrupt (jech) flag it is the interrupt of the digital end of chain conver sion for the injected channel; active when set. when this bit is set, a jech interrupt has occurred. 30 end of channel conversion interrupt (eoc) flag it is the interrupt of the digital end of conversion. when this bit is set, an eoc interrupt has occurred. 31 end of chain conversion interrupt (ech) flag it is the interrupt of the digital end of chain conver sion. when this bit is set, an ech interrupt has occurred. address: base + 0x0018 access: user read/write 0123456789101112131415 r eoc_ch63 eoc_ch62 eoc_ch61 eoc_ch60 eoc_ch59 eoc_ch58 eoc_ch57 eoc_ch56 eoc_ch55 eoc_ch54 eoc_ch53 eoc_ch52 eoc_ch51 eoc_ch50 eoc_ch49 eoc_ch48 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eoc_ch47 eoc_ch46 eoc_ch43 eoc_ch44 eoc_ch43 eoc_ch42 eoc_ch41 eoc_ch40 eoc_ch39 eoc_ch38 eoc_ch37 eoc_ch36 eoc_ch35 eoc_ch34 eoc_ch33 eoc_ch32 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 5-8. channel pending register 1 (ceocfr1) table 5-9. interrupt status register (isr) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-21 preliminary?subject to change without notice 5.4.3.3 interrupt mask register (imr) the interrupt mask register (imr) contains the interrupt enable bits for the adc. address: base + 0x001c access: user read/write 0123456789101112131415 r eoc_ch95 eoc_ch94 eoc_ch93 eoc_ch92 eoc_ch91 eoc_ch90 eoc_ch89 eoc_ch88 eoc_ch87 eoc_ch86 eoc_ch85 eoc_ch84 eoc_ch83 eoc_ch82 eoc_ch81 eoc_ch80 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eoc_ch79 eoc_ch78 eoc_ch77 eoc_ch76 eoc_ch75 eoc_ch74 eoc_ch73 eoc_ch72 eoc_ch71 eoc_ch70 eoc_ch69 eoc_ch68 eoc_ch67 eoc_ch66 eoc_ch65 eoc_ch64 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 5-9. channel pending register 2 (ceocfr2) table 5-10. channel pending register s (ceocfr[1..2]) field descriptions field description 31 eoc_ch0 when set, the measure of channel 0 is completed. n eoc_chn when set, the measure of channel n is completed. address: base + 0x0020 access: user read/write 0123456789101112131415 r0000000 0 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 0000 msk jeoc msk jech msk eoc msk ech w reset00000000 00000000 figure 5-10. interrupt mask register (imr)
pxd10 microcontroller reference manual, rev. 1 5-22 freescale semiconductor preliminary?subject to change without notice table 5-11. interrupt mask register (imr) field descriptions field description 0:24 reserved write of any value has no effect, read value is always 0. 25:26 reserved must be kept at 0. 27 reserved must be kept at 0. 28 mskjeoc: mask bit for jeoc when set, the jeoc interrupt is enabled. 29 mskjech: mask bit for jech when set, the jech interrupt is enabled. 30 mskeoc: mask bit for eoc when set, the eoc interrupt is enabled. 31 mskech: mask bit for ech when set, the ech interrupt is enabled.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-23 preliminary?subject to change without notice 5.4.3.4 channel interrupt mask register (cimr[1..2]) the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-5 . cimr1 = enable bits for channels 32 to 63 (extended internal channels) cimr2 = enable bits for channe ls 64 to 95 (external channels) address: base + 0x0028 access: user read/write 0123456789101112131415 r cim 63 cim 62 cim 61 cim 60 cim 59 cim 58 cim 57 cim 56 cim 55 cim 54 cim 53 cim 52 cim 51 cim 50 cim 49 cim 48 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cim 47 cim 46 cim 43 cim 44 cim 43 cim 42 cim 41 cim 40 cim 39 cim 38 cim 37 cim 36 cim 35 cim 34 cim 33 cim 32 w reset00000000 00000000 figure 5-11. channel interrupt mask register 1 (cimr1) address: base + 0x002c access: user read/write 0123456789101112131415 r cim 95 cim 94 cim 93 cim 92 cim 91 cim 90 cim 89 cim 88 cim 87 cim 86 cim 85 cim 84 cim 83 cim 82 cim 81 cim 80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cim 79 cim 78 cim 77 cim 76 cim 75 cim 74 cim 73 cim 72 cim 71 cim 70 cim 69 cim 68 cim 67 cim 66 cim 65 cim 64 w reset00000000 00000000 figure 5-12. channel interrupt mask register 2 (cimr2) table 5-12. channel interrupt mask register (cimr[1..2]) field descriptions field description 31 cim0: interrupt enable when set (cim0 = 1), interrupt for channel 0 is enabled. n cimn: interrupt enable when set (cimn = 1), interrupt for channel n is enabled.
pxd10 microcontroller reference manual, rev. 1 5-24 freescale semiconductor preliminary?subject to change without notice 5.4.3.5 watchdog threshold interr upt status register (wtisr) 5.4.3.6 watchdog threshold inte rrupt mask register (wtimr) reset value: 0x0000_0000 address: base + 0x0030 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000 0 wdg 3h wdg 2h wdg 1h wdg 0h wdg 3l wdg 2l wdg 1l wdg 0l w w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 5-13. watchdog threshold interrupt status register (wtisr) table 5-13. watchdog threshold interrupt st atus register (wtisr) field descriptions field description 0:23 reserved write of any value has no effect, read value is always 0. 24:27 wdgxh [x = 0..3] this corresponds to the status flag generated on the converted value being higher than the programmed higher threshold. 28:31 wdgxl [x = 0..3] this corresponds to the status flag generated on the converted value being lower than the programmed lower threshold. address: base + 0x0034 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0msk wdg 3h msk wdg 2h msk wdg 1h msk wdg 0h msk wdg 3l msk wdg 2l msk wdg 1l msk wdg 0l w reset00000000 00000000 figure 5-14. watchdog threshold interrupt mask register (wtimr)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-25 preliminary?subject to change without notice table 5-14. watchdog threshold interrupt m ask register (wtimr) field descriptions field description 0:23 reserved write of any value has no effect, read value is always 0. 24:27 mskwdgxh [x = 0..3] this corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold. when set the interrupt is enabled. 28:31 mskwdgxl [x = 0..3] this corresponds to the mask bit for the interrupt gene rated on the converted value being lower than the programmed lower threshold. when set the interrupt is enabled.
pxd10 microcontroller reference manual, rev. 1 5-26 freescale semiconductor preliminary?subject to change without notice 5.4.4 dma registers 5.4.4.1 dma enable register (dmae) the dma enable (dmae) register sets up the dma for use with the adc. address: base + 0x0040 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 000000 dcl r dma en w reset00000000 00000000 figure 5-15. dma enable register (dmae) table 5-15. dma enable register (dmae) field descriptions field description 0:29 reserved write of any value has no effect, read value is always 0. 30 dclr: dma clear sequence enable 0 dma request cleared by acknowledge from dma controller 1 dma request cleared on read of data registers 31 dmaen: dma global enable 0 dma feature disabled 1 dma feature enabled
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-27 preliminary?subject to change without notice 5.4.4.2 dma channel select register (dmar[1..2]) the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-5 . 31dmar1 = enable bits for channels 32 to 63 (extended internal channels) dmar2 = enable bits for channels 64 to 95 (external channels) reset value: 0x0000_0000 address: base + 0x0048 access: user read/write 0123456789101112131415 r dma 63 dma 62 dma 61 dma 60 dma 59 dma 58 dma 57 dma 56 dma 55 dma 54 dma 53 dma 52 dma 51 dma 50 dma 49 dma 48 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dma 47 dma 46 dma 43 dma 44 dma 43 dma 42 dma 41 dma 40 dma 39 dma 38 dma 37 dma 36 dma 35 dma 34 dma 33 dma 32 w reset00000000 00000000 figure 5-16. dma channel select register 1 (dmar1) address: base + 0x004c access: user read/write 0123456789101112131415 r dma 95 dma 94 dma 93 dma 92 dma 91 dma 90 dma 89 dma 88 dma 87 dma 86 dma 85 dma 84 dma 83 dma 82 dma 81 dma 80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dma 79 dma 78 dma 77 dma 76 dma 75 dma 74 dma 73 dma 72 dma 71 dma 70 dma 69 dma 68 dma 67 dma 66 dma 65 dma 64 w reset00000000 00000000 figure 5-17. dma channel select register 2 (dmar2) table 5-16. dma channel select register (dmar[1..2]) field descriptions field description 31 dma0: dma enable when set (dma0 = 1), channel 0 is enabled to transfer data in dma mode. n dman: dma enable when set (dman = 1), channel n is enabled to transfer data in dma mode.
pxd10 microcontroller reference manual, rev. 1 5-28 freescale semiconductor preliminary?subject to change without notice 5.4.5 threshold registers 5.4.5.1 introduction these four registers are used to store the user programmable lower and upper thresholds? values. the inverter bit and the mask bit for mask the interrupt are stored in the trc registers. 5.4.5.2 threshold control register (trcx, x = [0..3]) reset value: 0x0000_0000 0123456789101112131415 reserved ? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 thr en thr inv res. reserved thrch rw rw ? ? rw figure 5-18. threshold control register (trcx, x = [0..3]) table 5-17. threshold control register (trcx, x = [0..3]) field descriptions field description 0:15 reserved write of any value has no effect, read value is always 0. 16 thren: threshold enable when set, this bit enables the threshold detection feature for the selected channel. 17 thrinv: invert the output pin setting this bit inverts the behavior of the threshold output pin. 18 reserved must be kept at 0. 19:24 reserved write of any value has no effect, read value is always 0. 25:31 thrch: choose the channel for threshold comparison.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-29 preliminary?subject to change without notice 5.4.5.3 threshold register (thrhlr[0:3]) the four thrhlr n registers are used to store the user -programmable thresholds? 10-bit values. address: base + 0x0060 (thrhlr0) base + 0x0064 (thrhlr1) base + 0x0068 (thrhlr2) base + 0x006c (thrhlr3) access: user read/write 0123456789101112131415 r000000 thrh w reset00000011 11111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 thrl w reset00000000 00000000 figure 5-19. threshold register (thrhlr[0:3]) table 5-18. threshold register (thrhlr[0:3]) field descriptions field description 0:5 reserved write of any value has no effect, read value is always 0. 6:15 thrh: high threshold value for channel n . 16:21 reserved write of any value has no effect, read value is always 0. 22:31 thrl: low threshold value for channel n .
pxd10 microcontroller reference manual, rev. 1 5-30 freescale semiconductor preliminary?subject to change without notice 5.4.6 conversion timing registers ctr[1..2] the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-5 . ctr1 = associated to extended in ternal channels (from 32 to 63) ctr2 = associated to external channels (from 64 to 95) address: base + 0x0098 (ctr1) base + 0x009c (ctr2) access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inp latch 0 offshift [0:1] 0 inpcmp [0:1] 0 inpsamp[0:7] w reset00000010 00000101 figure 5-20. conversion ti ming registers ctr[1..2] table 5-19. conversion timing registers ctr[1..2] field descriptions field description 0:15 reserved write of any value has no effect, read value is always 0. 16 inplatch configuration bit for latching phase duration 17 reserved write of any value has no effect, read value is always 0. 18:19 offshift[0:1] configuration for offset shift characteristic 00 no shift (that is the transition between codes 000h and 001h) is reached when the a vin (analog input voltage) is equal to 1 lsb. 01 transition between code 000h and 001h is reached when the a vin is equal to1/2 lsb 10 transition between code 00h and 001h is reached when the a vin is equal to 0 11 not used 20 reserved write of any value has no effect, read value is always 0. 21:22 inpcmp[0:1] configuration bits for comparison phase duration 23 reserved write of any value has no effect, read value is always 0.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-31 preliminary?subject to change without notice 5.4.7 mask registers 5.4.7.1 introduction these registers are used to program which of the 96 input channels must be converted during normal and injected conversion. 5.4.7.2 normal conversion mask registers (ncmr[1..2]) the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-5 . ncmr1 = enable bits of normal sampling for ch annel 32 to 63 (extended internal channels) reset value: 0x0000_0000 24:31 inpsamp[0:7] configuration bits for sampling phase duration address: base + 0x00a8 access: user read/write 0123456789101112131415 r ch63 ch62 ch61 ch60 ch59 ch58 ch57 ch56 ch55 ch54 ch53 ch52 ch51 ch50 ch49 ch48 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch47 ch46 ch45 ch44 ch43 ch42 ch41 ch40 ch39 ch38 ch37 ch36 ch35 ch34 ch33 ch32 w reset00000000 00000000 figure 5-21. normal conversion mask register 1 (ncmr1) table 5-20. normal conversion mask registers (ncmr[1..2]) field descriptions field description 31 ch0: sampling enable when set sampling is enabled for channel 0. n chn: sampling enable when set sampling is enabled for channel n. table 5-19. conversion timing registers ct r[1..2] field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 5-32 freescale semiconductor preliminary?subject to change without notice 5.4.7.3 injected conversion mask registers (jcmr[1..2]) the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-5 . jcmr1 = enable bits of inject ed sampling for channel 32 to 63 (extended internal channels) jcmr2 = enable bits of inj ected sampling for channel 64 to 95 (external channels) reset value: 0x0000_0000 address: base + 0x00b8 access: user read/write 0123456789101112131415 r ch63 ch62 ch61 ch60 ch59 ch58 ch57 ch56 ch55 ch54 ch53 ch52 ch51 ch50 ch49 ch48 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch47 ch46 ch45 ch44 ch43 ch42 ch41 ch40 ch39 ch38 ch37 ch36 ch35 ch34 ch33 ch32 w reset00000000 00000000 figure 5-22. injected conversion mask register 1 (jcmr1) address: base + 0x00bc access: user read/write 0123456789101112131415 r ch95 ch94 ch93 ch92 ch91 ch90 ch89 ch88 ch87 ch86 ch85 ch84 ch83 ch82 ch81 ch80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch79 ch78 ch77 ch76 ch75 ch74 ch73 ch72 ch71 ch70 ch69 ch68 ch67 ch66 ch65 ch64 w reset00000000 00000000 figure 5-23. injected conversion mask register 2 (jcmr2) table 5-21. injected conversion mask registers (jcmr[1..2]) field descriptions field description 31 ch0: sampling enable when set, sampling is enabled for channel 0. n chn: sampling enable when set, sampling is enabled for channel n.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-33 preliminary?subject to change without notice 5.4.8 delay registers 5.4.8.1 decode signals delay register (dsdr) reset value: 0x0000_0000 5.4.8.2 power-down exit delay register (pdedr) reset value: 0x0000_0000 address: base + 0x00c4 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 dsd[0:7] w reset00000000 00000000 figure 5-24. decode signals delay register (dsdr) table 5-22. decode signals delay register (dsdr) field descriptions field description 0:23 reserved write of any value has no effect, read value is always 0. 24:31 dsd[0:7]: delay between the external decode signals and the start of the sampling phase it is used to take into account the se ttling time of the external multiplexer. the decode signal delay is calculated as: dsd 1/ frequency of system clock address: base + 0x00c8 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 pded[0:7] w reset00000000 00000000 figure 5-25. power-down exit delay register (pdedr)
pxd10 microcontroller reference manual, rev. 1 5-34 freescale semiconductor preliminary?subject to change without notice table 5-23. power-down exit delay register (pdedr) field descriptions field description 0:23 reserved write of any value has no effect, read value is always 0. 24:31 pded[0:7]: delay between the power-down bit reset and the start of conversion the power down delay is calculated as: pded x 1/frequency of adc clock.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 5-35 preliminary?subject to change without notice 5.4.9 data registers 5.4.9.1 introduction adc conversion results are stored in data re gisters. there is one register per channel. the 0 to 31 range shown below is the maximum range for the channel type. for the exact number of available channels, please refer to table 5-5 . cdr[32..63] = extended internal channels cdr[64..95] = external channels each data register also gives information rega rding the corresponding result as described below. 5.4.9.2 channel data register (cdr[0..95]) address: see ta b l e 5 - 5 access: user read/write 0123456789101112131415 r0000000 0 0000 va lid over w result [0:1] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 cdata[0:9] w reset00000000 00000000 figure 5-26. channel data register (cdr[0..95]) table 5-24. channel data register (cdr[0..95]) field descriptions field description 0:11 reserved write of any value has no effect, read value is always 0. 12 valid used to notify when the data is valid (a new value has been written). it is automatically cleared when data is read. 13 overw: overwrite data this bit signals that the previous converted dat a has been overwritten by a new conversion. this functionality depends on the value of mcr[owren]: ? when owren = 0, then overw is frozen to 0 and cdat a field is protected aga inst being overwritten until being read. ? when owren = 1, then overw flags the cdata field overwrite status. 0 converted data has not been overwritten 1 previous converted data has been overwritten before having been read
pxd10 microcontroller reference manual, rev. 1 5-36 freescale semiconductor preliminary?subject to change without notice 14:15 result[0:1] this bit reflects the mode of conversion for the corresponding channel. 00 data is a result of normal conversion mode 01 data is a result of injected conversion mode 10 reserved 11 reserved 16:21 reserved write of any value has no effect, read value is always 0 22:31 cdata[0:9]: channel 0-95 converted data table 5-24. channel data register (cdr[0..95]) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 6-1 preliminary?subject to change without notice chapter 6 boot assist module (bam) this chapter describes the boot assist module (bam). 6.1 overview the boot assist module is a bl ock of read-only memory containing vle code which is executed according to the boot mode of the device. the bam allows you to download code into internal sram through the followi ng serial protocol and execute it afterwards: ? flexcan (without autobaud) ? linflex (without autobaud) 6.2 features the bam provides the following features: ? locate and detect application boot code ? pxd10 in static mode if internal flash is not initialized or invalid ? system can recover from static mode only by reset ? programmable 64-bit password pr otection for serial boot mode ? serial boot loads the application boot code from a flexcan or linflex bus into internal sram ? censorship protection for internal flash module 6.3 boot modes the pxd10 supports the following boot modes: ? single chip (sc) - the device boot s from the first bootable section of the flash memory main array. ? serial boot (sbl) - the device downloads boot c ode from either linflex or flexcan interface and then executes it. if booting is not possible with the se lected configuration (e.g., if no boot id is found in the selected boot location) then the device enters the static mode.
pxd10 microcontroller reference manual, rev. 1 6-2 freescale semiconductor preliminary?subject to change without notice 6.4 memory map the bam code resides in a reserved 8 kb rom mapped from address 0xffff_c000. the address space and memory used by bam application is shown in table 6-1 . the ram location where to download the code can be any 4 byte aligned location starting from the address 0x4000_0100. 6.5 functional description 6.5.1 entering boot modes the pxd10 detects the boot mode based on external pins and device status (see figure 6-1 ). to boot either from flexcan or linflex, the device must be forced into an alternate boot loader mode via the fab (force alternate boot m ode) pin which must be asserted be fore initiating the reset sequence. the type of alternate boot mode is selected according to the abs (alternate boot selector) pin (see table 6-2 ). table 6-1. bam memory organization parameter address bam entry point 0xffff_c000 downloaded code base address 0x4000_0100
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 6-3 preliminary?subject to change without notice figure 6-1. boot mode selection table 6-2. hardware configuration to select boot mode fab abs standby-ram boot flag boot id boot mode 1 0 0 - linflex 11 0 - flexcan 0 - 0 valid sc (single chip) 0 - 0 not found static mode por fabm = 1 abs = ? serial boot (sbl) linflex serial boot (sbl) flexcan y abs=0 abs=1 flash boot-id in any boot sector? flash boot from lowest sector n static mode no boot-id the grey blocks represent action done by hardware; the white ones action done by software (bam).
pxd10 microcontroller reference manual, rev. 1 6-4 freescale semiconductor preliminary?subject to change without notice 6.5.2 reset configuration half word source (rchw) pxd10 flash memory is partitione d into boot sectors shown in table 6-4 . each boot sector contains at offset 0x00 the reset configurati on half-word (rchw). 0123456789101112131415 r reserved boot_id[0:7] w reset: 0000000000000000 figure 6-2. reset configuration half word (rchw) table 6-3. rchw field descriptions field description 0-7 reserved 8-15 boot_id[0:7] is valid if its value is 0x5a, then the sector is considered bootable
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 6-5 preliminary?subject to change without notice figure 6-3. pxd10 flash memory partitioning and rchw search 6.5.3 single chip boot mode in single chip mode the hardware se arches flash boot sector for a valid boot id. as soon the device detects a bootable sector, it jumps within this sector and reads the 32-bit word at offset 0x4. this word is the address where the startup code is located (reset boot vector). table 6-4. flash boot sector block address 0 0x0000_0000 1 0x0000_8000 2 0x0000_c000 3 0x0001_0000 4 0x0001_8000 32k boot information 16k 16k 32k $0000 0000 $0000 8000 $0000 c000 $0001 0000 $0002 0000 internal flash rchw $0000 0000 $0000 0004 $0000 0008 $0000 000c 32k $0001 8000 boot information 128k boot information boot information boot information application start address application application
pxd10 microcontroller reference manual, rev. 1 6-6 freescale semiconductor preliminary?subject to change without notice then the device executes this start up code. an user application should ha ve a valid instruction at the reset boot vector address. if a valid rchw is not found, the bam code is execut ed. in this case bam move s the pxd10 into static mode. 6.5.3.1 boot and alternate boot some applications require an altern ate boot sector so that the main boot can be erased and reprogrammed in the field. when an alternate boot is needed, user can create two bootable sectors; the lowest sector shall be the main boot sector and the highest shall be the alternate boot sector. the alternat e boot sector does not need to be consecutive to the main boot sector. this scheme allows to ensure that there is always one active boot sect or by erasing one of the boot sectors only: ? sector shall be activated (that is, program a valid boot_id instead of 0xff as initially programmed). ? sector shall be deactivated writing to 0 some of the bits boot-i d bit field (bit1 and/or bit3, and/or bit4, and/or bit6). 6.5.4 boot through bam 6.5.4.1 executing bam single chip mode is managed by ha rdware and bam does not participate. bam is executed only in the following two cases: ? serial boot mode has been selected by fab pin ? hardware has not found a valid b oot-id in any flash boot locations if one of these conditions is true , the device fetches code at locat ion 0xffff_c000 and bam application starts.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 6-7 preliminary?subject to change without notice 6.5.4.2 bam software flow with reference to figure 6-4 a description of bam logic flow is done. figure 6-4. bam logic flow the first action is to save the ini tial device configuration. in this way is possible to restore the initial configuration after downloading the new code but before executing it. this allows the new code being executed as the device was just coming out of reset. the bmode and abd fields of th e sscm status register (see section 38.2.2.1, system status register (status) ) indicate which boot has to be executed (see table 6-5 ). if bmode field shows either a single-chip value (0 11) or the reserved values, the boot mode is not considered valid and the bam pushe s the device into static mode. in all other cases the code of the relative boot is called. data is downloaded and saved into proper sram location. bam entry 0xffff_c000 save default configuration check boot mode boot mode valid? static mode restore default configuration no download new code and save it into sram yes restore default configuration execute new code which boot mode is selected is verified by reading the sscm_status register (bmode and abd)
pxd10 microcontroller reference manual, rev. 1 6-8 freescale semiconductor preliminary?subject to change without notice then, the initial device configurati on is restored and the code jumps to the address of downloaded code. at this point bam has ju st finished its task. if there is any error (that is, communication error, wrong boot selected, etc.), bam restores the default configuration and puts the device into static mode. st atic mode means the devi ce enters the low power mode safe and the processor executes a wait instruct ion. it is needed if the device cannot boot in the mode which was selected. during bam executi on and after, the mode reported by the field s_current_mode of the register me_gs in the module mc_me module is "drun". 6.5.4.3 bam resources bam uses/initializes the following mcu resources: ? mc_me and mc_cgm to initia lize mode and clock sources ? flexcan 0, linflex 0 and their pads when performing serial boot mode ? sscm to check the boot mode and during password check (see table 6-5 and figure 6-5 ) ? external oscillator ? swt (the bam disables it) the following hardware resources are used only when autobaud feature is selected: ? stm to measure the baud rate ? cmu to measure the external clock frequenc y related to the internal rc clock source ? fmpll to work with system clock near the ma ximum allowed frequency (this to have higher resolution during baud rate measurement). as already mentioned, the initial configuration is restored befo re executing the downloaded code. the system clock is selected direct ly from the external oscillator. t hus the oscillator frequency defines baud rates for serial interfaces used to download the user application (see table 6-6 ). table 6-5. fields of sscm status register used by bam field description bmode bmode device boot mode. 000 flexray boot serial boot loader (future use) 001 can serial boot loader 010 sci serial boot loader 011 single chip other values are reserved table 6-6. serial boot mode without autobaud - baud rates crystal frequency (mhz) linflex baud rate (baud) can bit rate (bit/sec) f extal f extal / 833 f extal / 40 8 9600 200k 12 14400 300k
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 6-9 preliminary?subject to change without notice 6.5.4.4 download and execute the new code from high level perspective, the download protocol follows steps: 0. (optional step) send message and receive acknow ledge message for autobaud or autobit rate selection 1. send 64 bits password 2. send start address, size of down loded code in bytes and vle bit 1 3. download data 4. execute code from start address. each step must be complete before the next step starts. the communication is done in half duplex manner, any transmission from host is foll owed by the mcu transmission: ? host sends data to mcu and start waiting ? mcu echoes to host the data received ? mcu verifies if echoes is correct ? if data is correct host can continue to send data ? if data is not correct host stops to transmit and mcu need to be reset. all multi-byte data structures are sent with msb first. a more detailed descripti on of these steps follows. 6.5.4.5 download 64-bit password and password check the first 64 bits received represen t the password. this password is sent to the password check procedure which verify if it is correct. password check data flow is shown in figure 6-5 where: ? sscm_status.sec = 1 means flash secured ? sscm_status.pub = 1 means flash with public access. in case of flash with public access, the received password is compared with the public password 0xfeed_face_cafe_beef. 16 19200 400k 20 24000 500k 40 48000 1m 1. since this device supports only vle code and it does not suppor t book e code, this flag is used only for backward compatibili ty. table 6-6. serial boot mode without autobaud - baud rates (continued) crystal frequency (mhz) linflex baud rate (baud) can bit rate (bit/sec)
pxd10 microcontroller reference manual, rev. 1 6-10 freescale semiconductor preliminary?subject to change without notice if public access is not allowed but the flash is not secured, the receiv ed password is compared with the value saved on nvpwd0 and nvpwd1 registers. in both of previous case s, comparison is done by bam applicat ion. if it goes wr ong, bam pushes mcu into static mode. in case of public access not allowed and flash secured, the password is written into sscm.pwcmph-l registers. after a fixed time waiting, comparison is done by hardware. then bam verifies again sscm_status?s sec flag: ? sec = 0, flash is now unsecur ed and bam continues its task ? sec = 1, flash is still secured because pass word was wrong; bam puts mcu to standby mode. this fixed time depends on the external crystal os cillator frequency (fxosc). with fxosc of 12 mhz, the fixed time is 350 ms. figure 6-5. password check flow 6.5.4.6 download start addre ss, vle bit and code size the next 8 bytes received by the mcu contain a 32-bit start address, th e vle mode bit and a 31-bit code length as shown in figure 6-6 . the vle bit (variable length instruction) is used to indicate for which instruction set the code has been compiled. this device family supports only vle = 1, the bit is used for backward compatibility. write received password to sscm.pwcmph-l verify if flash is unsecured sscm. status. pub sscm. status. sec comparison with password saved on nvpwd0-1 =1 =0 =1 =0 wait comparison with 0xfeedface cafebeef
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 6-11 preliminary?subject to change without notice the start address defines wh ere the received data will be stored and where the mcu will branch after the download is finished. the two lsb bits of the star t address are ignored by th e bam program, such that the loaded code should be 32-bit word aligned. the length defines how many data bytes have to be loaded. figure 6-6. start address, vle bit and download size in bytes 6.5.4.7 download data each byte of data received is stored into device? s sram, starting from the address specified in the previous protocol step. the address increments until the num ber of bytes of data received matches the numbe r of bytes specified in the previous protocol step. since the sram is protected by 32-bi t wide error correction code (ecc), bam always writes bytes into sram grouped into 32-bit words. if the last byte received does not fa ll onto a 32-bit boundary, bam fills it with 0 bytes. then a ?dummy? word (0x0000_0000) is written to avoid ecc error during core prefetch. 6.5.4.8 execute code the bam program waits for the last ech o message transmission being completed. then it restores the initial mcu c onfiguration and jumps to the loaded code at start address which was received in step 2 of the protocol. at this point bam has finished its tasks and mcu is controlled by new code executing from sram. start_address[31:16] start_address[15:0] vle code_length[30:16] code_length[15:0]
pxd10 microcontroller reference manual, rev. 1 6-12 freescale semiconductor preliminary?subject to change without notice 6.5.5 boot from uart 6.5.5.1 configuration boot from uart protocol is implemented by the linflex 0 module. the pins used are: ? linflex_tx corresponds to pin pb[2] ? linflex_rx corresponds to pin pb[3]. the system clock is driven by an external oscillator. the linflex controller is configur ed to operate at a baud rate = system clock frequency/833 (see table 6-6 for baud rate example), using an 8-bit data frame without parity bit and 1 stop bit. figure 6-7. linflex bit timing in uart mode 6.5.5.2 protocol table 6-7 summarizes the protocol and bam action during this boot mode. table 6-7. uart boot mode download protocol (autobaud disabled) protoc ol step host sent message bam response message action 1 64-bit password (msb first) 64-bit password password checked for validity and compared against stored password. 2 32-bit store address 32-bit store address load address is stored for future use. 3 vle bit + 31-bit number of bytes (msb first) vle bit + 31-bit number of bytes (msb first) size of download is stored for future use. verify if vle bit is set to 1 4 8 bits of raw binarydata 8 bits of raw binary data 8-bit data are packed into 32-bit words. this word is saved in sram starting from the ?load address?. ?load address? increments until the number of data received and stored matches the size as specified in the previous step. 5 none none branch to dowloaded code
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 6-13 preliminary?subject to change without notice 6.5.6 bootstrap with can 6.5.6.1 configuration boot from flexcan protocol is implemented by the flexcan _0 module. the pins used are: ? can_tx corresponds to pin pb[0] ? can_rx corresponds to pin pb[1]. boot from flexcan uses the system cl ock driven by an external oscillator. the flexcan controller is confi gured to operate at a baud rate = system clock fr equency/40 (see table 6-6 for examples of baud rate). it uses the standard 11-bit identifier format detailed in fl excan 2.0a specification. flexcan controller bit timing is pr ogrammed with 10 time quanta, and th e sample point is 2 time quanta before the end, as shown in figure 6-8 . figure 6-8. flexcan bit timing sync_seg time segment 1 time segment 2 sample point nrz signal transmit point 1 time quantum time quanta time quanta 7 2 1 bit time 1 time quantum = 4 sy stem clock periods
pxd10 microcontroller reference manual, rev. 1 6-14 freescale semiconductor preliminary?subject to change without notice 6.6 protocol table 6-8 summarizes the protocol and bam action during this boot mode. all data are transmitted byte wise. 6.6.1 interrupts no interrupts are generated by or are enabled by the bam. table 6-8. flexcan boot mode download protocol (autobaud disabled) protocol step host sent message bam response message action 1 can id 0x011+ 64-bit password can id 0x001+ 64-bit password password checked for validity and compared against stored password. 2 can id 0x012+ 32-bit store address+ vle bit+ 31-bit number of bytes can id 0x002+ 32-bit store address+ vle bit+ 31-bit number of bytes load address is stored for future use. size of download is stored for future use. verify if vle bit is set to 1 3 can id 0x013+ 8 to 64 bits of raw binary data can id 0x003+ 8 to 64 bits of raw binary data 8-bit data are packed into 32-bit words. these words are saved in sram starting from the ?load address?. ?load address? increments until the number of data received and stored matches the size as specified in the previous step. 5 none none branch to dowloaded code table 6-9. system clock frequency related to external clock frequency f osc [mhz] f rc /f osc 1 1 these values and consequently the f sys suffer from the precision of the rc internal oscillator used to measure f osc through the cmu module. f sys [mhz] 4 - 8 4 - 2 16 - 32 8 - 12 2 - 4/3 32 - 48 12 - 16 4/3 - 1 36 - 48 16 - 24 1 - 2/3 32 - 48 > 24 < 2/3 > 24
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 7-1 preliminary?subject to change without notice chapter 7 can sampler 7.1 introduction the can sampler peripheral has been designed to store the fi rst identifier of can message "detected" on the can bus while no precise clock (crystal) is running at that time on the device, typically in low power modes (stop, halt or standby) or in run mode with crystal switched off. depending on both can baudrate and low power mode used, it is possible to catch either the first or the second can frame by sampling one of two can rx ports and storing all samples in internal registers. after selection of the mode (first or second frame), the can sampler stores samples of the 48 bits or skips the first frame and stores samples of the 48 bits of second frame using the 16-mhz irc oscillator and the 5-bit clock prescaler. after completion, software has to process the sample d data in order to rebuild the 48 minimal bits. figure 7-1. extended can data frame base identifier (11 bit) sof spr extended identifier (18 bit) ide-bit rtr-bit r1 r0 data length code
pxd10 microcontroller reference manual, rev. 1 7-2 freescale semiconductor preliminary?subject to change without notice 7.2 main features ? store 384 samples, equivalent to 48 can bit @8 samples/bit ? sample frequency from 500 khz up to 16 mhz, equivalent at 8 samp les/bit to can baud rates of 62.5 kbps to 2 mbps ? user selectable can rx samp le port, can0rx or can1rx ? 16 mhz irc clock ? 5-bit clock prescaler ? configurable trigger mode (immediate, next frame) ? flexible samples processing by software ? very low power consumption 7.3 register description the can registers are listed in table 7-1 . 7.3.1 can sampler control register table 7-1. can registers register name address offset reset value location control register (cr) 00h 0000 0000h on page 2 sample registers 0 04h xxxx xxxxh 1 1 the initialization data is unknown. they wil l be filled only after first can sampling. on page 3 sample register 1 08h xxxx xxxxh 1 on page 3 ....... .... .... ....... .... .... sample register 11 30h xxxx xxxxh 1 on page 3 address offset: 0x00 reset value: 0000 0000h 0123456789101112131415 r 0000000000000000 w 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rx_c ompl ete busy active _ck 000 mode can_rx_sel brp can_ smpl r_en w figure 7-2. control register (cr)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 7-3 preliminary?subject to change without notice 7.3.2 can sampler sample registers 0?11 the can sampler sample registers 0?11 have the same structure; figure 7-3 and figure 7-4 show this structure for registers 0 and 11, respectively. table 7-2. control register (cr) field description 0-15 reserved 16 rx_complete 1: can frame is stored in the sample registers 0: can frame has not been stor ed in the sample registers 17 busy this bit indicates the status of sampling 1: sampling is ongoing 0: sampling is complete or has not started 18 active_ck this bit indicates which is current clock for sample registers i.e xmem_ck. 1: rc_clk is currently xmem_ck 0: ipg_clk_s is currently xmem_ck 19-21 reserved these are reserved bits. these bits are always read as ?0? . 22 mode 0:skip the first frame and sample and store the second frame (sf_mode) 1:sample and store the first frame (ff_mode) 23-25 can_rx_sel these bits determine which rx bit is sampled. 000: rx0 is selected 001: rx1 is selected 010: rx2 is selected 011: rx3 is selected 100: rx4 is selected 101: rx5 is selected (not valid on this device) 110: rx6 is selected (not valid on this device) 111: rx7 is selected (not valid on this device) 26-30 brp baud rate prescaler these bits are used to set the baud rate before going into standby mode 00000: prescaler has 1 11111: presacler has 32 31 can_smplr_e n can sampler enable this bit enables the can sampler before going into standby or stop mode. 0 can sampler is disabled 1 can sampler is enabled address offset: 0x04 reset value: xxxx xxxxh 0123456789101112131415 r sr[0:15] w 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sr[16:31] w figure 7-3. sample register 0
pxd10 microcontroller reference manual, rev. 1 7-4 freescale semiconductor preliminary?subject to change without notice 7.4 functional description as the can sampler is driven by the 16 mhz irc to sample properly the can identifier, two modes are possible depending on both can baudr ate and low power mode used: ? immediate sampling on falling edge detection (first can frame): this mode is used when the irc 16 mhz is available in lp mode, e.g. stop or halt. ? sampling on next frame (second can frame): this mode is used wh en the irc 16 mhz is switched off in lp mode, e.g. standby. du e to the start-up times of both th e voltage regulat or and the irc 16 mhz (~10 ? s), the can sampler would miss the first bi ts of a can identifi er sent at 500kbps. therefore the first identifier is ignored and the sa mpling is performed on the first falling edge of after interframe space. the can sampler performs sampling on a user selected can rx port, normally wh en the device is in standby or stop mode storing the sample s in internal registers. the user is required to configure the baud rate to achieve 8 samples per can nominal bit.it does not perform a ny sort of filteri ng on input samples. thereafter the software must enable the sampler by setting can_smplr_en bit in cr register.it then becomes the master controller for accessing the in ternal registers implemen ted for storing samples. the can sampler, when enabled, waits for a low pulse on the selected rx line, ta king it as a valid bit of the first can frame and generates the rc wakeup request which can be used to start the rc oscillator. depending upon the mode, it stores the first 8 samples of the 48 bits on sele cted rx line or skips the first frame and stores 8 bits for first 48 bits of second frame. in ff_mode, it sample s the can rx line on rc clock and stores the 8 samples of first 48 bits (384 samples). in sf_mode, it samples the rx and waits for 11 consecutive dominant bits ( 11 * 8 samples), taking it as the end of first frame. it then waits for first low pulse on the rx, taking it as a valid start of frame (sof) of the second frame. the sampler takes 384 samples (48 bytes * 8) using the rc clock (configuring 8 samples per nom inal bit) of the second frame, including the sof bit. these samples ar e stored in consecutive addresses of the (12 x 32) internal registers. rx_complete bit is set to ?1?, indi cating that sampling is complete. software should now process the sampled data by fi rst becoming master for accessing samples internal registers by resetting can_smplr_en bit.the sampler will need to be enabled again to start waiting for a new sampling routine. address offset: 0x30 reset value: xxxx xxxxh 0123456789101112131415 r sr[0:15] w 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sr[16:31] w figure 7-4. sample register 11
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 7-5 preliminary?subject to change without notice 7.4.1 enabling/disabling the can sampler the can sampler is disabled on reset and the cpu is able to access the 12 registers used for storing samples. the can sampler must be enabled be fore entering standby or stop mode by setting cr[can_smplr_en]. when the can sampler is enabled, the a, d, wen, cs n and ck to the (12 x 32) block of registers are switched to those generated by the kernel of the sampler. you can m onitor cr[active_ck] to check which is the active clock to the registers. any activity on selected rx line, the sampler enab les the 16 mhz rc oscillator. when can_smplr_en is reset to 0, the sampler should at least receive 3 rc clock pulses to reset itself, after which the rc can be switched off. when the software wishes to access the sample regist ers contents it must first reset the can_smplr_en bit by writing a ?0?. before accessing the register conten ts it must monitor active_ck bit for ?0?.when this bit is reset it can safely access th e (12 x 32) sample regist ers. while shifting from normal to sample mode and vice versa, the sample register signals must be static and inactive to ensure the data is not corrupt. 7.4.2 selecting the rx port one rx port can be selected per sampling routine; the port to be sampled is selected by can_rx_sel. 7.4.3 baud rate generation sampling is performed at a ba ud rate that is set by the software as a multiple of rc osci llator frequency of 62.5 ns (assuming rc is configured for high frequenc y mode i.e. 16 mhz). user must set the baud rate prescaler (brp) such that 8 samples per bit are achieved. baud rate setting must be made by software before going into standby or stop mode. this is done by setting brp bits 5:1 in control register. the reset value of brp is 00000 and can be set to max. 11111 which gives a prescale value of brp+1 thus providing a brp range of 1 to 32. ? max. bitrate supported for samp ling is 2mbps using brp as 1 ? min. bitrate supported for sampling is 62.5kbps using brp as 32 table 7-3. internal multiplexer correspondence can_rx_sel rx selected 000 canrx_0 pb[1] 001 canrx_1 pb[10] 010 canrx_2 pf[13] 011 canrx_3 pj[4] 100 canrx_4 pj[6] 101 reserved 110 reserved 111 reserved
pxd10 microcontroller reference manual, rev. 1 7-6 freescale semiconductor preliminary?subject to change without notice for example, suppose system is transmitting at 125kbps. in this case, nominal bit period: t=1/(125*10 3 )s =8*10 -3 *10 -3 s = 8 s eqn. 7-1 to achieve 8 samples per bit sample period= 8/8 s =1 s brp = 1 s/62.5ns = 16. thus in this case brp = 01111 7.5 register map table 7-4. can sampler register map addr. offset register name 0-15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 00 cr reserved rx_c omp lete busy active _ck brp can _sm plr _en 04 sample register 0 rw 08 sample register 1 rw ... .... .. . 30 sample register 11 rw ? ? ? ?
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-1 preliminary?subject to change without notice chapter 8 clock description this chapter describes the clock ar chitectural implem entation for pxd10. 8.1 clock architecture system clocks are generated from three sources: ? external oscillator fxosc (4-16 mhz) ? high speed internal rc (16 mhz) ? fmpll0 clocked by fxosc, stil l one of system clock sources additionally, there are tw o low power oscillators: ? low speed internal rc (128 khz) ? low-power external os cillator sxosc (32 khz) additionally, there is a secondary fmpll: ? fmpll1 clocked by fxosc is available as a clock source, only for emios_0, emios_1, quadspi, and dcu modules the clock architecture is shown in figure 8-1 .
pxd10 microcontroller reference manual, rev. 1 8-2 freescale semiconductor preliminary?subject to change without notice figure 8-1. pxd10 system clock generation 8.2 auxiliary clocks this device has four auxiliary cloc ks configurable using the mc_cgm registers. these auxiliary clocks allow the associated peripherals to operate at clock speeds independent of the system clock (sys_clk). the peripherals also use the undivided syst em clock to synchronously interface with the rest of the device. the auxiliary clock configur ation is as follows: /1 to /32 osca (xosc) irc fast irc slow system fmpll0 fxosc_clk_divided firc_clk_divided (64 mhz) (eg 8 mhz) (eg 16 mhz) sys_clk core, platform watchdog api/rtc oscb (xosc) sxosc_clk (32 khz) sxosc_clk_divided sirc_clk_divided sirc_clk_divided sirc_clk firc_clk fxosc_clk (via mc_rgm) clkout /1, /2, /4, /8 pll0_clk (eg 64 mhz) firc_clk fxosc_clk clkout selector peripheral /1 to /32 /1 to /32 firc_clk_divided fxosc_clk_divided emios_1 (8ch) emios_0 (16ch) /1 to /16 /1 to /16 note : no clock monitor associated with fmpll1 fmpll1 pll1_clk (e.g. 64 mhz) /1 to /32 optional clock to lcd in standby modes sxosc_clk_divided sirc_clk_divided firc_clk_divided fxosc_clk_divided clock selector clock selector fxosc_clk pll0_clk clock monitor unit firc_clk fxosc_clk clock selector sxosc_clk sirc_clk pll1_clk pll0_clk display controller unit dcu clock selector firc_clk pll0_clk ip_sync reset / int (128 khz) (4-16 mhz) (4-16 mhz) for emios set 3 /1 to /16 /1 to /16 /1 to /16 peripheral set 1 peripheral set 2 auxiliary clk0 auxiliary clk1 auxiliary clk2 optional clock to lcd in standby modes selector clock sys_clk/2 sys_clk pll1_clk pll1_clk/2 quadspi serial interface clk auxiliary clk 3 optional clock to lcd in stop and normal modes optional clock to lcd in stop and normal modes fxosc_clk_divided firc_clk_divided pll0_clk
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-3 preliminary?subject to change without notice ? auxiliary clock 0: display control unit (dcu) ? auxiliary clock 1: emios_1 ? auxiliary clock 2: emios_0 ? auxiliary clock 3: quadspi (uses undivi ded system clock when in dspi mode) 8.3 clock gating the pxd10 provides the user with the possibility of gating the clock to certain peripherals. see section 25.4.6, peripheral clock gating, for details. peripherals sets 1, 2, and 3 and the dcu, emios a nd quadspi peripherals can be configured to use specific clocks. in the case of peri pheral sets 1, 2 and 3 the choice of cl ock is limited to the system clock optionally divided by up to 16. see section 8.4.3.1.4, system clock divi der configuration registers (cgm_sc_dc0?2).? in the case of the dcu, emios_0, emio s_1 and quadspi peripherals there is a choice of source clocks. for the emio s0 and emios1 periphera ls there is the option to further divide the chosen clock. see section 8.4.4.2, auxiliary clock generation. table 8-1 shows the peripheral sets, their peripherals, and th e associated registers to enable and generate clocks to these peripherals. periphera ls not explicitly listed in a periphe ral set or using an auxiliary clock use the system clock (or where available an alternativ e chosen within the peripheral) as their reference. table 8-1. peripheral clock generation registers peripheral set peripherals registers to enable and generate clock 1linflex i 2 c smc ssd sgl lcd cgm_sc_dc0 2flexcan can sampler dspi cgm_sc_dc1 3 adc cgm_sc_dc2 ? dcu cgm_ac0_sc ? emios_0 cgm_ac1_sc cgm_ac1_dc0 ? emios_1 cgm_ac2_sc cgm_ac2_dc0 ? quadspi cgm_ac3_sc
pxd10 microcontroller reference manual, rev. 1 8-4 freescale semiconductor preliminary?subject to change without notice 8.4 clock generation module (mc_cgm) 8.4.1 introduction 8.4.1.1 overview the clock generation module (mc_cgm) generates reference clocks fo r all device bloc ks. the mc_cgm selects one of the system clock sour ces to supply the system clock. th e mc_me controls the system clock selection (see the mc_me chapter for more details). peripheral clock selection is controlled by mc_cgm control registers. a set of mc_cgm registers controls the clock divi ders which are used for divided system and peripheral cloc k generation. the memory spaces of syst em and peripheral cl ock sources which have addressable memory spaces , are accessed through the mc_cgm me mory space. the mc_cgm also selects and generates an output clock. figure 8-2 depicts the mc_cgm block diagram.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-5 preliminary?subject to change without notice 8.4.1.2 features the mc_cgm includes th e following features: ? generates system and peripheral clocks ? selects and enables/disables th e system clock supply from system clock sources according to mc_me control ? contains a set of registers to control cl ock dividers for divided clock generation output clock selector/divider registers platform interface core mc_cgm figure 8-2. mc_cgm block diagram mc_me auxiliary clock selector/divider system clock multiplexer/divider fxosc fmpll0 fmpll1 firc mapped modules interface mapped peripherals peripherals ph[4] mc_rgm
pxd10 microcontroller reference manual, rev. 1 8-6 freescale semiconductor preliminary?subject to change without notice ? contains a set of registers to control peripheral clock selection ? supports multiple clock sources and maps their address spaces to its memory map ? generates an output clock ? guarantees glitch-less clock transitions when changing the system clock selection ? supports 8-, 16- and 32-bit wide read/write accesses 8.4.1.3 modes of operation this section describes the basic functional modes of the mc_cgm. 8.4.1.3.1 normal and reset modes of operation during normal and reset modes of operation, the clock se lection for the system clock is controlled by the mc_me. 8.4.2 external signal description the mc_cgm delivers an output clock to the ph [4] pin for off-chip use and/or observation. 8.4.3 memory map and register definition note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content table 8-2. mc_cgm register description address name description size access 0xc3fe_0370 cgm_oc_en output clock enable word read/write 0xc3fe_0374 cgm_ocds_sc output clock division select byte read/write 0xc3fe_0378 cgm_sc_ss system clock select status byte read 0xc3fe_037c cgm_sc_dc0 system clock divi der configuration 0 byte read/write 0xc3fe_037d cgm_sc_dc1 system clock divi der configuration 1 byte read/write 0xc3fe_037e cgm_sc_dc2 system clock div ider configuration 2 byte read/write 0xc3fe_0380 cgm_ac0_sc aux clock 0 select control word read/write 0xc3fe_0388 cgm_ac1_sc aux clock 1 select control word read/write 0xc3fe_038c cgm_ac1_dc0 aux clock 1 divider configuration 0 byte read/write 0xc3fe_0398 cgm_ac2_sc aux clock 2 select control word read/write 0xc3fe_0394 cgm_ac2_dc0 aux clock 2 divi der configuration 0 byte read/write 0xc3fe_0398 cgm_ac3_sc aux clock 3 select control word read/write
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-7 preliminary?subject to change without notice ? cause a transfer error table 8-3. mc_cgm memory map address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe_0000 ? 0xc3fe_001c fxosc registers 0xc3fe_0020 ? 0xc3fe_003c reserved 0xc3fe_0040 ? 0xc3fe_005c sxosc registers 0xc3fe_0060 ? 0xc3fe_007c firc registers 0xc3fe_0080 ? 0xc3fe_009c reserved 0xc3fe_00a0 ? 0xc3fe_00bc fmpll0 registers 0xc3fe_00c0 ? 0xc3fe_00dc fmpll1 registers 0xc3fe_00e0 ? 0xc3fe_00fc reserved 0xc3fe_0100 ? 0xc3fe_011c cmu0 registers 0xc3fe_0120 ? 0xc3fe_013c reserved 0xc3fe_0140 ? 0xc3fe_015c reserved 0xc3fe_0160 ? 0xc3fe_017c reserved 0xc3fe_0180 ? 0xc3fe_019c reserved 0xc3fe_01a0 ? 0xc3fe_01bc reserved
pxd10 microcontroller reference manual, rev. 1 8-8 freescale semiconductor preliminary?subject to change without notice 0xc3fe_01c0 ? 0xc3fe_01dc reserved 0xc3fe_01e0 ? 0xc3fe_01fc reserved 0xc3fe_0200 ? 0xc3fe_021c reserved 0xc3fe_0220 ? 0xc3fe_023c reserved 0xc3fe_0240 ? 0xc3fe_025c reserved 0xc3fe_0260 ? 0xc3fd_c27c reserved 0xc3fe_0280 ? 0xc3fe_029c reserved 0xc3fe_02a0 ? 0xc3fe_02bc reserved 0xc3fe_02c0 ? 0xc3fe_02dc reserved 0xc3fe_02e0 ? 0xc3fe_02fc reserved 0xc3fe_0300 ? 0xc3fe_031c reserved 0xc3fe_0320 ? 0xc3fe_033c reserved 0xc3fe_0340 ? 0xc3fe_035c reserved 0xc3fe_0360 ? 0xc3fe_036c reserved table 8-3. mc_cgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-9 preliminary?subject to change without notice 0xc3fe_0370cgm_oc_en r0000000000000000 w r000000000000000 en w 0xc3fe_0374 cgm_ocds_sc r 0 0 seldiv selctl 00000000 w r0000000000000000 w 0xc3fe_0378cgm_sc_ss r0000 selstat 00000000 w r0000000000000000 w 0xc3fe_037c cgm_sc_dc0?2 r de0 000 div0 de1 000 div1 w r de2 000 div2 00000000 w 0xc3fe_0380 cgm_ac0_sc r 0 0 0 0 selctl 00000000 w r0000000000000000 w 0xc3fe_0384 reserved 0xc3fe_0388 cgm_ac1_sc r 0 0 0 0 selctl 00000000 w r0000000000000000 w 0xc3fe_038c cgm_ac1_dc0 r de0 000 div0 00000000 w r0000000000000000 w table 8-3. mc_cgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 8-10 freescale semiconductor preliminary?subject to change without notice 8.4.3.1 register descriptions all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for example, the cgm_oc_en register may be accessed as a word at address 0xc3fe_0370, as a half-word at address 0xc3fe_0372, or as a byte at address 0xc3fe_0373. 8.4.3.1.1 output clock enab le register (cgm_oc_en) this register is used to enab le and disable the output clock. 0xc3fe_0390 cgm_ac2_sc r 0 0 0 0 selctl 00000000 w r0000000000000000 w 0xc3fe_0394 cgm_ac2_dc0 r de0 000 div0 00000000 w r0000000000000000 w 0xc3fe_0398 cgm_ac3_sc r 0 0 0 0 selctl 00000000 w r0000000000000000 w 0xc3fe_039c reserved 0xc3fe_0400 ? 0xc3fe_3ffc reserved address 0xc3fe_0370 access: supervisor read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 en w reset0000000000000000 figure 8-3. output clock enable register (cgm_oc_en) table 8-3. mc_cgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-11 preliminary?subject to change without notice 8.4.3.1.2 output clock division se lect register (cgm_ocds_sc) this register is used to select th e current output clock source and by which factor it is divi ded before being delivered at the output clock. table 8-4. output clock enable register (cgm_oc_en) field descriptions field description en output clock enable control 0 output clock is disabled 1 output clock is enabled address 0xc3fe_0374 access: supervisor read/write 0123456789101112131415 r0 0 seldiv 0 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-4. output clock division select register (cgm_ocds_sc) table 8-5. output clock division select register (cgm_ocds_sc) field descriptions field description seldiv output clock division select 00 output selected output clock without division 01 output selected output clock divided by 2 10 output selected output clock divided by 4 11 output selected output clock divided by 8 selctl output clock source selection control ? this value selects the current source for the output clock. 000 16 mhz internal rc oscillator 001 4-16 mhz external oscillator 010 primary fmpll 011 secondary fmpll 100 128 khz internal rc oscillator 101 32 khz external oscillator 110 reserved 111 reserved
pxd10 microcontroller reference manual, rev. 1 8-12 freescale semiconductor preliminary?subject to change without notice 8.4.3.1.3 system clock select status register (cgm_sc_ss) this register provides the curren t system clock source selection. 8.4.3.1.4 system clock divider conf iguration registers (cgm_sc_dc0 ? 2) address 0xc3fe_0378 access: supervisor read 0123456789101112131415 r0000 selstat 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-5. system clock select status register (cgm_sc_ss) table 8-6. system clock select status register (cgm_sc_ss) field descriptions field description selstat system clock source selection status ? this value indicates the cl ock source for the system clock. 0000 16 mhz internal rc oscillator 0001 divided 16 mhz internal rc oscillator 0010 4-16 mhz external oscillator 0011 divided 4-16 mhz external oscillator 0100 primary fmpll 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled address 0xc3fe_037c access: supervisor read/write 0123456789101112131415 r de0 000 div0 de1 000 div1 w reset1000000010000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r de2 000 div2 00000000 w reset1000000000000000 figure 8-6. system clock divider configuration registers (cgm_sc_dc0?2)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-13 preliminary?subject to change without notice these registers control the system clock dividers. the divided clock is the reference for the associated peripheral set. 8.4.3.1.5 auxiliary clock 0 select control register (cgm_ac0_sc) this register is used to select the current auxiliary clock 0 sources. table 8-7. system clock divider configurati on registers (cgm_sc_dc0 ?2) field descriptions field description de0 divider 0 enable 0 disable system clock divider 0 1 enable system clock divider 0 div0 divider 0 division value ? the resultant peripheral set 1 clock will have a period div0 + 1 times that of the system clock. if the de0 is set to ?0? (divider 0 is disabled), any write access to the div0 field is ignored and the peripheral set 1 clock remains disabled. de1 divider 1 enable 0 disable system clock divider 1 1 enable system clock divider 1 div1 divider 1 division value ? the resultant peripheral set 2 clock will have a period div1 + 1 times that of the system clock. if the de1 is set to ?0? (divider 1 is disabled), any write access to the div1 field is ignored and the peripheral set 2 clock remains disabled. de2 divider 2 enable 0 disable system clock divider 2 1 enable system clock divider 2 div2 divider 2 division value ? the resultant peripheral set 3 clock will have a period div2 + 1 times that of the system clock. if the de2 is set to ?0? (divider 2 is disabled), any write access to the div2 field is ignored and the peripheral set 3 clock remains disabled. address 0xc3fe_0380 access: supervisor read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-7. auxiliary clock 0 select control register (cgm_ac0_sc)
pxd10 microcontroller reference manual, rev. 1 8-14 freescale semiconductor preliminary?subject to change without notice 8.4.3.1.6 auxiliary clock 1 select control register (cgm_ac1_sc) this register is used to select the current auxiliary clock 1 sources. table 8-8. auxiliary clock 0 select control register (cgm_ac0_sc) field descriptions field description selctl auxiliary clock 0 source selection control ? this value selects the current source for auxiliary clock 0. 0000 4-16 mhz external oscillator 0001 16mhz int. rc osc. 0010 secondary freq. mod. pll 0011 primary freq. mod. pll 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved address 0xc3fe_0388 access: supervisor read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-8. auxiliary clock 1 select control register (cgm_ac1_sc)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-15 preliminary?subject to change without notice 8.4.3.1.7 auxiliary clock 1 divider c onfiguration register (cgm_ac1_dc0) this register controls th e auxiliary clock 1 divider. table 8-9. auxiliary clock 1 select control register (cgm_ac1_sc) field descriptions field description selctl auxiliary clock 1 source selection control ? this value selects the current source for auxiliary clock 1. 0000 div. 4-16 mhz external oscillator 0001 div. 16mhz int. rc osc. 0010 secondary freq. mod. pll 0011 primary freq. mod. pll 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved address 0xc3fe_038c access: supervisor read/write 0123456789101112131415 r de0 000 div0 00000000 w reset1000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-9. auxiliary clock 1 divider configuration register (cgm_ac1_dc0) table 8-10. auxiliary clock 1 divider configurat ion register (cgm_ac1_dc0) field descriptions field description de0 divider 0 enable 0 disable auxiliary clock 1 divider 0 1 enable auxiliary clock 1 divider 0 div0 divider 0 division value ? the resultant emios0 clock will have a period div0 + 1 times that of auxiliary clock 1. if the de0 is set to 0 (divider 0 is disabled), any writ e access to the div 0 field is ignored and the emios0 clock remains disabled.
pxd10 microcontroller reference manual, rev. 1 8-16 freescale semiconductor preliminary?subject to change without notice 8.4.3.1.8 auxiliary clock 2 select control register (cgm_ac2_sc) this register is used to select the current auxiliary clock 1 sources. 8.4.3.1.9 auxiliary clock 2 divider c onfiguration register (cgm_ac2_dc0) address 0xc3fe_0398 access: supervisor read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-10. auxiliary clock 2 select control register (cgm_ac2_sc) table 8-11. auxiliary clock 2 select control register (cgm_ac2_sc) field descriptions field description selctl auxiliary clock 2 source selection control ? this value selects the current source for auxiliary clock 2. 0000 div. 4-16mhz external oscillator 0001 div. 16mhz int. rc osc. 0010 secondary freq. mod. pll 0011 primary freq. mod. pll 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved address 0xc3fe_0394 access: supervisor read/write 0123456789101112131415 r de0 000 div0 00000000 w reset1000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-11. auxiliary clock 2 divider configuration register (cgm_ac2_dc0)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-17 preliminary?subject to change without notice this register controls th e auxiliary clock 2 divider. 8.4.3.1.10 auxiliary clock 3 select control register (cgm_ac3_sc) this register is used to select the current auxiliary clock 3 sources. table 8-12. auxiliary clock 2 divider configurat ion register (cgm_ac2_dc0) field descriptions field description de0 divider 0 enable 0 disable auxiliary clock 2 divider 0 1 enable auxiliary clock 2 divider 0 div0 divider 0 division value ? the resultant emios1 clock will have a period div0 + 1 times that of auxiliary clock 2. if the de0 is set to 0 (divider 0 is disabled), any writ e access to the div 0 field is ignored and the emios1 clock remains disabled. address 0xc3fe_0398 access: supervisor read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 8-12. auxiliary clock 3 select control register (cgm_ac3_sc) table 8-13. auxiliary clock 3 select control register (cgm_ac3_sc) field descriptions field description selctl auxiliary clock 3 source selection control ? this value selects the current source for auxiliary clock 3. 0000 system clock 0001 system clock / 2 0010 secondary freq. mod. pll 0011 secondary freq. mod. pll / 2 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved
pxd10 microcontroller reference manual, rev. 1 8-18 freescale semiconductor preliminary?subject to change without notice 8.4.4 functional description 8.4.4.1 system clock generation figure 8-13 shows the block diagram of the system cl ock generation logic. the mc_me provides the system clock select and switch mask (see mc_me chapter for more details), and the mc_rgm provides the safe clock request (see mc_rgm chapter for more de tails). the safe clock request forces the selector to select the 16 mhz internal rc os cillator as the system clock and to ignore the system clock select. 8.4.4.1.1 system cloc k source selection during normal operation, the system clock selection is controlled ?on a safe mode event, by mc_rgm ? otherwise, by the mc_me 8.4.4.1.2 system clock disable during normal operation, the system cl ock can be disabled by the mc_me. 8.4.4.1.3 system clock dividers the mc_cgm generates three derived cl ocks from the system clock that are used as the reference clocks for their associated peripherals. 8.4.4.2 auxiliary clock generation figure 8-14 (and those following) shows the block diagram of the auxiliary clock generation logic. see section 8.4.3.1.5, auxiliary clock 0 select control register (cgm_ac0_sc) , section 8.4.3.1.6, auxiliary clock 1 select c ontrol register (cgm_ac1_sc) , section 8.4.3.1.8, auxiliar y clock 2 select control register (cgm_ac2_sc) , and section 8.4.3.1.10, auxiliary clock 3 select control register (cgm_ac3_sc) for auxiliary clock selection control.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-19 preliminary?subject to change without notice figure 8-13. mc_cgm system clock generation overview 16 mhz internal rc oscillator divided 4-16 mhz external oscillator 3 primary fmpll 4 divided 16 mhz internal rc oscillator 1 0 system clock ?0? mc_me system clock switch mask cgm_sc_ss register mc_rgm safe clock request mc_me clock select 1 0 cgm_sc_dc0 register clock divider peripheral set 1 clock cgm_sc_dc1 register clock divider peripheral set 2 clock cgm_sc_dc2 register clock divider peripheral set 3 clock
pxd10 microcontroller reference manual, rev. 1 8-20 freescale semiconductor preliminary?subject to change without notice dcu clock figure 8-14. mc_cgm auxiliary clock 0 generation overview secondary freq. mod. pll 2 primary freq. mod. pll 3 16mhz int. rc osc. 1 cgm_ac0_sc register 4-16 mhz external oscillator 0
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-21 preliminary?subject to change without notice cgm_ac1_dc0 register clock divider emios0 clock unused figure 8-15. mc_cgm auxiliary clock 1 generation overview secondary freq. mod. pll 2 primary freq. mod. pll 3 div. 16mhz int. rc osc. 1 cgm_ac1_sc register 4-16 mhz external oscillator 0
pxd10 microcontroller reference manual, rev. 1 8-22 freescale semiconductor preliminary?subject to change without notice cgm_ac2_dc0 register clock divider emios1 clock unused figure 8-16. mc_cgm auxiliary clock 2 generation overview secondary freq. mod. pll 2 primary freq. mod. pll 3 div. 16mhz int. rc osc. 1 cgm_ac2_sc register v. 4-16mhz external oscillator 0
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-23 preliminary?subject to change without notice 8.4.4.2.1 auxiliary clock source selection during normal operation, the auxiliary clock selection is done via the cgm_ac0?3_sc registers. if software selects an ?unavailable? source, the old se lection remains, and the register content does not change. 8.4.4.2.2 auxiliary clock dividers the selected auxiliary clock can be optionally divided before use. quadspi clock figure 8-17. mc_cgm auxiliary clock 3 generation overview secondary freq. mod. pll 2 secondary freq. mod. pll / 2 3 system clock / 2 1 cgm_ac3_sc register system clock 0
pxd10 microcontroller reference manual, rev. 1 8-24 freescale semiconductor preliminary?subject to change without notice 8.4.4.2.3 dividers fun ctional description dividers are used for the generation of divided system and peripheral clocks. the mc_cgm has the following control register s for built-in dividers: ? section 8.4.3.1.4, system clock divider conf iguration register s (cgm_sc_dc0?2) ? section 8.4.3.1.7, auxiliary clock 1 divider c onfiguration register (cgm_ac1_dc0) ? section 8.4.3.1.9, auxiliary clock 2 divider c onfiguration register (cgm_ac2_dc0) the reset value of all counters is ?1?. if a divider has its de bit in the respective configuration register set to ?0? (the divider is disabled), any value in its div n field is ignored. 8.4.4.3 output clock multiplexing the mc_cgm contains a mu ltiplexing function for a num ber of clock sources whic h can then be used as output clock sources. the selection is done via the cgm_ocds_sc register. 8.4.4.4 output clock division selection the mc_cgm provides the following output signals for the output clock generation: ? ph[4] (see figure 8-18 ). this signal is generated by using one of the 3-stage ripple counter outputs or the selected signal without division. the non-divided signal is not guaranteed to be 50% duty cycle by the mc_cgm. ? the mc_cgm also has an output clock enable register (see section 8.4.3.1.1, output clock enable register (cgm_oc_en) ) which contains the output clock enable/disable control bit. 8.5 fxosc external oscillator the fxosc digital interface c ontrols the external crystal oscillator (fxosc). it holds control and status registers accessible for application. cgm_ocds_sc.selctl cgm_ocds_sc.seldiv 0 1 2 3 register register figure 8-18. mc_cgm output clock multiplexer and ph[4] generation 16 mhz internal rc oscillator 0 4-16 mhz external oscillator 1 primary fmpll 2 secondary fmpll 3 128 khz internal rc oscillator 4 32 khz external oscillator 5 ph[4] ?0? cgm_oc_en register
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-25 preliminary?subject to change without notice 8.5.1 main features ? external crystal oscillator (fxosc) digital interface ? oscillator clock available interrupt ? oscillator bypass mode ? output clock division factors ranging from 1,2,3....32 8.5.2 functional description the crystal oscillator circui t includes an internal oscillator driver and an external crys tal circuitry. it provides an output clock that can be provided to pll or used as a reference clock to specific modules depending on system needs. the crystal oscillator is controlled by the mc_me module. the oscon bit of me_xxx_mcr registers controls the powerdown of oscillat or based on the current device mode while s_osc of me_gs register provides the oscillator cl ock available status. after system reset, the oscillator is put to power down state and soft ware has to switch on when required. whenever the crystal oscillat or is switched on from of f state, osccnt counter st arts and when it reaches the value eocv[7:0]*512, oscillator cl ock is made available to the syst em. also an interrupt pending bit i_osc of osc_ctl register is set. an interrupt will be generated if the interrupt mask bit m_osc is set. the oscillator circuit can be bypassed by setting osc_ctl[oscbyp]. this bit can only be set by the software. system reset is needed to reset this bit. in this bypass mode, the output clock has the same polarity as external clock applied on extal pin and th e oscillator status is fo rced to ?1?. the bypass configuration is independent of th e powerdown mode of the oscillator. table 8-14 shows the truth table of differen t configurations of oscillator. the crystal oscillator clock can be further divided by a configurable factor in the range 1 to 32 to generate the divided clock to match system requirements. this di vision factor is specified by the oscdiv[4:0] bits of osc_ctl register. table 8-14. truth table of crystal oscillator enable byp xtal extal ck_oscm osc mode 0 0 no crystal, hiz no crystal, hiz 0 power down, iddq x 1 x ext clock extal bypass, osc disabled 1 0 crystal crystal extal normal, osc enabled gnd ext clock extal normal, osc enabled
pxd10 microcontroller reference manual, rev. 1 8-26 freescale semiconductor preliminary?subject to change without notice 8.5.3 register description note: osc_ctl register is writable only in supervisor mode. address offset: 0x0000 base address: 0xc3fe0000 reset value: 0b00000000_10000000_00000000_00000000 0123456789101112131415 oscb yp reserved eocv rs r rw 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 m_os c reserved oscdiv i_osc reserved rw r rw rc r figure 8-19. crystal oscillator control register (osc_ctl) table 8-15. crystal oscillator control register (osc_ctl) field descriptions field description bit 0 oscbyp : crystal oscillator bypass this bit specifies whether the oscillator should be bypassed or not. software can only set this bit. system reset is needed to reset this bit. 0: oscillator output is used as root clock. 1: extal is used as root clock. bits 1-7 reserved bits 8-15 eocv[7:0] : end of count value these bits specify the end of count value to be used for comparison by the oscillator stabilization counter osccnt after reset or whenever it is swit ched on from the off stat e. this counting period ensures that external oscillator cl ock signal is stable before it can be selected by the system. when oscillator counter reaches the value eocv[7:0]*512 , oscillator available interrupt request is generated. the reset value of this field depends on the device specificat ion. the osccnt counter will be kept under reset if oscillator bypass mode is selected. bit 16 m_osc : crystal oscillator clock interrupt mask 0: crystal oscillator clock interrupt is masked. 1: crystal oscillator clock interrupt is enabled. bits 17-18 reserved bits 19-23 oscdiv[4:0] : crystal oscillator clock division factor these bits specify the crystal osci llator output clock division factor. the output clock is divided by the factor oscdiv+1. bit 24 i_osc : crystal oscillator clock interrupt this bit is set by hardware when osccnt counter reaches the count value eocv[7:0]*512. it is cleared by software by writing ?1?. 0: no oscillator clock interrupt occurred. 1: oscillator clock interrupt pending. bits 25-31 reserved
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-27 preliminary?subject to change without notice 8.6 32 khz osc digital interface 8.6.1 introduction the osc digital interface controls the external crys tal oscillator (sxosc). it holds control and status registers accessible for application. 8.6.2 main features ? external crystal oscillator (sxosc) digital interface ? oscillator powerdown control and status ? oscillator clock available interrupt ? oscillator bypass mode ? output clock division factors ranging from 1,2,3....32 8.6.3 functional description the crystal oscillator circui t includes an internal oscillator driver a nd an external crysta l circuitry. it can be used as a reference clock to spec ific modules depending on system needs. the crystal oscillator is contro lled by the osc_ctl register. the oscon bit controls the powerdown while s_osc bit provides the osci llator clock available status. after system reset, the oscillator is put to power down state and soft ware has to switch on when required. whenever the crystal oscillat or is switched on from of f state, osccnt counter st arts and when it reaches the value eocv[7:0]*512, oscillator cl ock is made available to the syst em. also an interrupt pending bit i_osc of osc_ctl register is set. an interrupt will be generated if the interrupt mask bit m_osc is set. the oscillator circuit can be bypasse d by writing oscbyp bit to osc_ctl register to ?1?. this bit can only be set by the software. system re set is needed to reset this bit. in this bypass mode , the output clock has the same polarity as external cl ock applied on extal32 pin and the osci llator status is forced to ?1?. the bypass configuration is independent of the powerdow n mode of the oscillator. the table below shows the truth table of different configurations of oscillator. table 8-16. truth table of crystal oscillator oscon oscbyp xtal32 extal32 ck_oscm osc mode 0 0 no crystal, high z no crystal, high z 0 power down, iddq x 1 ext clock x extal32 bypass, osc disabled 1 0 crystal crystal extal32 normal, osc enabled gnd ext clock extal32 normal, osc enabled
pxd10 microcontroller reference manual, rev. 1 8-28 freescale semiconductor preliminary?subject to change without notice the crystal oscillator clock can be further divided by a configurable factor in the range 1 to 32 to generate the divided clock to match system requirements. this di vision factor is specified by the oscdiv[4:0] bits of osc_ctl register. 8.6.4 register description note: osc32, after it is enabled, is always on, but ca n be configured off in standby by writing oscon bit. address offset: 0x0000 base address: 0xc3fe0040 reset value: 0b00000000_10000000_00000000_00000000 0123456789101112131415 oscb yp reserved eocv rs r rw 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 m_os c reserved oscdiv i_osc reserved s_osc osco n rw r rw rc r r rw table 8-17. crystal oscillator control register (osc_ctl) table 8-18. crystal oscillator control register (osc_ctl) field descriptions field description bit 0 oscbyp : crystal oscillator bypass this bit specifies whether the oscillator should be bypassed or not. software can only set this bit. system reset is needed to reset this bit. 0: oscillator output is used as root clock. 1: extal32 is used as root clock. bits 1-7 reserved bits 8-15 eocv[7:0] : end of count value these bits specify the end of count value to be used for comparison by the oscillator stabilization counter osccnt after reset or whenever it is swit ched on from the off stat e. this counting period ensures that external oscillator cl ock signal is stable before it can be selected by the system. when oscillator counter reaches the value eocv[7:0]*512 , oscillator available interrupt request is generated. the reset value of this field depends on the device specificat ion. the osccnt counter will be kept under reset if oscillator bypass mode is selected. bit 16 m_osc : crystal oscillator clock interrupt mask 0: crystal oscillator clock interrupt is masked. 1: crystal oscillator clock interrupt is enabled. bits 17-18 reserved bits 19-23 oscdiv[4:0] : crystal oscillator clock division factor these bits specify the crystal osci llator output clock division factor. the output clock is divided by the factor oscdiv+1.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-29 preliminary?subject to change without notice note: osc_ctl register is writable only in supervisor mode. 8.7 sirc digital interface 8.7.1 introduction the sirc digital interface controls the internal low power 128 khz rc oscillator (sirc). it holds control and status registers ac cessible for application. 8.7.2 low power rc oscillator (128 khz) the low power rc oscillator provides a low frequency (f lprc ) clock in the range of tens of khz requiring less current consumption. this clock ca n be used as reference clock when a fixed base time is required for specific modules. the low power rc oscillator is always on in all device modes. the sirc clock can be further divide d by a configurable divi sion factor in the range 1 to 32 to generate the divided clock to match system requirements. th is division factor is sp ecified by the lprcdiv[4:0] bits of lprc_ctl register. the sirc oscillator output freque ncy can be trimmed by lprctrim[4: 0] bits of lprc_ctl register. these bits can be programmed to modify internal capacitor/resistor. after power on reset, the trimming bits are provided by the flash options . only after first write access, th e value specified by lprctrim[4:0] bits will contol the trimming. bit 24 i_osc : crystal oscillator clock interrupt this bit is set by hardware when osccnt counter reaches the count value eocv[7:0]*512. it is cleared by software by writing ?1?. 0: no oscillator clock interrupt occurred. 1: oscillator clock interrupt pending. bits 25-29 reserved bit 30 s_osc : crystal oscillator statusl 0: crystal oscillator output clock is not stable. 1: crystal oscillator is providing a stable clock. bit 31 oscon : crystal oscillator powerdown control 0: crystal oscillator is switched off. 1: crystal oscillator is switched on. table 8-18. crystal oscillator control register (osc_ctl) field descriptions
pxd10 microcontroller reference manual, rev. 1 8-30 freescale semiconductor preliminary?subject to change without notice 8.7.3 register description note: lprc_ctl register is writable only in supervisor mode. 8.8 firc digital interface 8.8.1 introduction the firc digital interface controls the main internal 16 mhz rc oscillator (fir c). it holds control and status registers accessi ble for application. address offset: 0x0000 base address: 0xc3fe_0080 reset value: 0b00000000_00000000_00000011_00000000 0123456789101112131415 reserved lprctrim rrw 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved lprcdiv reserved s_lpr c reserved rrwrrr figure 8-20. low power rc control register (lprc_ctl) table 8-19. low power rc control register (lprc_ctl) field descriptions field description bits 0-10 reserved bits 11-15 lprctrim[4:0] : low power rc trimming bits note: all configurations cannot be used. please refer to the device data sheet. bits 16-18 reserved bits 19-23 lprcdiv[4:0] : low power rc clock division factor these bits specify the low power rc oscillator outpu t clock division factor. the output clock is divided by the factor lprcdiv+1. bits 24-26 reserved bits 27 s_lprc : low power rc clock status 0: lprc is not providing a stable clock. 1: lprc is providing a stable clock. bits 28-31 reserved
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-31 preliminary?subject to change without notice 8.8.2 functional description (16 mhz) the main rc oscillator pr ovides a high-frequency (f mrc ) clock. this clock can be used to fasten the exit from reset and wakeup sequence from low power mode s of the system. it is controlled by the mc_me module based on the current device mode. the clock source status is updated in s_rc bit of me_gs register. please refer to mc_me specification for further details. the mrc clock can be further divided by a configurable divi sion factor in the range 1 to 32 to generate the divided clock to match system re quirements. this division factor is specified by the rcdiv[4:0] bits of rc_ctl register. the main rc oscillator output frequency can be trimmed by rctrim[5:0] b its of rc_ctl register. these bits can be programmed to modify internal capacitor/resistor values. after power on reset, the trimming bits are provided by the flash options. only after first write access, the value specified by rctrim[5:0] bits will contol the trimming. during standby mode entry process, the rc osci llator is controlled based on rcon bit of me_standby_mc register. the is th e last step in the standby entry sequence. on any system wake-up event, device exits st andby mode and switches on the rc oscillator. 8.8.3 register description address offset: 0x0000 base address: 0xc3fe_0060 reset value: 0b00000000_00000000_00000000_00000000 0123456789101112131415 reserved rctrim r rw 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved rcdiv reserved rrw r table 8-20. rc oscillator control register (rc_ctl) table 8-21. rc oscillator control regi ster (rc_ctl) field descriptions field description bits 0-9 reserved bits 10-15 rctrim[5:0] : low power rc trimming bits note: not all configurations can be used. please refer to the device data sheet. bits 16-18 reserved
pxd10 microcontroller reference manual, rev. 1 8-32 freescale semiconductor preliminary?subject to change without notice note: rc_ctl register is writable only in supervisor mode. 8.9 frequency-modulated phase locked loops and system clocks (fmpll0 and fmpll1) 8.9.1 introduction this section describes the features and functions of the two independent fmpll mo dules implemented in pxd10. 8.9.2 overview the fmplls enable the user to generate high speed system clocks from a common 4 mhz to 16 mhz input clock. further, the fmplls support programmabl e frequency modulation of the system clock. the pll multiplication factor, out put clock divider ratio are all software configurable. note the user must take care not to program device with frequency higher than allowed (no hardware check). the fmpll?s block di agram is shown in figure 8-21 . figure 8-21. fmpll block diagram 8.9.3 features each fmpll has the foll owing major features: ? input clock frequency from an 4 mhz to 40 mhz ? voltage controlled oscillator (vco) range from 256 mhz to 512 mhz ? reduced frequency divider (rfd) for reduced frequency operation without forcing the pll to relock bits 19-23 rcdiv[4:0] : low power rc clock division factor these bits specify the low power rc oscillator outpu t clock division factor. the output clock is divided by the factor lprcdiv+1. bits 24-31 reserved table 8-21. rc oscillator control register (rc_ctl) field descriptions (continued) buffer charge pump low pass filter vco idf div2 ndiv loop frequency divider fxosc mode odf div4 mode phi
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-33 preliminary?subject to change without notice ? frequency modulated pll ? modulation enabled/disabled through software ? triangle wave modulation ? programmable modulation depth ? 0.25% to 4% deviation fr om center spread frequency ? -0.5% to +8% deviation from down spread frequency ? programmable modulation frequency dependent on reference frequency ? self-clocked mode (scm) operation ? five available modes ? normal mode ? progressive clock switching ? normal mode with fm ? powerdown mode ? 1:1 mode (fmpll0 only) 8.9.4 memory map 1 table 8-22 shows the memory map locations. addresses are given as offsets of the module base address. 8.9.5 register description the pll operation is controlled by two registers. thos e registers can only be writ ten in supervisor mode. 1.fmpll_x are mapped through the me_cgm register slot table 8-22. fmpll memory map address register access location base: 0xc3fe00a0 (fmpll0) 0xc3fe00c0 (fmpll1) 0x0000 control register (cr) r/w on page 34 0x0004 modulation register (mr) special on page 36
pxd10 microcontroller reference manual, rev. 1 8-34 freescale semiconductor preliminary?subject to change without notice 8.9.5.1 control register (cr) offset 0x0000 access: user read/write 0123456789101112131415 r 0 0 idf odf 0 ndiv w reset 0000000101000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000 en_pll _sw mode unlock _once 0 i_lock s_lock pll_fail _mask pll_fail _flag 0 w w1c w1c reset 0000000000000000 1 reset value is determined by the soc integration. table 8-23. control register (cr) table 8-24. cr field descriptions field description 2-5 idf the value of this field sets the pll input division factor as described in ta bl e 8 - 2 5 . the reset value is set during integration. 6-7 odf the value of this field sets the pll ou tput division factor as described in ta b l e 8 - 2 6 . the reset value is set during integration. 9-15 ndiv the value of this field sets the pll loop division factor as described in ta bl e 8 - 2 7 . the reset value is set during integration. 23 en_pll_sw this bit is used to enable progressive clock switching. after the pll locks, the pll output initially is divided by 8 then progressively divides down until divide by 1. 0 => progressive clock switching disabled 1 => progressive clock switching enabled note: the pll output should not be used if a non-c hanging clock is needed (such as for serial communications) until the division has finished 24 mode this bit is used to activate the 1:1 mode. 25 unlock_once this bit is a sticky indication of pll loss of lo ck condition. unlock_once is set when the pll loses lock. whenever the pll reacquires lock, unlock_once remains set. only a power-on reset can clear this bit. 27 i_lock this bit is set by hardware whenever there is a lock/unlock event.it is cleared by software, writing 1. 28 s_lock this bit is an indication of whether the pll has acquired lock. 0 => pll unlocked 1 => pll locked
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-35 preliminary?subject to change without notice 29 pll_fail_mask this bit is used to mask the pll_fail output. 0 => pll_fail not masked 1 => pll_fail masked 30 pll_fail_flag this bit is asynchronously set by hardware whenever a loss of lock event occurs while pll is switched on. it is cleared by software, writing 1. table 8-25. input divide ratios idf[3:0] input divide ratios 0000 divide by 1 0001 divide by 2 0010 divide by 3 0011 divide by 4 0100 divide by 5 0101 divide by 6 0110 divide by 7 0111 divide by 8 1000 divide by 9 1001 divide by 10 1010 divide by 11 1011 divide by 12 1100 divide by 13 1101 divide by 14 1110 divide by 15 1111 clock inhibit table 8-26. output divide ratios odf[1:0] output divide ratios 00 divide by 2 01 divide by 4 10 divide by 8 11 divide by 16 table 8-24. cr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 8-36 freescale semiconductor preliminary?subject to change without notice 8.9.5.2 modulation register (mr) table 8-27. loop divide ratios ndiv[6:0] loop divide ratios 0000000-0011111 na 0100000 divide by 32 0100001 divide by 33 0100010 divide by 34 ... ... 1011111 divide by 95 1100000 divide by 96 1100001-1111111 na offset 0x0004 access: user read/write 01234567 8 9101112131415 rstr b_b ypa ss 0 spr d_s el mod_period w reset00000000 0 00 0 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fm_ en inc_step w reset00000000 0 0? 1 0 0000 table 8-28. modulation register (mr) table 8-29. mr field descriptions field description 0 strb_bypass strobe bypass the strb_bypass signal is used to bypass the strb signal used inside pll to latch the correct values for control bits (inc_step, mod_period and sprd_sel). 0 = strb is used to latch pll modulation control bits 1 = strb is bypassed. in this case control bits need to be static. the control bits must be changed only when pll is in power down mode. 2 sprd_sel spread type selection the sprd_sel control the spread type in frequency modulation mode. 0 = center spread 1 = down spread
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-37 preliminary?subject to change without notice 8.9.6 functional description 8.9.6.1 normal mode in normal mode the pll inputs are driven by the cr (see section 8.9.5.1, control register (cr)? ). this means that, when the pll is in lock state, the p ll output clock (phi) is derived by the reference clock (clkin) through equation 8-1 : eqn. 8-1 where the value of idf, ldf and odf ar e set in cr and can be derived from table 8-25 , table 8-26 , and table 8-27 . 8.9.6.2 progressive clock cwitching progressive clock switching allows to switch system clock to pll output clock stepping through different division factors. this means that th e current consumption gradually incr eases and so the voltage regulator has a better response. 3-15 mod_period modulation period the mod_period field is the binary equivalent of the value modperiod derived from following formula: where: fref: represents the frequency of the feedback divider fmod : represents the modulation frequency the maximum value of mod_period is 0x1000. 16 fm_en frequency modulation enable the fm_en enables the frequency modulation. 0 = frequency modulation disabled 1= frequency modulation enabled 17-31 inc_step increment step the inc_step field is the binary equivalent of the value incstep derived from following formula: where: md : represents the peak modulation depth in percentage (center spread -- pk-pk=+/-md, downspread -- pk-pk=-2*md) mdf : represents the nominal value of loop di vider (ndiv in pll control register) table 8-29. mr field descriptions (continued) field description modperiod f ref 4f mod ? -------------------- = incstep round 2 15 1 ? ?? md ? mdf ? 100 5 ? modperiod ? -------------------------------------------------------------- - ?? ?? = phi clkin ldf ? idf odf ? ----------------------------- =
pxd10 microcontroller reference manual, rev. 1 8-38 freescale semiconductor preliminary?subject to change without notice this feature can be enabled by pr ogramming the en_pll_sw bit in cr. th en, when the input pin pll_select goes high, the output cloc k ck_pll_div will progres sively increase its freque ncy as described in table 8-30 and figure 8-22 . figure 8-22. diagram of progressive clock switching 8.9.6.3 normal mode with frequency modulation the fmpll default mode is wit hout frequency modulation enabled. when frequency modulation is enabled, however, two parameters must be set to ge nerate the desired level of modulation: the period, and the step. the modulation waveform is always a triangle wave and its sh ape is not programmable. fm modulation shall be activated in two steps: ? first: configure the fm modulation charact eristics : mod_period, inc_step. ? second: enable the fm modulation by programming th e fm_en bit of mr register to 1. fm modulated mode can be enabled only when pll is in lock state. to latch these values inside the pll, two ways are usable depending on the value of strb_bypass register bit in mr. if strb_bypass is low, the modulat ion [parameters are latched in the pll only when the strb signal goes high for at least 2 cycles of infin clock. the st rb signal is automatically generated in the plld when the modulation is enabled (fm_en goes high) if the pll is[ locked (s_lock=1) or when the modulation has been enabled (fm_en=1) and p ll enters in lock state (s_lock goes high). if strb_bypass is high, the strb signal is bypassed. in this case, control bits (m od_period[12:0], inc_step[14:0], spread_cont rol) need to be static or hardwi red to constant values. the control bits must be changed only when the pll is in power down mode. the modulation depth in % is table 8-30. progressive clock switching on pll_select rising edge number of pll output clock cycles ck_pll_frequency (pll output clock frequency) 8 (ck_pll_out frequency)/8 16 (ck_pll_out frequency)/4 32 (ck_pll_out frequency)/2 onward (ck_pll_out frequency) ck_pll_out ck_pll_div ? 8 ? 4 ? 2 ? 1
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-39 preliminary?subject to change without notice note you must ensure that the value of modperiod does not exceed 0x1000 and that the product of inctep and modperiod is less than (2 15 -1). figure 8-23. pll frequency modulation modes 8.9.6.4 powerdown mode the pll can be switched off when not required to achieve lower consumption by programming the registers me_x_mc register on mc_me module. 8.9.6.5 1:1 mode (fmpll0 only) 1:1 mode is set by asserti ng the mode bit in cr (see section 8.9.5.1, contro l register (cr)? ). an external input signal (mode_en) has been provided to disable this feature. if mode_en is ti ed to 0, the mode bit in cr is disabled and there is no way to activate 1:1 mode. in 1:1 mode the inputs of the pll are driven by cr and mr, but the division factors and the modulation parameters have no influence on the output clock. in fact the dividers and the fm control are bypassed inside the pll. the pll output clock (phi) fre quency is determined by the following relation: modulationdepth 100 5 ? incstepxmodperiod ? 2 15 1 ? ?? mdf ? -------------------------------------------------------------------------------------------- - ?? ?? = phi clkin 2 ------------ - =
pxd10 microcontroller reference manual, rev. 1 8-40 freescale semiconductor preliminary?subject to change without notice 8.9.7 recommendations to avoid any unpredictable behavior of the pll cl ock, it is recommended to respect the following guidelines: ? the pll vco frequency should re side in the range 256 mhz to 512 mhz. care is required when programming the multiplication and division factors to respect this requirement. ? the user must change the mult iplication, division factors only wh en the pll output clock is not selected as system clock. mod_period, inc_ step, spread_sel bits should be modified before activating the fm modulated mode. then st robe has to be generated to enable the new settings. if strb_byp is set to 1 then mod_period, inc_step and spread_sel can be modified only when pll is in power down mode. ? use progressive clock switching. 8.10 clock monito r unit (cmu) 8.10.1 introduction the clock monitor unit (cmu), also referred to as clock quality checker or cl ock fault detector, serves two purposes. the main task is to permanently supervise the integrity of the device?s syst em clock sources, i.e., crystal oscillator fxosc, firc, and fmpll 0. if fmpll0 leaves an upper or lower frequency boundary or the crystal oscillator fails it can detect and forward this kind of event towards the mode and clock management unit. the clock management unit in turn can then switch to a safe mode where it uses a safe fallback clock source such as an on-chip rc os cillator, reset the device or generate the interrupt according to the system needs. it can also monitor external crysta l oscillator clock which must be gr eater than the internal rc clock divided by a division factor given by rcdiv[1:0] of cmu_csr regist er and generates a system clock transition request or an interrupt when enabled. the second task of the cmu is to provide a frequenc y meter, which allows to measure the frequency of one clock source vs. a reference clock. this is us eful to allow the calibration of the on-chip rc oscillator(s), as well as being able to correct/calcula te the time deviation of a counter which is clocked by the rc oscillator. note the cmu does not monitor sxosc, sirc, or fmpll_1.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-41 preliminary?subject to change without notice figure 8-24. cmu component interaction 8.10.2 main features ? rc oscillator frequency measurement ? external oscillator clock monitori ng with respect to ck_firc/n clock ? pll clock frequency monitoring wi th respect to ck_firc/4 clock ? event generation for various failur es detected insi de monitoring unit cmu ck 0 (reference) ck fxosc ck pll olr fll ircosc_clk 16 mhz fxosc_clk 4?16 mhz fmpll_0 64 mhz fxosc valid (on and stable)/off fmpll_0 valid (on and locked)/off mc_cgm fcu loss of crystal fmpll_0 freq. out of range
pxd10 microcontroller reference manual, rev. 1 8-42 freescale semiconductor preliminary?subject to change without notice 8.10.3 block diagram figure 8-25. clock monitor unit diagram 8.10.4 functional description the names of the clocks involved in th is block have the following meaning: ? ck_fxosc : clock coming from th e external crystal oscillator. ? ck_sirc: clock coming from the low frequency internal rc oscillator. ? ck_firc: clock coming from the high frequency internal rc oscillator. ? ck_pll : clock coming from the pll. ? fosc : frequency of external crystal oscillator clock. ? frcslow: frequency of low fre quency internal rc oscillator. ? frcfast: frequency of high fr equency internal rc oscillator. ? fpll : frequency of fmpll clock. cmu_mdr register fxosc supervisor fosc < frc fast / n cmu_href register fixed prescaler /4 fpll > href or fpll < frc fast / 4 fpll < lfref cmu_lfref register frequency meter cmu_fdr register pll supervisor olr_evt flc_evt_a fhh_evt_a fll_evt_a fxosc on/off from mc_me pll on/off from mc_me mux 1 cksel1[1:0] 00 01 10 11 ck_firc ck_firc ck_sirc ck_sxosc ck_fxosc ckpll_a
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-43 preliminary?subject to change without notice 8.10.4.1 crystal clock monitor if fosc is smaller than frcfast divided by 2 rcdiv . bits of cmu_csr and th e ck_fxosc is ?on? as signalled by the mc_me then: ? an event pending bit olri in cmu_isr is set. ? a failure event olr is signalled to the mc_rgm which in turn can automatically switch to a safe fallback clock and generate an interrupt or a reset. 8.10.4.2 pll clock monitor the pll clock ck_pll frequency can be monitored by programming cme bit of cmu_csr register to ?1?. ck_pll monitor starts as soon as cme bit is set. this monitor can be disabled at any time by writing cme bit to ?0?. if ck_pll frequency (fpll) is grea ter than a reference value determin ed by the hfref[11:0] bits of cmu_hfrefr and the ck _pll is ?on? as signalled by the mc_me then ? an event pending bit fhhi in cmu_isr is set, ? a failure event is signalled to the mc_rgm and fault co llection unit which in turn can generate an interrupt or a reset. if fpll is less than a reference clock frequency (f rc/4) and the ck_pll is ?on? as signalled by the mc_me then an event pending bit flci in cmu_isr will be set. if fpll is less than a reference value determined by the lfref[11:0] bits of cmu_lfrefr and the ck_pll is ?on? as signalled by the mc_me then ? an event pending bit flli in cmu_isr is set, ? a failure event fll is signalled to the mc_rgm which can generate an interrupt or a reset. note the on-chip rc oscillator is used as the reliable reference clock for the clock supervision. in order to avoid false events, proper programming of the dividers is required. these have to take into account the accuracy and frequency deviation of the rc oscillator. 8.10.4.3 frequency meter the purpose of frequency meter is to calibrate th e internal rc oscillator (ck_irc) using a known frequency. hint: this value can then be stored into the flash so that application software can reuse it later on. the reference clock will be always the fxosc. the frequency meter returns a precise value of ck_32k, ck_firc or ck_sirc according to cksel1 bit value. the measure starts when sfm (start frequency measure) bit in cmu_csr is set to ?1?. the meas urement duration is given by the cmu_mdr register in numbers of clock cycles of the selected clock source with a width of 20 bits. the sfm bit is reset to ?0? by the hardware once the frequency measurement is done and the count is loaded in the cmu_fdr .the frequency frc can be derived from the value lo aded in the cmu_fdr register as follows :
pxd10 microcontroller reference manual, rev. 1 8-44 freescale semiconductor preliminary?subject to change without notice frc = (fosc * md) / n, eqn. 8-2 where n is the value in cmu_fdr regist er and md is the value in cmu_mdr. frequency meter by default evaluate s ck_firc, but the software can swap to ck_sirc or ck_sxosc by programming the cksel bits in cmu_csr register.t he ckon bits indicate wh ich is the actual clock at the output of the multiplexer mux1 8.10.5 memory map and register description the memory map of the cmu is shown in the following table. 8.10.5.1 control status register (cmu_csr) table 8-31. rc digital interface register set - base address 0xc3fe_0100 register name address offset location control status register (cmu_csr) 0x00 on page 44 frequency display register (cmu_fdr) 0x04 on page 45 high frequency reference register fmpll0(cmu_hfrefr_a) 0x08 on page 46 low frequency reference register fmpll0(cmu_lfrefr_a) 0x0c on page 46 interrupt status register (cmu_isr) 0x10 on page 47 reserved 0x14 ? measurement duration register (cmu_mdr) 0x18 on page 48 address offset: 0x00 reset value: 0x00000006 0123456789101112131415 reserved sfm reserved rrsr 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved cksel1 reserved rcdiv cme_ a r rw r rw rw table 8-32. control status register (cmu_csr)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-45 preliminary?subject to change without notice 8.10.5.2 frequency display register (cmu_fdr) . table 8-33. control status register (cmu_csr) field descriptions field description 8 sfm start frequency measure the software can only set this bit to start a clock frequency measure. it is reset by hardware when the measure is ready in the cmu_fdr register. 0: frequency measurement is completed or not yet started. 1: frequency measurement is not completed. 22-23 cksel1 rc oscillator(s) selection bit cksel1 selects the clock to be measured by the frequency meter. 00: ck_firc is selected. 01: ck_sirc is selected. 10: ck_sxosc crystal oscillator clock is selected. 11: ck_firc is selected. 29-30 rcdiv[1:0 ] rc clock division factor these bits specify the rc clock divisi on factor. the output clock is ck_irc fast divided by the factor 2 rcdiv . this output clock is used to compare with ck_fxosc for crystal clock monitor feature.the clock division coding is as follows. 00: clock divided by 1 (no division) 01: clock divided by 2 10: clock divided by 4 11: clock divided by 8 31 cme_a fmpll0 clock monitor enable 0: fmpll0 monitor is disabled. 1: fmpll0 monitor is enabled. address offset: 0x04 reset value: 0x00000000 0123456789101112131415 reserved fd[19:16] rr 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 fd[15:0] r table 8-34. frequency display register (cmu_fdr) table 8-35. frequency display register (cmu_fdr) field descriptions field description 12-31 fd measured frequency bits this register displays the measured frequency frc with respect to fosc. the measured value is given by the following formula: frc = (fosc * md) / n, where n is the value in cmu_fdr register
pxd10 microcontroller reference manual, rev. 1 8-46 freescale semiconductor preliminary?subject to change without notice 8.10.5.3 high frequency referenc e register fmpll0 (cmu_hfrefr) 8.10.5.4 low frequency reference register fmpll0 (cmu_lfrefr) address offset: 0x08 reset value: 0x00000fff 0123456789101112131415 reserved r 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved hfref[11:0] rrw table 8-36. high frequency reference register fmpll0 table 8-37. high frequency reference register fmpll0 field descriptions field description 20-31 hfref high frequency reference value these bits determine the high reference valu e for the fmpll0 clock. the reference value is given by: (hfref [11:0]/16) * (frc fast /4). address offset: 0x0c reset value: 0x00000000 0123456789101112131415 reserved r 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved lfref[11:0] rrw table 8-38. low frequency reference register fmpll0 table 8-39. low frequency reference register fmpll0 field descriptions field description 20-31 lfref low frequency reference value these bits determine the low reference value for the fmpll0. the reference value is given by: (lfref[11:0]/16) * (frc fast /4).
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 8-47 preliminary?subject to change without notice 8.10.5.5 interrupt status register (cmu_isr) address offset: 0x10 reset value: 0x00000000 0123456789101112131415 reserved r 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved fhhi flli olri r rcrcrc table 8-40. interrupt status register (cmu_isr) table 8-41. interrupt status regi ster (cmu_isr) field descriptions field description 29 fhhi fmpll0 clock frequency higher than high reference interrupt this bit is set by hardware when ck_fmpll frequency becomes higher than hfref value and ck_fmpll is ?on? as signalled by the mc_me. it can be cleared by software by writing ?1?. 0: no fhh event. 1: fhh event is pending. 30 flli fmpll0 clock frequency less than low reference event this bit is set by hardware when ck_fmpll frequency becomes lower than lfref value and ck_fmpll is ?on? as signalled by the mc_m e. it can be cleared by software by writing ?1?. 0: no fll event. 1: fll event is pending. 31 olri oscillator frequency less than rc frequency event this bit is set by hardware when the frequency of ck_fxosc is less than ck_firc/2 rcdiv frequency and ck_fxosc is ?on? as signalled by the mc_me. it can be cleared by software by writing ?1?. 0: no olr event. 1: olr event is pending.
pxd10 microcontroller reference manual, rev. 1 8-48 freescale semiconductor preliminary?subject to change without notice 8.10.5.6 measurement duration register (cmu_mdr) 8.10.6 register map address offset: 0x18 reset value: 0x00000000 0123456789101112131415 reserved md[19:16] rrw 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 md[15:0] rw table 8-42. measurement duration register (cmu_mdr) table 8-43. measurement duration register (cmu_mdr) field descriptions field description 12-31 md measurement duration bits this register displays the measured duration in term of irc clock cycles. this value is loaded in the frequency meter downcounter. wh en sfm bit is set to ?1?, downcounter starts counting. address offset register name 012345678910111213141516171819202122232425262728293031 00 cmu_csr reserved sfm reserved cksel1 reserved rcdiv cme 04 cmu_fdr reserved fd[12:31] 08 cmu_hfre fr reserved hfref 0c cmu_lfre fr reserved lfref 10 cmu_isr reserved fhhi_a flli_a olri 14 reserved reserved 18 cmu_mdr reserved md[12:31] table 8-44. cmu register map
pxd10 microcontroller reference manual, rev. 1 9-1 freescale semiconductor preliminary?subject to change without notice chapter 9 configurable enhanced modular io subsystem (emios200) 9.1 device-specific information this section describes the features actually implem ented on this device. the features which are not specified in this section are not implemented, even if they are present in other parts of the chapter. the emios provides timer (ic/oc) and pwm functiona lity. on this device, two emios blocks have channels clocked by either a m odulated or a non-modulated clock. emios200_0 is a 16-channel module; emios200_1 is an 8-channel module. 9.1.1 unsupported features ? real-time signal bus client ? wheel speed channels ? emios0 channels 0-7 and channels 24-31 ? channels 9-15 do not support ope rations on internal counter ? emios1 channels 0-15 and channels 24-31 9.1.2 device-specific configuration ? both emios200_0 and emios200_1 can work on a ny of the four auxiliary clock sources: ?irc ?fxosc ? fmpll0 ? fmpll1 ? for emios200_0: ? counter bus a is driven by unified channel #23 ? counter bus c is driven by unified channel #8 ? counter bus d is driven by unified channel #16 ? unified channels 9?15 do not have their own time base ? for emios200_1: ? counter bus a is driven by unified channel #23 ? counter bus d is driven by unified channel #16
pxd10 microcontroller reference manual, rev. 1 9-2 freescale semiconductor preliminary?subject to change without notice 9.1.3 emios clocking configuration the clocking configurations of the emios200_0 and emios200_1 modules on this device are shown in figure 9-1 . figure 9-1. emios clocking configuration 9.1.4 pxd10 family comparison the following table shows the require d split of emios channel functiona lity across the pxd10 family as a function of flash memory size. 9.1.5 channel types the channels of the emios200_0 an d emios200_1 blocks on th is device are implemented using a variety of different channel configurati ons. the available modes of operati on for each channel are shown in table 9-2 and table 9-3 . table 9-1. emios total channel summary pxd1005 pxd1010 16-bit opwm 16 16 16-bit ic/oc 8 8 fmpll_0 emios200_0 cgm_ac1_sc[selctl] modulated clock fmpll_1 emios200_1 non-modulated clock 8 channel ic/oc 8 channel opwm 8 channel opwm 16 mhz irc 4-16 mhz fxosc (in mc_cgm) cgm_ac2_sc[selctl] (in mc_cgm)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-3 preliminary?subject to change without notice table 9-2. emios200_0 channel configurations acronym mode channels 8 ic/oc counter 9-15 ic/oc 16 pwm counter 17-22 pwm 23 pwm counter gpio general purpose input/output xxxxx saic single action input capture xxxxx saoc single action output compare xxxxx mcb modulus counter buffered xxx opwfmb output pulse width and frequency modulation buffered xxx opwmb output pulse width modulation buffered xxx table 9-3. emios200_1 channel configurations acronym mode channels 16 pwm counter 17-22 pwm 23 pwm counter gpio general purpose input/output xxx saic single action input capture xxx saoc single action output compare xxx mcb modulus counter buffered xx opwfmb output pulse width and frequency modulation buffered xxx opwmb output pulse width modulation buffered xxx
pxd10 microcontroller reference manual, rev. 1 9-4 freescale semiconductor preliminary?subject to change without notice 9.1.6 unified channel block figure 9-2 shows the block diagram of unified channel bl ock as it is implemented in this device. figure 9-2. unified channel block 9.1.6.1 channel mode selection the following is a portion of em ios200 uc control register (e miosc[n]), (please refer to section 9.4.2.8, emios200 uc cont rol register (emiosc[n]) ).
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-5 preliminary?subject to change without notice address : base + 0x0000 access: read/write 0123456789101112131415 r 00000000000 0 0000 w 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000 mode[0:6] w = reserved figure 9-3. channel mode selection field table 9-4. channel mode selection field description field description bit 25:31 mode[25:31 ] the mode[0:6] bits select the chan nel mode operation, as shown in ta bl e 9 - 5 . table 9-5. channel mode selection mode[0:6] 1 1 b = adjust parameters for the mode of operation. refer to section 9.5.1.1, uc modes of operation,? for details. mode of operation 0000000 general purpose input/output mode (input) 0000001 general purpose input/output mode (output) 0000010 single action input capture 0000011 single action output compare 0000100 to 1001111 reserved 101000b modulus counter buffered (up counter) 1010010 reserved 10101bb modulus counter buffered (up/down counter) 10110b0 output pulse width and frequency modulation buffered 10110b1 to 10111b1 reserved 11000b0 output pulse width modulation buffered 1100001 to 1111111 reserved
pxd10 microcontroller reference manual, rev. 1 9-6 freescale semiconductor preliminary?subject to change without notice 9.2 introduction figure 9-4 shows the block diagram of th e configurable emios200 block. figure 9-4. emios200 block diagram 1 1.this diagram shows a 24-channel emios200. on pxd10, emios200_0 has 16 channels (8?23) and emios200_1 has 8 channels (16?23). thus, not all channels shown are available. redc real-time signal biu counter buses (time bases) ip interface submodules all iib interrupt signals slave bus signals global signals dma interface signals global time global time enhanced modular input/output system clock prescaler system clock internal counter clock enable ................ output disable control bus [a] ch[0] emiosi[0] emioso[0] ipp_obe_emios_ch[0] see note 1 emios_flag_out[0] notes: 1. connection between uc[n-1] and uc[n] ch[7] emiosi[7] emioso[7] ipp_obe_emios_ch[7] emios_flag_out[7] [b] [a] ch[8] emiosi[8] emioso[8] ipp_obe_emios_ch[8] emios_flag_out[8] ch[15] emiosi[15] emioso[15] ipp_obe_emios_ch[15] emios_flag_out[15] [c] [a] ch16] emiosi[16] emioso[16] ipp_obe_emios_ch[16] emios_flag_out[16] ch[23] emiosi[23] emioso[23] ipp_obe_emios_ch[23] emios_flag_out[23] [d] counter buses (time bases) ................ counter buses (time bases) ................ necessary to implement qdec mode base enable out base enable in output disable input[0:3] notes: 2: illustration of a 28 channel emios200
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-7 preliminary?subject to change without notice 9.2.1 overview the configurable enhanced modul ar input/output subsystem (emios 200) provides functionality to generate or measure time events. it is the para meterized version of the emios block keeping full functional backwards compatibility. its overall architecture resembles that of the mios figure 9-4 . the predecessor mios timer block provides a framework where a set of subl ocks with different timer functions are assembled to attend the specific needs of a so c. the emios200 builds on this concept by using a unified channel module that provides a superset of the functionality of all the individual mios channels, while providing a consistent user inte rface. this allows more flexibility as each unified channel can be programmed for different functions in different applications of the soc. besides that, emios200 architecture allows usi ng dedicated channels which perform spec ific functions not included in mios inheritance. 9.2.2 features the basic features of the emios 200 on this device are the following: ? 24 channels (16 in emios200_0 and 8 in em ios200_1) chosen among unified or dedicated channels not necessarily numbered in a continuous sequence ? data registers of 16-bit width ? counter buses c and d can be driven by unified channel 8 and 16, respectively ? counter bus a can be driven by the unified channel #23 or by th e external shared timer bus (real-time signal bus client) ? each channel has its own time base , alternative to the counter buses ? one global prescaler ? one prescaler per channel (cp) ? shared timebases through the counter buses ? one real-time signal bus client (redc) ? control and status bits grouped in a single register ? synchronization among timebases ? global flag register ? state of the uc can be frozen for debug purposes ? motor control capability 9.2.3 modes of operation the unified channels can be configured to operate in the following modes: ? general purpose input/output ? single action input capture ? single action output compare ? modulus counter buffered ? output pulse width and frequency modulation buffered
pxd10 microcontroller reference manual, rev. 1 9-8 freescale semiconductor preliminary?subject to change without notice ? output pulse width modulation buffered these modes are described in section 9.5.1.1, uc modes of operation .? each channel can have a specific set of mode s implemented, according to devices requirements. if an unimplemented mode is selected the results ar e unpredictable such as writing a reserved value to mode[0:6] in section 9.4.2.8, emios200 uc cont rol register (emiosc[n]) . 9.3 external signal description 9.3.1 overview each channel has one external input and one external output signal, as described in table 9-6 . depending on the chip integration, the input and output signals can be connected to two separate pins, or to a single bidirectional pin. 9.3.2 detailed signal descriptions 9.3.2.1 emiosi[n] - emios200 channel input signal emiosi[n] is synchronized and filtered by the input programmabl e filter (ipf). the output of the ipf is then used by the channel logic an d is available to be read by the mcu through the ucin bit of the emioss[n] register. 9.3.2.2 emioso[n] - emios200 channel output signal emioso[n] is a registered output and is available for reading by th e mcu through the ucout bit of the emioss[n] register. whilst the channel is opera ting in input modes the signal state is unknown. 9.3.2.3 emios_flag_out[n] - emios200 channel flag signal emios_flag_out[n] outputs the state of f[n] bit of emiosgflag register. table 9-6. external signals signal direction function reset state pull up emiosi[n] input emios200 channel n input - chip dependent emioso[n] output emios200 channel n output 0/ hi-z 1 1 value ?0? refers to the reset value of the signal. hi-z refers to the state of the external pin if a tristate output buffer is controlled by the corresponding ipp_obe_emios_ch[n] signal. chip dependent emios_flag_out[n] output emios200 channel n flag 0 chip dependent
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-9 preliminary?subject to change without notice 9.4 memory map and register description 9.4.1 memory map the overall address map or ganization is shown in table 9-7 . whenever an access to either an absent register or absent channel is perf ormed the emios200 responds asserting transfer error signal from the slave bus in terface, as well as for access to reserved address. 9.4.1.1 unified channel memory map addresses of unified channel register s are specified as offsets from the channel?s base address, otherwise the emios200 base address is used as reference. table 9-8 describes the unified channel memory map. table 9-7. emios200 memory map emios200[n] base address description location 0x000 0x003 module configuration register (emiosmcr) on page 10 0x004 0x007 global flag register (emiosgflag) on page 12 0x008 0x00b output update disable (emiosoudis) on page 13 0x00c 0x00f disable channel (emiosucdis) on page 14 0x010 0x11f reserved ? 0x120 0x21f channel [8] to channel [15] 0x220 0x31f channel [16] to channel [23] 0x320 0xfff reserved ? table 9-8. unified channel memory map uc[n] base address description 0x00 a register (emiosa[n]) 0x04 b register (emiosb[n]) 0x08 counter register (emioscnt[n])
pxd10 microcontroller reference manual, rev. 1 9-10 freescale semiconductor preliminary?subject to change without notice 9.4.2 register description all control registers are 32 bits wi de. this document illustrates the emios200 with 24 unified channels and 16-bit wide data registers. 9.4.2.1 emios200 module config uration register (emiosmcr) the emiosmcr contains global co ntrol bits for the emios200 block. 0x0c control register (emiosc[n]) 0x10 status register (emioss[n]) 0x14 alternate a register (emiosalta[n]) 0x18 - 0x1f reserved address: emios200 base address +0x00 0123456789101112131415 r 0 mdis frz gtbe etb gpre n 000000 srv w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r gpre 00000000 w reset: 0000000000000000 = unimplemented or reserved figure 9-5. emios200 module configuration register (emiosmcr) table 9-8. unified channel memory map
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-11 preliminary?subject to change without notice table 9-9. emiosmcr field descriptions field description mdis module disable puts the emios200 in low power mode. the mdis bit is used to stop the clock of the block, except the access to registers emiosm cr, emiosoudis and emiosucdis. 1 = enter low power mode 0 = clock is running frz freeze enable the emios200 to freeze t he registers of the unified cha nnels when the mcu is stopped by a debugger. each unified channel should have fren bit set in order to enter freeze state. while in freeze state, the emios200 continues to operate to allow the mcu access to the unified channels registers. the unified channel will remain frozen until the frz bit is written to zero or the mcu exits debug mode or the unified channel fren bit is cleared. 1 = stops unified channels operation when in debug mode and the fren bit is set in the emiosc[n] register 0 = exit freeze state gtbe global time base enable the gtbe bit is used to export a global time base enable from the module and provide a method to start time bases of several blocks simultaneously. 1 = global time base enable out signal asserted 0 = global time base enable out signal negated note: the global time base enable input pin controls the internal counters. when asserted, internal counters are enabled. when negated, internal counters disabled. etb external time base the etb bit selects the time base so urce that drives counter bus[a]. 1 = counter bus[a] assigned to redc 0 = counter bus[a] assigned to unified channel gpren global prescaler enable the gpren bit enables the prescaler counter. 1 = prescaler enabled 0 = prescaler disabled (no clock) and prescaler counter is cleared srv server time slot the srv[0:3] bits select the address of a specific real-time signal server to which the redc is assigned (refer to section 9.5.3, real-time signal client submodule (redc),? for details). gpre global prescaler the gpre[0:7] bits select the clock divider value for the global prescaler, as shown in ta b l e 9 - 1 0 . table 9-10. global prescaler clock divider gpre[0:7] divide ratio 00000000 1 00000001 2 00000010 3 00000011 4
pxd10 microcontroller reference manual, rev. 1 9-12 freescale semiconductor preliminary?subject to change without notice 9.4.2.2 emios200 global flag register (emiosgflag) the emiosgflag is a read-only register that groups the flag bits from all ch annels. this organization improves interrupt handling on simpler devi ces. each bit relates to one channel. the two modules on this device, emios0 and emios1, have diff erent structures for th is register as shown in figure 9-6 and figure 9-7 . for unified channels these bits are mirrors of the flag bits in the emioss[n] register. . . . . . . . . 11111110 255 11111111 256 address: emios0 base address +0x04 0123456789101112131415 r 00000000f23f22f21f20f19f18f17f16 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r f15f14f13f12f11f10f9f800000000 w reset: 0000000000000000 = unimplemented or reserved figure 9-6. emios200 global flag register (emiosgflag) for emios0 table 9-10. global prescaler clock divider (continued) gpre[0:7] divide ratio
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-13 preliminary?subject to change without notice f[n] ? channel [n] flag bit channels that occupy a pair of slots are referred to by their lower slot number (l sb=0 standard), therefore the bits corresponding to their hi gher slot number always read 0. 9.4.2.3 emios200 output update disable (emiosoudis) the two modules on this device, emios0 and emios1, have diff erent structures for th is register as shown in figure 9-8 and figure 9-9 . address: emios1 base address +0x04 0123456789101112131415 r 00000000f23f22f21f20f19f18f17f16 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w reset: 0000000000000000 = unimplemented or reserved figure 9-7. emios200 global flag register (emiosgflag) for emios1 address: emios0 base address +0x08 0123456789101112131415 r 00000000ou23ou22ou21ou20ou19ou18ou17ou16 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ou15ou14ou13ou12ou11ou10ou9ou800000000 w reset: 0000000000000000 = unimplemented or reserved figure 9-8. emios200 output update disable register (emiosoudis) for emios0
pxd10 microcontroller reference manual, rev. 1 9-14 freescale semiconductor preliminary?subject to change without notice 9.4.2.4 emios200 disable channel (emiosucdis) the two modules on this device, emios0 and emios1, have diff erent structures for th is register as shown in figure 9-10 and figure 9-11 . address: emios1 base address +0x08 0123456789101112131415 r 00000000ou23ou22ou21ou20ou19ou18ou17ou16 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w reset: 0000000000000000 = unimplemented or reserved figure 9-9. emios200 output update disable register (emiosoudis) for emios1 table 9-11. emios200 output update disable register (emiosoudis) field descriptions field description ou[n] channel [n] output update disable bit when running mcb or an output mode, values are written to registers a2 and b2. ou[n] bits are used to disable transfers from registers a2 to a1 and b2 to b1. each bit controls one channel. 1 = transfers disabled 0 = transfer enabled. depending on the operation mode, transfer may occur immediately or in the next period. unless stated otherwise, transfer occurs immediately.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-15 preliminary?subject to change without notice address: emios0 base address +0x0c 0123456789101112131415 r 00000000chdi s23 chdi s22 chdi s21 chdi s20 chdi s19 chdi s18 chdi s17 chdi s16 w reset: 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r chdi s15 chdi s14 chdi s13 chdi s12 chdi s11 chdis 10 chdi s9 chdi s8 00000000 w reset: 00000000 = unimplemented or reserved figure 9-10. emios200 enable channel register (emiosucdis) for emios200_0 address: emios1 base address +0x0c 0123456789101112131415 r 00000000chdi s23 chdi s22 chdi s21 chdi s20 chdi s19 chdi s18 chdi s17 chdi s16 w reset: 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w reset: = unimplemented or reserved figure 9-11. emios200 enable channel register (emiosucdis) for emios200_1
pxd10 microcontroller reference manual, rev. 1 9-16 freescale semiconductor preliminary?subject to change without notice 9.4.2.5 emios200 uc a re gister (emiosa[n]) depending on the mode of operation, in ternal registers a1 or a2, used for matches and captures, can be assigned to address emiosa[n]. both a1 and a2 are cleared by reset. figure 9-13 summarizes the emiosa[n] writing and reading acces ses for all operation modes. for more information see section section 9.5.1.1, uc modes of operation . table 9-12. emios200 enable channel register (emiosucdis) field descriptions field description chdis[n] enable channel [n] bit the chdis[n] bit is used to disable each of t he channels by stopping its respective clock. 1 = channel [n] disabled 0 = channel [n] enabled note: channels that occupy a pair of slots are referr ed to as by their lower slot number (lsb=0 standard), therefore the bits corresponding to their higher slot number are reserved and read 0. address: uc[n] base address + 0x00 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r a w reset: 0000000000000000 = unimplemented or reserved figure 9-12. emios200 uc a register (emiosa[n])
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-17 preliminary?subject to change without notice 9.4.2.6 emios200 uc b re gister (emiosb[n]) depending on the mode of operation, internal registers b1 or b2 can be assigned to address emiosb[n]. both b1 and b2 are cleared by reset. table 9-13 summarizes the emiosb[n] writing and reading accesses for all operation modes. for mo re information see section section 9.5.1.1, uc modes of operation . depending on the channel configurati on it may have emiosb register or not. emiosb register is required for the following modes: op wmb, opwfmb, mcb. it means that if no mode requiring emiosb register is implemented then the register can be rem oved during synthesis through proper parameterization. address: uc[n] base address + 0x04 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r b w reset: 0000000000000000 = unimplemented or reserved figure 9-13. emios200 uc b register (emiosb[n]) table 9-13. emiosa[n], emiosb[n] and emiosalta [n] values assignments operation mode register access write read write read alt write alt read gpio a1, a2 a1 b1,b2 b1 a2 a2 saic 1 - a2b2b2 - - saoc 1 1 in these modes, the register emiosb[n] is not used, but b2 can be accessed. a2 a1 b2 b2 - - mcb 1 a2 a1 b2 b2 - - opwfmb a2 a1 b2 b1 - - opwmb a2a1b2b1 - -
pxd10 microcontroller reference manual, rev. 1 9-18 freescale semiconductor preliminary?subject to change without notice 9.4.2.7 emios200 uc counter register (emioscnt[n]) the emioscnt[n] register contains th e value of the internal counter. when gpio mode is selected or the channel is frozen, the emioscnt[n] re gister is read/write. for all others modes, the emioscnt[n] is a read-only register. when entering some operation modes, this register is automatically cleared (refer to section 9.5.1.1, uc modes of operation,? for details). depending on the channel c onfiguration it may have em ioscnt register or not. emioscnt register is required for the following modes: opwfmb, mcb. it means that if no m ode requiring emioscnt register is implemented then the register can be removed during synthesis through proper parameterization. it is possible that, for particular reasons, emioscnt be available in one device even if the respective channel does not feature any mode that requires it . in this case emioscnt availability should be explicitly described in the device soc guide. 9.4.2.8 emios200 uc control register (emiosc[n]) the control register gathers bits reflecting the stat us of the uc input/output signals and the overflow condition of the internal counter, as we ll as several read/write control bits. address: uc[n] base address + 0x08 0123456789101112131415 r 0000000000000000 w 1 1 in gpio mode or freeze action, this register is writable. reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r c w 1 reset: 0000000000000000 = unimplemented or reserved figure 9-14. emios200 uc count er register (emioscnt[n])
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-19 preliminary?subject to change without notice address: uc[n] base address + 0x0c 0123456789101112131415 r fren odis odissl[0:1] ucpre[0:1] ucpr en dma 0 if[0:3] fck fen 0 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000 bsl[0:1] edse l edpo l mode[0:6] w forc ma forc mb reset: 0000000000000000 = unimplemented or reserved figure 9-15. emios200 uc control register (emiosc[n]) table 9-14. emiosc[n] field descriptions field description bit 0 fren freeze enable bit the fren bit, if set and validated by frz bit in emiosmcr register allows the channel to enter freeze state, freezing all registers values when in debug mode and allowing the mcu to perform debug functions. 1 = freeze uc registers values 0 = normal operation bit 1 odis output disable bit the odis bit allows disabling the output pin when running any of the output modes with the exception of gpio mode. 1 = if the selected output disable input signal is asserted, the output pin goes to edpol for opwfmb and opwmb modes and to the complement of edpol for other output modes, but the unified channel continues to operate normally, i. e., it continues to produce flag and matches. when the selected output disable input signal is negated, the output pin operates normally 0 = the output pin operates normally bit 2:3 odissl[0:1] output disable select bits the odissl[0:1] bits select one of the four output disable input signals, as shown in ta b l e 9 - 1 5 . bit 4:5 ucpre[0:1] prescaler bits the ucpre[0:1] bits select the clock divider value for the internal prescaler of unified channel, as shown in ta b l e 9 - 1 6 . bit 6 ucpren prescaler enable bit the ucpren bit enables the prescaler counter. 1 = prescaler enabled 0 = prescaler disabled (no clock)0:1
pxd10 microcontroller reference manual, rev. 1 9-20 freescale semiconductor preliminary?subject to change without notice bit 7 dma direct memory access bit the dma bit selects if the flag generation will be used as an interrupt or as a dma request. 1 = flag/overrun assigned to dma request 0 = flag/overrun assigned to interrupt request bit 9:12 if[0:3] input filter bits the if[0:3] bits control the programmable input filt er, selecting the minimum input pulse width that can pass through the filter, as shown in ta b l e 9 - 1 7 . for output modes, these bits have no meaning. bit 13 fck filter clock select bit the fck bit selects the clock source for the programmable input filter. 1 = main clock 0 = prescaled clock bit 14 fen flag enable bit the fen bit allows the unified channel flag bit to generate an interrupt signal or a dma request signal (the type of signal to be generated is defined by the dma bit). 1 = enable (flag will generate an interrupt or dma request) 0 = disable (flag does not generate an interrupt or dma request) bit 18 forcma force match a bit for output modes, the forcma bit is equivalent to a successful comparison on comparator a (except that the flag bit is not set). this bit is cleared by reset and is always read as zero. this bit is valid for every output operation mode which us es comparator a, othe rwise it has no effect. 1 = force a match at comparator a 0 = has no effect note: for input modes, the forcma bit is not used and writing to it has no effect. bit 19 forcmb force match b bit for output modes, the forcmb bit is equivalent to a successful comparison on comparator b (except that the flag bit is not set). this bit is cleared by reset and is always read as zero. this bit is valid for every output operation mode which us es comparator b, otherwise it has no effect. 1 = force a match at comparator b 0 = has not effect note: for input modes, the forcmb bit is not used and writing to it has no effect. bit 21:22 bsl[0:1] bus select bits the bsl[0:1] bits are used to select either one of the counter buses or the internal counter to be used by the unified channel. refer to ta b l e 9 - 1 8 for details. bit 23 edsel edge selection bit for input modes, the edsel bit selects whether the internal counter is triggered by both edges of a pulse or just by a single edge as defined by the edpol bit. when not shown in the mode of operation description, this bit has no effect. 1 = both edges triggering 0 = single edge triggering defined by the edpol bit for gpio in mode, the edsel bit selects if a flag can be generated. 1 = no flag is generated 0 = a flag is generated as defined by the edpol bit for saoc mode, the edsel bit selects the behavi or of the output flip-flop at each match. 1 = the output flip-flop is toggled 0 = the edpol value is transferred to the output flip-flop table 9-14. emiosc[n] field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-21 preliminary?subject to change without notice bit 24 edpol edge polarity bit for input modes (except qdec mode), the edpol bi t asserts which edge triggers either the internal counter or an input capture or a flag. when not shown in the mode of operation description, this bit has no effect. 1 = trigger on a rising edge 0 = trigger on a falling edge for qdec (mode[6] cleared), the edpol bit selects the count direction according to direction signal (uc[n] input). 1 = counts up when uc[n] is asserted 0 = counts down when uc[n] is asserted note: uc[n-1] edpol bit selects which edge clocks the internal counter of uc[n] 1 = trigger on a rising edge 0 = trigger on a falling edge for qdec (mode[6] set), the edpol bit selects the count direction according to the phase difference. 1 = internal counter increments if phase_a is ahead phase_b signal 0 = internal counter decrements if phase_a is ahead phase_b signal note: in order to operate properly, edpol bit must contain the same value in uc[n] and uc[n-1] for output modes, the edpol bit is used to select the logic level on the output pin. 1 = a match on comparator a sets the output f lip-flop, while a match on comparator b clears it 0 = a match on comparator a clears the output flip -flop, while a match on comparator b sets it bit 25:31 mode[0:6] mode selection bits the mode[0:6] bits select the mode of operation of the unified channel, as shown in ta bl e 9 - 1 9 . note: if a reserved value is written to mode the results are unpredictable. table 9-15. uc odissl selection odissl[0:1] emios200_0 channel emios200_1 channel input signal 00 emios_flag_out[8] emios_flag_out[16] output disable input 0 01 emios_flag_out[9] emios_flag_out[17] output disable input 1 10 emios_flag_out[10] emios_flag_out[18] output disable input 2 11 emios_flag_out[11] emios_flag_out[19] output disable input 3 table 9-16. uc internal prescaler clock divider ucpre[0:1] divide ratio 00 1 01 2 10 3 11 4 table 9-14. emiosc[n] field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 9-22 freescale semiconductor preliminary?subject to change without notice table 9-17. uc input filter bits if[0:3] 1 1 filter latency is 3 clock edges. minimum input pulse width [flt_clk periods] 0000 bypassed 2 2 the input signal is synchronized befor e arriving to the digital filter. 0001 02 0010 04 0100 08 1000 16 all others reserved table 9-18. uc bsl bits bsl[0:1] selected bus 00 all channels: counter bus[a] 01 channels 8 to 15: counter bus[c] channels 16 to 23: counter bus[d] 10 reserved 11 all channels: internal counter
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-23 preliminary?subject to change without notice 9.4.2.9 emios200 uc status register (emioss[n]) emioss[n] address: uc [n] base address + 0x10 figure 9-16. emios200 uc status register (emioss[n]) table 9-19. uc mode bits mode[0:6] 1 1 b = adjust parameters for the mode of operation. refer to section 9.5.1.1, uc modes of operation,? for details. mode of operation 0000000 general purpose input/output mode (input) 0000001 general purpose input/output mode (output) 0000010 single action input capture 0000011 single action output compare 0000100 through 1001111 reserved 101000b modulus counter buffered (up counter) 101001b reserved 10101bb modulus counter buffered (up/down counter) 10110b0 output pulse width and frequency modulation buffered 10110b1 reserved 10111b0 reserved 10111b1 reserved 11000b0 output pulse width modulation buffered 1100001 through 1111111 reserved 0123456789101112131415 rovr000000000000000 ww1c reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rovf l 000000000000ucinuco ut fla g ww1c w1c reset: 0 0 00000000000000 = unimplemented or reserved
pxd10 microcontroller reference manual, rev. 1 9-24 freescale semiconductor preliminary?subject to change without notice ovr ? overrun bit the ovr bit indicates that flag generation occurred when the flag bit was already set. this bit can be cleared by writing a 1 to it or by writing a 1 to the flag bit. 1 = overrun has occurred 0 = overrun has not occurred ovfl ? overflow bit the ovfl bit indicates that an overflow has occurred in the internal counter. ovfl must be cleared by software writing a 1 to it. 1 = an overflow had occurred 0 = no overflow ucin ? unified channel input pin bit the ucin bit reflects the input pin stat e after being filter ed and synchronized. ucout ? unified channel output pin bit the ucout bit reflects the output pin state. flag ? flag bit the flag bit is set when an input capture or a match event in the co mparators occurred. to clear this bit, write a 1 to it. 1 = flag set event has occurred 0 = flag cleared note emios_flag_out reflects the flag bit value. when dma bit is set, the flag bit can be cleared by the dma controller. 9.4.2.10 emios200 uc alternate a register (emiosalta[n]) emiosalta[n] address: uc[n] base address + 0x14
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-25 preliminary?subject to change without notice figure 9-17. emios200 uc alternate a register (emiosalta[n]) the emiosalta[n] register provides an alternate address to access a2 channel registers in restricted modes (gpio) only. if emiosa[n] re gister is used along with emiosalta[n], both a1 and a2 registers can be accessed in these modes. table 9-13 summarizes the emiosalta[n] writing and reading accesses for all operation modes. 9.5 functional description the emios200 provides i ndependent channels (uc) that can be configured and accessed by a host mcu. up to four time bases can be shared by the channe ls through four counter bu ses and each channel can generate its own time base. optionally one of the count er buses can be driven by an external time base imported through the real -time signal interface. the emios200 module is based on a mult i-bus timer architecture in which several timer channels are used to drive counter buses that are sh ared among the channels. there are 4 counter buses in the module: one global counter bus, shared by all channels and 4 loca l counter buses, each one de dicated to a slice of 8 channels. counter bus a is referred to as the global counter bus. counter buses b, c, and d are the local counter buses. the emios200 counter buses ar e driven by channels in specific locati ons. the global count er bus is driven by the channel in channel slot [23]. co unter buses b, c, and d are driven by channels in slots [0], [8], and [16] respectively. counter bus a dr ives all channels. counter bus b dr ives channels in slots from [0] through [7]. counter bus c drives channels in slots from [8] through [15]. counter bus d drives channels in slots from [16] through [23]. note that the first channel in an 8-ch annel slice drives the local counter bus for that slice, therefore this channel should not be assigned to be driven by the same counter bus, otherwise a loop occurs. the emios200 interrupt re quest signal, dma transf er request signal among others, are wired to a specific channel, thus the chip integrator should connect those signals having the emios200 channel configuration in mind. 0123456789101112131415 r 0000000000000000 w reset 0 000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ralta w reset: 0 000000000000000 = unimplemented or reserved
pxd10 microcontroller reference manual, rev. 1 9-26 freescale semiconductor preliminary?subject to change without notice the emios200 block is reset asynchronously . all registers ar e cleared on reset. figure 9-18 describes an emios200 block c onfigured with 32 unified channels. note that the redline is also present. note also that indepe ndent of the configuration the channels are fixed in their slots, thus for exempla if channel [2] is not required this location will be empty, meaning that th e other channels locations are not affected. in this case th e application software should not ac cess any register located in the channel[2] memory. any attempt to access those regist ers will return no meaningful data and a transfer error will be generated . figure 9-18. emios200 full channel configuration using unified channels only channel[23] channel[16] channel[15] channel[8] channel[7] channel[0] bus [d] bus [c] bus [b] global counter bus [a] real-time signals (former stac bus) emios[15] emios[8] emios[7] emios[0] emios[23] emios[16] output disable inputs[3:0] biu all global prescaler all system ip clock gtbe_out global regs gtbe_in all channels interface output disable bus[3:0] enhanced modular i/o subsystem emios200 channels channels
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-27 preliminary?subject to change without notice 9.5.1 unified channel (uc) figure 9-19 shows the unified channel block diagra m. each unified ch annel consists of: ? counter bus selector, which selects the time base to be used by the channel for all timing functions ? a programmable clock prescaler ? two double buffered data registers a and b that allow up to two input capture and/or output compare events to occur before software intervention is needed. ? two comparators (equal only) a and b, which compares the selected counter bus with the value in the data registers ? internal counter, which can be used as a local time base or to count input events ? programmable input filter, which ensures that only valid pin transitions are received by channel ? programmable input edge de tector, which detects the ri sing, falling or either edges ? an output flip-flop, which holds the logic level to be applied to the output pin ? emios200 status and control register ? an output disable input selector, which selects the output disable input signal that will be used as output disable figure 9-19. unified ch annel block diagram figure 9-20 shows both the unified channel control and da tapath block diagram. the control block is responsible for the generation of signa ls to control the multiplexes in the datapath sub-block. each mode is implemented by a dedicated logic independent from others modes, t hus allowing to optimize the logic by disabling the mode and therefore its associated logic. the unused gates are removed during the synthesis phase. targeting the logic optimization a set of registers is shared by the modes thus providing sequencial events to be stored. ips_rwb uc_int_flag rwcb biu_channel_en biu_a_en biu_b_en biu_cnt_en biu_control_en biu_status_en ips_byte_7_0 ips_byte_15_8 ips_byte_23_16 ips_byte_31_24 iib programmable filter clock prescaler uc_ctrl ipd_req ipd_done rqb mode logic unified channel ips_addr[27:29] uc_rd_data[0:31] ips_wdata[0:31] uc_datapath comparator a comparator b internal counter counter bus local counter [b/c/d/e] global counter [a]
pxd10 microcontroller reference manual, rev. 1 9-28 freescale semiconductor preliminary?subject to change without notice the datapath block provides the channel a and b regi sters, the internal time base and comparators. multiplexors select the input of comp arators and data for the registers inputs, thus c onfiguring the datapath in order to implement the channel m odes. the outputs of a and b compar ators are connected to the uc_ctrl control block. figure 9-20. unified channel control and datapath block diagrams 9.5.1.1 uc modes of operation the mode of operation of the unified channel is dete rmined by the mode select bits mode[0:6] in the emiosc[n] register (see figure 9-19 for details). when entering an output mode (except for gpio mode), the output flip-flop is set to disabled state according to odis bit in the emiosc[n] register. a2 b2 b1 a1 cnt local counter bus global counter bus[a] a comparator bsl[0] bsl[1]+logic bsl[1]+logic bsl[1]+logic internal counter [b/c/d/e] b comparator uc_datapath uc_ctrl control signals input filter input mode 0 logic general purpose registers mode 1 logic mode n logic mode decoder mode register == ==
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-29 preliminary?subject to change without notice as the internal counter emioscnt[n] continues to run in all modes (excep t for gpio mode), it is possible to use this as a time base if the re source is not used in the current mode. in order to provide smooth waveform generation even if a and b registers are ch anged on the fly, it is available the mcb, opwfmb, and opwmb modes. in these modes a and b registers are double buffered. 9.5.1.1.1 general purpose i nput/output mode (gpio) mode in gpio mode, all input capture and output compare functions of the uc are disabled, the internal counter (emioscnt[n] register) is cleared a nd disabled. all control bits remain accessible. in order to prepare the uc for a new operation mode, writing to register s emiosa[n] or emiosb[n] stores the same value in registers a1/a2 or b1/b2, respectively. writing to register emiosalta[n] stores a value only in register a2. mode[6] bit selects between input (mode[6] = 0) and output (mode[6] = 1) modes. it is required that when changing m ode[0:6], the application software goes to gpio mode first in order to reset the uc?s internal functions properly. failure to do this could lead to invalid and unexpected output compare or input capture results or the flags being set incorrectly. in gpio input mode (mode[0:6]=0000000), the flag generation is determined according to edpol and edsel bits and the input pin status ca n be determined by reading the ucin bit. in gpio output mode (mode[0:6]=0000001), the unified channel is used as a single output port pin and the value of the edpol bit is permanen tly transferred to the output flip-flop. 9.5.1.1.2 single action in put capture (saic) mode in saic mode (mode[0:6]=0000010), when a triggeri ng event occurs on the i nput pin, the value on the selected time base is captured into register a2. the flag bit is set along with the capture event to indicate that an input capture has occurred. register emiosa[n ] returns the value of register a2. as soon as the saic mode is entered comin g out from gpio mode the channel is re ady to capture events. the events are captured as soon as they occur thus reading register a always returns the value of the latest captured event. subsequent captures are enabled with no need of further reads from em iosa[n] register. the flag is set at any time a new event is captured. the input capture is triggered by a ri sing, falling or either edges in th e input pin, as c onfigured by edpol and edsel bits in emiosc[n] register. figure 9-21 and figure 9-22 shows how the unified channel can be used for input capture.
pxd10 microcontroller reference manual, rev. 1 9-30 freescale semiconductor preliminary?subject to change without notice figure 9-21. single action input captur e with rising edge triggering example figure 9-22. single action input capture with both edges triggering example 9.5.1.1.3 single action out put compare (saoc) mode in saoc mode (mode[0:6]=0000011) a match value is loaded in regi ster a2 and then immediately transferred to register a1 to be compared with the selected time ba se. when a match occurs, the edsel bit selects whether the output flip-fl op is toggled or the value in edpo l is transferred to it. along with the match the flag bit is set to indicate that the out put compare match has occurr ed. writing to register emiosa[n] stores the value in regist er a2 and reading to re gister emiosa[n] returns the value of register a1. an output compare match can be simulated in so ftware by setting the forcma bit in emiosc[n] register. in this case, the flag bit is not set. when saoc mode is entered coming out from gpio mo de the output flip-flop is set to the complement of the edpol bit in the emiosc[n] register. counter bus can be either internal or extern al and is selected th rough bsl[0:1] bits. figure 9-23 and figure 9-24 show how the unified channel can be used to perform a single output compare with edpol value being transferred to the output flip-flop and toggli ng the output flip-flop at each match, respectively. note that once in saoc m ode the matches are enabled thus the desired match value on register a1 must be written before the mode is entered. a1 register can be updated at any time thus modifying the match value which will reflect in the output signal generated by the channel. selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 flag pin/register a2 (captured) value 2 0xxxxxxx 0x001000 0x001250 0x0016a0 input signal 1 edge detect edge detect edge detect notes: 1. afte r input filter 2. emiosa[n] <= a2 edsel = 0 edpol = 1 selected counter bus 0x001000 0x001102 flag set event a2 (captured) value 2 0xxxxxxx 0x001000 input signal 1 edge detect notes: 1. after input filter 2. emiosa[n] <= a2 0x001103 0x001108 0x001104 0x001105 0x001106 0x001107 0x001001 flag pin/register edge detect flag clear edge detect 0x001103 0x001108 edsel = 1 edpol = x
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-31 preliminary?subject to change without notice subsequent matches are enabled with no need of further writes to em iosa[n] register. the flag is set at the same time a match occurs. note the channel internal counter in sa oc mode is free-running. it starts counting as soon as the saoc mode is entered. figure 9-23. saoc example with edpol value being transferred to the output flip-flop figure 9-24. saoc example togg ling the output flip-flop 9.5.1.1.4 modulus counter buffered (mcb) mode the mcb mode provides a time base which can be shared with other ch annels through the internal counter buses. register a1 is double buffere d thus allowing smooth transitions between cycles when changing a2 register value on the fly. a1 register is updated at th e cycle boundary, which is defined as when the internal counter transitions to 0x1. selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 output flip-flop update to a1 a1 value 1 0xxxxxxx 0x001000 flag pin/register 0x001000 0x001000 0x001000 a1 match a1 match a1 match notes: 1. emiosa[n] = a2 edsel = 0 edpol = 1 a2 = a1 according to ou[n] bit selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 a1 value 1 0xxxxxxx 0x001000 output flip-flop update to a1 flag pin/register a1 match a1 match a1 match 0x001000 0x001000 0x001000 notes: 1. emiosa[n] = a2 edsel = 1 edpol = x a2 = a1 according to ou[n] bit selected counter bus 0x0 0x2 flag set event a2 value 1 0x1 output flip-flop note: 1. emiosa[n] <= a2 0x0 0x2 0x1 0x2 0x0 0x1 0x1 flag pin/register flag clear edsel = 1 system clock a1 match edpol = x
pxd10 microcontroller reference manual, rev. 1 9-32 freescale semiconductor preliminary?subject to change without notice the internal counter values operates within a range from 0x1 up to register a1 value. if when entering mcb mode coming out from gpio mode the internal counter value is not within that range then the a match will not occur causi ng the channel internal counter to wrap at the maximum count er value which is 0xffff for a 16-bit counter. after the counter wrap occurs it returns to 0x1 and resume normal mcb mode operation. thus in order to avoid the counter wrap c ondition make sure its value is within the 0x1 to a1 register value range when the mcb mode is entered. mode[6] bit selects internal clock source if cleared or external if set. when exte rnal clock is selected the input channel pin is used as the channel clock source. the active edge of this clock is defined by edpol and edsel bits in the emiosc[n] channel register. when entering in mcb mode, if up counter is selected by mode[4]=0 (mode[0:6]=101000b), the internal counter starts c ounting from its current value to up direct ion until a1 match occurs. the internal counter is set to 0x1 when its value matches a1 value and a clock tick occurs (either prescaled clock or input pin event). if up/down counter is selected by setting mode[4]= 1, the counter changes dire ction at a1 match and counts down until it reaches the valu e 0x1. after it has reache d 0x1 it is set to count in up direction again. b1 register is used to generate a match in order to set the internal c ounter in up-count di rection if up/down mode is selected. register b1 cannot be changed while this mode is selected. note that the mcb mode counts betw een 0x1 and a1 register value. only values greater than 0x1 must be written at a1 register. loading values other than th ose leads to unpredictable results. the counter cycle period is equal to a1 value in up counter mode. if in up/down counter mode the period is defined by the expression: (2*a1)-2. figure 9-25 describes the counter cycle for se veral a1 values. register a1 is loaded with a2 register value at the cycle boundary. thus any value written to a2 register within cycle n will be updated to a1 at the next cycle boundary and therefore will be used on cycle n+1 . the cycle boundary between cycle n and cycle n+1 is defined as when the internal count er transitions from a1 value in cycle n to 0x1 in cycle n+1 . note that the flag is generated at the cycle boundary and has a s ynchronous operation, meaning that it is asserted one system clock cycle after the flag set event.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-33 preliminary?subject to change without notice figure 9-25. modulus counter buffered (mcb) up count mode figure 9-26 describes the mcb in up/down counter mode (mode[0:6]=10101bb). a1 register is updated at the cycle boundary. if a2 is written in cycle n , this new value will be used in cycle n+1 for a1 match. flags are generated only at a1 match start if mode[5] is 0. if mode[5] is set to 1 flags are also generated at the cycle boundary. figure 9-26. modulus counter buffered (mcb) up/down mode figure 9-27 describes in more detail the a1 register update proce ss in up counter mode. the a1 load signal is generated at the last system clock period of a count er cycle. thus, a1 is updated with a2 value at the same time that the counter (emioscnt[n]) is loaded with 0x1. the load signal pulse has the duration of one system clock period. if a2 is written within cycle n its value is available at a1 at the first clock of cycle n+1 and the new value is used for match at cycle n+1 . the update disable bits ou[n] of emiosoudis register can be used to control the update of this regist er, thus allowing to delay the a1 register update for synchronization purposes. emioscnt[n] time write to a2 match a1 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000007 flag set event a1 value 0x000006 0x000005 0x000007 0x000007 0x000005 0x000007 a2 value flag pin/register prescaler ratio = 1 cycle n cycle n+1 cycle n+2 flag clear emioscnt[n] time write to a2 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000007 flag set event a1 value 0x000006 0x000005 0x000007 0x000005 0x000007 a2 value flag pin/register prescaler ratio = 1 cycle n+1 cycle n+2 cycle n flag clear
pxd10 microcontroller reference manual, rev. 1 9-34 freescale semiconductor preliminary?subject to change without notice figure 9-27. mcb mode a1 register update in up counter mode figure 9-28 describes the a1 register update in up/down counter mode. note th at a2 can be written at any time within cycle n in order to be used in cycle n+1 . thus a1 receives this new value at the next cycle boundary. note that the update disabl e bits ou[n] of emiosoudis regist er can be used to disable the update of a1 register. figure 9-28. mcb mode a1 register update in up/down counter mode 9.5.1.1.5 output pulse wi dth and frequency modulatio n buffered (opwfmb) mode this mode (mode[0:6]=10110b0) provides waveforms with variable duty cycle and frequency. the internal channel counter is automatica lly selected as the time base when this mode is selected. a1 register indicates the duty cycle and b1 register the frequenc y. both a1 and b1 registers are double buffered to allow smooth signal generation when changing the regi sters values on the fly. 0% and 100% duty cycles are supported. at opwfmb mode entry the output flip-flop is set to the value of the edpol bit in the emiosc[n] register. a1 value 0x000008 0x000008 0x000001 internal counter 0x000004 0x000006 a2 value 0x000008 0x000004 0x000006 0x000002 0x000004 0x000006 write to a2 write to a2 match a1 match a1 a1 load signal 8 4 6 match a1 counter = a1 time cycle n cycle n+1 cycle n+2 prescaler ratio = 2 a1 value 0x000006 a2 value 0x000006 0x000005 0x000006 0x000005 a1 load signal counter = 2 emioscnt[n] time write to a2 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000006 cycle n cycle n+1 cycle n+2 prescaler ratio = 2
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-35 preliminary?subject to change without notice if when entering opwfmb mode co ming out from gpio mode the intern al counter value is not within that range then the b match will not occur causing th e channel internal counter to wrap at the maximum counter value which is 0xffff for a 16-bit counter. after the counter wrap occurs it returns to 0x1 and resume normal opwfmb mode operation. thus in orde r to avoid the counter wrap condition make sure its value is within the 0x1 to b1 register va lue range when the opwfmb mode is entered. when a match on comparator a occurs the output register is set to the value of edpol. when a match on comparator b occurs the output register is set to th e complement of edpol. b1 match also causes the internal counter to transition to 0x1, thus restarting the counter cycle. only values greater than 0x1 are allowed to be written to b1 register. loading valu es other than those leads to unpredictable results. figure 9-29 describes the operation of the opwfmb mode regarding output pin transitions and a1/b1 registers match events. note that the output pin tran sition occurs when the a1 or b1 match signal is deasserted which is indicated by the a1 match negedge detection signal. if register a1 is set to 0x4 the output pin transitions 4 count er periods after the cycle had started, plus one system clock cycle. note that in the example shown in figure 9-29 the internal counter prescaler has a ratio of two. figure 9-29. opwfmb a1 and b1 match to output register delay figure 9-30 describes the generated output si gnal if a1 is set to 0x0. since the counter does not reach zero in this mode, the channel internal logic infers a match as if a1=0x1 with the difference that in this case, the posedge of the match signal is used to trigger the output pin transition instead of the negedge used when a1=0x1. note that a1 posed ge match signal from cycle n+1 occurs at the same time as b1 negedge match signal from cycle n . this allows to use the a1 posedge match to mask the b1 negedge match when they occur at the same time. the result is that no transition occurs on the output flip-flop a nd a 0% duty cycle is generated. 8 1 4 match a1 negedge detection 5 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 emioscnt time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 system clock prescaler prescaler ratio = 2
pxd10 microcontroller reference manual, rev. 1 9-36 freescale semiconductor preliminary?subject to change without notice figure 9-30. opwfmb mode with a1 = 0 (0% duty cycle) figure 9-31 describes the timing for the a1 and b1 register s load. the a1 and b1 load use the same signal which is generated at the last sy stem clock period of a counter cy cle. thus, a1 and b1 are updated respectively with a2 and b2 values at the same time that the counter (emioscnt[n]) is loaded with 0x1. this event is defined as the cycle boundary. the load signal pulse has the duration of one system clock period. if a2 and b2 ar e written within cycle n their values are available at a1 and b1, respectively, at the first clock of cycle n+1 and the new values are used for matches at cycle n+1 . the update disable bits ou[n] of emiosoudis regist er can be used to control the update of these registers, thus allowing to delay the a1 and b1 registers update for synchronization purposes. in figure 9-31 it is assumed that both the channel and global prescalers are set to 0x1 (each divide ratio is two), meaning that the channel intern al counter transitions at every f our system clock cycles. flags can be generated only on b1 matches when mode[5] is cleared, or on both a1 and b1 matches when mode[5] is set. since b1 flag occurs at the cycle bounda ry, this flag can be used to indicate that a2 or b2 data written on cycle n were loaded to a1 or b1, respectiv ely, thus generating matches in cycle n+1 . note that the flag has a synchronous operation, meaning that it is assert ed one system cl ock cycle after the flag set event. 1 4 match a1 negedge detection 5 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 emioscnt time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 system clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection no transition at this point 1 cycle n cycle n+1 prescaler ratio = 2
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-37 preliminary?subject to change without notice figure 9-31. opwfmb a1 and b1 registers update and flags figure 9-32 describes the operation of the output disable feature in op wfmb mode. the output disable forces the channel output flip-flop to edpol bit value. this functionali ty targets applications that use active high signals and a high to low transition at a1 match. in this ca se edpol should be set to 0. note that both the channel and global prescalers are set to 0x0 (each divide ratio is one), meaning that the channel internal counter transiti ons at every system clock cycle. edpol = 0 cycle n cycle n+1 cycle n+2 a1 value 1 b1 value b2 value 0x8 0x2 0x6 0x8 0x1 internal counter 0x4 0x6 mode [6] = 1 a2 value 1 0x2 0x4 0x6 0x2 0x4 0x6 0x8 0x6 output pin write to b2 write to a2 write to a2 match a1 match a1 match b1 match b1 match b1 a1/b1 load signal due to b1 match cycle n-1 flag set event flag pin/register prescaler ratio = 4 flag clear
pxd10 microcontroller reference manual, rev. 1 9-38 freescale semiconductor preliminary?subject to change without notice figure 9-32. opwfmb mode with active output disable note that the output disabl e has a synchronous operation, meaning that the assertion of th e output disable input pin causes the channel output flip-flop to transition to edpol at the next system clock cycle. if the output disable input is deasserted the output pin transition at the following a1 or b1 match. in figure 9-32 it is assumed that the output disable input is enabled and selected for the channel. see section 9.4.2.8, emios200 uc contro l register (emiosc[n]),? for a detailed descri ption about the odis and odissl bits, respectively enable and selection of the output disable inputs. the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on comparators a or b respectively. simi larly to a b1 match forcmb sets the internal counter to 0x1. the flag bit is not set by the forcma or forcmb bits being asserted. figure 9-33 describes the generation of 100% and 0% duty cycle signals. it is assumed edpol =0 and the resultant prescaler value is 1. initially a1=0x8 and b1=0x8. in this case, b1 match has precedence over a1 match, thus the output flip-flop is set to the comp lement of edpol bit. this cycle corresponds to a 100% duty cycle signal. the same out put signal can be generated for any a1 value greater or equal to b1. edpol = 0 cycle n cycle n+1 cycle n+2 a1 value b1 value b2 value 0x000008 0x000002 0x000006 0x000008 0x000001 internal counter 0x000004 0x000006 mode [6] = 1 a2 value 0x000002 0x000004 0x000006 0x000002 0x000004 0x000006 0x000008 0x000006 output pin write to b2 write to a2 write to a2 match a1 match a1 match b1 match b1 match b1 due to b1 match cycle n-1 flag set event output disable flag pin/register prescaler ratio = 1 flag set event
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-39 preliminary?subject to change without notice figure 9-33. opwfmb mode from 100% to 0% duty cycle a 0% duty cycle signal is gene rated if a1=0x0 as shown in figure 9-33 cycle 9. in this case b1=0x8 match from cycle 8 occurs at the same time as the a1=0x0 match from cycle 9. see figure 9-30 for a description of the a1 and b1 match generation. in this case a1 match has precedence over b1 match and the output signal transitions to edpol. 9.5.1.1.6 output pulse width m odulation buffered (opwmb) mode opwmb mode (mode[0:6]=11000b0) is used to genera te pulses with programma ble leading and trailing edge placement. an external counte r driven in mcb up mode must be selected from one of the counter buses. a1 register value defines the first edge and b1 the second edge. the output signal polarity is defined by the edpol bit. if edpol is zero, a negative edge occurs when a1 matches the selected counter bus; and a positive edge occu rs when b1 matches the selected counter bus. the a1 and b1 registers are double buffered and updated from a2 and b2, respectively, at the cycle boundary. the load operation is similar to the opwfmb mode. see figure 9-31 for more information about a1 and b1 registers update. flag can be generated at b1 matches, when mode[5 ] is cleared, or in both a1 and b1 matches, when mode[5] is set. if subsequent matches occur on co mparators a and b, the pwm pulses continue to be generated, regardless of the state of the flag bit. forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on a1 or b1 respectively. flag bi t is not set by the forcma and forcmb operations. at opwmb mode entry the output flip-flop is set to the value of the edpol bit in the emiosc[n] register. following are described some rule s applicable to the opwmb mode: ? b1 matches have precedence over a1 matches if they occur at the same time within the same counter cycle ? a1=0 match from cycle n has precedence over b1 match from cycle n-1 ? a1 matches are masked out if they occur after b1 match within the same cycle ? any value written to a2 or b2 on cycle n is loaded to a1 and b1 re gisters at the following cycle boundary (assuming ou[n] bit of emioso udis register is not asserted ). thus the new values will be used for a1 and b1 matches in cycle n+1 0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 0% 100% emioscnt edpol = 0 a1 value b1 value output pin 0x000008 prescaler ratio = 1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 a2 value 0x000008 0x000001
pxd10 microcontroller reference manual, rev. 1 9-40 freescale semiconductor preliminary?subject to change without notice figure 9-34 describes the operation of the opwmb mode regardi ng a1 and b1 matches and the transition of the channel output pin. in this example edpol is set to zero. figure 9-34. opwmb mode matches and flags note that the output pin transitions are based on the negedges of the a1 and b1 match signals. figure 9-34 shows in cycle n+1 the value of a1 regist er being set to zero. in this case the match posedge is used instead of the negedge to transi tion the output flip-flop. figure 9-35 describes the channel operation for 0% duty cy cle. note that the a1 match posedge signal occurs at the same time as the b1=0x8 negedge si gnal. in this case a1 match has precedence over b1 match, causing the output pin to rema in at edpol bit value, thus generating a 0% duty cycle signal. 1 4 match a1 negedge detection 6 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000006 clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection 1 cycle n cycle n+1 8 6 flag set event selected counter bus flag pin/register
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-41 preliminary?subject to change without notice figure 9-35. opwmb mode with 0% duty cycle figure 9-36 describes the operation of the opwmb mode with the out put disable signal being asserted. the output disable forces a transition in the output pin to the edpol bit value. after deasserted, the output disable allows the output pin to transition at the following a1 or b1 match. note that the output disable does not modify the flag b it behavior. note that there is one system clock delay between the assertion of the output disable signal and the transition of the output pin to edpol. 1 4 match a1 negedge detection 8 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 selected time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection 1 cycle n cycle n+1 8 counter bus flag set event flag pin/register
pxd10 microcontroller reference manual, rev. 1 9-42 freescale semiconductor preliminary?subject to change without notice figure 9-36. opwmb mode with active output disable figure 9-37 shows a waveform changing from 100% to 0% duty cycle. edpol in this case is zero. in this example b1 is programmed to the same value as the period of the external selected time base. figure 9-37. opwmb mode from 100% to 0% duty cycle in figure 9-37 if b1 is set to a value lower than 0x8 it is not possible to achieve 0% duty cycle by only changing a1 register value. since b1 matches have precedence ove r a1 matches the out put pin transitions to the opposite of edpol bit at b1 match. note also that if b1 is set to 0x9, for inst ance, b1 match does not occur, thus a 0% duty cycle signal is generated. 9.5.1.2 input programmable filter (ipf) the ipf ensures that only valid i nput pin transitions are received by the unified channel edge detector. a block diagram of the ipf is shown in figure 9-38 . edpol = 0 cycle n cycle n+1 cycle n+2 a1 value b1 value b2 value 0x000008 0x000002 0x000006 0x000008 0x000001 selected 0x000004 0x000006 mode [6] = 1 a2 value 0x000002 0x000004 0x000006 0x000002 0x000004 0x000006 0x000008 0x000006 output pin write to b2 write to a2 write to a2 match a1 match a1 match b1 match b1 match b1 due to b1 match cycle n-1 flag set event output disable counter bus flag pin/register flag clear 0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 0% 100% selected edpol = 0 a1 value b1 value output pin 0x000008 prescaler = 1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 counter bus 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 a2 value
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-43 preliminary?subject to change without notice the ipf is a 5-bit programmable up counter that is in cremented by the selected clock source, according to bits if[0:3] in emiosc[n] register. figure 9-38. lnput programmabl e filter submodule diagram the input signal is synchronized by sy stem clock. when a state change occurs in this signal, the 5-bit counter starts counti ng up. as long as the new state is stable on the pin, the counter remains incrementing. if a counter overflows occurs , the new pin value is valida ted. in this case, it is transmitted as a pulse edge to the edge detector. if the opposite edge appears on the pin before validation (o verflow), the counter is reset. at the next pin tran sition, the counter starts coun ting again. any pulse that is shorter than a full range of the masked counter is regarded as a glitch and it is not passed on to the edge de tector. a timing diagram of the input filter is shown in figure 9-39 . figure 9-39. input programmable filter example the filter is not disabled during eith er freeze state or negated gtbe input. 9.5.1.3 clock prescaler (cp) the cp divides the gcp output signal to generate a cl ock enable for the internal counter of the unified channels. the gcp output signal is prescaled by the value defined in figure 9-16 according to the ucpre[0:1] bits in emiosc[n] re gister. the prescaler is enabled by setting the ucpren bit in the emiosc[n] and can be stopped at any time by clearing this bit, thereby stopping the internal counter in the unified channel. if3 filter out ipg_clk prescaled clock if2 if1 if0 clk fck emiosi 5-bit up counter synchronizer clock time selected clock emiosi 5-bit counter filter out if [0:3] = 0010
pxd10 microcontroller reference manual, rev. 1 9-44 freescale semiconductor preliminary?subject to change without notice in order to ensure safe working and avoid glitches the following steps must be performed whenever any updtate in the prescali ng rate is desired: 1. write 0 at both gpren bit in em iosmcr register and ucpren bi t in emiosc[n] register, thus disabling prescalers; 2. write the desired value for pr escaling rate at ucpre[0:1] bits in emiosc[n] register; 3. enable channel prescaler by writing 1 at ucpren bit in emiosc[n] register; 4. enable global prescaler by writing 1 at gpren bit in emiosmcr register. the prescaler is not disabl ed during either freeze stat e or negated gtbe input. 9.5.1.4 effect of freeze on the unified channel when in debug mode, frz b it in the emiosmcr register and the fren bit in the emiosc[n] are both set, the internal counter and unif ied channel capture and compare func tions are halted. the uc is frozen in its current state. during freeze, all registers are accessi ble. when the unified channel is operating in an output mode, the force match functions remain available, allowing the software to force the output to the desired level. note that for input modes, any i nput events that may occur while the channel is frozen are ignored. when exiting debug mode or freeze enable bit is cleared (frz in the emio smcr or fren in the emiosc[n] register) the channel acti ons resume, but may be inconsistent until channel enters gpio mode again. 9.5.2 ip bus interface unit (biu) the biu provides the interface betw een the internal interface bus (iib ) and the peripheral bus, allowing communication among a ll submodules and this ip interface. the biu allows 8, 16 and 32 bits access. they are perf ormed over a 32-bit data bus in a single cycle clock. 9.5.2.1 effect of freeze on the biu when the frz bit in the emiosmcr register is se t and the module is in debug mode, the operation of biu is not affected. 9.5.3 real-time signal client submodule (redc) the redc provides one external time base, importe d from the real-time signa l bus (also called stac bus), to the un ified channels. figure 9-40 provides a block diagra m for the redc module.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-45 preliminary?subject to change without notice figure 9-40. redc block diagram bits srv[0:3] in register emiosmcr, selects the desire d time slot of the real- time signal bus to be output. figure 9-41 shows a timing diagram for the redc. figure 9-41. timing diagram for the real-time signal bus and redc output every time the selected time slot change, the redc output is updated. 9.5.3.1 effect of freeze on the redc when the frz bit in the emiosmcr register is se t and the module is in debug mode, the operation of redc submodule is not affected, i.e., ther e is no freeze functi on in this submodule. 9.5.4 global clock prescaler submodule (gcp) the gcp divides the system clock to generate a clock for the cps of the channels. the main clock signal is prescaled by the value defined in figure 9-10 according to the gpre[0:7] bits in emiosmcr register. the global prescaler is enabled by setting the gpren bit in the emiosmcr regi ster and can be stopped at any time by clearing this bit, thereby stoppi ng the internal counters in all the channels. in order to ensure safe working and avoid glitches the following steps must be performed whenever any updtate in the prescali ng rate is desired: 1. write 0 at gpren bit in emiosmcr regi ster, thus disabli ng global prescaler; 2. write the desired value for prescaling rate at gpre[0:7] bits in emiosmcr register; 3. enable global prescaler by writing 1 at gpren bit in emiosmcr register. the prescaler is not disabl ed during either freeze stat e or negated gtbe input. 9.5.4.1 effect of freeze on the gcp when the frz bit in the emiosmcr register is se t and the module is in debug mode, the operation of gcp submodule is not affected, i.e., there is no freeze function in this submodule. real-time signalbus time base redc output (16-bit wide) time slot selector bits srv2 srv1 srv0 srv3 real-time signal bus (redc input) ts[00] ts[01] ts[02] 1. maximum of 16 time slots (ts[n]) notes: ts[01] ts[00] ts[n] 1 ts[02] time base (redc output) ts[01] ts[01] xx 2. in this case, srv bits were set to capture ts[01]
pxd10 microcontroller reference manual, rev. 1 9-46 freescale semiconductor preliminary?subject to change without notice 9.6 initialization/application information on resetting the emios200 the unified channels enter gpio input mode. 9.6.1 considerations before changing an operating mode, the uc must be programmed to gpio mode and emiosa[n] and emiosb[n] registers must be updated with the corr ect values for the next operating mode. then the emiosc[n] register can be written with the new operating mode. if a uc is changed from one mode to another without performing this proc edure, the first operation cycle of the selected time base can be random, i.e., matches can occur in random time if th e contents of emiosa[n] or emiosb[n] were not updated with the correct value before the time base matches the previous c ontents of emiosa[n] or emiosb[n]. when interrupts are enabled, the software must clear the flag bits before exi ting the interrupt service routine. 9.6.2 application information correlated output signals can be generated by all output operation modes. bi ts ou[n] of emiosoudis register can be used to control the update of these output signals. in order to guarantee that the inte rnal counters of correlated channels are incremented in the same clock cycle, the internal prescalers must be set up before en abling the global prescaler. if the internal prescalers are set after enabling the global presca ler, the internal counters may increment in the same ratio, but at a different clock cycle. it is recommended to drive output disable input si gnals with the emios_fla g_out signals of some ucs running in saic mode. when an out put disable condition happens, the so ftware interrupt routine must service the output channels before servicing the channels running saic. this procedure avoid glitches in the output pins. 9.6.2.1 time base generation for the opwfm with internal clock source operation m ode, the internal counter rate can be modified by configuring the clock prescaler ratio. figure 9-42 shows an example of a time base with prescaler ratio equal to one. note mcb and opwfmb modes have a different behavior.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-47 preliminary?subject to change without notice figure 9-42. time base period when running in the fastest prescaler ratio if the prescaler ratio is greater than one or external clock is selected, the c ounter may behave in three different ways dependi ng on the channel mode: ? if mc mode and clear on match start and external clock sour ce are selected the internal counter behaves as described in figure 9-43 . ? if mc mode and clear on match start and internal clock source are selected the internal counter behaves as described in figure 9-44 . ? if mc mode and clear on match end are selected the internal counter behaves as described in figure 9-45 . ? if opwfm mode is selected the intern al counter behaves as described in figure 9-44 . the internal counter clears at the start of the match signal, skips the next prescaled clock edge and then increments in the subsequent prescaled clock edge. note mcb and opwfmb modes have a different behavior. figure 9-43. time base generation with external clock and clear on match start system clock input event/prescaler clock enable = 1 internal counter match value = 3 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 pre scaled clock ratio = 1 (bypassed) see note 1 flag set event note 1: when a match occurs, the first clock cycle is used to clear the internal counter, starting another period. flag pin/register flag clear system clock input event internal counter match value = 3 1 2 3 0 see note 1 note 1: when a match occurs, the first system clock cycle is used to clear the internal counter, and at the next edge of prescaler clock enable 1 2 the counter will start counting. 1 2 3 0 flag set event flag clear flag pin/register
pxd10 microcontroller reference manual, rev. 1 9-48 freescale semiconductor preliminary?subject to change without notice figure 9-44. time base generation with internal clock and clear on match start figure 9-45. time base generation with clear on match end 9.6.2.2 coherent accesses the flag set event can be detected by polling the fl ag bit or by enabling the interrupt or dma request generation. reading the emiosa[n] register again in the same period of th e last read of emiosb [n] register may lead to incoherent results. this will occur if the last re ad of emiosb[n] register o ccurred after a disabled b2 to b1 transfer. 9.6.2.3 channel/modes initialization the following basic steps summarize basic output mode startup, assuming the cha nnels are initially in gpio mode: 1. [global] disable global prescaler; 2. [timebase channel] disable channel prescaler; system clock prescaler clock enable internal counter match value = 3 0 1 3 0 2 0 3 0 prescaled clock ratio = 3 see note 1 note 1: when a match occurs, the first clock cycle is used to clear the internal counter, and only after a second edge of pre scaled clock 1 2 the counter will start counting. flag set event flag clear flag pin/register system clock input event/prescaler clock enable internal counter match value = 3 0 1 3 2 0 prescaled clock ratio = 3 see note 1 note 1: the match occurs only when the input event/prescaler clock enable is active. then, the internal counter is immediately cleared. 1 2 3 flag set event flag clear flag pin/register
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 9-49 preliminary?subject to change without notice 3. [timebase channel] write initial value at internal counter; 4. [timebase channel] set a/b register; 5. [timebase channel] set channel to mc(b) up mode; 6. [timebase channel] set prescaler ratio; 7. [timebase channel] enable channel prescaler; 8. [output channel] disable channel prescaler; 9. [output channel] set a/b register; 10. [output channel] select timebase input through bsl[1:0] bits; 11. [output channel] enter output mode; 12. [output channel] set prescaler ratio (same ratio as timebase channel); 13. [output channel] enable channel prescaler; 14. [global] enable global prescaler; 15. [global] enable global time base. the timebase channel and the output channel may be the same for some applications such as in opwfm(b) mode or whenever the output channe l is intended to run the timebase itself. at any time the flags can be configured.
pxd10 microcontroller reference manual, rev. 1 9-50 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 10-1 preliminary?subject to change without notice chapter 10 crossbar switch (xbar) 10.1 introduction this chapter describes the multi-por t crossbar switch (xbar), which supports simultane ous connections between four master ports and four slave ports. a port splitter allo ws three of the pxd10 slaves to be consolidated on one slave port. xbar supports a 32-bi t address bus width and a 32-bit data bus width at all master and slave ports. the crossbar of pxd10 is similar to that us ed on many ppc55xx and ppc56xx pr oducts except that it cannot be configured by software and th at it has a hard-wired configuration. 10.2 block diagram figure 10-1 shows a block diagram of the crossbar switch. figure 10-1. xbar block diagram 10.3 overview the xbar allows for concurre nt transactions to occur fr om any master port to any slave port. it is possible for all master ports and slave ports to be in use at the same time as a re sult of independent master requests. if a slave port is simultaneously requested by more th an one master port, arbitrat ion logic selects the higher e200z0h crossbar switch 512k master slave 16-ch dma display control unit (dcu) port splitter graphics core pbridge gram 4x128 page buffer (3-instruction/1-data) 4x128 page buffer (2-dcu/2-dma) pflash controller 4x16k flash eee 512k flash sram (no ecc) 160k sram (ecc) 48k data inst memory protection unit (mpu) modules modules ctrl pram ctrl quadspi
pxd10 microcontroller reference manual, rev. 1 10-2 freescale semiconductor preliminary?subject to change without notice priority master and grants it owne rship of the slave port. all other ma sters requesting that slave port are stalled until the higher priority master completes its transactions. requesting masters are gran ted access based on a fixed priority. a block diagram of th e xbar is shown in figure 10-1 . 10.4 features ? four master ports: ? core: e200z0h core instructions ? core: e200z0h core data / nexus ?edma ? display controller unit (dcu) ? six slave ports ? pflash-cpu ? pflash-dcu ? internal sram ? graphics sram ? peripheral bridge (pbridge) ? quadspi ? 32-bit address, 32-bit data paths ? fully concurrent transfers betwee n independent master and slave ports ? fixed priority scheme and fixed parking strategy 10.5 modes of operation 10.5.1 normal mode in normal mode, the xbar provides the logic th at controls crossbar switch configuration. 10.5.2 debug mode the xbar operation is unchanged when the cpu has debug mode active. 10.6 functional description this section describes the functiona lity of the xbar in more detail. 10.6.1 overview the main goal of the xbar is to increase overall system performance by allowing multiple masters to communicate concurrently with mult iple slaves. to maximize data th roughput, it is esse ntial to keep arbitration delays to a minimum.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 10-3 preliminary?subject to change without notice this section examines data throughput from the point of view of mast ers and slaves, detailing when the xbar stalls masters, or in serts bubbles on the slave side. 10.6.2 general operation when a master makes an access to the xbar from an idle master state, the access is taken immediately by the xbar. if the targeted slave por t of the access is availabl e (that is, the requesting master is currently granted ownership of the slave port), the access is immediately presented on the slave port. it is possible to make single clock (zero wait state) accesses through the xbar by a granted master . if the targeted slave port of the access is busy or parked on a different master port, the reques ting master receives wait states until the targeted slave port can se rvice the master request. the latenc y in servicing the request depends on each master?s priority level a nd the responding slave?s access time. because the xbar appears to be simply another slav e to the master device, the master device has no indication that it owns the slave port it is targeting. while the master doe s not have control of the slave port it is targeting, it is wait-stated. a master is given control of a targ eted slave port only after a previous access to a different slave port has completed, regardless of its priority on the newly targeted slave port. this prevents deadlock from occurring when a master has the following conditions: ? outstanding request to slave por t a that has a long response time ? pending access to a different slave port b ? lower priority master also makes a request to the different slave port b. in this case, the lower priority mast er is granted bus owners hip of slave port b after a cycle of arbitration, assuming the higher priority master sl ave port a access is not terminated. after a master has control of the slav e port it is targeting, the master re mains in control of that slave port until it gives up the slave port by running an idle cycle, leaves that slave port for its next access, or loses control of the slave port to a higher pr iority master with a request to the same slave port. however, because all masters run a fixed-length burst transfer to a slave port, it retain s control of the slave port until that transfer sequence is completed. when a slave bus is idled by the xbar, it is pa rked on the master which did the last transfer. 10.6.3 master ports a master access is taken if the slave port to which the access decodes is either currently servicing the master or is parked on the master. in this case, the xbar is completely transpar ent and the master access is immediately transmitted on the slave bus and no arbitr ation delays are incurred. a master access stall if the access decodes to a slave port that is busy serving another master, parked on another master. if the slave port is currently parked on another master , and no other master is re questing access to the slave port, then only one clock of arbitrati on is incurred. if the slave port is currently serving another master of a lower priority and the master has a higher priority than all other requesting masters, then the master gains control over the slave port as soon as the data phase of the current access is completed. if the slave port is currently servicing another ma ster of a higher priority, then the mast er gains control of the slave port after
pxd10 microcontroller reference manual, rev. 1 10-4 freescale semiconductor preliminary?subject to change without notice the other master releases control of the slave port if no other higher priority master is also waiting for the slave port. a master access is responded to with an error if th e access decodes to a locati on not occupied by a slave port. this is the only time the xbar directly responds with an error response. all other error responses received by the master are the result of error responses on the slave por ts being passed through the xbar. 10.6.4 slave ports the goal of the xbar with respect to the slave ports is to keep them 100% sa turated when masters are actively making requests. to do this the xbar must not insert any bubbles onto the slave bus unless absolutely necessary. there is only one instance when the xbar forces a bubble onto the slave bus when a master is actively making a request. this occurs when a handoff of bus ownership occurs and there are no wait states from the slave port. a requesting master which does not own the slave port is granted access after a one clock delay. 10.6.5 priority assignment each master port is assigned a fixe d 3-bit priority level (hard-wired priority). the following table shows the priority levels assigned to each ma ster (the lowest ha s highest priority). 10.6.6 arbitration xbar supports only a fixed-pr iority comparison algorithm. 10.6.6.1 fixed priority operation when operating in fixed-priority arbi tration mode, each master is assi gned a unique priority level in the xbar_mpr. if two masters bot h request access to a slave port, the master with the highest priority in the selected priority register ga ins control over the slave port. any time a master makes a request to a slave port, the slave port ch ecks to see if the new requesting master?s priority level is higher than that of the master that currently has control over the slave port (if any). the slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. table 10-1. hardwired bus master priorities module port priority level type number e200z0h core?cpu instructions master 0 7 e200z0h core?cpu data / nexus master 0 6 edma master 2 5 display control unit master 3 4
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 10-5 preliminary?subject to change without notice if the new requesting master?s priority level is higher than th at of the master that currently has control of the slave port, the higher priority master is grante d control at the terminati on of any currently pending access, assuming the pending transfer is not part of a burst transfer. a new requesting master must wait until the end of th e fixed-length burst transfer, before it is granted control of the slave port. but if the new requesting master ?s priority level is lower than that of the master that currently has control of the slav e port, the new requesting master is fo rced to wait until the master that currently has control of the slave port is finished accessing the current slave port. 10.6.6.1.1 parking if no master is currently requesting the slave port, the slave port is parked. the slave por t parks always to the last master (park-on-last). when parked on the last master, the slave port is passing that master?s signals through to the slave bus. when the ma ster accesses the slave port again, no other arbitration penalties are incurred except that a one clock arbitration penalt y is incurred for each access request to the slave port made by another master port. all ot her masters pay a one clock penalty.
pxd10 microcontroller reference manual, rev. 1 10-6 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-1 preliminary?subject to change without notice chapter 11 deserial serial peripheral interface (dspi) 11.1 introduction this chapter describes the deserial serial peripheral interface (dspi) , which provides a synchronous serial bus for communication between the mcu and an external peripheral device. this device implements d spi 0 and dspi 1. the "x" appended to signal names signifies the dspi module to which the signal applies. thus cs0_0 is the cs0 si gnal that applies to dspi 0, cs0_1 is the cs0 signal that applies to dspi 1. 11.2 block diagram a block diagram of the dspi is shown in figure 11-1 . figure 11-1. dspi block diagram cmd dma and interrupt control tx fifo rx fifo tx data rx data 16 16 shift register sout _x spi spi baud rate, delay and transfer control sin _x sck _x cs0_ x cs1:4 _x cs5 _x intc edma 4
pxd10 microcontroller reference manual, rev. 1 11-2 freescale semiconductor preliminary?subject to change without notice 11.3 overview the register content is tr ansmitted using an spi protocol. there are two identical dspi modules (dspi 0 and dspi 1) on the device. for queued operations the spi queues reside in inte rnal sram which is external to the dspi. data transfers between the queues and the dspi fifos are accomplished through the use of the edma controller or through host software. figure 11-2 shows a dspi with external queues in internal sram. figure 11-2. dspi with queues and edma 11.4 features the dspi supports these spi features: ? full-duplex, three-wire synchronous transfers ? master and slave mode ? buffered transmit and r eceive operation using the tx and rx fi fos, with depths of five entries ? visibility into tx and rx fifos for ease of debugging ? fifo bypass mode for low-latency updates to spi queues internal sram tx queue rx queue address/control tx fifo dspi rx fifo rx data tx data tx data rx data shift register edma controller address/control or host cpu
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-3 preliminary?subject to change without notice ? programmable transfer attributes on a per-frame basis ? 8 clock and transfer attribute registers ? serial clock with programmable polarity and phase ? programmable delays ? cs to sck delay ? sck to cs delay ? delay between frames ? programmable serial frame size of 4 to 16 bits, expanda ble with software control ? continuously held chip select capability ? 3 peripheral chip select s, expandable to 64 with external demultiplexer ? deglitching support for up to 32 peripheral ch ip selects with external demultiplexer ? 2 dma conditions for spi queues residing in ram or flash ? tx fifo is not full (tfff) ? rx fifo is not empty (rfdf) ? 6 interrupt conditions: ? end of queue reached (eoqf) ? tx fifo is not full (tfff) ? transfer of current frame complete (tcf) ? rx fifo is not empty (rfdf) ? fifo overrun (attempt to transmit with an empt y tx fifo or serial frame received while rx fifo is full) (rfof) ? fifo under flow (slave only and spi mode, the slave is asked to transfer data when the tx fifo is empty) (tfuf) ? modified spi transfer formats for comm unication with slower peripheral devices ? continuous serial comm unications clock (sck) 11.5 modes of operation the dspi has five modes of operation. these modes can be divided into two categories: ? module-specific modes such as mast er, slave, and module disable modes ? mcu-specific modes such as external stop and debug modes the module-specific modes are ente red by host software writing to a register. the mcu-specific modes are controlled by signals external to the dspi. the mcu-specific modes are modes that the entire device may enter, in parallel to the dspi bei ng in one of its module-specific modes. 11.5.1 master mode master mode allows the dspi to in itiate and control seri al communication. in this mode the sck, and cs n signals are controlled by the dspi and confi gured as outputs. (sout is always an output.)
pxd10 microcontroller reference manual, rev. 1 11-4 freescale semiconductor preliminary?subject to change without notice for more information, refer to section 11.8.1.1, master mode . 11.5.2 slave mode slave mode allows the dspi to communicate with spi bus masters. in this mode the dspi responds to externally controlled serial transfers. the dspi cannot initiate serial transfers in slave mode. in slave mode, the sck signal and the cs0_ x signal are configured as input s and provided by a bus master. cs0_ x must be configured as input and pul led high. if the internal pullup is be ing used then the appropriate bits in the relevant siu_pcr must be se t (siu_pcr [wpe = 1], [wps = 1]). for more information, refer to section 11.8.1.2, slave mode . 11.5.3 module disable mode the module disable mode is used for mcu power management. the clock to the non-memory mapped logic in the dspi is stopped while in module disabl e mode. the dspi enters the module disable mode when the mdis bit in dspi x _mcr is set. for more information, refer to section 11.8.1.3, modul e disable mode . 11.5.4 external stop mode the external stop mode is used for mcu power management. the dspi supports the ipi green-line interface stop mode mechanism. when a request is made to enter ex ternal stop mode, the dspi block acknowledges the request and complete s the transfer in progress. when the dspi reaches the frame boundary it signals that the system clocks to the dspi block may be shut off. 11.5.5 debug mode debug mode is used for system development and debugging. if the mcu is stopped by a debugger while the dspi x _mcr[frz] bit is set, the dspi halts opera tion on the next frame boundary. if the mcu is stopped by a debugger while the frz bit is cleared, the dspi behavior is unaffected and remains dictated by the module-specific mode a nd configuration of the dspi. for more information, refer to section 11.8.1.5, debug mode . 11.6 external signal description 11.6.1 signal overview table 11-1 lists off-chip dspi signals.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-5 preliminary?subject to change without notice 11.6.2 signal names and descriptions 11.6.2.1 peripheral chip sele ct / slave select (cs_0) in master mode, the cs_0 signal is a peripheral chip select output that selects the slave device to which the current transmission is intended. in slave mode, the cs_0 signal is a slave select input si gnal that allows an spi ma ster to select the dspi as the target for transmission. cs_0 must be configured as input and pulled high. if the internal pullup is being used then the appropriate bits in the re levant siu_pcr must be set (siu_pcr [wpe = 1], [wps = 1]). set the ibe and obe bits in the si u_pcr for all cs_0 pins when the dspi chip select or slave select primary function is selected for that pin. when the pin is used for dspi master mode as a chip select output, set the obe bit. when the pin is used in dspi sl ave mode as a slave select input, set the ibe bit. 11.6.2.2 peripheral chip selects 1?2 (cs1:2) cs1:2 are peripheral chip select out put signals in master mode. in slav e mode these signals are not used. 11.6.2.3 serial input (sin_ x ) sin_ x is a serial data input signal. 11.6.2.4 serial output (sout_ x ) sout_ x is a serial data output signal. 11.6.2.5 serial clock (sck_ x ) sck_ x is a serial communication clock signal. in mast er mode, the dspi generates the sck. in slave mode, sck_ x is an input from an external bus master. table 11-1. signal properties name i/o type function master mode slave mode cs0_ x output / input peripheral ch ip select 0 slave select cs1:2_x output peripheral chip select 1?2 unused 1 1 the siu allows you to select alte rnate pin functions for the device. sin_x input serial data in serial data in sout_x output serial data out serial data out sck_x output / input serial clock (output) serial clock (input)
pxd10 microcontroller reference manual, rev. 1 11-6 freescale semiconductor preliminary?subject to change without notice 11.7 memory map and register description 11.7.1 memory map table 11-2 shows the dspi memory map. table 11-2. dspi detailed memory map address register name register description location base: 0xfff9_0000 (dspi 0) 0xfff9_4000 (dspi 1) dspi x _mcr dspi module configuration register on page 7 base + 0x0004 ? reserved ? base + 0x0008 dspi x _tcr dspi transfer count register on page 9 base + 0x000c dspi x _ctar0 dspi clock and transfer attributes register 0 on page 10 base + 0x0010 dspi x _ctar1 dspi clock and transfer attributes register 1 on page 10 base + 0x0014 dspi x _ctar2 dspi clock and transfer attributes register 2 on page 10 base + 0x0018 dspi x _ctar3 dspi clock and transfer attributes register 3 on page 10 base + 0x001c dspi x _ctar4 dspi clock and transfer attributes register 4 on page 10 base + 0x0020 dspi x _ctar5 dspi clock and transfer attributes register 5 on page 10 base + 0x0024 dspi x _ctar6 dspi clock and transfer attributes register 6 on page 10 base + 0x0028 dspi x _ctar7 dspi clock and transfer attributes register 7 on page 10 base + 0x002c dspi x _sr dspi status register on page 16 base + 0x0030 dspi x _rser dspi dma/interrupt request select and enable register on page 18 base + 0x0034 dspi x _pushr dspi push tx fifo register on page 20 base + 0x0038 dspi x _popr dspi pop rx fifo register on page 22 base + 0x003c dspi x _txfr0 dspi transmit fifo register 0 on page 23 base + 0x0040 dspi x _txfr1 dspi transmit fifo register 1 on page 23 base + 0x0044 dspi x _txfr2 dspi transmit fifo register 2 on page 23 base + 0x0048 dspi x _txfr3 dspi transmit fifo register 3 on page 23 base + 0x004c? base + 0x0078 ? reserved ? base + 0x007c dspi x _rxfr0 dspi receive fifo register 0 on page 24 base + 0x0080 dspi x _rxfr1 dspi receive fifo register 1 on page 24 base + 0x0084 dspi x _rxfr2 dspi receive fifo register 2 on page 24 base + 0x0088 dspi x _rxfr3 dspi receive fifo register 3 on page 24 base + 0x008c? base + 0x00cc ? reserved ?
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-7 preliminary?subject to change without notice 11.7.2 register description 11.7.2.1 dspi module configuration register (dspi x _mcr) the dspi x _mcr contains bits which confi gure attributes of th e dspi operation. the values of the halt and mdis bits can be cha nged at any time, but their effect begi ns on the next frame boundary. the halt and mdis bits in the dspi x _mcr are the only bit valu es software can change while the dspi is running. table 11-3 describes the fields in the d spi module configuration register. address: base + 0x0000 access: r/w 0 1 23456789101112131415 r mst r cont_ scke dconf frz mtf e 0 ro oe 00 pcsi s5 pcsi s4 pcsi s3 pcsi s2 pcsi s1 pcsi s0 w reset0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 mdis dis_ txf dis_ rxf clr_ txf clr_ rxf smpl_pt 0000000 halt w w1c w1c reset0 1 00000000000001 figure 11-3. dspi module c onfiguration register (dspi x _mcr) table 11-3. dspi x _mcr field descriptions field description 0 mstr master/slave mode select. configures the dspi for master mode or slave mode. 0 dspi is in slave mode 1 dspi is in master mode 1 cont_scke continuous sck enable. enables the serial communication clock (sck) to run continuously. refer to section 11.8.6, continuous serial communications clock , for details. 0 continuous sck disabled 1 continuous sck enabled 2?3 dconf [0:1] dspi configuration. the following table lists the dconf values for the various configurations. dconf configuration 00 spi 01 invalid value 10 invalid value 11 invalid value
pxd10 microcontroller reference manual, rev. 1 11-8 freescale semiconductor preliminary?subject to change without notice 4 frz freeze. enables the dspi transfers to be stopped on the next frame boundary when the device enters debug mode. 0 do not halt serial transfers 1 halt serial transfers 5 mtfe modified timing format enable. enables a modified transfer format to be used. refer to section 11.8.5.4, modified spi trans fer format (mtfe = 1, cpha = 1) , for more information. 0 modified spi transfer format disabled 1 modified spi transfer format enabled 6 reserved. this bit is writable, but has no effect. 7 rooe receive fifo overflow overwrite enable. enables an rx fifo overflow condition to ignore the incoming serial data or to overwrite existing data. if the rx fifo is full and new data is received, the data from the transfer that generated the overfl ow is ignored or put in the shift register. if the rooe bit is set, the incoming data is put in the shift register. if the rooe bit is cleared, the incoming data is ignored. refer to section 11.8.7.6, receive fifo overflow interrupt request (rfof) , for more information. 0 incoming data is ignored 1 incoming data is put in the shift register 8?9 reserved, but implemented. these bits are writable, but have no effect. 10?15 pcsis n peripheral chip select inactive state. determines the inacti ve state of the cs0_ x signal. cs0_ x must be configured as inactive high for slave mode operation. 0 the inactive state of cs0_ x is low 1 the inactive state of cs0_ x is high 16 reserved. 17 mdis module disable. allows the clock to stop to the non-memory mapped logic in the dspi, effectively putting the dspi in a software controlled power-saving state. refer to section 11.8.8, power saving features,? for more information. the reset value of the mdis bit is parameterized, with a default reset value of 0. 0 enable dspi clocks 1 allow external logic to disable dspi clocks 18 dis_txf disable transmit fifo. enables and disables th e tx fifo. when the tx fifo is disabled, the transmit part of the dspi operates as a simplified double-buffered spi. refer to section 11.8.3.3, fifo disable operation,? for details. 0 tx fifo is enabled 1 tx fifo is disabled 19 dis_rxf disable receive fifo. enables and disables the rx fifo. when the rx fifo is disabled, the receive part of the dspi operates as a simplified double-buffered spi. refer to section 11.8.3.3, fifo disable operation,? for details. 0 rx fifo is enabled 1 rx fifo is disabled table 11-3. dspi x _mcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-9 preliminary?subject to change without notice 11.7.2.2 dspi transfer count register (dspi x _tcr) the dspi x _tcr contains a counter that i ndicates the number of spi transf ers made. the tr ansfer counter is intended to assist in queue management. the user must not write to the dspi x _tcr while the dspi is running. 20 clr_txf clear tx fifo. flushes the tx fifo. write a 1 to the clr_txf bit to clear the tx fifo counter. the clr_txf bit is always read as zero. 0 do not clear the tx fifo counter 1 clear the tx fifo counter 21 clr_rxf clear rx fifo. flushes the rx fifo. write a 1 to the clr_rxf bit to clear the rx counter. the clr_rxf bit is always read as zero. 0 do not clear the rx fifo counter 1 clear the rx fifo counter 22?23 smpl_ pt [0:1] sample point. allows the host software to select when the dspi master samples sin in modified transfer format. figure 11-16 shows where the master can sample the sin pin. the following table lists the delayed sample points. 24?30 reserved. 31 halt halt. provides a mechanism for software to start and stop dspi transfers. refer to section 11.8.2, start and stop of dspi transfers , for details on the operation of this bit. 0 start transfers 1 stop transfers table 11-3. dspi x _mcr field descriptions (continued) field description smpl_pt number of system clock cycles between odd-numbered edge of sck_ x and sampling of sin_ x . 00 0 01 1 10 2 11 invalid value
pxd10 microcontroller reference manual, rev. 1 11-10 freescale semiconductor preliminary?subject to change without notice table 11-4 describes the field in the ds pi transfer count register. 11.7.2.3 dspi clock and transfer attributes registers 0?7 (dspi x _ctar n ) the dspi modules each contain eight cloc k and transfer attr ibute registers (dspi x _ctar n ) which are used to define different transfer attribute configurations. each dspi x _ctar controls: ?frame size ? baud rate and transfer delay values ? clock phase ? clock polarity ? msb or lsb first at the initiation of an spi transf er, control logic selects the dspi x _ctar that contains the transfer?s attributes.do not write to the dspi x _ctars while the dspi is running. in master mode, the dspi x _ctar n registers define combinations of tran sfer attributes such as frame size, clock phase and polarity, data bit or dering, baud rate, and vari ous delays. in slave mode , a subset of the bit fields in the dspi x _ctar0 and dspi x _ctar1 registers are used to set th e slave transfer attributes. refer to the individual bit descriptions for deta ils on which bits are used in slave modes. when the dspi is configured as an spi master, th e ctas field in the command portion of the tx fifo entry selects which of the dspi x _ctar registers is used on a per-frame basis. when the dspi is configured as an spi bus slave, the dspi x _ctar0 register is used. address: base + 0x0008 access: r/w 0123456789101112131415 r spi_tcnt w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 11-4. dspi transfer count register (dspi x _tcr) table 11-4. dspi x _tcr field descriptions field description 0?15 spi_tcnt [0:15] spi transfer counter. counts the number of spi transfer s the dspi makes. the spi_tcnt field is incremented every time the last bit of an spi frame is transmitted. a va lue written to spi_tcnt presets the counter to that value. spi_tcnt is reset to zero at the beginning of the frame when the ctcnt field is set in the executing spi command. the transfer counter ?wraps around,? incrementing the counter pas t 65535 resets the counter to zero. 16?31 reserved.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-11 preliminary?subject to change without notice . address: base + 0x000c (dspi x _ctar0) base + 0x0010 (dspi x _ctar1) base + 0x0014 (dspi x _ctar2) base + 0x0018 (dspi x _ctar3) base + 0x001c (dspix_ctar4) base + 0x0020 (dspi x _ctar5) base + 0x0024 (dspi x _ctar6) base + 0x0028 (dspi x _ctar7) access: r/w 0123456789101112131415 r dbr fmsz cpo l cph a lsb fe pcssck pasc pdt pbr w reset0111100000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cssck asc dt br w reset0000000000000000 figure 11-5. dspi clock and transfer attributes registers 0?7 (dspi x _ctarn) table 11-5. dspi x _ctar n field descriptions field descriptions 0 dbr double baud rate. the dbr bit doubles the effective baud rate of the serial communications clock (sck). this field is only used in master mode. it effectively halves the baud rate division ratio supporting faster frequencies and odd division ratios for the serial communications clock (sck). when the dbr bit is set, the duty cycle of the serial communications clock (sck) depends on the value in the baud rate prescaler and the clock phase bit as listed in ta b l e 1 1 - 6 . see the br field description for details on how to compute the baud rate. if the overall baud rate is divide by two or divide by three of the system clock then neither t he continuous sck enable or the modified timing format enable bits should be set. 0 the baud rate is computed normally with a 50/50 duty cycle 1 the baud rate is doubled with the duty cycle depending on the baud rate prescaler 1?4 fmsz[0:3] frame size. the fmsz field selects the number of bi ts transferred per frame. the fmsz field is used in master mode and slave mode. ta b l e 1 1 - 7 lists the frame size encodings. when operating in tsb confirmation, the fmsz defines the point with in the 32-bit (maximum length) frame where control of the cs switches from th e dspi_dsicr to the dspi_dsicr1 register. the cross over point must range between 4 bits and 16 bits and is encoded per ta bl e 1 1 - 7 . the remaining frame after the cross over point, regardless of how many bits are remaining, will be controlled by the dspi_dsicr1 register. 5 cpol clock polarity. the cpol bit selects the inactive state of the serial communications clock (sck). this bit is used in both master and slave mode. for successful communication between serial devices, the devices must have identical clock po larities. when the continuous selection format (see section 11.8.5.5, continuous selection format? ) is selected, switching between clock polarities without stopping the dspi can cause errors in the transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge. 0 the inactive state value of sck is low 1 the inactive state value of sck is high
pxd10 microcontroller reference manual, rev. 1 11-12 freescale semiconductor preliminary?subject to change without notice 6 cpha clock phase. the cpha bit selects which edge of sck causes data to change and which edge causes data to be captured. this bit is used in both master and slave mode. for successful communication between serial devices, the device s must have identical clock phase settings. continuous sck is only supported for cpha=1. 0 data is captured on the leading edge of sck and changed on the following edge 1 data is changed on the leading edge of sck and captured on the following edge 7 lsbfe lsb first. the lsbfe bit selects if the lsb or msb of the frame is transferred first. this bit is only used in master mode. when operating in tsb configuration, this bit should be always 1. 0 data is transferred msb first 1 data is transferred lsb first 8?9 pcssck[0:1 ] pcs to sck delay prescaler. the pcssck field se lects the prescaler value for the delay between assertion of pcs and the first edge of the sck. this field is only used in master mode. the table below lists the prescaler values. see the cssck[0:3] field description for details on how to compute the pcs to sck delay. 10?11 pasc[0:1] after sck delay prescaler. the pasc field selects the prescaler value for the delay between the last edge of sck and the negation of pcs. this field is only used in master mode. the table below lists the prescaler values. see the asc[0:3] field description for details on how to compute the after sck delay. table 11-5. dspi x _ctar n field descriptions (continued) field descriptions pcssck pcs to sck delay prescaler value 00 1 01 3 10 5 11 7 pasc after sck delay prescaler value 00 1 01 3 10 5 11 7
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-13 preliminary?subject to change without notice 12?13 pdt[0:1] delay after transfer prescaler. the pdt field selects the prescaler value for the delay between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. the pdt field is only used in master mode. the table below lists the prescaler values. see the dt[0:3] field description for details on how to compute the delay after transfer. 14?15 pbr[0:1] baud rate prescal. the pbr field selects the prescaler value for the baud rate. this field is only used in master mode. the baud rate is the frequency of the serial communications clock (sck). the system clock is divided by the prescaler value befo re the baud rate selectio n takes place. the baud rate prescaler values are listed in the table below. see the br[0:3] field description for details on how to compute the baud rate. 16?19 cssck[0:3] pcs to sck delay scaler. the cssck field selects the scaler value for the pc s to sck delay. this field is only used in master mode. the pcs to sc k delay is the delay between the assertion of pcs and the first edge of the sck. ta bl e 1 1 - 8 list the scaler values.the pcs to sck delay is a multiple of the system clock period and it is computed according to the following equation: eqn. 11-1 20?23 asc[0:3] after sck delay scaler. the asc field selects the scaler value for the after sck delay. this field is only used in master mode. the after sck delay is the delay between the last edge of sck and the negation of pcs. table 11-9 list the scaler values .the after sck delay is a multiple of the system clock period, and it is computed according to the following equation: eqn. 11-2 table 11-5. dspi x _ctar n field descriptions (continued) field descriptions pdt delay after transfer prescaler value 00 1 01 3 10 5 11 7 pbr baud rate prescaler value 00 2 01 3 10 5 11 7 t csc 1 f sys ---------- - pcssck cssck ? ? = t asc 1 f sys ----------- pasc ? asc ? =
pxd10 microcontroller reference manual, rev. 1 11-14 freescale semiconductor preliminary?subject to change without notice 24?27 dt[0:3] delay after transfer scaler. the dt field selects the delay after transfer scaler. this field is only used in master mode. the delay after transfer is the time between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. ta b l e 1 1 - 1 0 lists the scaler values. in the continuous serial communicatio ns clock operation the dt value is fixed to one tsck, except when the tsbc bit from dspi_dsicr register is enab ling the tsb configuration. the delay after transfer is a multiple of the system cl ock period and it is co mputed according to the following equation: eqn. 11-3 28?31 br[0:3] baud rate scaler. the br field selects the scaler value for the baud rate. this field is only used in master mode. the prescaled system clock is divided by the baud rate scaler to generate the frequency of the sck. table 11-11 lists the baud rate scaler values.the baud rate is computed according to the following equation: eqn. 11-4 table 11-6. dspi sck duty cycle dbr cpha pbr sck duty cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43 table 11-7. dspi transfer frame size fmsz framesize fmsz framesize 0000 reserved 1000 9 0001 reserved 1001 10 0010 reserved 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16 table 11-5. dspi x _ctar n field descriptions (continued) field descriptions t dt 1 f sys ----------- pdt ? dt ? = sck baud rate f sys pbr ----------- - 1dbr + br --------------------- - ? =
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-15 preliminary?subject to change without notice table 11-8. dspi pcs to sck delay scaler cssck pcs to sck delay scaler value c ssck pcs to sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 11-9. dspi after sck delay scaler asc after sck delay scaler value asc after sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 11-10. dspi delay after transfer scaler dt delay after transfer scaler value dt delay after transfer scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536
pxd10 microcontroller reference manual, rev. 1 11-16 freescale semiconductor preliminary?subject to change without notice 11.7.2.4 dspi status register (dspi x _sr) the dspi x _sr contains status and flag bits. the bits are se t by the hardware and reflect the status of the dspi and indicate the occurrence of events that can generate interr upt or dma requests. software can clear flag bits in the dspi x _sr by writing a 1 to clear it (w1c). wr iting a 0 to a flag bit has no effect. table 11-11. dspi baud rate scaler br baud rate scaler value br baud rate scaler value 0000 2 1000 256 0001 4 1001 512 0010 6 1010 1024 0011 8 1011 2048 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 32768 address: base + 0x002c access: r/w 0 1 2 3 4 5 6 7 8 9 101112131415 r tcf txrx s 0 eoq f tfu f 0tfff0 0 0 0 0 rfo f 0 rfd f 0 w w1c w1c w1c w1c w1c w1c reset0 0 0 0 001000 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txctr txnxtptr rxctr popnxtptr w reset0 0 0 0 000000 0 0 0 0 0 0 dspi status register (dspi x _sr)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-17 preliminary?subject to change without notice table 11-12 describes the fields in the dspi status register. table 11-12. dspi x _sr field descriptions field description 0 tcf transfer complete flag. indicates that all bits in a frame have been shifted out. the tcf bit is set after the last incoming databit is sampled, but before the tasc delay starts. refer to section 11.8.5.1, classic spi transfer format (cpha = 0) for details. the tcf bit is cleared by writing 1 to it. 0 transfer not complete 1 transfer complete 1 txrxs tx and rx status. reflects the status of the dspi. refer to section 11.8.2, start and stop of dspi transfers for information on what clears and sets this bit. 0 tx and rx operations are disa bled (dspi is in stopped state) 1 tx and rx operations are enabled (dspi is in running state) 2 reserved. 3 eoqf end of queue flag. indicates that transmission in progress is the last entry in a queue. the eoqf bit is set when the tx fifo entry has the eoq bi t set in the command halfword and after the last incoming databit is sampled, but before the tasc delay starts. refer to section 11.8.5.1, classic spi transfer format (cpha = 0) for details. the eoqf bit is cleared by writing 1 to it. when th e eoqf bit is set, the txrxs bit is automatically cleared. 0 eoq is not set in the executing command 1 eoq bit is set in the executing spi command note: eoqf does not function in slave mode. 4 tfuf transmit fifo underflow flag. indicates that an und erflow condition in the tx fifo has occurred. the transmit underflow condition is detected only for dspi modules operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi operating in spi slave mode is empty, and a transfer is initiated by an external spi master. the tfuf bit is cleared by writing 1 to it. 0 tx fifo underflow has not occurred 1 tx fifo underflow has occurred 5 reserved. 6 tfff transmit fifo fill flag. indicates t hat the tx fifo can be filled. pr ovides a method for the dspi to request more entries to be added to the tx fifo. th e tfff bit is set while t he tx fifo is not full. the tfff bit can be cleared by writing 1 to it, or an by acknowledgement fr om the edma controller when the tx fifo is full. 0 tx fifo is full 1 tx fifo is not full 7?11 reserved. 12 rfof receive fifo overflow flag. indicates that an over flow condition in the rx fifo has occurred. the bit is set when the rx fifo and shift register are full and a transfer is initiated. the bit is cleared by writing 1 to it. 0 rx fifo overflow has not occurred 1 rx fifo overflow has occurred 13 reserved.
pxd10 microcontroller reference manual, rev. 1 11-18 freescale semiconductor preliminary?subject to change without notice 11.7.2.5 dspi dma / interrupt request select and enable register (dspi x _rser) the dspi x _rser serves two purposes: enables flag bits in the dspi x _sr to generate dma requests or interrupt requests, and selects the type of request to generate . refer to the bit descriptions for the type of requests that are supported. do not write to the dspi x _rser while the dspi is running. 14 rfdf receive fifo drain flag. indicates that the rx fifo can be drained. provides a method for the dspi to request that entries be removed from the rx fifo. the bit is set while the rx fifo is not empty. the rfdf bit can be cleared by writing 1 to it, or by acknowledgement from the edma controller when the rx fifo is empty. 0 rx fifo is empty 1 rx fifo is not empty note: in the interrupt service routin e, rfdf must be cleared only after the dspix_ popr register is read. 15 reserved. 16?19 txctr [0:3] tx fifo counter. indicates the nu mber of valid entries in the tx fifo. the txctr is incremented every time the dspi _pushr is written. the tx ctr is decremented every time an spi command is executed and the spi data is transferred to the shift register. 20?23 txnxtptr [0:3] transmit next pointer. indicates which tx fifo entry is transmitted during the next transfer. the txnxtptr field is updated every time spi data is tr ansferred from the tx fifo to the shift register. refer to section 11.8.3.4, transmit first in fi rst out (tx fifo) buffering mechanism for more details. 24?27 rxctr [0:3] rx fifo counter. indicates the number of entr ies in the rx fifo. the rxctr is decremented every time the dspi _popr is read. the rxctr is incremented after the last incoming databit is sampled, but before the tasc delay starts. refer to section 11.8.5.1, classic spi transfer format (cpha = 0) for details. 28?31 popnxtptr [0:3] pop next pointer. contains a pointer to the rx fifo entry that is returned when the dspi x _popr is read. the popnxtptr is updated when the dspi x _popr is read. refer to section 11.8.3.5, receive first in first out (rx fifo) buffering mechanism for more details. address: base + 0x0030 access: r/w 0123456789101112131415 r tcf_ re 00 eoq f_re tfuf _re 0 tfff _re tfff _ dirs 0000 rfof _re 0 rfdf _re rfdf_ dirs w reset000000000000000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 0 w reset000000000000000 0 figure 11-6. dspi dma / interrupt request select and enable register (dspi x _rser) table 11-12. dspi x _sr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-19 preliminary?subject to change without notice table 11-13 describes the fields in the dspi dma / interrupt request and enable register. table 11-13. dspi x _rser field descriptions field description 0 tcf_re transmission complete request enable. enables tcf flag in the dspi x _sr to generate an interrupt request. 0 tcf interrupt requests are disabled 1 tcf interrupt requests are enabled 1?2 reserved. 3 eoqf_re dspi finished request enable. enables the eoqf flag in the dspi x _sr to generate an interrupt request. 0 eoqf interrupt requests are disabled 1 eoqf interrupt requests are enabled 4 tfuf_re transmit fifo underflow request enable. the tf uf_re bit enables the tfuf flag in the dspi x _sr to generate an interrupt request. 0 tfuf interrupt requests are disabled 1 tfuf interrupt requests are enabled 5 reserved. 6 tfff_re transmit fifo fill request enable. enables the tfff flag in the dspi x _sr to generate a request. the tfff_dirs bit selects between generating an interrupt request or a dma requests. 0 tfff interrupt requests or dma requests are disabled 1 tfff interrupt requests or dma requests are enabled 7 tfff_dirs transmit fifo fill dma or interrupt request sele ct. selects between generating a dma request or an interrupt request. when the tfff flag bit in the dspi x _sr is set, and the tfff_re bit in the dspi x _rser is set, this bit selects between gener ating an interrupt request or a dma request. 0 interrupt request is selected 1 dma request is selected 8?11 reserved. 12 rfof_re receive fifo overflow request enable. enables the rfof flag in the dspi x _sr to generate an interrupt requests. 0 rfof interrupt requests are disabled 1 rfof interrupt requests are enabled 13 reserved. 14 rfdf_re receive fifo drain request enable. enables the rfdf flag in the dspi x _sr to generate a request. the rfdf_dirs bit selects between generati ng an interrupt request or a dma request. 0 rfdf interrupt requests or dma requests are disabled 1 rfdf interrupt requests or dma requests are enabled
pxd10 microcontroller reference manual, rev. 1 11-20 freescale semiconductor preliminary?subject to change without notice 11.7.2.6 dspi push tx fifo register (dspi x _pushr) the dspi x _pushr provides a means to write to the tx fifo. data written to this register is transferred to the tx fifo. refer to section 11.8.3.4, transmit first in firs t out (tx fifo) buffering mechanism , for more information. write accesse s of 8- or 16-bits to the dspi x _pushr transfers 32 bits to the tx fifo. note txdata is used in master and slave modes. 15 rfdf_dirs receive fifo drain dma or interrupt request se lect. selects between gener ating a dma request or an interrupt request. when the rfdf flag bit in the dspi x _sr is set, and the rfdf_re bit in the dspi x _rser is set, the rfdf_dirs bit selects betw een generating an interrupt request or a dma request. 0 interrupt request is selected 1 dma request is selected 16?31 reserved. address: base + 0x0034 access: r/w 0123456789101112131415 r con t ctas eoq ct cnt 00 00 000 pcs 2 pcs 1 pcs 0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txdata w reset0000000000000000 figure 11-7. dspi push tx fifo register (dspi x _pushr) table 11-13. dspi x _rser field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-21 preliminary?subject to change without notice table 11-14 describes the fields in the d spi push transmit fifo register. table 11-14. dspi x _pushr field descriptions field description 0 cont continuous peripheral chip select enable. selects a co ntinuous selection format. the bit is used in spi master mode. the bit enables the selected cs signals to remain asserted between transfers. refer to section 11.8.5.5, continuous selection format , for more information. 0 return peripheral chip select signals to their inactive state between transfers 1 keep peripheral chip select signals asserted between transfers 1?3 ctas [0:2] clock and transfer attributes select. selects which of the dspi x _ctars is used to set the transfer attributes for the spi frame. in spi slave mode, dspi x _ctar0 is used. the following table shows how the ctas values map to the dspi x _ctars. there are eight dspi x _ctars in the device dspi implementation. note: use in spi master mode only. 4 eoq end of queue. provides a means for host software to si gnal to the dspi that the current spi transfer is the last in a queue. at the end of the transfer the eoqf bit in the dspi x _sr is set. 0 the spi data is not the last data to transfer 1 the spi data is the last data to transfer note: use in spi master mode only. 5 ctcnt clear spi_tcnt. provides a means for host software to clear the spi transfer counter. the ctcnt bit clears the spi_tcnt field in the dspi x _tcr. the spi_tcnt field is clea red before transmission of the current spi frame begins. 0 do not clear spi_tcnt field in the dspi x _tcr 1 clear spi_tcnt field in the dspi x _tcr note: use in spi master mode only. 6?7 reserved. 8?9 reserved, but implemented. these bits are writable, but have no effect. 10?12 reserved. ctas use clock and transfer attributes from 000 dspi x _ctar0 001 dspi x _ctar1 010 dspi x _ctar2 011 dspi x _ctar3 100 dspi x _ctar4 101 dspi x _ctar5 110 dspi x _ctar6 111 dspi x _ctar7
pxd10 microcontroller reference manual, rev. 1 11-22 freescale semiconductor preliminary?subject to change without notice 11.7.2.7 dspi pop rx fifo register (dspi x _popr) the dspi x _popr allows you to read the rx fifo. refer to section 11.8.3.5, receive first in first out (rx fifo) buffering mechanism for a description of the rx fifo operations. eight or 16-bit read accesses to the dspi x _popr fetch the rx fifo data, a nd update the counter and pointer. note reading the rx fifo field fetches da ta from the rx fifo. once the rx fifo is read, the read data pointer is moved to the next entry in the rx fifo. therefore, read dspi x _popr only when you need the data. for compatibility, configure the tl b (mmu table) entry for dspi x _popr as guarded. 13?15 pcs x peripheral chip select x . selects which cs x signals are asserted for the transfer. 0 negate the cs x signal 1 assert the cs x signal note: use in spi master mode only. 16?31 txdata [0:15] transmit data. holds spi data for transfe r according to the associated spi command. note: use txdata in master and slave modes. address: base + 0x0038 access: r/o 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxdata w reset0000000000000000 figure 11-8. dspi pop rx fifo register (dspi x _popr) table 11-14. dspi x _pushr field descrip tions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-23 preliminary?subject to change without notice table 11-15 describes the fields in the dspi pop receive fifo register. 11.7.2.8 dspi transmit fi fo registers 0?4 (dspi x _txfr n ) the dspi x _txfr n registers provide visibility into the tx fifo for debugging purposes . each register is an entry in the tx fifo. the registers are re ad-only and cannot be m odified. reading the dspi x _txfr n registers does not alter the state of the tx fifo. the mcu us es four registers to implement the tx fifo, that is dspi x _txfr0?dspi x _txfr3 are used. table 11-16 describes the fields in the dspi transmit fifo register. table 11-15. dspi x _popr field descriptions field description 0?15 reserved, must be cleared. 16?31 rxdata [0:15] received data. the rxdata field contains the spi dat a from the rx fifo entry pointed to by the pop next data pointer (popnxtptr). address: base + 0x003c (dspi x _txfr0) base + 0x0040 (dspi x _txfr1) base + 0x0044 (dspi x _txfr2) base + 0x0048 (dspi x _txfr3) base + 0x004c (dspi x _txfr4) access: r/o 0123456789101112131415 rtxcmd w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtxdata w reset0000000000000000 figure 11-9. dspi transmit fifo register 0?4 (dspi x _txfr n ) table 11-16. dspi x _txfr n field descriptions field description 0?15 txcmd [0:15] transmit command. contains the command that sets th e transfer attributes for the spi data. refer to section 11.7.2.6, dspi push tx fifo register (dspix_pushr) , for details on the command field. 16?31 txdata [0:15] transmit data. contains the spi data to be shifted out.
pxd10 microcontroller reference manual, rev. 1 11-24 freescale semiconductor preliminary?subject to change without notice 11.7.2.9 dspi receive fifo registers 0?4 (dspi x _rxfr n ) the dspi x _rxfr n registers provide visibility into the rx fifo for debuggi ng purposes. each register is an entry in the rx fifo. the dspi x _rxfr registers are read-only. reading the dspi x _rxfr n registers does not alter the state of the rx fi fo. the device uses four registers to implement the rx fifo, that is dspi x _rxfr0?dspi x _rxfr3 are used. table 11-17 describes the field in the dspi receive fifo register. 11.8 functional description the dspi supports full-duplex, s ynchronous serial communications between the mcu and peripheral devices. all communica tions are through an spi-like protocol. the dspi has one configuration: ? serial peripheral interface (spi) configuration in which the dspi operates as a basic spi or a queued spi. the dconf field in the dspi x _mcr register determines the dspi configuration. refer to table 11-3 for the dspi configuration values. address: base + 0x007c (dspi x _rxfr0) base + 0x0080 (dspi x _rxfr1) base + 0x0084 (dspi x _rxfr2) base + 0x0088 (dspi x _rxfr3) base + 0x008c (dspi x _rxfr4) access: r/o 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxdata w reset0000000000000000 figure 11-10. dspi receive fifo registers 0?4 (dspi x _rxfr n ) table 11-17. dspi x _rxfr n field descriptions field description 0?15 reserved, must be cleared. 16?31 rxdata [15:0] receive data. contains the received spi data.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-25 preliminary?subject to change without notice the dspi x _ctar0?dspi x _ctar7 registers hold clock and transfer attributes.t he spi configuration can select which ctar to use on a frame by fram e basis by setting the ctas field in the dspi x _pushr. the 16-bit shift register in the master and the 16-bit shift register in the sl ave are linked by the sout_ x and sin_ x signals to form a distributed 32-bit register. when a data tran sfer operation is performed, data is serially shifted a predetermined number of bit pos itions. because the registers are linked, data is exchanged between the master and the slave; the data th at was in the master?s shift register is now in the shift register of the slave, a nd vice versa. at the end of a tr ansfer, the tcf bit in the dspi x _sr is set to indicate a completed transfer. figure 11-11 illustrates how master a nd slave data is exchanged. figure 11-11. spi serial protocol overview the dspi has three peri pheral chip select (cs x ) signals that are be used to select which of the slaves to communicate with. transfer protocols and timing propert ies are shared by the three dspi c onfigurations; these properties are described independently of the configuration in section 11.8.5, transfer formats . the transfer rate and delay settings are de scribed in section section 11.8.4, dspi baud rate and clock delay generation . refer to section 11.8.8, power saving features for information on the power-s aving features of the dspi. 11.8.1 modes of operation the dspi modules have five available distinct modes: ? master mode ? slave mode ? module disable mode ? external stop mode ? debug mode master, slave, and module disable modes are module- specific modes. the exte rnal stop and debug modes are device-specific modes. the module-specific modes are de termined by bits in the dspi x _mcr. the device-specific modes are modes that the entire device can enter in parallel with the dspi being conf igured in one of its module-specific modes. dspi master shift register baud rate generator dspi slave shift register sout_ x sin_ x sout_ x sin_ x sck_ x sck_ x cs_ x cs0_ x
pxd10 microcontroller reference manual, rev. 1 11-26 freescale semiconductor preliminary?subject to change without notice 11.8.1.1 master mode in master mode the dspi can init iate communications with peripheral devices. the dspi operates as bus master when the mstr bit in the dspi x _mcr is set. the serial co mmunications clock (sck) is controlled by the master dspi. all three dspi configurations are va lid in master mode. in spi configuration, master mode tr ansfer attributes are c ontrolled by the spi command in the current tx fifo entry. the ctas field in the spi command selects which of the eight dspi x _ctars are used to set the transfer attributes. transfer attrib ute control is on a fr ame by frame basis. refer to section 11.8.3, serial peripheral interface (spi) configuration for more details. 11.8.1.2 slave mode in slave mode the dspi responds to transfers initiat ed by an spi master. the dspi operates as bus slave when the mstr bit in the dspi x _mcr is negated. the dspi slave is selected by a bus master by having the slave?s cs0_ x asserted. in slave mode the sck is provide d by the bus master. all transfer attributes are controlled by the bus master, except the clock polarit y, clock phase and the numbe r of bits to transfer which must be configured in the dspi slave to communicate correctly. 11.8.1.3 module disable mode the module disable mode is used for mcu power management. the clock to the non-memory mapped logic in the dspi is stopped while in module disabl e mode. the dspi enters the module disable mode when the mdis bit in dspi x _mcr is set. refer to section 11.8.8, power saving features , for more details on th e module disable mode. 11.8.1.4 external stop mode for devices with low-power mode s, the dspi supports the global signal stop mode mechanism. the dspi will not acknowledge the request to enter external stop mode until it has reach ed a frame boundary. when the dspi has reached a frame boundary it will halt al l operations and indicate th at it is ready to have its clocks shut off. the dspi ex its external stop mode and resumes normal opera tion once the clocks are turned on. serial communications or register accesses made wh ile in external stop mode are ignored even if the clocks have not been shut off yet. see section 11.8.8, power saving features ,? for more details on the external stop mode. 11.8.1.5 debug mode the debug mode is used for syst em development and debugging. if the mcu is stopped by a debugger while the dspi x _mcr[frz] bit is set, the d spi halts operation on the next frame boundary and enters a stopped state. if the mcu is stopped by a debugger whil e the frz bit is cleared, the dspi behavior is unaffected and remains dictated by the module-specific mode and confi guration of the dspi. the frz bit operation is only available when the cpu has an active debug mode. see figure 11-12 for a state diagram.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-27 preliminary?subject to change without notice 11.8.2 start and stop of dspi transfers the dspi has two operating states: stopped and running. the states are independent of dspi configuration. the default state of the dspi is stopped. in the sto pped state no serial transfers are initiated in master mode and no tr ansfers are responded to in slave mode. the stopped state is also a safe state for writing the various c onfiguration registers of the dspi without causin g undetermined results. the txrxs bit in the dspi x _sr is cleared in this state. in the runn ing state, serial transfers take place. the txrxs bit in the dspi x _sr is set in the running state. figure 11-12 shows a state diagram of th e start and stop mechanism. figure 11-12. dspi start and stop state diagram the transitions are described in table 11-18 . state transitions from running to stopped occur on the next frame boundary if a transfer is in progress, or on the next system clock cycle if no transfers are in progress. 11.8.3 serial peripheral in terface (spi) configuration the spi configuration transfers data se rially using a shift register and a selection of programmable transfer attributes. the dspi is in spi configuration when th e dconf field in the dspi x _mcr is 0b00. the spi frames can be from 4 to 16 bits long. the data to be transmitted can come fr om queues stored in ram external to the dspi. host software or an edma controller can transf er the spi data from the queues to a table 11-18. state transitions for start and stop of dspi transfers transition # current st ate next state description 0 reset stopped generic power-on-reset transition 1 stopped running the dspi starts (transitions from stopped to running) when all of the following conditions are true: ? eoqf bit is clear ? debug mode is unselected or the frz bit is clear ? halt bit is clear 2 running stopped the dspi stops (transitions from running to stopped) after the current frame for any one of the following conditions: ? eoqf bit is set ? debug mode is selected and the frz bit is set ?halt bit is set running txrxs = 1 stopped txrxs = 0 reset power-on-reset 0 1 2
pxd10 microcontroller reference manual, rev. 1 11-28 freescale semiconductor preliminary?subject to change without notice first-in first-out (fifo) buffer. the received data is stored in entries in the receive fifo (rx fifo) buffer. host software or an edma controll er transfers the received data from the rx fifo to memory external to the dspi. the fifo buffer operations are described in section 11.8.3.4, transmit first in first out (tx fifo) buffering mechanism , and section 11.8.3.5, receive first in first out (rx fifo) buffering mechanism . the interrupt and dma request conditions are described in section 11.8.7, interrupts/dma requests . the spi configuration supports two module-specific modes; master mode and slave mode. the fifo operations are similar for the master mode and slave mode. the main differ ence is that in master mode the dspi initiates and controls the transfer according to the fields in the spi command field of the tx fifo entry. in slave mode the dspi only responds to transfers initiated by a bus master external to the dspi and the spi command field of the tx fifo entry is ignored. 11.8.3.1 spi master mode in spi master mode the dspi initia tes the serial transfers by controll ing the serial communications clock (sck_ x ) and the peripheral chip select (cs x ) signals. the spi command fiel d in the executing tx fifo entry determines which ctars are used to set the transfer attributes and which cs x signal to assert. the command field also contains various bi ts that help with queue management and transfer protocol. the data field in the executing tx fifo entry is loaded into the shift register and shifted out on the serial out (sout _x ) pin. in spi master mode, each spi frame to be transmitted has a command associated with it allowing for transfer attribute control on a frame by frame basis. refer to section 11.7.2.6, dspi push tx fi fo register (dspix_pushr) , for details on the spi command fields. 11.8.3.2 spi slave mode in spi slave mode the dspi responds to transfers initiated by an spi bus master. the dspi does not initiate transfers. certain transfer attributes such as clock polarity, clock phase and frame size must be set for successful communication with an spi master. the spi slave mode transfer attr ibutes are set in the dspi x _ctar0. 11.8.3.3 fifo disable operation the fifo disable mechanisms allo w spi transfers without using the tx fifo or rx fifo. the dspi operates as a double-buffered simplified spi when th e fifos are disabled. the tx and rx fifos are disabled separately. the tx fi fo is disabled by writing a 1 to the dis_txf bit in the dspi x _mcr. the rx fifo is disabled by writing a 1 to the dis_rxf bit in the dspi x _mcr. the fifo disable mechanisms are transparent to the user and to host software; transmit data and commands are written to the dspi x _pushr and receiv ed data is read from the dspi x _popr. when the tx fifo is disabled, the tfff, tfuf, and txctr fields in dspi x _sr behave as if th ere is a one-entry fifo but the contents of the dspi x _txfrs and txnxtptr are undefined. when the rx fifo is disabled, the rfdf, rfof, a nd rxctr fields in the dspi x _sr behave as if there is a one-entry fifo but the contents of the dspi x _rxfrs and popnxtptr are undefined.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-29 preliminary?subject to change without notice disable the tx and rx fifos only if the fifo must be disabled as a requirement of the application's operating mode. a fifo must be disabled before it is accessed. failure to disable a fifo prior to a first fifo access is not supported, and can result in incorrect results. 11.8.3.4 transmit first in first ou t (tx fifo) buffering mechanism the tx fifo functions as a buffer of spi data and spi commands fo r transmission. the tx fifo holds five entries, each consisting of a co mmand field and a data field. spi commands and data are added to the tx fifo by writing to the dspi push tx fifo register (dspi x _pushr). for more information on dspi x _pushr. tx fifo entries can only be removed from the tx fifo by being shifted out or by flushing the tx fifo. refer to section 11.7.2.6, dspi push tx fi fo register (dspix_pushr) . the tx fifo counter field (txctr) in the dspi status register (dspi x _sr) indicates the number of valid entries in the tx fifo. the txctr is updated every time the dspi _pus hr is written or spi data is transferred into the shift register from the tx fifo. refer to section 11.7.2.4, dspi status register (dspix_sr) for more information on dspi x _sr. the txnxtptr field indicates which tx fifo entr y is transmitted during the next transfer. the txnxtptr contains the pos itive offset from dspi x _txfr0 in number of 32-bit registers. for example, txnxtptr equal to two means that the dspi x _txfr2 contains the spi data and command for the next transfer. the txnxtptr field is incr emented every time spi da ta is transferred from the tx fifo to the shift register. 11.8.3.4.1 filling the tx fifo host software or the edma controller can add (push) entries to the tx fifo by writing to the dspi x _pushr. when the tx fifo is not full, the tx fifo fi ll flag (tfff) in the dspi x _sr is set. the tfff bit is cleared when the tx fifo is full and the edma controller indi cates that a write to dspi x _pushr is complete or alternatively by host so ftware writing a 1 to the tfff in the dspi x _sr. the tfff can generate a dma request or an interrupt request. refer to section 11.8.7.2, transmit fifo fill interrupt or dma request (tfff) , for details. the dspi ignores attempts to push da ta to a full tx fifo; that is, th e state of the tx fifo is unchanged. no error condition is indicated. 11.8.3.4.2 draining the tx fifo the tx fifo entries are re moved (drained) by shifting spi data out through the sh ift register. entries are transferred from the tx fifo to the shift register and shifted out as l ong as there are valid entries in the tx fifo. every time an entry is tr ansferred from the tx fifo to the sh ift register, the tx fifo counter is decremented by one. at the end of a transfer, the tcf bit in the dspi x _sr is set to indicate the completion of a transfer. the tx fifo is flus hed by writing a 1 to the clr_txf bit in dspi x _mcr. if an external spi bus master init iates a transfer with a dspi slave while the slave?s dspi tx fifo is empty, the transmit fifo underflow flag (tfuf) in the slave?s dspi x _sr is set.
pxd10 microcontroller reference manual, rev. 1 11-30 freescale semiconductor preliminary?subject to change without notice refer to section 11.8.7.4, transmit fifo unde rflow interrupt request (tfuf) , for details. 11.8.3.5 receive first in first ou t (rx fifo) buffering mechanism the rx fifo functions as a buffer for data receiv ed on the sin pin. the rx fifo holds four received spi data frames. spi data is added to the rx fifo at the completion of a transfer when the received data in the shift register is transferred into the rx fifo . spi data is removed (popped) from the rx fifo by reading the dspi x _popr register. rx fifo entries can only be removed from the rx fifo by reading the dspi x _popr or by flushing the rx fifo. refer to section 11.7.2.7, dspi pop rx fi fo register (dspix_popr) for more information on the dspi x _popr. the rx fifo counter field (rxctr) in the dspi status register (dspi x _sr) indicates the number of valid entries in the rx fifo. the rxctr is updated ev ery time the dspi _popr is read or spi data is copied from the shift re gister to the rx fifo. the popnxtptr field in the dspi x _sr points to the rx fifo entry that is returned when the dspi x _popr is read. the popnxtptr contains th e positive, 32-bit word offset from dspi x _rxfr0. for example, popnxtptr equal to two means that the dspi x _rxfr2 contains the received spi data that is returned when dspi x _popr is read. the popnxtptr fiel d is incremented every time the dspi x _popr is read. popnxtptr rolls ove r every four frames on the mcu. 11.8.3.5.1 filling the rx fifo the rx fifo is filled with the rece ived spi data from the shift regist er. while the rx fifo is not full, spi frames from the shift re gister are transferred to the rx fifo. every time an spi frame is transferred to the rx fifo the rx fifo counter is incremented by one. if the rx fifo and shift register are full and a transfer is initiated, the rfof bit in the dspi x _sr is set indicating an overflow condition. depending on the state of the rooe bit in the dspi x _mcr, the data from the transfer that gene rated the overflow is ignored or put in the shift register . if the rooe bit is set, the incoming data is put in the shift register. if th e rooe bit is cleared, the incoming data is ignored. 11.8.3.5.2 draining the rx fifo host software or the edma ca n remove (pop) entries from th e rx fifo by reading the dspi x _popr. a read of the dspi x _popr decrements the rx fifo counter by one. attempts to pop data from an empty rx fifo are ignored, the rx fifo counter remains unchanged. the data returned from reading an empty rx fifo is undetermined. refer to section 11.7.2.7, dspi pop rx fi fo register (dspix_popr) for more information on dspi x _popr. when the rx fifo is not empty, the rx fifo drain flag (rfdf) in the dspi x _sr is set. the rfdf bit is cleared when the rx_fifo is empty and the ed ma controller indicates that a read from dspi x _popr is complete; alternatively the rfdf bit ca n be cleared by the host writing a 1 to it.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-31 preliminary?subject to change without notice 11.8.4 dspi baud rate and clock delay generation the sck_ x frequency and the delay values for serial transfer are genera ted by dividing the system clock frequency by a prescaler and a scaler wi th the option of doubling the baud rate. figure 11-13 shows conceptually how the sck signal is generated. figure 11-13. communications clock prescalers and scalers 11.8.4.1 baud rate generator the baud rate is the frequency of the serial communication clock (sck_ x ). the system clock is divided by a baud rate prescaler (defined by dspi x _ctar[pbr]) and baud rate scaler (defined by dspi x _ctar[br]) to produce sck_ x with the possibility of doubling the baud rate. the dbr, pbr, and br fields in the dspi x _ctars select the frequency of sck_ x using the following formula: table 11-19 shows an example of a computed baud rate. 11.8.4.2 cs to sck delay (t csc ) the cs _x to sck _x delay is the length of time from assertion of the cs _x signal to the first sck _x edge. refer to figure 11-14 for an illustration of the cs _x to sck _x delay. the pcssck and cssck fields in the dspi x _ctar n registers select the cs _x to sck _x delay, and the relationship is expressed by the following formula: table 11-20 shows an example of the computed cs to sck _x delay. table 11-19. baud rate computation example f sys pbr prescaler value br scaler value dbr value baud rate 100 mhz 0b00 2 0b0000 2 0 25 mb/sec 20 mhz 0b00 2 0b0000 2 1 10 mb/sec table 11-20. cs to sck delay computation example pcssck prescaler value cssck scaler value f sys cs to sck delay 0b01 3 0b0100 32 100 mhz 0.96 ? s prescaler 1 scaler 1 + dbr system clock sck_x sck baud rate f sys pbrprescalervalue ---------------------------------------------------------- 1dbr + brscalervalue -------------------------------------------- ? = t csc = f sys cssck ? pcssck 1 ?
pxd10 microcontroller reference manual, rev. 1 11-32 freescale semiconductor preliminary?subject to change without notice 11.8.4.3 after sck delay (t asc ) the after sck _x delay is the length of time between the last edge of sck _x and the negation of cs _x . refer to figure 11-14 and figure 11-15 for illustrations of the after sck _x delay. the pasc and asc fields in the dspi x _ctar n registers select the after sck delay. the relationship between these variables is given in the following formula: table 11-21 shows an example of the computed after sck delay. 11.8.4.4 delay after transfer (t dt ) the delay after transfer is the lengt h of time between negation of the cs x signal for a frame and the assertion of the cs x signal for the next frame. the pdt and dt fields in the dspi x _ctar n registers select the delay after transfer. refer to figure 11-14 for an illustration of the delay after transfer. the following formula expresses the pdt/ dt/delay after transfer relationship: table 11-22 shows an example of the computed delay after transfer. when in non-continuous clock mode the t dt delay is configurable as outlined in the dspi_ctarx registers. when in continuous clock mode and tsb is not enabled the de lay is fixed at 1 sck period. when in tsb and continuous mode the dela y is programmed as outli ned in the dspi_ctarx registers but in the event that the delay does not coincide with an sck pe riod in duration the delay is extended to the next sck active edge. table 11-23 shows an example of how to compute th e delay after transfer with the clock period of sck defined as t sck . the values calculated assume 1 tsck period = 4 ipg_clk. table 11-21. after sck delay computation example pas c prescaler value asc scaler value f sys after sck delay 0b01 3 0b0100 32 100 mhz 0.96 ? s table 11-22. delay after transfer computation example pdt prescaler value dt scaler value f sys delay after transfer 0b01 3 0b1110 32768 100 mhz 0.98 ms t asc = f sys asc ? pasc 1 ? dt = f sys dt ? pdt 1 ?
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-33 preliminary?subject to change without notice 11.8.5 transfer formats the spi serial communication is controlled by the serial communications clock (sck_ x ) signal and the cs x signals. the sck_ x signal provided by the master device synchronizes shifting and sampling of the data by the sin_ x and sout_ x pins. the cs x signals serve as enable si gnals for the slave devices. when the dspi is the bus master, the cpol and cpha bits in the dspi clock and transfer attributes registers (dspi x _ctar n ) select the polarity and phase of the serial clock, sck_ x . the polarity bit selects the idle state of the sck_ x . the clock phase bit selects if the data on sout_ x is valid before or on the first sck_ x edge. when the dspi is the bus slave, cpol and cpha bits in the dspi x _ctar0 (spi slave mode) select the polarity and phase of the serial clock. even though th e bus slave does not control the sck signal, clock polarity, clock phase and number of b its to transfer must be identical for the master device and the slave device to ensure proper transmission. the dspi supports four different transfer formats: table 11-23. delay after transfer computation example in tsb configuration pdt field t dt 1 (tsck) 1 some values are not reachable (i. e. 9, 11, 13, 15, 17, 18, 19...). to calculate these values, please see equation 11-3 . 0123 dt field 0 2 2 the values in this row were rounded to the next integer value. 1234 1 1357 2261014 3 4 12 20 28 4 8 24 40 56 5 164880112 6 32 96 160 224 7 64 192 320 448 8 128 384 640 896 9 256 768 1280 1792 10 512 1536 2560 3584 11 1024 3072 5120 7168 12 2048 6144 10240 14336 13 4096 12288 20480 28672 14 8192 24576 40960 57344 15 16384 49152 81920 114688
pxd10 microcontroller reference manual, rev. 1 11-34 freescale semiconductor preliminary?subject to change without notice ? classic spi with cpha = 0 ? classic spi with cpha = 1 ? modified transfer format with cpha = 0 ? modified transfer format with cpha = 1 a modified transfer format is supported to allow for high-speed communication with peripherals that require longer setup times. the dspi can sample the incoming data later than halfway through the cycle to give the peripheral more set up time. the mtfe bit in the dspi x _mcr selects between classic spi format and modified transfer format. th e classic spi format s are described in section 11.8.5.1, classic spi transfer format (cpha = 0) and section 11.8.5.2, classic spi transfer format (cpha = 1) . the modified transfer formats are described in section 11.8.5.3, modified spi transfer format (mtfe = 1, cpha = 0) and section 11.8.5.4, modified spi transf er format (mtfe = 1, cpha = 1) . in the spi configuration, the dspi provides the option of keeping the cs signals asserted between frames. refer to section 11.8.5.5, continuous selection format for details.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-35 preliminary?subject to change without notice 11.8.5.1 classic spi transfer format (cpha = 0) the transfer format shown in figure 11-14 is used to communicate with peripheral spi slave devices where the first data bit is available on the first clock edge. in this format , the master and slave sample their sin_ x pins on the odd-numbered sck_ x edges and change the data on their sout_ x pins on the even-numbered sck_ x edges. figure 11-14. dspi transfer timing diagram (mtfe = 0, cpha = 0, fmsz = 8) the master initiates the transfer by placing its first data bit on the sout_ x pin and asserting the appropriate peripheral chip select signals to the slav e device. the slave responds by placing its first data bit on its sout_ x pin. after the t csc delay has elapsed, the master outputs the first edge of sck_ x . this is the edge used by the mast er and slave devices to samp le the first input data bit on their se rial data input signals. at the second edge of the sck_ x the master and slave devices place their second data bit on their serial data output signals. for th e rest of the frame the master and the slave sample their sin_ x pins on the odd-numbered clock edges and cha nges the data on their sout_ x pins on the even-numbered clock edges. after the last clock edge occurs a delay of t asc is inserted before the mast er negates the cs signals. a delay of t dt is inserted before a new frame tran sfer can be initiated by the master. for the cpha = 0 condition of the master, tcf and eoqf are set and the rxctr counter is updated at the next to last serial clock edge of the frame (edge 15) of figure 11-14 . for the cpha = 0 condition of the sl ave, tcf is set and the rxctr count er is updated at the last serial clock edge of the frame (edge 16) of figure 11-14 . sck (cpol = 0) pcs x / ss t asc sck (cpol = 1) master and slave sample master sout / slave sin master sin / slave sout bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb lsb t dt t csc t csc msb first (lsbfe = 0): lsb first (lsbfe = 1): t csc = cscs to sck delay. t asc = after sck delay. t dt = delay after transfer (minimum cs idle time). master (cpha = 0): tcf and eoqf are set and rxctr counter is updated at next to last sck edge of frame (edge 15) slave (cpha = 0): tcf is set and rxctr counter is updated at last sck edge of frame (edge 16) 1234567891011121314 16 15
pxd10 microcontroller reference manual, rev. 1 11-36 freescale semiconductor preliminary?subject to change without notice 11.8.5.2 classic spi transfer format (cpha = 1) this transfer format shown in figure 11-15 is used to communicate with peripheral spi slav e devices that require the first sck_ x edge before the firs t data bit becomes avai lable on the slave sout_ x pin. in this format the master and slave devices change the data on their sout_ x pins on the odd-numbered sck_ x edges and sample the data on their sin_ x pins on the even-numbered sck_ x edges. figure 11-15. dspi transfer timing diagram (mtfe = 0, cpha = 1, fmsz = 8) the master initiates the tr ansfer by asserting the cs x signal to the slave. after the t csc delay has elapsed, the master generates the first sck_ x edge and at the same time pla ces valid data on the master sout_ x pin. the slave responds to the first sck_ x edge by placing its first da ta bit on its slave sout_ x pin. at the second edge of the sck_ x the master and slave sample their sin_ x pins. for the rest of the frame the master and the slave change the data on their sout_ x pins on the odd-numbered clock edges and sample their sin_ x pins on the even-numbered clock edges. afte r the last clock edge occurs a delay of t asc is inserted before the master negates the cs x signal. a delay of t dt is inserted before a new frame transfer can be ini tiated by the master. for cpha = 1 the master eoqf and tcf and slave tcf ar e set at the last serial clock edge (edge 16) of figure 11-15 . for cpha = 1 the master and slave rxctr counters are updated on the same clock edge. slave (cpha = 1): tcf is set and rxctr counter is updated at last sck edge of frame (edge 16) sck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (cpol = 0) pcsx / ss t asc sck (cpol = 1) master and slave sample master sout/ slave sin master sin/ slave sout bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb lsb t dt t csc msb first (lsbfe = 0): lsb first (lsbfe = 1): t csc = cs to sck delay. t asc = after sck delay. t dt = delay after transfer (minimum cs negation time). master (cpha = 1): tcf and eoqf are set and rxctr counter is updated at last sck edge of frame (edge 16) 16
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-37 preliminary?subject to change without notice 11.8.5.3 modified spi transfer format (mtfe = 1, cpha = 0) in this modified transfer format bot h the master and the slave sample later in the sck period than in classic spi mode to allow for delays in device pads and boa rd traces. these delays become a more significant fraction of the sck period as the sck pe riod decreases with increasing baud rates. note for the modified transfer format to operate correctly, you must thoroughly analyze the spi link timing budget. the master and the slave place data on the sout_ x pins at the assertion of the cs x signal. after the cs x to sck_ x delay has elapsed the first sck_ x edge is generated. the slave samples the master sout_ x signal on every odd numbered sck_ x edge. the slave also places new data on the slave sout_ x on every odd numbered clock edge. the master places its second data bit on the sout_ x line one system clock after odd numbered sck_ x edge. the point where the master samples the slave sout_ x is selected by writing to the smpl_pt field in the dspi x _mcr. table 11-24 lists the number of system clock cycles between the active edge of sck_ x and the master sample point for different values of the smpl_pt bit field. the master sample point can be delayed by one or two system clock cycles. table 11-24. delayed master sample point smpl_pt number of system clock cycles between odd-numbered edge of sck and sampling of sin 00 0 01 1 10 2 11 invalid value
pxd10 microcontroller reference manual, rev. 1 11-38 freescale semiconductor preliminary?subject to change without notice figure 11-16 shows the modified transfer format for cpha = 0. only the condition where cpol = 0 is illustrated. the delayed master sample points are indicated with a lighter shaded arrow. figure 11-16. dspi modified transfer format (mtfe = 1, cpha = 0, f sck = f sys / 4) 11.8.5.4 modified spi transfer format (mtfe = 1, cpha = 1) at the start of a transfer the dspi asserts the cs signal to the slave de vice. after the cs to sck delay has elapsed the master and the slave put data on their sout pins at the firs t edge of sck. the slave samples the master sout signal on the even numbered edges of sck. the mast er samples the slave sout signal on the odd numbered sck edges starting with the third sck edge. the slave samples the last bit on the last edge of the sck. the master samples the last sl ave sout bit one half sck cycle after the last edge of sck. no clock edge is visible on the master sck pin during the sampling of the last bit. the sck to cs delay must be greater or e qual to half of the sck period. note for the modified transfer format to operate correctly, analyze the spi link timing budget thoroughly. t csc = cs to sck delay. t asc = after sck delay. system clock 123456 cs x t asc sck master sample slave sout master sout system clock system clock slave sample t csc
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-39 preliminary?subject to change without notice figure 11-17 shows the modified transfer format for cpha = 1. only the condition where cpol = 0 is described. figure 11-17. dspi modified transfer format (mtfe = 1, cpha = 1, f sck = f sys / 4) 11.8.5.5 continuous selection format some peripherals must be deselected between every transfer. other peripherals must remain selected between several sequential se rial transfers. the continuous selectio n format provides the flexibility to handle both cases. the conti nuous selection format is enabled for the spi configuration by setting the cont bit in the spi command. when the cont bit = 0, the dspi drives the asserted ch ip select signals to their idle states in between frames. the idle states of the chip select si gnals are selected by the pcsis field in the dspi x _mcr. figure 11-18 shows the timing diagram for two four-b it transfers with cpha = 1 and cont = 0. figure 11-18. example of non-continuous format (cpha = 1, cont = 0) t csc = cs to sck delay. t asc = after sck delay. system clock 123456 cs t asc sck master sample master sout slave sout slave sample t csc sck (cpol = 0) csx t asc sck (cpol = 1) master sout t dt t csc t csc = cs to sck delay. t asc = after sck delay. t dt = delay after transfer (minimum cs negation time). master sin t csc
pxd10 microcontroller reference manual, rev. 1 11-40 freescale semiconductor preliminary?subject to change without notice when the cont = 1 and the cs signal for the next transf er is the same as for the current transfer, the cs signal remains asserted for the duration of the two transfers. the delay between transfers (t dt ) is not inserted between the transfers. figure 11-19 shows the timing diagram for two 4-bi t transfers with cpha = 1 and cont = 1. figure 11-19. example of continuous transfer (cpha = 1, cont = 1) in figure 11-19 , the period length at the start of th e next transfer is the sum of t asc and t csc ; i.e., it does not include a half-clock peri od. the default settings for these provide a total of f our system clocks. in many situations, t asc and t csc must be increased if a full half-clock period is required. when the cont bit = 1 and the cs sign als for the next transfer are differ ent from the present transfer, the cs signals behave as if the cont bit was not set. switching ctar registers or changing which pcs si gnals are asserted betw een frames while using continuous selection can cause errors in the transfer. the pcs signal s hould be negated before ctar is switched or different pcs signals are selected. 11.8.5.6 clock polarity switching between dspi transfers if it is desired to switch polar ity between non-continuous dspi frames, the edge generated by the change in the idle state of the clock occurs one system clock before the assertio n of the chip select for the next frame. refer to section 11.7.2.3, dspi clock and transfer attributes registers 0?7 (dspix_ctarn) . sck (cpol = 0) cs t asc sck (cpol = 1) master sout t csc t csc t csc = cs to sck delay. t asc = after sck delay. master sin
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-41 preliminary?subject to change without notice in figure 11-20 , time ?a? shows the one clock interval. time ?b? is user programmable from a minimum of two system clocks. figure 11-20. polarity switching between frames 11.8.6 continuous serial communications clock the dspi provides the option of ge nerating a continuous sck signal for slave peripherals that require a continuous clock. continuous sck is enabled by setti ng the cont_scke bit in the dspi x _mcr. continuous sck is valid in all configurations. continuous sck is only supported fo r cpha = 1. setting cpha = 0 is i gnored if the cont_scke bit is set. continuous sck is supported for modified transfer format. clock and transfer attributes fo r the continuous sck mode are set according to the following rules: ? when the dspi is in spi confi guration, ctar0 is used initially. at the start of each spi frame transfer, the ctar specified by the ctas for the frame is used. ? in all configurations, the currentl y selected ctar remains in use until the start of a frame with a different ctar specified, or the c ontinuous sck mode is terminated. the device is designed to use the same baud rate for all transfers ma de while using the continuous sck. switching clock polarity between frames while using continuous sck can cause errors in the transfer. continuous sck operation is not guaranteed if the dspi is put into module disable mode. enabling continuous sck disables the cs to sck delay and th e after sck delay. the delay after transfer is fixed at one sck cycle. figure 11-21 shows timing diagram for conti nuous sck format with continuous selection disabled. cs system clock sck frame 1 frame 0 cpol = 0 cpol = 1 ab
pxd10 microcontroller reference manual, rev. 1 11-42 freescale semiconductor preliminary?subject to change without notice figure 11-21. continuous sck timing diagram (cont= 0) if the cont bit in the tx fifo entry is set, cs rema ins asserted between the tr ansfers when the cs signal for the next transfer is the same as for the curren t transfer. under certain co nditions, sck can continue with pcs asserted, but with no data being shifted out of sout (sou t pulled high). this can cause the slave to receive incorrect da ta. those conditions include: ? continuous sck with cont bit set, but no data in the transmit fifo. ? continuous sck with cont bit set a nd entering stopped state (refer to section 11.8.2, start and stop of dspi transfers ?). ? continuous sck with cont bit set and en tering stop mode or module disable mode. figure 11-22 shows timing diagram for continuous sck fo rmat with continuous selection enabled. figure 11-22. continuous s ck timing diagram (cont=1) sck (cpol = 0) cs sck (cpol = 1) master sout t dt t dt = 1 sck. master sin sck (cpol = 0) sck (cpol = 1) master sout master sin transfer 1 transfer 2
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-43 preliminary?subject to change without notice 11.8.7 interrupts/dma requests the dspi has five conditions that can generate interrupt requests only, and two conditions that can generate interrupt. table 11-25 lists the six conditions. each condition has a flag bit and a request enab le bit. the flag bits are described in the section 11.7.2.4, dspi status register (dspix_sr) and the request enable bi ts are described in the section 11.7.2.5, dspi dma / interrupt request select and enable register (dspix_rser) . the tx fifo fill flag (tfff) and rx fifo drain flag (rfdf) gene rate interrupt requests or dma requests depending on the tfff_dirs and rfdf_dirs bits in the dspi x _rser. 11.8.7.1 end of queue interrupt request (eoqf) the end of queue equest indi cates that the end of a tr ansmit queue is reached. th e end of queue request is generated when the eoq bit in the executing spi co mmand is asserted and the eoqf_re bit in the dspi x _rser is set. refer to the eoq bit description in section 11.7.2.4, dspi status register (dspix_sr) . refer to figure 11-14 and figure 11-15 that illustrate when eoqf is set. 11.8.7.2 transmit fifo fill in terrupt or dma request (tfff) the transmit fifo fill request indicates that the tx fifo is not full. the transmit fifo fill request is generated when the number of entries in the tx fifo is less than the maximum number of possible entries, and the tfff_re bit in the dspi x _rser is set. the tfff_ dirs bit in the dspi x _rser selects whether a dma request or an interrupt request is generated. 11.8.7.3 transfer complete interrupt request (tcf) the transfer complete request indicates the end of the transfer of a serial frame. the transfer complete request is generated at the end of each frame tr ansfer when the tcf_re bit is set in the dspi x _rser. refer to the tcf bit description in section 11.7.2.4, dspi status register (dspix_sr) . refer to figure 11-14 and figure 11-15 that illustrate when tcf is set. table 11-25. interrupt and dma request conditions condition flag interrupt dma end of transfer queue has been reached (eoq) eoqf x tx fifo is not full tfff x x current frame transfer is complete tcf x tx fifo underflow has occurred tfuf x rx fifo is not empty rfdf x x rx fifo overflow occurred rfof x a fifo overrun occurred 1 1 the fifo overrun condition is created by oring the tfuf and rfof flags together. tfuf ored with rfof x
pxd10 microcontroller reference manual, rev. 1 11-44 freescale semiconductor preliminary?subject to change without notice 11.8.7.4 transmit fifo underf low interrupt request (tfuf) the transmit fifo unde rflow request indicates that an underflow condition in th e tx fifo has occurred. the transmit underflow condition is detected only fo r dspi modules operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi operating in slave mode and spi configuration is empty, and a transfer is initiated from an external spi master. if the tfuf bit is set while the tfuf_re bit in the dspi x _rser is set, an interrupt request is generated. 11.8.7.5 receive fifo drain in terrupt or dma request (rfdf) the receive fifo drain reque st indicates that the rx fifo is not empty. the r eceive fifo drain request is generated when the number of entries in the rx fifo is not zero, and the rfdf_re bit in the dspi x _rser is set. the rfdf_dirs bit in the dspi x _rser selects whether a dma request or an interrupt request is generated. 11.8.7.6 receive fifo overfl ow interrupt request (rfof) the receive fifo overflow request in dicates that an overflow condition in the rx fifo has occurred. a receive fifo overflow request is generated when rx fi fo and shift register are full and a transfer is initiated. the rfof_re bit in the dspi x _rser must be set for the inte rrupt request to be generated. depending on the state of the rooe bit in the dspi x _mcr, the data from the tr ansfer that generated the overflow is either ignored or shifted in to the shift re gister. if the rooe bit is set, the incoming data is shifted in to the shift register. if the rooe bit is negated, the incoming data is ignored. 11.8.7.7 fifo overrun request (tfuf) or (rfof) the fifo overrun request indicates th at at least one of th e fifos in the dspi has exceeded its capacity. the fifo overrun request is genera ted by logically or?ing together th e rx fifo overflow and tx fifo underflow signals. 11.8.8 power saving features the dspi supports three power-saving strategies: ? external stop mode ? module disable mode?clock gating of non-memory mapped logic ? clock gating of slave interface signals and clock to memory-mapped logic 11.8.8.1 external stop mode the dspi supports the stop mode protocol. when a reque st is made to enter exte rnal stop mode, the dspi block acknowledges the request by negating ipg_stop_ack. when the dspi is ready to have its clocks shut off the ipg_stop_ack signal is asserted. if a serial transfer is in progress, the dspi wa its until it reaches the frame boundary before it asserts ipg_stop_ack. while th e clocks are shut off, the dspi memory-mapped logic is not accessible. the states of the interrupt and dma request signals ca nnot be changed while in external stop mode. implementation of ipi gr een line stop mode in an soc is optional.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-45 preliminary?subject to change without notice 11.8.8.2 module disable mode module disable mode is a module-specific mode that the dspi can enter to save power. host software can initiate the module disable mode by writ ing a 1 to the mdis bit in the dspi x _mcr. in module disable mode, the dspi is in a dormant state, but the memory mapped registers are still accessible. certain read or write operations have a different affect when the dspi is in the module disa ble mode. reading the rx fifo pop register does not change the state of the rx fifo. likewise, writi ng to the tx fifo push register does not change the state of the tx fifo. cl earing either of the fifos does not have any effect in the module disable mode. changes to the dis_txf a nd dis_rxf fields of the dspi x _mcr does not have any affect in the module disable mode. in the mo dule disable mode, all status bits and register flags in the dspi return the correct values when read, but writing to them has no affect. writing to the dspi x _tcr during module disable mode does not have an effect. interrupt and dma request signals cannot be cleared while in the module disable mode. 11.8.8.3 slave interface signal gating the dspi module enable signal is used to gate sl ave interface signals such as address, byte enable, read/write and data. this prevents toggling slave interface signals fr om consuming power unless the dspi is accessed. 11.9 initialization and application information 11.9.1 how to change queues dspi queues are not part of the dspi module, but the dspi includes features in support of queue management. queues are primarily s upported in spi configuration. this section presents an example of how to change queues for the dspi. 1. the last command word from a queue is execute d. the eoq bit in the command word is set to indicate to the dspi that this is the last entry in the queue. 2. at the end of the tran sfer, corresponding to the command word with eoq set is sampled, the eoq flag (eoqf) in the dspi x _sr is set. 3. the setting of the eoqf flag disables both serial transmission, and serial reception of data, putting the dspi in the stopped state. the txrxs bi t is negated to indicate the stopped state. 4. the edma continues to fill tx fifo until it is full or step 5 occurs. 5. disable dspi dma transfers by disabling the dma enable request for the dma channel assigned to tx fifo and rx fifo. this is done by clea ring the corresponding dma en able request bits in the edma controller. 6. ensure all received data in rx fifo has been transferred to me mory receive queue by reading the rxcnt in dspi x _sr or by checking rfdf in the dspi x _sr after each read operation of the dspi x _popr. 7. modify dma descriptor of tx a nd rx channels for ?new? queues. 8. flush tx fifo by writing a 1 to the clr_txf bit in the dspi x _mcr register and flush the rx fifo by writing a 1 to the clr_rxf bit in the dspi x _mcr register.
pxd10 microcontroller reference manual, rev. 1 11-46 freescale semiconductor preliminary?subject to change without notice 9. clear transfer count eith er by setting ctcnt bit in the command word of the first entry in the new queue or via cpu writing directly to spi_tcnt field in the dspi x _tcr. 10. enable dma channel by enabling the dma enable request for th e dma channel assigned to the dspi tx fifo, and rx fifo by setting th e corresponding dma set enable request bit. 11. enable serial transmission and serial reception of data by clearing the eoqf bit. 11.9.2 baud rate settings table 11-26 shows the baud rate that is ge nerated based on the combination of the baud rate prescaler pbr and the baud rate scaler br in the dspi x _ctars. the values are calculated at a 64 mhz system frequency with dbr = 0. table 11-26. baud rate values baud rate divider prescaler values (dspi_ctar[pbr]) 2357 baud rate scaler values (dspi_ctar[br]) 2 16.0 mhz 10.7 mhz 6.4 mhz 4.57 mhz 4 8 mhz 5.33 mhz 3.2 mhz 2.28 mhz 6 5.33 mhz 3.56 mhz 2.13 mhz 1.52 mhz 8 4 mhz 2.67 mhz 1.60 mhz 1.15 mhz 16 2 mhz 1.33 mhz 800 khz 571 khz 32 1 mhz 670 khz 400 khz 285 khz 64 500 khz 333 khz 200 khz 142 khz 128 250 khz 166 khz 100 khz 71.7 khz 256 125 khz 83.2 khz 50 khz 35.71 khz 512 62.5 khz 41.6 khz 25 khz 17.86 khz 1024 31.2 khz 20.8 khz 12.5 khz 8.96 khz 2048 15.6 khz 10.4 khz 6.25 khz 4.47 khz 4096 7.81 khz 5.21 khz 3.12 khz 2.23 khz 8192 3.90 khz 2.60 khz 1.56 khz 1.11 khz 16384 1.95 khz 1.31 khz 781 hz 558 hz 32768 979 hz 653 hz 390 hz 279 hz
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-47 preliminary?subject to change without notice 11.9.3 delay settings table 11-27 shows the values for th e delay after transfer (t dt ) and cs to sck delay (t csc ) that can be generated based on the prescaler values and the scaler values set in the dspi x _ctars. the values calculated assume a 100 mhz system frequency. 11.9.4 calculation of fifo pointer addresses the user has complete visibility of the tx and rx fifo contents th rough the fifo registers, and valid entries can be identified through a memory mapped pointer and a memory mapped counter for each fifo. the pointer to the first-in entry in each fifo is me mory mapped. for the tx fifo the first-in pointer is the transmit next pointer (txnxtpt r). for the rx fifo the first-in pointer is the pop next pointer (popnxtptr). table 11-27. delay values delay prescaler values (dspi_ctar[pbr]) 1357 delay scaler values (dspi_ctar[dt]) 2 20.0 ns 60.0 ns 100.0 ns 140.0 ns 4 40.0 ns 120.0 ns 200.0 ns 280.0 ns 8 80.0 ns 240.0 ns 400.0 ns 560.0 ns 16 160.0 ns 480.0 ns 800.0 ns 1.1 ? s 32 320.0 ns 960.0 ns 1.6 ? s2.2 ? s 64 640.0 ns 1.9 ? s3.2 ? s4.5 ? s 128 1.3 ? s3.8 ? s6.4 ? s9.0 ? s 256 2.6 ? s7.7 ? s 12.8 ? s 17.9 ? s 512 5.1 ? s 15.4 ? s 25.6 ? s 35.8 ? s 1024 10.2 ? s 30.7 ? s 51.2 ? s 71.7 ? s 2048 20.5 ? s 61.4 ? s 102.4 ? s 143.4 ? s 4096 41.0 ? s 122.9 ? s 204.8 ? s 286.7 ? s 8192 81.9 ? s 245.8 ? s 409.6 ? s 573.4 ? s 16384 163.8 ? s 491.5 ? s 819.2 ? s 1.1 ms 32768 327.7 ? s 983.0 ? s 1.6 ms 2.3 ms 65536 655.4 ? s 2.0 ms 3.3 ms 4.6 ms
pxd10 microcontroller reference manual, rev. 1 11-48 freescale semiconductor preliminary?subject to change without notice refer to section 11.8.3.4, transmit first in first out (tx fifo) buffering mechanism , and section 11.8.3.5, receive first in first out (rx fifo) buffering mechanism , for details on the fifo operation. the tx fifo is chosen for the illustra tion, but the concepts carry over to the rx fifo. figure 11-23 illustrates the concept of first-in and last -in fifo entries along w ith the fifo counter. figure 11-23. tx fifo pointers and counter 11.9.4.1 address calculation for the firs t-in entry and last-i n entry in the tx fifo the memory address of the first-in entry in th e tx fifo is computed by the following equation: first-in entry address = txfifo base + 4 (txnxtptr) the memory address of the last-in entry in the tx fifo is computed by the following equation: last-in entry address = txfifo base + 4 x [(txctr + txnxtptr - 1) modulo txfifo depth] where: txfifo base = base a ddress of transmit fifo txctr = transmit fifo counter txnxtptr = transmit next pointer tx fifo depth = transmit fifo depth, implementation specific 11.9.4.2 address calculation for the firs t-in entry and last-i n entry in the rx fifo the memory address of the first-in entry in th e rx fifo is computed by the following equation: first-in entry address = rxfifo base + 4 x (popnxtptr) the memory address of the last-in entry in th e rx fifo is computed by the following equation: last-in entry address = rxfifo base + 4 x [(rxctr + popnxtptr - 1) modulo rxfifo depth] where: rxfifo base = base a ddress of receive fifo entry c entry a (first in) ? 1 entry b entry d (last in) tx fifo base push tx fifo tx fifo counter shift register sout register transmit next data pointer ? ? ? ? + 1 (txnxtptr)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 11-49 preliminary?subject to change without notice rxctr = receive fifo counter popnxtptr = pop next pointer rx fifo depth = receive fifo depth, implementation specific
pxd10 microcontroller reference manual, rev. 1 11-50 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-1 preliminary?subject to change without notice chapter 12 display control unit (dcu) 12.1 introduction the display controller unit (dcu) modul e is a system master that fetches graphics stored in internal or external memory and displays them on a tft lcd pa nel. a wide range of pa nel sizes is supported and the timing of the interface signals is highly configurable. graphics are read directly from memory and then blended in real-time, wh ich allows for dynamic cont ent creation with minimal cpu intervention. graphics may be encoded in a variety of formats to optimise memory usage. the dcu also has the capability of displaying real-time video from an external video source.
pxd10 microcontroller reference manual, rev. 1 12-2 freescale semiconductor preliminary?subject to change without notice 12.1.1 overview figure 12-1. display cont rol unit block diagram figure 12-1 shows the dcu architecture. this comprises tw o distinct sections. th e lower section shows the functional blocks of the dcu th at fetch the graphic a nd video content and drive the tft lcd panel. the upper section describes the user interface through which th e user configures the graphical content of the tft lcd panel. registers interface (control layer0 layer1 layer2 pixel format converter blending gamma correction out fifo display driver parallel data interface gamma dcu_clk pdi_clk pdi_datain[17:0] ahb master i/f external video tft display pdi_hsync pdi_vsync timing and control unit pix_clk_in pdi_clk mux clk,hsync,vsync timing signals to other modules mode ram cursor . . . layer14 layer15 bgcolor (1 kb) (256 x 8 x3) signature calculator crc_ready interrupt crc value ch1 ch2 ch3 ch4 clut/ tile ram in fifo (6kb) crc pos descriptors for each layer) slave bus i/f in fifo in fifo in fifo ram source
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-3 preliminary?subject to change without notice the sections are analogous to the st ructure of communications modules, such as the flexcan, where one part of the module is configured to connect with the communications bus th rough bit-timin g, parity, baud rate, etc., while a different part is used to store the data content and message identifiers. the configuration of the lower sec tion is dependent on the specific tf t lcd panel and opt ional real-time video hardware that are attached to the dcu inputs and outputs. in most cases, this is configured once for the hardware in use before the dcu is enab led. when active, this section automatically: ? calculates the relevant gra phical content for each pixel ? fetches the source graphics from memory using its internal dma channels (labelled ch1 to ch4) ? converts the graphic value of each fetched pixe l into full quality color format (if required) ? calculates the required pixel value by blending the values of up to four separate graphics ? performs a gamma correction on the pixel value (if required) ? sends the pixel value to the tft lcd display over its data bus ? sets flags to indicate end of frame, buf fer threshold, and other status changes the upper section describes the characteristics of the graphics to be displayed on the panel and how they are blended together. the dcu manage s the graphical content of the pane l through sets of registers called layers. there are 16 layers available in the dc u and each contains the following information: ? horizontal and vertic al size of graphic ? position of graphic on the panel ? address of graphic in memory ? color encoding format and color palettes (if required) ? type and depth of blending ? range of colors identified for chroma blending ? tile size the values in these registers may be changed at any time, and the pane l content will be updated when the next full frame is ready to be displa yed. the layers are set to a fixed priority, and this is used by the lower section to define which layers are bl ended, in which order, on the panel. the upper section also cont ains configuration register s for a cursor graphic, th e default background color, interrupt enables, test graphic, and simple register pr otection settings. 12.1.2 features the dcu has these features: ? full rgb888 output to tft lcd panel ? 16 graphics layers, a default background color laye r and a cursor layer with integrated blinking option ? blending of each pixel using up to 4 sour ce layers dependent on size of panel ? programmable panel size up to a maximum of wide vga (800 x 480) ? gamma correction with 8-bit resolution on each color component ? safety mode for tagging pixels on highest priority layers
pxd10 microcontroller reference manual, rev. 1 12-4 freescale semiconductor preliminary?subject to change without notice ? digital video input with and without sync extraction per itu- r bt.656 supporting multiple video input formats including rgb666, rgb565, monochrome and ycbcr422 ? dedicated memory blocks to store a cu rsor and color look up tables (cluts) each graphic layer has the following attributes ? can be placed with one pixe l resolution in either axis ? supports multiple color-encoding formats includi ng 1, 2, 4 and 8 bits per pixel indexed colors, rgb565 and rgb888 direct colors, and ar gb1555, argb4444 and argb8888 direct colors with an alpha channel ? alpha blending with 8-bit resolution ? chroma-key blending fo r anti-mask encoding ? multiple alpha and chroma-key blending modes ? transparency modes for anti -aliased text and graphics ? luminance mode for highlighting content ? tile mode for efficient creati on of textured background content 12.1.3 modes of operation the dcu has four modes of operation: ? dcu_off : when in this mode, the dcu is turned off. all the logic in the design is put in reset state to reduce power. ? normal_mode : the dcu displays and blends the gra phics specified by the layer descriptors. ? pdi_mode : a mode which fetches video from an external video source and combines that with the graphics configured on the layers. ? colbar_mode : color bar generation for testing purposes. 12.2 external signal description 12.2.1 overview the dcu has up to 22 input signal s and up to 30 output signals. see figure 12-2 . the choice of signals used depends on the configuration of the dcu. all active signals must be enabled by configuring the appropriate pcr registers in the siul module.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-5 preliminary?subject to change without notice figure 12-2. external signals 12.2.2 detailed signal descriptions table 12-1. detailed signal descriptions signal direction description parallel data interface (camera interface) pdi_clk in clock for the parallel data from the input video data pdi_vsync in vertical sync to indicate t he start of new frame for the display pdi_hsync in horizontal sync to indicate the start of new line for the display pdi_de in data enable for the camera data input pdi_datain[17:0] in 18-bit parallel input data for the display display interface pix_clk_out out pixel clock used to drive the display panel dcu_vsync out vertical sync signal, indicating the beginning of a new frame dcu_hsync out horizontal sync signal, indicating the beginning of a new line dcu_csync out composite sync signal, combining horizontal and vertical sync signals to form a composite sync signal. it includes both the hsync pulse and the vsync pulse. note: not used on this device. dcu_tag out when high, this signal indicates t hat the pixel is tagged and an application can calculate crc externally on this pixel. dcu_de out data enable. qualif ies the data output (dcu_ld) dcu_r[7:0], dcu_g[7:0], dcu_b[7:0] out red, green and blue data output. dcu top level parallel data interface display interface pdi_clk pix_clk_out dcu_vsync dcu_hsync dcu_csync dcu_de dcu_r[7:0], dcu_g[7:0], dcu_b[7:0] pdi _ datain[17:0] pdi _ vsync pdi_ hsync pdi_ de dcu_tag
pxd10 microcontroller reference manual, rev. 1 12-6 freescale semiconductor preliminary?subject to change without notice 12.3 memory map and register definition 12.3.1 memory map table 12-2 shows the memory map of the dcu. 12.3.2 register map table 12-3 provides the register map of the dcu. only 32-bit writes and 32-bit alig ned access are supported. by te and half-word acce sses are not supported. table 12-2. dcu memory map parameter address range register address space 0x0000 ? 0x03ff cursor address space 0x0400 ? 0x07ff gamma_r address space 0x0800 ? 0x0bff gamma_g address space 0x0c00 ? 0x0fff gamma_b address space 0x1000 ? 0x13ff empty space 0x1400 ? 0x1fff clut/tile address space 0x2000 ? 0x3fff table 12-3. dcu register map address offset register access reset value location general registers 0x000 ctrldescl0_1 register r/w 0x00000000 on page 22 0x004 ctrldescl0_2 register r/w 0x00000000 on page 23 0x008 ctrldescl0_3 register r/w 0x00000000 on page 24 0x00c ctrldescl0_4 register r/w 0x00000000 on page 25 0x010 ctrldescl0_5 register r/w/ 0x00000000 on page 27 0x014 ctrldescl0_6 register r/w/ 0x00000000 on page 28 0x018 ctrldescl0_7 register r/w/ 0x00000000 on page 30 0x01c ctrldescl1_1 register r/w 0x00000000 on page 22 0x020 ctrldescl1_2 register r/w 0x00000000 on page 23 0x024 ctrldescl1_3 register r/w 0x00000000 on page 24 0x028 ctrldescl1_4 register r/w 0x00000000 on page 25 0x02c ctrldescl1_5 register r/w 0x00000000 on page 27 0x030 ctrldescl1_6 register r/w 0x00000000 on page 28 0x034 ctrldescl1_7 register r/w 0x00000000 on page 30
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-7 preliminary?subject to change without notice 0x038 ctrldescl2_1 register r/w 0x00000000 on page 22 0x03c ctrldescl2_2 register r/w 0x00000000 on page 23 0x040 ctrldescl2_3 register r/w 0x00000000 on page 24 0x044 ctrldescl2_4 register r/w 0x00000000 on page 25 0x048 ctrldescl2_5 register r/w 0x00000000 on page 27 0x04c ctrldescl2_6 register r/w 0x00000000 on page 28 0x050 ctrldescl2_7 register r/w 0x00000000 on page 30 0x054 ctrldescl3_1 register r/w 0x00000000 on page 22 0x058 ctrldescl3_2 register r/w 0x00000000 on page 23 0x05c ctrldescl3_3 register r/w 0x00000000 on page 24 0x060 ctrldescl3_4 register r/w 0x00000000 on page 25 0x064 ctrldescl3_5 register r/w 0x00000000 on page 27 0x068 ctrldescl3_6 register r/w 0x00000000 on page 28 0x06c ctrldescl3_7 register r/w 0x00000000 on page 30 0x070 ctrldescl4_1 register r/w 0x00000000 on page 22 0x074 ctrldescl4_2 register r/w 0x00000000 on page 23 0x078 ctrldescl4_3 register r/w 0x00000000 on page 24 0x07c ctrldescl4_4 register r/w 0x00000000 on page 25 0x080 ctrldescl4_5 register r/w 0x00000000 on page 27 0x084 ctrldescl4_6 register r/w 0x00000000 on page 28 0x088 ctrldescl4_7 register r/w 0x00000000 on page 30 0x08c ctrldescl5_1 register r/w 0x00000000 on page 22 0x090 ctrldescl5_2 register r/w 0x00000000 on page 23 0x094 ctrldescl5_3 register r/w 0x00000000 on page 24 0x098 ctrldescl5_4 register r/w 0x00000000 on page 25 0x09c ctrldescl5_5 register r/w 0x00000000 on page 27 0x0a0 ctrldescl5_6 register r/w 0x00000000 on page 28 0x0a4 ctrldescl5_7 register r/w 0x00000000 on page 30 0x0a8 ctrldescl6_1 register r/w 0x00000000 on page 22 0x0ac ctrldescl6_2 register r/w 0x00000000 on page 23 0x0b0 ctrldescl6_3 register r/w 0x00000000 on page 24 0x0b4 ctrldescl6_4 register r/w 0x00000000 on page 25 0x0b8 ctrldescl6_5 register r/w 0x00000000 on page 27 table 12-3. dcu register map (continued) address offset register access reset value location
pxd10 microcontroller reference manual, rev. 1 12-8 freescale semiconductor preliminary?subject to change without notice 0x0bc ctrldescl6_6 register r/w 0x00000000 on page 28 0x0c0 ctrldescl6_7 register r/w 0x00000000 on page 30 0x0c4 ctrldescl7_1 register r/w 0x00000000 on page 22 0x0c8 ctrldescl7_2 register r/w 0x00000000 on page 23 0x0cc ctrldescl7_3 register r/w 0x00000000 on page 24 0x0d0 ctrldescl7_4 register r/w 0x00000000 on page 25 0x0d4 ctrldescl7_5 register r/w 0x00000000 on page 27 0x0d8 ctrldescl7_6 register r/w 0x00000000 on page 28 0x0dc ctrldescl7_7 register r/w 0x00000000 on page 30 0x0e0 ctrldescl8_1 register r/w 0x00000000 on page 22 0x0e4 ctrldescl8_2 register r/w 0x00000000 on page 23 0x0e8 ctrldescl8_3 register r/w 0x00000000 on page 24 0x0ec ctrldescl8_4 register r/w 0x00000000 on page 25 0x0f0 ctrldescl8_5 register r/w 0x00000000 on page 27 0x0f4 ctrldescl8_6 register r/w 0x00000000 on page 28 0x0f8 ctrldescl8_7 register r/w 0x00000000 on page 30 0x0fc ctrldescl9_1 register r/w 0x00000000 on page 22 0x100 ctrldescl9_2 register r/w 0x00000000 on page 23 0x104 ctrldescl9_3 register r/w 0x00000000 on page 24 0x108 ctrldescl9_4 register r/w 0x00000000 on page 25 0x10c ctrldescl9_5 register r/w 0x00000000 on page 27 0x110 ctrldescl9_6 register r/w 0x00000000 on page 28 0x114 ctrldescl9_7 register r/w 0x00000000 on page 30 0x118 ctrldescl10_1 register r/w 0x00000000 on page 22 0x11c ctrldescl10_2 register r/w 0x00000000 on page 23 0x120 ctrldescl10_3 register r/w 0x00000000 on page 24 0x124 ctrldescl10_4 register r/w 0x00000000 on page 25 0x128 ctrldescl10_5 register r/w 0x00000000 on page 27 0x12c ctrldescl10_6 register r/w 0x00000000 on page 28 0x130 ctrldescl10_7 register r/w 0x00000000 on page 30 0x134 ctrldescl11_1 register r/w 0x00000000 on page 22 0x138 ctrldescl11_2 register r/w 0x00000000 on page 23 0x13c ctrldescl11_3 register r/w 0x00000000 on page 24 table 12-3. dcu register map (continued) address offset register access reset value location
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-9 preliminary?subject to change without notice 0x140 ctrldescl11_4 register r/w 0x00000000 on page 25 0x144 ctrldescl11_5 register r/w 0x00000000 on page 27 0x148 ctrldescl11_6 register r/w 0x00000000 on page 28 0x14c ctrldescl11_7 register r/w 0x00000000 on page 30 0x150 ctrldescl12_1 register r/w 0x00000000 on page 22 0x154 ctrldescl12_2 register r/w 0x00000000 on page 23 0x158 ctrldescl12_3 register r/w 0x00000000 on page 24 0x15c ctrldescl12_4 register r/w 0x00000000 on page 25 0x160 ctrldescl12_5 register r/w 0x00000000 on page 27 0x164 ctrldescl12_6 register r/w 0x00000000 on page 28 0x168 ctrldescl12_7 register r/w 0x00000000 on page 30 0x16c ctrldescl13_1 register r/w 0x00000000 on page 22 0x170 ctrldescl13_2 register r/w 0x00000000 on page 23 0x174 ctrldescl13_3 register r/w 0x00000000 on page 24 0x178 ctrldescl13_4 register r/w 0x00000000 on page 25 0x17c ctrldescl13_5 register r/w 0x00000000 on page 27 0x180 ctrldescl13_6 register r/w 0x00000000 on page 28 0x184 ctrldescl13_7 register r/w 0x00000000 on page 30 0x188 ctrldescl14_1 register r/w 0x00000000 on page 22 0x18c ctrldescl14_2 register r/w 0x00000000 on page 23 0x190 ctrldescl14_3 register r/w 0x00000000 on page 24 0x194 ctrldescl14_4 register r/w 0x00000000 on page 25 0x198 ctrldescl14_5 register r/w 0x00000000 on page 27 0x19c ctrldescl14_6 register r/w 0x00000000 on page 28 0x1a0 ctrldescl14_7 register r/w 0x00000000 on page 30 0x1a4 ctrldescl15_1 register r/w 0x00000000 on page 22 0x1a8 ctrldescl15_2 register r/w 0x00000000 on page 23 0x1ac ctrldescl15_3 register r/w 0x00000000 on page 24 0x1b0 ctrldescl15_4 register r/w 0x00000000 on page 25 0x1b4 ctrldescl15_5 register r/w 0x00000000 on page 27 0x1b8 ctrldescl15_6 register r/w 0x00000000 on page 28 0x1bc ctrldescl15_7 register r/w 0x00000000 on page 30 0x1c0 ctrldesccursor_1 register r/w 0x00000000 on page 30 table 12-3. dcu register map (continued) address offset register access reset value location
pxd10 microcontroller reference manual, rev. 1 12-10 freescale semiconductor preliminary?subject to change without notice 0x1c4 ctrldesccursor_2 register r/w 0x00000000 on page 31 0x1c8 ctrldesccursor_3 register r/w 0x00000000 on page 32 0x1cc ctrldesccursor_4 register r/w 0x00000000 on page 32 0x1d0 dcu_mode register r/w 0x00000000 on page 33 0x1d4 bgnd register r/w 0x00000000 on page 35 0x1d8 disp_size register r/w 0x00000000 on page 36 0x1dc hsyn_para register r/w 0x00c01803 on page 37 0x1e0 vsyn_para register r/w 0x00c01803 on page 37 0x1e4 synpol register r/w 0x00000000 on page 38 0x1e8 threshold register r/w 0x0000780a on page 40 0x1ec int_status register r 0x00000000 on page 40 0x1f0 int_mask regi ster r/w 0x000f7fff on page 42 0x1f4 colbar_1 register r/w 0xff000000 on page 45 0x1f8 colbar_2 register r/w 0xff0000ff on page 45 0x1fc colbar_3 register r/w 0xff00ffff on page 46 0x200 colbar_4 register r/w 0xff00ff00 on page 46 0x204 colbar_5 register r/w 0xffffff00 on page 47 0x208 colbar_6 register r/w 0xffff0000 on page 47 0x20c colbar_7 register r/w 0xffff00ff on page 48 0x210 colbar_8 register r/w 0xffffffff on page 48 0x214 div_ratio register r/w 0x0000001f on page 48 0x218 sign_calc_1 register r/w 0x00000000 on page 49 0x21c sign_calc_2 register r/w 0x00000000 on page 50 0x220 crc_val register r/w 0x00000000 on page 50 0x224 pdi_status register r/w 0x00000000 on page 51 0x228 mask_pdi_status register r/w 0x000003ff on page 52 0x22c parr_err_status register r/w 0x00000000 on page 54 0x230 mask_parr_err_status register r/w 0x0007ffff on page 56 0x234 threshold_inp_buf_1 register r/w 0xff00ff00 on page 58 0x238 threshold_inp_buf_2 register r/w 0xff00ff00 on page 59 0x23c luma_comp register r/w 0x9512a254 on page 60 0x240 chroma_red register r/w 0x03310000 on page 60 0x244 chroma_green register r/w 0x06600f38 on page 61 table 12-3. dcu register map (continued) address offset register access reset value location
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-11 preliminary?subject to change without notice 0x248 chroma_blue register r/w 0x00000409 on page 62 0x24c crc_pos register r/w 0x00000000 on page 62 0x250 fg0_fcolor register r/w 0x00000000 on page 63 0x254 fg0_bcolor register r/w 0x00000000 on page 64 0x258 fg1_fcolor register r/w 0x00000000 on page 63 0x25c fg1_bcolor register r/w 0x00000000 on page 64 0x260 fg2_fcolor register r/w 0x00000000 on page 63 0x264 fg2_bcolor register r/w 0x00000000 on page 64 0x268 fg3_fcolor register r/w 0x00000000 on page 63 0x26c fg3_bcolor register r/w 0x00000000 on page 64 0x270 fg4_fcolor register r/w 0x00000000 on page 63 0x274 fg4_bcolor register r/w 0x00000000 on page 64 0x278 fg5_fcolor register r/w 0x00000000 on page 63 0x27c fg5_bcolor register r/w 0x00000000 on page 64 0x280 fg6_fcolor register r/w 0x00000000 on page 63 0x284 fg6_bcolor register r/w 0x00000000 on page 64 0x288 fg7_fcolor register r/w 0x00000000 on page 63 0x28c fg7_bcolor register r/w 0x00000000 on page 64 0x290 fg8_fcolor register r/w 0x00000000 on page 63 0x294 fg8_bcolor register r/w 0x00000000 on page 64 0x298 fg9_fcolor register r/w 0x00000000 on page 63 0x29c fg9_bcolor register r/w 0x00000000 on page 64 0x2a0 fg10_fcolor register r/w 0x00000000 on page 63 0x2a4 fg10_bcolor register r/w 0x00000000 on page 64 0x2a8 fg11_fcolor register r/w 0x00000000 on page 63 0x2ac fg11_bcolor register r/w 0x00000000 on page 64 0x2b0 fg12_fcolor register r/w 0x00000000 on page 63 0x2b4 fg12_bcolor register r/w 0x00000000 on page 64 0x2b8 fg13_fcolor register r/w 0x00000000 on page 63 0x2bc fg13_bcolor register r/w 0x00000000 on page 64 0x2c0 fg14_fcolor register r/w 0x00000000 on page 63 0x2c4 fg14_bcolor register r/w 0x00000000 on page 64 0x2c8 fg15_fcolor register r/w 0x00000000 on page 63 table 12-3. dcu register map (continued) address offset register access reset value location
pxd10 microcontroller reference manual, rev. 1 12-12 freescale semiconductor preliminary?subject to change without notice 12.3.3 register summary figure 12-3 provides a key for register figures and tables and the register summary. the conventions in table 12-4 serve as a key for the register summ ary and individual register diagrams. 0x2cc fg15_bcolor register r/w 0x00000000 on page 64 0x2d0-0x2fc reserved 0x300 global protection register r/w 0x00000000 on page 65 0x304 soft lock bit register l0 r/w 0x00000000 on page 66 0x308 soft lock bit register l1 r/w 0x00000000 on page 68 0x30c soft lock bit register disp_size r/w 0x00000000 on page 69 0x310 soft lock bit register vsync/hsync para r/w 0x00000000 on page 70 0x314 soft lock bit register pol r/w 0x00000000 on page 71 0x318 soft lock bit register l0_transp r/w 0x00000000 on page 71 0x31c soft lock bit register l1_transp r/w 0x00000000 on page 73 always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 12-3. key to register fields table 12-4. register conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writable fieldname identifies the field. its pres ence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect w write only r/w standard read/write bit. only software can c hange the bit?s value (other than a hardware reset). rwm a read/write bit that can be modified by hardware in some fashion other than by a reset w1c write one to clear. a status bit that can be read, and is cleared by writing a one. self-clearing bit writing a one has some effect on the m odule, but it always reads as zero. (previously designated slfclr) s set: pattern on the data bus is ored with and written into the register. c clear: pattern on the data bus is a mask. if a bit on the mask is set, then the corresponding register bit is cleared. table 12-3. dcu register map (continued) address offset register access reset value location
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-13 preliminary?subject to change without notice reset values 0 resets to zero 1 resets to one ? undefined at reset u unaffected by reset [ signal_name ] reset value is determined by polarity of indicated signal. table 12-5. register descriptions name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ctrldescl0_1 0x000 r000000 height w r0000 width w ctrldescl0_2 0x004 r000000 posy w r0000 posx w ctrldescl0_3 0x008 r addr w r w ctrldescl0_4 0x00c r en til e_e n dat a_s el saf ety _en trans bpp w r0 luoffs 0 bb ab w ctrldescl0_5 0x010 r00000000 ckmax_r w r ckmax_g ckmax_b w table 12-4. register conventions (continued) convention description
pxd10 microcontroller reference manual, rev. 1 12-14 freescale semiconductor preliminary?subject to change without notice ctrldescl0_6 0x014 r00000000 ckmin_r w r ckmin_g ckmin_b w ctrldescl0_7 0x018 r000000 tile_ver_size w r00000000 tile_hor_size w ctrldesccurs or_1 0x1c0 r000000 height w r000000 width w ctrldesccurs or_2 0x1c4 r000000 posy w r000000 posx w ctrldesccurs or_3 0x1c8 rcu r_e n 0000000 default_cursor_color[0:7] w r default_cursor_color[8:23] w ctrldesccurs or_4 0x1cc r00000000 hwc_blink_off w r0000000 en_blink hwc_blink_on w table 12-5. register descriptions (continued) name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-15 preliminary?subject to change without notice dcu_mode 0x1d0 r dcu_sw_ reset 00000000 blend_iter pdi_sync_lock w r pdi_interpol_en raster_en pdi_en pdi_byte_rev pdi_de_mode pdi_narrow_mode pdi_mode pdi_slave_mode tag_en sig_en pdi_sync 0 en_gamma dcu_mode w bgnd 0x1d4 r00000000 bgnd_r w r bgnd_g bgnd_b w disp_size 0x1d8 r000000 delta_y w r00000000 delta_x w hsyn_para 0x1dc r0 bp_h 00 pw_h[0:3] w r pw_h[4:8] 00 fp_h w vsyn_para 0x1e0 r0 bp_v 00 pw_v[0:3] w r pw_v[4:8] 00 fp_v w syn_pol 0x1e4 r0000000000000000 w r00000 inv_pdi_de inv_pdi_hs inv_pdi_vs inv_pdi_clk inv_pxck neg bp_vs bp_hs inv_cs inv_vs inv_hs w table 12-5. register descriptions (continued) name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 12-16 freescale semiconductor preliminary?subject to change without notice threshold 0x1e8 r000000 ls_bf_vs w r out_buf_high out_buf_low w int_status 0x1ec r000000000000 p4_fifo_hi_flag p4_fifo_lo_flag p3_fifo_hi_flag p3_fifo_lo_flag w w1c w1c w1c w1c r0 dma_trans_finish 00 ipm_error prog_end p2_fifo_hi_flag p2_fifo_lo_flag p1_fifo_hi_flag p1_fifo_lo_flag crc_overflow crc_ready vs_blank ls_bf_vs undrun vsync w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c int_mask 0x1f0 r000000000000 m_p4_fifo_hi_flag m_p4_fifo_lo_flag m_p3_fifo_hi_flag m_p3_fifo_lo_flag w r0 m_dma_trans_finish 00 m_ipm_error m_prog_end m_p2_fifo_hi_flag m_p2_fifo_lo_flag m_p1_fifo_hi_flag m_p1_fifo_lo_flag m_crc_overflow m_crc_ready m_vs_blank m_ls_bf_vs m_undrun m_vsync w colbar_1 0x1f4 r11111111 colbar_1_r w r colbar_1_g colbar_1_b w table 12-5. register descriptions (continued) name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-17 preliminary?subject to change without notice colbar_2 0x1f8 r11111111 colbar_2_r w r colbar_2_g colbar_2_b w colbar_3 0x1fc r11111111 colbar_3_r w r colbar_3_g colbar_3_b w colbar_4 0x200 r11111111 colbar_4_r w r colbar_4_g colbar_4_b w colbar_5 0x204 r11111111 colbar_5_r w r colbar_5_g colbar_5_b w colbar_6 0x208 r11111111 colbar_6_r w r colbar_6_g colbar_6_b w colbar_7 0x20c r11111111 colbar_7_r w r colbar_7_g colbar_7_b w colbar_8 0x210 r11111111 colbar_8_r w r colbar_8_g colbar_8_b w div_ratio 0x214 r0000000000000000 w r00000000 div_ratio w table 12-5. register descriptions (continued) name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 12-18 freescale semiconductor preliminary?subject to change without notice sign_calc_ 1 0x218 r000000 sig_ver_size w r000000 sig_hor_size w sign_calc_ 2 0x21c r000000 sig_ver_pos w r000000 sig_hor_pos w crc_val 0x220 r crc_val w r w pdi_status 0x224 r0000000000000000 w r000000 pdi_blanking_err pdi_ecc_err2 pdi_ecc_err1 pdi_lock_lost pdi_lock_det pdi_vsync_det pdi_hsync_det pdi_de_det pdi_clk_lost pdi_clk_det w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c mask_pdi_s tat u s 0x228 r0000000000000000 w r000000 m_pdi_blanking_err m_pdi_ecc_err2 m_pdi_ecc_err1 m_pdi_lock_lost m_pdi_lock_det m_pdi_vsync_det m_pdi_hsync_det m_pdi_de_det m_pdi_clk_lost m_pdi_clk_det w table 12-5. register descriptions (continued) name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-19 preliminary?subject to change without notice parr_err_ status 0x22c r0000000000000 hwc_err sig_err disp_err w w1c w1c w1c r l15_parr_err l14_parr_err l13_parr_err l12_parr_err l11_parr_err l10_parr_err l9_parr_err l8_parr_err l7_parr_err l6_parr_err l5_parr_err l4_parr_err l3_parr_err l2_parr_err l1_parr_err l0_parr_err w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c mask_parr_ err_status 0x230 r0000000000000 m_hwc_err m_sig_err m_disp_err w r m_l15_parr_err m_l14_parr_err m_l13_parr_err m_l12_parr_err m_l11_parr_err m_l10_parr_err m_l9_parr_err m_l8_parr_err m_l7_parr_err m_l6_parr_err m_l5_parr_err m_l4_parr_err m_l3_parr_err m_l2_parr_err m_l1_parr_err m_l0_parr_err w threshold _inp_buf 0x234 r inp_buf_p2_hi inp_buf_p2_lo w r inp_buf_p1_hi inp_buf_p1_lo w threshold _inp_buf 0x238 r inp_buf_p4_hi inp_buf_p4_lo w r inp_buf_p3_hi inp_buf_p3_lo w luma_comp 0x23c r y_red y_green[0:4] w r y_green[5:9] y_blue w table 12-5. register descriptions (continued) name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 12-20 freescale semiconductor preliminary?subject to change without notice chroma_re d 0x240 r00000 cr_red w r0000 cb_red w chroma_g reen 0x244 r00000 cr_green w r0000 cb_green w chroma_bl ue 0x248 r00000 cr_blue w r0000 cb_blue w crc_pos 0x24c r crc_pos w r w fgx_fcolor 0x250 r11111111 fgx_fcolor[0:7] w r fgx_fcolor[8:23] w fgx_bcolor 0x254 r11111111 fgx_bcolor[0:7] w r fgx_bcolor[8:23] w global_protec tion 0x300 r hlb 000000000000000 w r0000000000000000 w table 12-5. register descriptions (continued) name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-21 preliminary?subject to change without notice soft_lock_bit l0 0x304 r0000 slb_l0_1 slb_l0_2 slb_l0_3 slb_l0_4 0000 slb_l0_5 slb_l0_6 slb_l0_7 0 w wen_lo_1 wen_lo_2 wen_lo_3 wen_lo_4 wen_lo_5 wen_lo_6 wen_lo_7 r0000000000000000 w soft_lock_bit l1 0x308 r0000 slb_l1_1 slb_l1_2 slb_l1_3 slb_l1_4 0000 slb_l1_5 slb_l1_6 slb_l1_7 0 w wen_l1_1 wen_l1_2 wen_l1_3 wen_l1_4 wen_l1_5 wen_l1_6 wen_l1_7 r0000000000000000 w soft_lock_di sp_size 0x30c r0000 slb_disp 00000000000 w wen_disp r0000000000000000 w soft_lock_hs ync/vsync pa r a 0x310 r0000 slb_hsync slb_vsync 0000000000 w wen_hsync wen_vsync r0000000000000000 w soft_lock_p ol 0x314 r0000 slb_pol 00000000000 w wen_pol r0000000000000000 w table 12-5. register descriptions (continued) name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 12-22 freescale semiconductor preliminary?subject to change without notice 12.3.4 register descriptions this section describes the dcu registers. 12.3.4.1 control descriptor l0 _1 register (ctrldescl0_1) figure 12-4 represents the control descriptor l0_1 register. this register se ts the height and width of the layer associated with the register. soft_lock l0_transp 0x318 r0000 slb_fcolor slb_bcoloe 0000000000 w wen_fcolor wen_bcolor r0000000000000000 w soft_lock l1_transp 0x31c r0000 slb_fcolor slb_bcoloe 0000000000 w wen_fcolor wen_bcolor r0000000000000000 w table 12-5. register descriptions (continued) name 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-23 preliminary?subject to change without notice figure 12-4. ctrldescl0_1 register 12.3.4.2 control descr iptor l0_2 register figure 12-5 represents the control descriptor l0_2 register. this register se ts the origin (top/left) of the layer associated with the register. offset: 0x000 (ctrldescl0_1) 0x01c (ctrldescl1_1) 0x038 (ctrldescl2_1) 0x054 (ctrldescl3_1) 0x070 (ctrldescl4_1) 0x08c (ctrldescl5_1) 0x098 (ctrldescl6_1) 0x0c4 (ctrldescl7_1) 0x0e0 (ctrldescl8_1) 0x0fc (ctrldescl9_1) 0x118 (ctrldescl10_1) 0x134 (ctrldescl11_1) 0x150 (ctrldescl12_1) 0x16c (ctrldescl13_1) 0x188 (ctrldescl14_1) 0x194 (ctrldescl15_1) access: user read/write 0123456789101112131415 r000000 height w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 width w reset0000000000000000 figure 1. table 12-6. ctrldescl0_1 field descriptions field description 6?15 height height of the layer in pixels 20?31 width width of the layer (in pixels). the layer width must be in multiples of the number of pixels that can be stored in 32 bits (except for the special case of 1 bit per pixel), and therefore differs depending on color encoding. for example, if 2 bits per pixel format is used, then the layer width must be configured in multiples of 16. see section 12.4.5.3, layer size and positioning .?
pxd10 microcontroller reference manual, rev. 1 12-24 freescale semiconductor preliminary?subject to change without notice figure 12-5. ctrldescl0_2 register 12.3.4.3 control descr iptor l0_3 register figure 12-6 represents the control descript or l0_3 register. this register sets the beginning address of layer data. offset: 0x004 (ctrldescl0_2) 0x020 (ctrldescl1_2) 0x03c (ctrldescl2_2) 0x058 (ctrldescl3_2) 0x074 (ctrldescl4_2) 0x090 (ctrldescl5_2) 0x0ac (ctrldescl6_2) 0x0c8 (ctrldescl7_2) 0x0e4 (ctrldescl8_2) 0x100 (ctrldescl9_2) 0x11c (ctrldescl10_2) 0x138 (ctrldescl11_2) 0x154 (ctrldescl12_2) 0x170 (ctrldescl13_2) 0x18c (ctrldescl14_2) 0x198 (ctrldescl15_2) access: user read/write 0123456789101112131415 r000000 posy w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 posx w reset0000000000000000 figure 2. table 12-7. ctrldescl0_2 field descriptions field description 6?15 posy amount of pixels from the top of display frame 20?31 posx amount of pixels from the left of display frame
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-25 preliminary?subject to change without notice figure 12-6. ctrldescl0_3 register 12.3.4.4 control descr iptor l0_4 register figure 12-7 represents the control descriptor l0_4 register. this register controls various graphics options and whether the layer is enabled. offset: 0x008 (ctrldescl0_3) 0x024 (ctrldescl1_3) 0x040 (ctrldescl2_3) 0x05c (ctrldescl3_3) 0x078 (ctrldescl4_3) 0x094 (ctrldescl5_3) 0x0b0 (ctrldescl6_3) 0x0cc (ctrldescl7_3) 0x0e8 (ctrldescl8_3) 0x104 (ctrldescl9_3) 0x120 (ctrldescl10_3) 0x13c (ctrldescl11_3) 0x158 (ctrldescl12_3) 0x174 (ctrldescl13_3) 0x18c (ctrldescl14_3) 0x1ac (ctrldescl15_3) access: user read/write 0123456789101112131415 r addr[0:15] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r addr16:31] w reset0000000000000000 figure 3. table 12-8. ctrldescl0_3 field descriptions field description 0?31 addr address of layer data in the memory. the address programmed should be 32-bit aligned.
pxd10 microcontroller reference manual, rev. 1 12-26 freescale semiconductor preliminary?subject to change without notice figure 12-7. ctrldescl0_4 register offset: 0x00c (ctrldescl0_4) 0x028 (ctrldescl1_4) 0x044 (ctrldescl2_4) 0x060 (ctrldescl3_4) 0x07c (ctrldescl4_4) 0x098 (ctrldescl5_4) 0x0b4 (ctrldescl6_4) 0x0d0 (ctrldescl7_4) 0x0ec (ctrldescl8_4) 0x108 (ctrldescl9_4) 0x124 (ctrldescl10_4) 0x140 (ctrldescl11_4) 0x15c (ctrldescl12_4) 0x178 (ctrldescl13_4) 0x190 (ctrldescl14_4) 0x1b0 (ctrldescl15_4) access: user read/write 0123456789101112131415 r en tile _en dat a_s el saf ety _en trans bpp w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 luoffs 0 bb ab w reset0000000000000000 figure 4. table 12-9. ctrldescl0_4 field descriptions field description 0 en enable the layer 1?b1: on 1?b0: off 1 tile_en enable the tile mode 1?b1: on 1?b0: off 2 data_sel selects the tile data either from mcu memory or clut 1?b0: tile mode data resides in the mcu memory 1?b1: tile mode data resides in the clut 3 safety_en safety mode enable bit. valid only for layer 0 a nd layer 1. for registers of all other layers, this should be set to 0. 1?b1: safety mode is enabled for this layer 1?b0: safety mode is disabled
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-27 preliminary?subject to change without notice 12.3.4.5 control descr iptor l0_5 register figure 12-8 represents the control descriptor l0_5 regist er. this register sets the maximum chroma keying values for rgb. refer to section 12.4.5.5, alpha and chroma-key blending,? for a description of chroma keying. 4?11 trans transparency level. specifies the alpha value for the layer. this value may be used by the blending engine to blend pixels on this layer. value can vary between 0-255 where 0 is completely transparent and 255 is completely opaque. 12?15 bpp bits per pixel 4?b0000 = 1 bpp 4?b0001 = 2 bpp 4?b0010 = 4 bpp 4?b0011 = 8 bpp 4?b0100 = 16 bpp (rgb565) 4?b0101 = 24 bpp 4?b0110 = 32 bpp (argb8888) 4?b0111 = transparency mode 4 bpp 4?b1000 = transparency mode 8bpp 4?b1001 = luminance offset mode 4 bpp 4?b1010 = luminance offset mode 8 bpp 4?b1011 = 16 bpp (argb1555) 4?b1100 = 16 bpp (argb4444) 4?b1101-1111 = reserved 17?27 luoffs look up table offset. value gives the offset to t he start address of the clut or tile (when used in internal tile mode) in the clut/tile ram. 29 bb chroma keying 1?b1: on 1?b0: off 30?31 ab alpha blending 2?b00: no alpha blending 2?b01: blend only the pixels selected by chroma keying in case bb=1?b1 2?b10: blend the whole frame 2?b11: same functionality as 2?b00. table 12-9. ctrldescl0_4 field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 12-28 freescale semiconductor preliminary?subject to change without notice figure 12-8. ctrldescl0_5 register 12.3.4.6 control descr iptor l0_6 register figure 12-9 represents the control descri ptor l0_6 register. this regist er sets the minimum chroma keying values for rgb. refer to section 12.4.5.5, alpha and chroma-key blending,? for a description of chroma keying. offset: 0x010 (ctrldescl0_5) 0x02c (ctrldescl1_5) 0x048 (ctrldescl2_5) 0x064 (ctrldescl3_5) 0x080 (ctrldescl4_5) 0x09c (ctrldescl5_5) 0x0b8 (ctrldescl6_5) 0x0d4 (ctrldescl7_5) 0x0f0 (ctrldescl8_5) 0x10c (ctrldescl9_5) 0x128 (ctrldescl10_5) 0x144 (ctrldescl11_5) 0x160 (ctrldescl12_5) 0x17c (ctrldescl13_5) 0x198 (ctrldescl14_5) 0x1b4 (ctrldescl15_5) access: user read/write 0123456789101112131415 r00000000 ckmax_r w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ckmax_g ckmax_b w reset0000000000000000 figure 5. table 12-10. ctrldescl0_5 field descriptions field description 8?15 ckmax_r chroma keying max red component 16?23 ckmax_g chroma keying max green component 24?31 ckmax_b chroma keying max blue component
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-29 preliminary?subject to change without notice figure 12-9. ctrldescl0_6 register offset: 0x014 (ctrldescl0_6) 0x030 (ctrldescl1_6) 0x04c (ctrldescl2_6) 0x068 (ctrldescl3_6) 0x084 (ctrldescl4_6) 0x0a0 (ctrldescl5_6) 0x0bc (ctrldescl6_6) 0x0d8 (ctrldescl7_6) 0x0f4 (ctrldescl8_6) 0x110 (ctrldescl9_6) 0x12c (ctrldescl10_6) 0x148 (ctrldescl11_6) 0x164 (ctrldescl12_6) 0x180 (ctrldescl13_6) 0x198 (ctrldescl14_6) 0x1b8 (ctrldescl15_6) access: user read/write 0123456789101112131415 r00000000 ckmin_r w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ckmin_g ckmin_b w reset0000000000000000 figure 6. table 12-11. ctrldescl0_6 field descriptions field description 8?15 ckmin_r chroma keying minimum red component 16?23 ckmin_g chroma keying minimum green component 24?31 ckmin_b chroma keying minimum blue component
pxd10 microcontroller reference manual, rev. 1 12-30 freescale semiconductor preliminary?subject to change without notice 12.3.4.7 control descr iptor l0_7 register figure 12-10 represents the control descriptor l0_7 register. figure 12-10. control descriptor l0_7 register for the other 16 layers, the control de scriptor register set is identical. 12.3.4.8 control descriptor cursor 1 register (ctrldesccursor_1) figure 12-11 represents the control desc riptor cursor 1 register. offset: 0x018 (ctrldescl0_7) 0x034 (ctrldescl1_7) 0x050 (ctrldescl2_7) 0x06c (ctrldescl3_7) 0x088 (ctrldescl4_7) 0x094 (ctrldescl5_7) 0x0c0 (ctrldescl6_7) 0x0dc (ctrldescl7_7) 0x0f8 (ctrldescl8_7) 0x114 (ctrldescl9_7 0x130 (ctrldescl10_7) 0x14c (ctrldescl11_7) 0x168 (ctrldescl12_7) 0x184 (ctrldescl13_7) 0x19c (ctrldescl14_7) 0x1bc (ctrldescl15_7) access: user read/write 0123456789101112131415 r000000 tile_ver_size w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 tile_hor_size w reset0000000000000000 figure 7. table 12-12. control descriptor l0_7 register field description 6?15 tile_ver_size height of the tile (in pixels) 24?31 tile_hor_size width of the tile (in multiples of 16 pixels)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-31 preliminary?subject to change without notice figure 12-11. control descriptor cursor 1 register (ctrldesccursor_1) 12.3.4.9 control descriptor cursor 2 register (ctrldesccursor_2) figure 12-12 represents the control desc riptor cursor 2 register. figure 12-12. control descriptor cursor 2 register (ctrldesccursor_2) offset: 0x1c0 access: user read/write 0123456789101112131415 r000000 height w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 width w reset0000000000000000 figure 8. table 12-13. ctrldesccursor_1 field descriptions field description 6?15 height height of the cursor in pixels 22?31 width width of the cursor in pixels offset: 0x1c4 access: user read/write 0123456789101112131415 r000000 posy w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 posx w reset0000000000000000 figure 9.
pxd10 microcontroller reference manual, rev. 1 12-32 freescale semiconductor preliminary?subject to change without notice 12.3.4.10 control descriptor cursor 3 register (ctrldesccursor_3) figure 12-13 represents the control desc riptor cursor 3 register. figure 12-13. control descriptor cursor 3 register (ctrldesccursor_3) 12.3.4.11 control descriptor cursor 4 register (ctrldesccursor_4) figure 12-14 represents the control desc riptor cursor 4 register. table 12-14. ctrldesccursor_2 field descriptions field description 6?15 posy y position of the cursor in pixels 22?31 posx x position of the cursor in pixels offset: 0x1c8 access: user read/write 0123456789101112131415 r cur _en default_cursor_color[0:8] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r default_cursor_color[9:24] w reset0000000000000000 figure 10. table 12-15. control descriptor cursor_3 field descriptions field description 0 cur_en cursor enable signal 1?b1: enable the cursor 1?b0: cursor is disabled 8?31 default_curso r_color default pixel color value for the cursor. in the dcu, the pixel value for the cursor is fixed for a particular frame.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-33 preliminary?subject to change without notice figure 12-14. control descriptor cursor 4 register (ctrldesccursor_4) 12.3.4.12 dcu mode register (dcu_mode) figure 12-15 represents the dcu_mode regi ster.this register se ts the mode in which dcu is operating. offset: 0x1cc access: user read/write 0123456789101112131415 r00000000 hwc_blink_off w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 en_blink hwc_blink_on w reset0000000000000000 figure 11. table 12-16. ctrldesccursor_4 field descriptions field description 8?15 hwc_blink_off hwc blink register. loads the counter value (number of frames) for which the cursor will remain turned off. 23 en_blink enable the cursor blink mode. 1?b1:enable the blink mode 1?b0:disable the blink mode 24?31 hwc_blink_on hwc blink register. loads the counter value (number of frames) for which the cursor will remain turned on.
pxd10 microcontroller reference manual, rev. 1 12-34 freescale semiconductor preliminary?subject to change without notice figure 12-15. dcu mode register (dcu_mode) offset: 0x1d0 access: user read/write 0123456789101112131415 r dcu_sw_reset 00000000 blend_iter pdi_sync_lock w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pdi_interpol_en raster_en pdi_en pdi_byte_rev pdi_de_mode pdi_narrow_mode pdi_mode pdi_slave_mode tag_en sig_en pdi_sync 0 en_gamma dcu_mode w reset1000000000000000 figure 12. table 12-17. dcu_mode field descriptions field description 0 dcu_sw_reset used to clear all the registers to reset state 1?b1:all the dcu registers are put in reset state 9?11 blend_iter defines the number of planes used for blending. 3?d4:four-plane blending 3?d3:three-plane blending 3?d2:two-plane blending if any other value is written, two-plane blending is selected and blend_iter is set to 2. 12?15 pdi_sync_lock defines the number of frames which should be received by the pdi validation state machine before it locks and sets the pdi_lock_det bit in the pdi status register (see section 12.3.4.26, pdi status register? ). 16 pdi_interpol_e n control bit to decide whether the conversion fr om ycbcr 4:2:2 to 4:4:4 needs to be done using interpolation or chroma value is same for two pixels 1?b1:interpolation is enabled. 1?b0:chroma value is same for two pixels 17 raster_en enables raster scanning of pixel data including the vsync and hsync signals and the pixel data. for correct operation raster_en shou ld only be changed when dcu_mode is configured to off. changes to this bit take ef fect after the completion of the current frame. 1?b1: enabled 1?b0:disabled
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-35 preliminary?subject to change without notice 12.3.4.13 bgnd register figure 12-16 represents the bgnd register. 18 pdi_en enables the pdi 1?b1: enabled 1?b0:disabled 19 pdi_byte_rev controls the byte ordering in narrow mode 1?b0:lsb is followed by msb data 1?b1:msb is followed by lsb data 20 pdi_de_mode enables the pdi data enable mode. here data enable is treated as an input. 1?b0: value on data enable signal is ignored 1?b1: data enable signal must be present in incoming stream 21 pdi_narrow_m ode enables the pdi narrow mode (refer to section 12.8.2.4, normal and narrow mode? ) 1?b0: narrow mode is disabled 1?b1: narrow mode is enabled 22?23 pdi_mode defines the different modes in which pdi is operating 2?b00: 8 bit monochrome data input 2?b01: 16 bit rgb 565 format 2?b10:18 bit rgb 666 data format. 2?b11:ycbcr data in 4:2:2 format. 24 pdi_slave_mod e enables pdi slave mode 1?b0:disabled 1?b1:enabled 25 tag _ e n enables the calculation of crc only on the safety layers 1?b0: crc calculated over the whole area of in terest (area of interest given by sig_desc registers) 1?b1: calculates crc only on safety enabled layers 26 sig_en enables the signature calculator block 1?b0: signature calculator is disabled 1?b1: signature calculator is enabled 27 pdi_sync decides whether the pdi uses external or internal synchronization. 1?b0: external synchronization. the pdi receives the sync (hsync,vsync) signals from external source. 1?b1: internal synchronization. pdi extracts the sync information from the digital data. 29 en_gamma enables/disables the gamma correction 1?b0: gamma correction is disabled 1?b1: gamma correction is enabled 30?31 dcu_mode dcu operating mode and pixel clock enable 2?b00: dcu off 2?b01: normal mode. pixel clock active and panel content controlled by layer configuration 2?b10: test mode. panel content fetched from clut/tile memory 2?b11: color bar generation. pixel clock acti ve and panel content controlled by color bar registers. table 12-17. dcu_mode field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 12-36 freescale semiconductor preliminary?subject to change without notice figure 12-16. bgnd register 12.3.4.14 disp_size register figure 12-17 represents the disp_size register figure 12-17. disp_size register offset: 0x1d4 access: user read/write 0123456789101112131415 r00000000 bgnd_r w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bgnd_g bgnd_b w reset0000000000000000 figure 13. table 12-18. bgnd field descriptions field description 8?15 bgnd_r red component of the default color displayed in the sectors where no layer is active 16?23 bgnd_g green component of the default color displa yed in the sectors where no layer is active 24?31 bgnd_b blue component of the default color displayed in the sectors where no layer is active offset: 0x1d8 access: user read/write 0123456789101112131415 r000000 delta_y w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 delta_x w reset0000000000000000 figure 14.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-37 preliminary?subject to change without notice 12.3.4.15 hsyn_para register figure 12-18 represents the hsyn_para register. hsyn_para register sets timing parameters related to the horizontal synchronization si gnal generation. the fields fp_h, bp_h, and pw_h stand for hsync signal front-porch, back-porch, a nd active pulse width, respectively. figure 12-18. hsyn_para register 12.3.4.16 vsyn_para register figure 12-19 represents the vsyn_para register. vsyn_para register sets timing parameters related to the vertical synchronization signal generation. th e fields fp_v, bp_v, and pw_v stand for vsync signal front-porch, back-porch, a nd active pulse width, respectively. table 12-19. disp_size field descriptions field description 6?15 delta_y sets the display size vertical resolution (in pixels) 24?31 delta_x sets the display size horizontal resolution (in multiples of 16 pixels) offset: 0x1dc access: user read/write 0123456789101112131415 r0 bp_h 00 pw_h[0:3] w reset0000000011000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pw_h[4:8] 00 fp_h w reset0001100000000011 figure 15. table 12-20. hsyn_para field descriptions field description 1?9 bp_h hsync back-porch pulse width (in pixel clock cycl es). pulse width has a minimum value of 1. 12?20 pw_h hsync active pulse width (in pixel clock cycles). 23?31 fp_h hsync front-porch pulse width (in pixel clock c ycles). pulse width has a minimum value of 1.
pxd10 microcontroller reference manual, rev. 1 12-38 freescale semiconductor preliminary?subject to change without notice figure 12-19. vsyn_para register 12.3.4.17 syn_pol register figure 12-20 represents the syn_pol re gister. syn_pol register se lects polarity for corresponding synchronize signals (hsync, vsync, csync), and controls the bypass of hsync or vsync with csync signal. offset: 0x1e0 access: user read/write 0123456789101112131415 r0 bp_v 00 pw_v[0:3] w reset0000000011000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pw_v[4:8] 00 fp_v w reset0001100000000011 figure 16. table 12-21. vsyn_para field descriptions field description 1?9 bp_v vsync back-porch pulse width (in horizontal line cycles). pulse width has a minimum value of 1. 12?20 pw_v vsync active pulse width (in horizontal line cycles). 23?31 fp_v vsync front-porch pulse width (i n horizontal line cycles). pulse width has a minimum value of 1.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-39 preliminary?subject to change without notice figure 12-20. syn_pol register offset: 0x1e4 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 inv_pdi_de inv_pdi_hs inv_pdi_vs inv_pdi_clk inv_pxck neg bp_vs bp_hs inv_cs inv_vs inv_hs w reset0000000000000000 figure 17. table 12-22. syn_pol field descriptions field description 21 inv_pdi_de polarity change of pdi input data enable. 1?b0: de is active high 1?b1: de is active low 22 inv_pdi_hs polarity change of pdi input hsync. 1?b0: hsync is active high 1?b1: hsync is active low 23 inv_pdi_vs polarity change of pdi input vsync. 1?b0: vsync is active high 1?b1: vsync is active low 24 inv_pdi_clk polarity change of pdi input clock. 1?b0: dcu samples data on the rising edge 1?b1: dcu samples data on the falling edge 25 inv_pxck polarity change of pixel clock. 1?b0: display samples data on the falling edge 1?b1: display samples data on the rising edge 26 neg indicates if value at the output (pixel data output) needs to be negated. 1?b0: output is to remain same 1?b1: output to be negated 27 bp_vs bypass vertical synchronize signal (internal pin muxing). 1?b0: do not bypass vsync signal output 1 ?b1: csync bypass vsync signal, output csync in stead of vsync 28 bp_hs bypass horizontal synchronize signal (internal pin muxing). 1?b0: do not bypass hsync signal output 1?b1: csync bypass hsync signal, output csync instead of hsync
pxd10 microcontroller reference manual, rev. 1 12-40 freescale semiconductor preliminary?subject to change without notice 12.3.4.18 threshold register figure 12-21 represents the th reshold register. figure 12-21. threshold register 12.3.4.19 interrupt status register (int_status) figure 12-22 indicates the interrupt status register. see section 12.5.4, interrupt generation ,? for a description of how the dcu collects interr upt events into different source groups. 29 inv_cs invert composite synchronize signal. 1?b0: not invert csync signal, active high 1 ?b1: invert csync signal, active low 30 inv_vs invert vertical synchronize signal 1?b0: not invert vsync signal, active high 1 ?b1: invert vsync signal, active low 31 inv_hs invert horizontal synchronize signal. 1?b0: not invert hsync signal, active high 1?b1: invert hsync signal, active low offset: 0x1e8 access: user read/write 0123456789101112131415 r000000 ls_bf_vs w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r out_buf_high out_buf_low w reset0111100000001010 figure 18. table 12-23. threshold register field descriptions field description 6?15 ls_bf_vs lines before vsync threshold value. the ls_bf_vs status flag (in int_status) is set this number of lines before the vsync signal is asserted. 16?23 out_buf_high output buffer high threshold (in pixels). when t he output buffer exceeds this value the datapath clock is suspended. 24?31 out_buf_low output buffer filling low threshold (in pixels ).this value is used to generate the underrun exception (undrun in int_status). table 12-22. syn_pol field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-41 preliminary?subject to change without notice figure 12-22. interrupt status register (int_status) offset: 0x1ec access: user read/write 0123456789101112131415 r 000000000000 p4_fifo_hi_flag p4_fifo_lo_flag p3_fifo_hi_flag p3_fifo_lo_flag w w1cw1cw1cw1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 dma_trans_finish 00 ipm_error prog_end p2_fifo_hi_flag p2_fifo_lo_flag p1_fifo_hi_flag p1_fifo_lo_flag crc_overflow crc_ready vs_blank ls_bf_vs undrun vsync w w1c w1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1c reset0000000000000000 figure 19. table 12-24. int_status field descriptions field description 12 p4_fifo_hi_flag interrupt signal to indicate that high thresh old has been reached for plane 4(fg2plane) input buffer 13 p4_fifo_lo_flag interrupt signal to indicate that low threshold has been reached for plane 4(fg2plane) input buffer 14 p3_fifo_hi_flag interrupt signal to indicate that high thresh old has been reached for plane 3(fg1plane) input buffer 15 p3_fifo_lo_flag interrupt signal to indicate that low threshold has been reached for plane 3(fg1plane) input buffer 17 dma_trans_finis h interrupt signal which indicates that the dcu dm a has fetched the last pixel of data from the memory 20 ipm_error interrupt signal which indicates that an error has occured in the magenta line transaction 21 prog_end interrupt signal which indicates that the duratio n for programming of dcu registers and internal memories is finished
pxd10 microcontroller reference manual, rev. 1 12-42 freescale semiconductor preliminary?subject to change without notice 12.3.4.20 interrupt mask register (int_mask) figure 12-23 represents the interrupt mask register.this register enables or ma sks corresponding interrupt. 22 p2_fifo_hi_flag interrupt signal to indicate that high threshol d has been reached for plane 2 (fgplane) input buffer 23 p2_fifo_lo_flag interrupt signal to indicate that low threshold has been reached for plane 2 (fgplane) input buffer 24 p1_fifo_hi_flag interrupt signal to indicate that high threshold has been reached for plane 1 (bgplane) input buffer 25 p1_fifo_lo_flag interrupt signal to indicate that low threshold has been reached for plane 1 (bgplane) input buffer 26 crc_overflow interrupt signal to indicate that crc_ready has not been serviced and crc has been calculated for the next frame 27 crc_ready interrupt signal to indicate crc calculation is done and ready to be compared with precomputed crc value by the software 28 vs_blank interrupt signal to indicate vertical blanking peri od. this is the period in which all the registers that affect the visible state of the layers need to be latched. this is needed so that cpu writes to the register while the display is be ing updated does not cause any errors. 29 ls_bf_vs lines before vsync interrupt. it is generated threshold ls_bf_vs number of lines ahead of the vertical front porch (fp_v) if enabled. th e cpu can program the registers after ls_bf_vs interrupt. 30 undrun under run exception interrupt. asserted when display needs data and output buffer filling is lower than or equal to the out_buf_low threshol d. interrupt is cleared when the data in the output buffer is greater than thres hold and cpu writes 1 to this bit. 31 vsync vertical synchronize interrupt. if enabled, an in terrupt is generated at the beginning of a frame. table 12-24. int_status field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-43 preliminary?subject to change without notice figure 12-23. interrupt mask register (int_mask) offset: 0x1f0 access: user read/write 0123456789101112131415 r000000000000 m_p4_fifo_hi_flag m_p4_fifo_lo_flag m_p3_fifo_hi_flag m_p3_fifo_lo_flag w reset0000000000001111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 m_dma_trans_finish 00 m_ipm_error m_prog_end m_p2_fifo_hi_flag m_p2_fifo_lo_flag m_p1_fifo_hi_flag m_p1_fifo_lo_flag m_crc_overflow m_crc_ready m_vs_blank m_ls_bf_vs m_undrun m_vsync w reset0100111111111111 figure 20. table 12-25. int_mask field descriptions field description 12 m_p4_fifo_hi_flag mask the interrupt 1?b1: interrupt is masked 1?b0: not masked 13 m_p4_fifo_lo_flag mask the interrupt 1?b1: interrupt is masked 1?b0: not masked 14 m_p3_fifo_hi_flag mask the interrupt 1?b1: interrupt is masked 1?b0: not masked 15 m_p3_fifo_lo_flag mask the interrupt 1?b1: interrupt is masked 1?b0: not masked 17 m_dma_trans_finis h mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 20 m_ipm_error mask the interrupt 1?b1: interrupt is masked 1?b0:not masked
pxd10 microcontroller reference manual, rev. 1 12-44 freescale semiconductor preliminary?subject to change without notice 12.3.4.21 colbar registers the colbar registers are used to generate color bars in functional test mode. ei ght different pixel values are taken as input data, to disp lay 8 color bars on the display. 21 m_prog_end mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 22 m_p2_fifo_hi_flag mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 23 m_p2_fifo_lo_flag mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 24 m_p1_fifo_hi_flag mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 25 m_p1_fifo_lo_flag mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 26 m_crc_overflow mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 27 m_crc_ready mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 28 m_vs_blank mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 29 m_ls_bf_vs mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 30 m_undrun mask the interrupt 1?b1: interrupt is masked 1?b0:not masked 31 m_vsync mask the interrupt 1?b1: interrupt is masked 1?b0:not masked table 12-26. colbar_ n register field descriptions field name description colbar_ n _r red component value table 12-25. int_mask field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-45 preliminary?subject to change without notice 12.3.4.21.1 colbar_1 register figure 12-24. colbar_1 register (black) 12.3.4.21.2 colbar_2 register figure 12-25. colbar_2 register (blue) colbar_ n _g green component value colbar_ n _b blue component value offset: 0x1f4 access: user read/write 0123456789101112131415 r11111111 colbar_1_r w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_1_g colbar_1_b w reset0000000000000000 figure 21. offset: 0x1f8 access: user read/write 0123456789101112131415 r11111111 colbar_2_r w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_2_g colbar_2_b w reset0000000011111111 figure 22. table 12-26. colbar_ n register field descriptions field name description
pxd10 microcontroller reference manual, rev. 1 12-46 freescale semiconductor preliminary?subject to change without notice 12.3.4.21.3 colbar_3 register figure 12-26. colbar_3 register (cyan) 12.3.4.21.4 colbar_4 register figure 12-27. colbar_4 register (green) offset: 0x1fc access: user read/write 0123456789101112131415 r11111111 colbar_3_r w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_3_g colbar_3_b w reset1111111111111111 figure 23. offset: 0x200 access: user read/write 0123456789101112131415 r11111111 colbar_4_r w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_4_g colbar_4_b w reset1111111100000000 figure 24.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-47 preliminary?subject to change without notice 12.3.4.21.5 colbar_5 register figure 12-28. colbar_5 register (yellow) 12.3.4.21.6 colbar_6 register figure 12-29. colbar_6 register (red) offset: 0x204 access: user read/write 0123456789101112131415 r11111111 colbar_5_r w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_5_g colbar_5_b w reset1111111100000000 figure 25. offset: 0x208 access: user read/write 0123456789101112131415 r11111111 colbar_6_r w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_6_g colbar_6_b w reset0000000000000000 figure 26.
pxd10 microcontroller reference manual, rev. 1 12-48 freescale semiconductor preliminary?subject to change without notice 12.3.4.21.7 colbar_7 register figure 12-30. colbar_7 register (purple) 12.3.4.21.8 colbar_8 register figure 12-31. colbar_8 register (white) 12.3.4.22 divide ratio register (div_ratio) figure 12-32 shows the divide ratio register. offset: 0x20c access: user read/write 0123456789101112131415 r11111111 colbar_7_r w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_7_g colbar_7_b w reset0000000011111111 figure 27. offset: 0x210 access: user read/write 0123456789101112131415 r11111111 colbar_8_r w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r colbar_8_g colbar_8_b w reset1111111111111111 figure 28.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-49 preliminary?subject to change without notice figure 12-32. divide ratio register (div_ratio) 12.3.4.23 sign_calc_1 register figure 12-33 presents the register for vertical/horiz ontal size of the ar ea for crc calculation. figure 12-33. sign _calc_1 register offset: 0x214 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 div_ratio w reset0000000000011111 figure 29. table 12-27. div_ratio field descriptions field description 24?31 div_ratio specifies the divide value for the input clock. used to generate the pixel clock to support different types of displays. to divide by n, set the div_ratio to (n-1). offset: 0x218 access: user read/write 0123456789101112131415 r000000 sig_ver_size w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 sig_hor_size w reset0000000000000000 figure 30.
pxd10 microcontroller reference manual, rev. 1 12-50 freescale semiconductor preliminary?subject to change without notice 12.3.4.24 sign_calc_2 register figure 12-34 represents the register fo r position of the window of interest for crc calculation. figure 12-34. sign _calc_2 register 12.3.4.25 crc_val register figure 12-35 represents the register presenting the crc value to the software for comparison. table 12-28. sign_calc_1 field descriptions field description 6?15 sig_ver_size vertical size of the window of interest of pixels for crc calculation (in pixels) 22?31 sig_hor_size horizontal size of window of interest of pixels for crc calculations (in pixels) offset: 0x21c access: user read/write 0123456789101112131415 r000000 sig_ver_pos w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 sig_hor_pos w reset0000000000000000 figure 31. table 12-29. sign_calc_2 field descriptions field description 6?15 sig_ver_pos vertical position of the window of interest of pixels for crc calculation (in pixels) 22?31 sig_hor_pos horizontal position of window of interest of pixels for crc calculation (in pixels)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-51 preliminary?subject to change without notice figure 12-35. crc_val register 12.3.4.26 pdi status register figure 12-36 represents the pdi status register. figure 12-36. pdi status register offset: 0x220 access: user read/write 0123456789101112131415 r crc_val[0:15] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r crc_val[16:31] w reset0000000000000000 figure 32. table 12-30. crc_val field descriptions field description 0?31 crc_val crc value calculated for safety enabled layers to be presented to the software for comparison. offset: 0x224 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 pdi_blanking_err pdi_ecc_err2 pdi_ecc_err1 pdi_lock_lost pdi_lock_det pdi_vsync_det pdi_hsync_det pdi_de_det pdi_clk_lost pdi_clk_det w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 33.
pxd10 microcontroller reference manual, rev. 1 12-52 freescale semiconductor preliminary?subject to change without notice 12.3.4.27 pdi status mask register figure 12-37 represents the mask pdi status register table 12-31. pdi status register field descriptions field description 22 pdi_blanking_err status bit to inform the software that 80h,10h sequence is not present during the blanking period in internal sync mode. 1?b1:correct data sequence not present in blanking period 1?b0:correct data sequence present in blanking period 23 pdi_ecc_err2 status bit to inform the software about multibit bit error that is detected. 1?b1: multibit ecc error detected 1?b0: multibit ecc error is not detected 24 pdi_ecc_err1 status bit to inform the software about one bit error is detected. 1?b1: one bit ecc error detected 1?b0: one bit ecc error is not detected 25 pdi_lock_lost status bit to inform the software that frame lock is lost. 1?b1: frame lock is lost 1?b0: frame is locked 26 pdi_lock_det status bit to inform the software pdi is frame locked to the camera interface. 1?b1: frame lock is detected 1?b0: waiting for frame to lock 27 pdi_vsync_det status bit to inform the software that vsyn c for the camera data has been detected. 1?b1: pdi_vsync is detected 1?b0: pdi_vsync not detected 28 pdi_hsync_det status bit to inform the software that hsync for the camera data has been detected. 1?b1: pdi_hsync is detected 1?b0: pdi_hsync not detected 29 pdi_de_det status bit to inform the software that data enable for the camera data has been detected. 1?b1: pdi_de is detected 1?b0: pdi_de not detected 30 pdi_clk_lost status bit to inform the software that pdi_clk is lost 1?b1: pdi_clk is lost 1?b0: pdi_clk is present 31 pdi_clk_det status bit to inform the software that clock for the camera data has been detected. 1?b1: pdi_clk is detected 1?b0: pdi_clk not detected
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-53 preliminary?subject to change without notice figure 12-37. pdi status mask register offset: 0x228 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 m_pdi_blanking_err m_pdi_ecc_err2 m_pdi_ecc_err1 m_pdi_lock_lost m_pdi_lock_det m_pdi_vsync_det m_pdi_hsync_det m_pdi_de_det m_pdi_clk_lost m_pdi_clk_det w reset0000001111111111 figure 34. table 12-32. pdi status mask register field descriptions field description 22 m_pdi_blanking_er r mask the pdi_blanking_err bit 1?b1: mask the pdi_blank_err interrupt 1?b0: do not mask he pdi_blank_err interrupt 23 m_pdi_ecc_err2 mask the pdi_ecc_err2 bit 1?b1: mask the pdi_ecc_err2 interrupt 1?b0: do not mask he pdi_ecc_err2 interrupt 24 m_pdi_ecc_err1 mask the pdi_ecc_err1 bit 1?b1: mask the pdi_ecc_err1 interrupt 1?b0: do not mask he pdi_ecc_err1 interrupt 25 m_pdi_lock_lost mask the pdi_lock_lost bit 1?b1: mask the pdi_lock_lost interrupt 1?b0: do not mask he pdi_lock_lost interrupt 26 m_pdi_lock_det mask the pdi_lock_det bit 1?b1: mask the pdi_lock_det interrupt 1?b0: do not mask he pdi_lock_det interrupt 27 m_pdi_vsync_det mask the pdi_vsync_det bit 1?b1: mask the pd i_vsync interrupt 1?b0: do not mask he pdi_vsync interrupt 28 m_pdi_hsync_det mask the pdi_hsync_det bit 1?b1: mask the pdi_hsync interrupt 1?b0: do not mask he pdi_hsync interrupt 29 m_pdi_de_det mask the pdi_de_det bit 1?b1: mask the pdi_de_det interrupt 1?b0: do not mask he pdi_de_det interrupt
pxd10 microcontroller reference manual, rev. 1 12-54 freescale semiconductor preliminary?subject to change without notice 12.3.4.28 parr_err status register figure 12-38 shows the parameter error status register. an error in a layer can occur under the following conditions: a) number of pixels in a tile > maximum tile memory size in case of tile bandwidth optimized mode (when in internal memory mode) b) there is an automatic error checking mechan ism when a layer is enabled that detects a non-valid horizontal size and co lor format combination. see section 12.4.5.3, layer size and positioning,? for details. these errors are grouped into a single bit error for each layer. the paramete r error specific to each layer is signalled only when the layer is enabled. disp_err occurs when the size of di splay (height or width) is set to zero or when the pulse width of hsync/vsync is pr ogrammed as zero. sig_err occurs when the area of interest for cal culating crc value is progr ammed with values which are outside the display. hwc_err occurs if size of cursor program med is greater than memory size(256x32).see section 12.4.6, hardware cursor,? for further details on how cursor can be programmed. 30 m_pdi_clk_lost mask the pdi_clk_lost bit 1?b1: mask the pdi_clk_lost interrupt 1?b0: do not mask he pdi_clk_lost interrupt 31 m_pdi_clk_det mask the pdi_clk_det bit 1?b1: mask the pdi_clk interrupt 1?b0: do not mask he pdi_clk interrupt table 12-32. pdi status mask register field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-55 preliminary?subject to change without notice figure 12-38. parameter error status register offset: 0x22c access: user read/write 0123456789101112131415 r 0000000000000 hwc_err sig_err disp_err w w1c w1c w1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r l15_parr_err l14_parr_err l13_parr_err l12_parr_err l11_parr_err l10_parr_err l9_parr_err l8_parr_err l7_parr_err l6_parr_err l5_parr_err l4_parr_err l3_parr_err l2_parr_err l1_parr_err l0_parr_err ww1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1cw1c reset0000000000000000 figure 35. table 12-33. parameter error status register field descriptions field description 13 hwc_err interrupt signal to indicate hwc error. this can occur if hwc position is out of display area or cursor memory is bigger than the hwc size. when this occurs, the hwc is disabled. 14 sig_err interrupt occurs whenever the area of interest specified by sig_calc r egister is outside the display size. 1?b0: sig_err is not set 1?b1: sig_err is set 15 disp_err interrupt occurs whenever width and height of disp lay, pulse width (both vertical and horizontal sync) value is 0. 1?b0: disp_err is not set 1?b1: disp_err is set 16 l15_parr_err interrupt occurs whenever there is an error in layer 15. 1?b0: parameter error is not set 1?b1: parameter error is set 17 l14_parr_err interrupt occurs whenever there is an error in layer 14. 1?b0: parameter error is not set 1?b1: parameter error is set 18 l13_parr_err interrupt occurs whenever there is an error in layer 13. 1?b0: parameter error is not set 1?b1: parameter error is set 19 l12_parr_err interrupt occurs whenever there is an error in layer 12. 1?b0: parameter error is not set 1?b1: parameter error is set
pxd10 microcontroller reference manual, rev. 1 12-56 freescale semiconductor preliminary?subject to change without notice 12.3.4.29 mask parr_err status register figure 12-39 shows the mask regi ster for parameter error status register. 20 l11_parr_err interrupt occurs whenever there is an error in layer 11. 1?b0: parameter error is not set 1?b1: parameter error is set 21 l10_parr_err interrupt occurs whenever there is an error in layer 10. 1?b0: parameter error is not set 1?b1: parameter error is set 22 l9_parr_err interrupt occurs whenever there is an error in layer 9 1?b0: parameter error is not set 1?b1: parameter error is set 23 l08_parr_err interrupt occurs whenever there is an error in layer 8. 1?b0: parameter error is not set 1?b1: parameter error is set 24 l7_parr_err interrupt occurs whenever there is an error in layer 7 1?b0: parameter error is not set 1?b1: parameter error is set 25 l6_parr_err interrupt occurs whenever there is an error in layer 6. 1?b0: parameter error is not set 1?b1: parameter error is set 26 l5_parr_err interrupt occurs whenever there is an error in layer 5. 1?b0: parameter error is not set 1?b1: parameter error is set 27 l4_parr_err interrupt occurs whenever there is an error in layer 4 1?b0: parameter error is not set 1?b1: parameter error is set 28 l3_parr_err interrupt occurs whenever there is an error in layer 3. 1?b0: parameter error is not set 1?b1: parameter error is set 29 l2_parr_err interrupt occurs whenever there is an error in layer 2. 1?b0: parameter error is not set 1?b1: parameter error is set 30 l1_parr_err interrupt occurs whenever there is an error in layer 1. 1?b0: parameter error is not set 1?b1: parameter error is set 31 l0_parr_err interrupt occurs whenever there is an error in layer 0. 1?b0: parameter error is not set 1?b1: parameter error is set table 12-33. parameter error status register field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-57 preliminary?subject to change without notice figure 12-39. mask parame ter error status register offset: 0x230 access: user read/write 0123456789101112131415 r0000000000000 m_hwc_err m_sig_err m_disp_err w reset0000000000000111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m_l15_parr_err m_l14_parr_err m_l13_parr_err m_l12_parr_err m_l11_parr_err m_l10_parr_err m_l9_parr_err m_l8_parr_err m_l7_parr_err m_l6_parr_err m_l5_parr_err m_l4_parr_err m_l3_parr_err m_l2_parr_err m_l1_parr_err m_l0_parr_err w reset1111111111111111 figure 36. table 12-34. mask parameter error status register field descriptions field description 13 m_hwc_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 14 m_sig_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 15 m_disp_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 16 m_l15_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 17 m_l14_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 18 m_l13_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 19 m_l12_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt
pxd10 microcontroller reference manual, rev. 1 12-58 freescale semiconductor preliminary?subject to change without notice 12.3.4.30 threshold_inp_buf_1 register figure 12-40 shows the threshold re gister for input buffer. 20 m_l11_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 21 m_l10_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 22 m_l9_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 23 m_l8_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 24 m_l7_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 25 m_l6_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 26 m_l5_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 27 m_l4_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 28 m_l3_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 29 m_l2_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 30 m_l1_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt 31 m_l0_parr_err mask the interrupt 1?b1: mask the interrupt 1?b0: do not mask interrupt table 12-34. mask parameter error status register field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-59 preliminary?subject to change without notice figure 12-40. threshold input buffer 1 register (threshold_inp_buf_1) 12.3.4.31 threshold_inp_buf_2 register figure 12-41 represents the threshol d register for input buffer for plane 3 and plane 4. figure 12-41. threshold_inp_buf_2 register offset: 0x234 access: user read/write 0123456789101112131415 r inp_buf_p2_hi inp_buf_p2_lo w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inp_buf_p1_hi inp_buf_p1_lo w reset1111111100000000 figure 37. table 12-35. threshold_inp_buf_1 field descriptions field description 0?7 inp_buf_p2_hi high threshold for input buffer for blend stage 2. 8?15 inp_buf_p2_lo low threshold for input buffer for blend stage 2. 16?23 inp_buf_p1_hi high threshold for input buffer for blend stage 1 (background). 24?31 inp_buf_p1_lo low threshold for input buffer for blend stage 1 (background plane). offset: 0x238 access: user read/write 0123456789101112131415 r inp_buf_p4_hi inp_buf_p4_lo w reset1111111100000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inp_buf_p3_hi inp_buf_p3_lo w reset1111111100000000 figure 38.
pxd10 microcontroller reference manual, rev. 1 12-60 freescale semiconductor preliminary?subject to change without notice 12.3.4.32 luma component register figure 12-42 represents the luma component register. figure 12-42. luma component register 12.3.4.33 red chroma components figure 12-43 represents the red chro ma component register. table 12-36. threshold_inp_buf_2 field descriptions field description 0?7 inp_buf_p4_hi high threshold for input buffer for blend stage 4. 8?15 inp_buf_p4_lo low threshold for input buffer for blend stage 4. 16?23 inp_buf_p3_hi high threshold for input buffer for blend stage 3. 24?31 inp_buf_p3_lo low threshold for input buffer for blend stage 3. offset: 0x23c access: user read/write 0123456789101112131415 r y_red 0 y_green[0:4] w reset1001010100010010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r y_green[5:9] 0 y_blue w reset1010001001010100 figure 39. table 12-37. luma component register field descriptions field description 0?9 y_red luminance coefficient for red matrix 11?20 y_green luminance coefficient for green matrix 22?31 y_blue luminance coefficient for blue matrix
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-61 preliminary?subject to change without notice figure 12-43. red chroma component register 12.3.4.34 green chroma component register figure 12-44 represents the green chroma component register figure 12-44. green chroma component register offset: 0x240 access: user read/write 0123456789101112131415 r00000 cr_red w reset0000001100110001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_red w reset0000000000000000 figure 40. table 12-38. red chroma component register field descriptions field description 5?15 cr_red cr coefficient for red matrix 20?31 cb_green cb coefficient for red matrix offset: 0x244 access: user read/write 0123456789101112131415 r00000 cr_green w reset0000011001100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_green w reset0000111100111000 figure 41.
pxd10 microcontroller reference manual, rev. 1 12-62 freescale semiconductor preliminary?subject to change without notice 12.3.4.35 blue chroma component register figure 12-45 represents the blue ch roma component register. figure 12-45. blue chroma component register 12.3.4.36 crc_pos register figure 12-46 represents the crc_pos register. table 12-39. green chroma component register field descriptions field description 5?15 cr_green cr coefficient for green matrix 20?31 cb_green cb coefficient for green matrix offset: 0x248 access: user read/write 0123456789101112131415 r00000 cr_blue w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0 cb_blue w reset0000010000001001 figure 42. table 12-40. blue chroma component register field descriptions field description 5?15 cr_blue cr coefficient for blue matrix 20?31 cb_blue cb coefficient for blue matrix
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-63 preliminary?subject to change without notice figure 12-46. crc_pos register 12.3.4.37 fg0_fcolor register figure 12-47 represents the fg0_fcolor register. offset: 0x24c access: user read/write 0123456789101112131415 r crc_pos[0:15] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r crc_pos[16:31] w reset0000000000000000 figure 43. table 12-41. crc_pos field descriptions field description 0?31 crc_pos crc position value calculated for safety enabled layers to be presented to the software for comparison
pxd10 microcontroller reference manual, rev. 1 12-64 freescale semiconductor preliminary?subject to change without notice figure 12-47. fg0_fcolor register 12.3.4.38 fg0_bcolor figure 12-48 represents the fg0_bcolor register. offset: 0x250 (fg0_fcolor) 0x258 (fg1_fcolor) 0x260 (fg2_fcolor) 0x268 (fg3_fcolor) 0x270 (fg4_fcolor) 0x278 (fg5_fcolor)) 0x280 (fg6_fcolor) 0x288 (fg7_fcolor) 0x290 (fg8_fcolor) 0x298 (fg9_fcolor) 0x2a0 (fg10_fcolor) 0x2a8 (fg11_fcolor) 0x2b0 (fg12_fcolor) 0x2b8 (fg13_fcolor) 0x2c0 (fg14_fcolor) 0x2c8 (fg15_fcolor) access: user read/write 0123456789101112131415 r00000000 fg0_fcolor[0:7] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fg0_fcolor[8:23] w reset0000000000000000 figure 44. table 12-42. fg0_fcolor field descriptions field description 8?31 fg0_fcolor foreground color for layer fg0 for pre-blending engine
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-65 preliminary?subject to change without notice figure 12-48. fg0_bcolor register 12.3.4.39 global protection register figure 12-49 represents the global protection register. offset: 0x254 (fg0_bcolor) 0x25c (fg1_bcolor) 0x264 (fg2_bcolor) 0x26c (fg3_bcolor) 0x274 (fg4_bcolor) 0x27c (fg5_bcolor)) 0x284 (fg6_bcolor) 0x28c (fg7_bcolor) 0x294 (fg8_bcolor) 0x29c (fg9_bcolor) 0x2a4 (fg10_bcolor) 0x2ac (fg11_bcolor) 0x2b4 (fg12_bcolor) 0x2bc (fg13_bcolor) 0x2c4 (fg14_bcolor) 0x2cc (fg15_bcolor) access: user read/write 0123456789101112131415 r00000000 fg0_bcolor[0:7] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fg0_bcolor[8:23] w reset0000000000000000 figure 45. table 12-43. fg0_bcolor field descriptions field description 8?31 fg0_bcolor background color for layer fg0 for pre-blending engine
pxd10 microcontroller reference manual, rev. 1 12-66 freescale semiconductor preliminary?subject to change without notice figure 12-49. global protection register 12.3.4.40 soft lock bit register l0 figure 12-50 represents the soft lock bit register for la yer0. this is used to protect the 7 control descriptor layer re gisters for layer0. figure 12-50. soft lock register l0 offset: 0x300 access: user read/write 0123456789101112131415 r hlb 000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 46. table 12-44. global protection register field descriptions field description 0 hlb hard lock bit. this bit cannot be cleared once it is set by software. it can only be cleared by a system reset. 1?b1:all slb?s are write protected & cannot be modified 1?b0:all slb?s are accessible & can be modified offset: 0x304 access: user read/write 0123456789101112131415 r0 0 0 0 slb_l0_1 slb_l0_2 slb_l0_3 slb_l0_4 0000 slb_l0_5 slb_l0_6 slb_l0_7 0 w wen_lo_1 wen_lo_2 wen_lo_3 wen_lo_4 wen_lo_5 wen_lo_6 wen_lo_7 reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 47.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-67 preliminary?subject to change without notice table 12-45. soft lock register l0 field descriptions field description 0 wen_l0_1 write enable for soft lock bit slb_l0_1 1?b1: value is written to slb 1?b0: slb is not modified 1 wen_l0_2 write enable for soft lock bit slb_l0_2 1?b1: value is written to slb 1?b0: slb is not modified 2 wen_l0_3 write enable for soft lock bit slb_l0_3 1?b1: value is written to slb 1?b0: slb is not modified 3 wen_l0_4 write enable for soft lock bit slb_l0_4 1?b1: value is written to slb 1?b0: slb is not modified 4 slb_l0_1 soft lock bit for control desc l0_1 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 5 slb_l0_2 soft lock bit for control desc l0_2 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 6 slb_l0_3 soft lock bit for control desc l0_3 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 7 slb_l0_4 soft lock bit for control desc l0_4 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 8 wen_l0_5 write enable for soft lock bit slb_l0_5 1?b1: value is written to slb 1?b0: slb is not modified 9 wen_l0_6 write enable for soft lock bit slb_l0_6 1?b1: value is written to slb 1?b0: slb is not modified 10 wen_l0_7 write enable for soft lock bit slb_l0_7 1?b1: value is written to slb 1?b0: slb is not modified 12 slb_l0_5 soft lock bit for control desc l0_5 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 13 slb_l0_6 soft lock bit for control desc l0_6 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 14 slb_l0_7 soft lock bit for control desc l0_7 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable
pxd10 microcontroller reference manual, rev. 1 12-68 freescale semiconductor preliminary?subject to change without notice 12.3.4.41 soft lock bit register l1 figure 12-51 represents the soft lock bit register for la yer1. this is used to protect the 7 control descriptor layer re gisters for layer1. figure 12-51. soft lock register l1 offset: 0x308 access: user read/write 0123456789101112131415 r0 0 0 0 slb_l1_1 slb_l1_2 slb_l1_3 slb_l1_4 0000 slb_l1_5 slb_l1_6 slb_l1_7 0 w wen_l1_1 wen_l1_2 wen_l1_3 wen_l1_4 wen_l1_5 wen_l1_6 wen_l1_7 reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 48. table 12-46. soft lock register l1 field descriptions field description 0 wen_l1_1 write enable for soft lock bit slb_l1_1 1?b1: value is written to slb 1?b0: slb is not modified 1 wen_l1_2 write enable for soft lock bit slb_l1_2 1?b1: value is written to slb 1?b0: slb is not modified 2 wen_l1_3 write enable for soft lock bit slb_l1_3 1?b1: value is written to slb 1?b0: slb is not modified 3 wen_l1_4 write enable for soft lock bit slb_l1_4 1?b1: value is written to slb 1?b0: slb is not modified 4 slb_l1_1 soft lock bit for control desc l1_1 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 5 slb_l1_2 soft lock bit for control desc l1_2 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 6 slb_l1_3 soft lock bit for control desc l1_3 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-69 preliminary?subject to change without notice 12.3.4.42 soft lock disp_size register figure 12-52 represents the soft lock disp_size register. figure 12-52. soft lock disp_size register 7 slb_l1_4 soft lock bit for control desc l1_4 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 8 wen_l1_5 write enable for soft lock bit slb_l1_5 1?b1: value is written to slb 1?b0: slb is not modified 9 wen_l1_6 write enable for soft lock bit slb_l1_6 1?b1: value is written to slb 1?b0: slb is not modified 10 wen_l1_7 write enable for soft lock bit slb_l1_7 1?b1: value is written to slb 1?b0: slb is not modified 12 slb_l1_5 soft lock bit for control desc l1_5 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 13 slb_l1_6 soft lock bit for control desc l1_6 register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 14 slb_l1_7 soft lock bit for control desc l1_7 register. this bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable offset: 0x30c access: user read/write 0123456789101112131415 r0 0 0 0 slb_disp 00000000000 w wen_disp reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 49. table 12-46. soft lock register l1 field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 12-70 freescale semiconductor preliminary?subject to change without notice 12.3.4.43 soft lock hsy nc/vsync para register figure 12-53 represents the soft lock hsync/vsync register. figure 12-53. soft lock hsync/vsync para register table 12-47. soft lock disp_size register field descriptions field description 0 wen_disp write enable for soft lock bit slb_disp 1?b1: value is written to slb 1?b0: slb is not modified 4 slb_disp soft lock bit for disp_size register. this bit cannot be cleared once set by software. can only be cleared by system reset. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable offset: 0x310 access: user read/write 0123456789101112131415 r0 0 0 0 slb_hsync slb_vsync 0000000000 w wen_hsync wen_vsync reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 50. table 12-48. soft lock hsync/vsync para register field descriptions field description 0 wen_hsync write enable for soft lock bit slb_hsync 1?b1: value is written to slb 1?b0: slb is not modified 1 wen_vsync write enable for soft lock bit slb_vsync 1?b1: value is written to slb 1?b0: slb is not modified
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-71 preliminary?subject to change without notice 12.3.4.44 soft lock pol register figure 12-54 represents the soft lock pol register. figure 12-54. soft lock pol register 12.3.4.45 soft lock l0_transp register figure 12-55 represents the soft lo ck l0_transp register. 4 slb_hsync soft lock bit for hsync register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 5 slb_vsync soft lock bit for vsync register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable offset: 0x314 access: user read/write 0123456789101112131415 r0 0 0 0 slb_pol 00000000000 w wen_pol reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 51. table 12-49. soft lock pol register field descriptions field description 0 wen_pol write enable for so ft lock bit slb_pol 1?b1: value is written to slb 1?b0: slb is not modified 4 slb_pol soft lock bit for syn_pol register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable table 12-48. soft lock hsync/vsync para re gister field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 12-72 freescale semiconductor preliminary?subject to change without notice figure 12-55. soft lock l0_transp register offset: 0x318 access: user read/write 0123456789101112131415 r0 0 0 0 slb_l0_fcolor slb_l0_bcolor 0000000000 w wen_l0_fcolor wen_l0_bcolor reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 52. table 12-50. soft lock l0_transp register field descriptions field description 0 wen_l0_fcolo r write enable for soft lock bit slb_l0_fcolor 1?b1: value is written to slb 1?b0: slb is not modified 1 wen_l0_bcolo r write enable for soft lo ck bit slb_l0_bcolor 1?b1: value is written to slb 1?b0: slb is not modified 4 slb_l0_fcolor soft lock bit for l0_fcolor register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 5 slb_l0_bcolor soft lock bit for l0_bcolor register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-73 preliminary?subject to change without notice 12.3.4.46 soft lock l1_transp register figure 12-56 represents the soft lo ck l1_transp register. figure 12-56. soft lock l1_transp register 12.4 functional description the dcu is a master on the crossbar switch; it fetches gra phic source information directly from memory and dynamically performs bl ending and bit-blitting opera tions before delivering data to a tft lcd panel. offset: 0x31c access: user read/write 0123456789101112131415 r0 0 0 0 slb_l1_fcolor slb_l1_bcolor 0000000000 w wen_l1_fcolor wen_l1_bcolor reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 53. table 12-51. soft lock l0_transp register field descriptions field description 0 wen_l1_fcolo r write enable for soft lock bit slb_l1_fcolor 1?b1: value is written to slb 1?b0: slb is not modified. 1 wen_l1_bcolo r write enable for soft lo ck bit slb_l1_bcolor 1?b1: value is written to slb 1?b0: slb is not modified. 4 slb_l1_fcolor soft lock bit for l1_fcolor register. 1?b1: associated protected register is locked for write access 1?b0: associated protected register is not locked & writeable 5 slb_l1_bcolor soft lock bit for l1_bcolor register. 1?b1:associated protected register is locked for write access 1?b0:associated protected regist er is not locked & writeable
pxd10 microcontroller reference manual, rev. 1 12-74 freescale semiconductor preliminary?subject to change without notice 12.4.1 graphic sources as the dcu is a master on the crossbar switch, it can access directly any memory or device connected to the crossbar switch as a slave. th is includes all on-chip flash, all on-ch ip ram, and any slave capable of providing high enough data rates, such as, for exampl e an expanded bus interface or a quadspi module. therefore, any compatible graphic stored anywhere on -chip or in an accessible interface can be displayed on the connected tft lcd panel with no further intervention from the cpu, except to program the dcu to fetch and place it. the dcu also includes a dedicated memory to store the graphic for its cursor layer. 12.4.2 tft lcd panel configuration the nature and timing of the signals required by tf t lcd panels vary greatly between manufacturers. therefore, the dcu allows highly flexible a nd detailed configurati on of these signals. timing diagrams for tft lcd panels are typically divided into a horiz ontal timing chart and a vertical timing chart. see figure 12-57 for details. figure 12-57. hsync and vsync timing diagram pix_clk pixel data invalid data 12 3 4 delta x invalid data pw_h bp_h fp_h delta_x hsync data enable hsync invalid data invalid data 1 2 3 4 delta y bp_v pw_v fp_v line data vsync data enable 1/rr where rr is the frame refresh rate delta_x is the horizontal resolution of the display
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-75 preliminary?subject to change without notice the number of pixel data slots in the horizontal timing diagram is defi ned by the width of the panel. the number of line data slots is define d by the height of the panel. both of these values are defined in the disp_size register (delta_x, delta_y). the width of the panel must always be defined as a multiple of 16. the timing of the pixel clock is defined by the div_ratio register and the frequency of the clock supplied to the dcu. in addition to defining the number a nd timing of pixels in each line and the number of lines, it is normal for tft lcd panel manufacturers to de fine other timing signals in terms of pixel clock pe riods or of the number of horizontal lines. the dc u also follows this convention. if the tft lcd panel requires a horizontal synchroni zing signal (hsync) and/or a data enable signal, then these can be configured usi ng the fields in the hsyn_para re gister. hsync provides a pulse to give the panel notice that the next line of pixel data is about to start, and the data enable signal indicates when that data is present. the pw _h bit field indicates th e width of the hsync pulse , in pixel data clock periods. the bp_h bit field defines the delay between the end of the hsync pulse and the start of the data enable signal (and pixe l data delivery), in pixel clock peri ods. the fp_h bit field defines the delay between the end of the data enable signal (and pixel data delivery) and the ne xt hsync pulse, in pixel clock periods. fp_h and bp_h have minimum values of 1. if the tft lcd panel require s a vertical synchronizing signal (vsync), then this can be configured using the fields in the vsyn_para register. vsync provide s a pulse to give the pa nel notice that the next frame of pixel data lines is about to start, and the pa nel defines delays before a nd after this pul se, in terms of pixel clock periods. the pw_v bi t field indicates the width of th e vsync pulse in horizontal line periods. the bp_v bit field defines the delay between the end of the vsync pulse and the start of the next pixel data (data enable signa l), in horizontal line periods. the fp_v bit field defines the delay between the end of the last pixel data (data enable signal) and the next vsync pulse, in horizontal line periods. fp_v and bp_v ha ve minimum values of 1. the polarity of all these signals, including the pixel data itself, may be inverted by using the control bits in the syn_pol register. the refresh rate for the pa nel can be calculated using equation 12-54 and equation 12-55 below. eqn. 12-54 where: pix_clk is the pixel clock delta_x is the horizontal resolution (in pixels) delta_y is the vertical resolution (in pixels) fp_h is the hsync front porch pulse width (in pixel clock cycles) bp_h is the hsync back porch pul se width (in pixel clock cycles) pw_h is the hsync active pulse width (in pixel clock cycles) fp_v is the vsync front porch pulse width (in pixel clock cycles) bp_v is the vsync back porch pul se width (in pixel clock cycles) pw_v is the vsync active pulse width (in pixel clock cycles) rr pix_clk delta_xfp_hpw_hbp_h ++ + ?? delta_yfp_vpw_vbp_v ++ + ?? ? --------------------- --------------------- --------------------- --------------------- ---------------------- --------------------- ------------------ ---------------- - =
pxd10 microcontroller reference manual, rev. 1 12-76 freescale semiconductor preliminary?subject to change without notice pixel clock = (dcu clock) / prescale value eqn. 12-55 where prescale value is an integer value that can range from 2?32. 12.4.3 dcu mode selectio n and background color once the dcu is configured for use with a particular tft lcd panel, it can be enabled for use. there are five modes to choose from, as shown in table 12-52 . the dcu_mode, pdi_en and pdi_slave_mode cont rol bits are in the dcu_mode register. the dcu has an interface enable bit for the tft lcd panel interface called raster_en, also in the dcu_mode register. when raster_en is 0 the raster scanning of pixels to the panel is disabled but the pixel clock continues to run as long as dcu_mode is in an active state. color bar mode is intended for testing the interfa ce between the dcu and the tft lcd panel. in this mode, the panel is divided into eight vertical strips of equal width, and the strips display a single color whose rgb value is specified in the colbar_1 to colb ar_8 registers. at reset, the colors are set to black, blue, cyan, green, yellow, red, magenta, and white, where positive logic for the rgb values is assumed. the mode can be used to ve rify correct connection of the inte rface to the dcu and correct timing configuration of the interface. in this mode, any layer configuration settings are ignored. in normal mode, the dcu operates acco rding to the timings specified in section 12.4.2, tft lcd panel configuration ? and displays graphics according to the confi guration of its layers. the bgnd register sets the rgb color of the background shown when no other layers are present. this background color is included in the layer blending proces s but, since it is always the bac kground, it does not include any layer blending settings. in pdi normal mode, the dcu adopts the timing pr ovided on the pdi interface and replaces the background color by the pixel data coming from the pdi interface. the timing values set in the dcu are ignored in this mode, and the pixe l clock and synchr onization signals are taken from the pdi interface and passed to the tft lcd panel. the c ontent of the panel is a combinati on of the incoming pixel stream and layers generated by the dcu. pdi slave mode allows the dcu to synchronize wi th the external timing signals on the pdi input. table 12-52. list of dcu operating modes mode dcu_mode[1:0] pdi_en description off 00 x dcu disabled; the tft lcd panel is not driven. color bar 11 x dcu displays a test pattern consis ting of vertical bands of programmable color. normal 01 0 dcu blends layers and displays result on tft lcd panel. pdi normal 01 1 as normal mode, except that the panel timing is defined by the input on the pdi interface, and the background color is replaced by the content provided on the pdi interface. pdi slave 01 0 the dcu synchronizes its timing to an external signal when pdi_slave_mode is enabled.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-77 preliminary?subject to change without notice 12.4.4 proper sequence for en abling and disabling the dcu it is important to follow a correct se quence when enabling and disabling the dcu. to enable the panel it is possible to set dcu_mode to be active and th en set raster_en. it is possible to set raster_en and then set dcu_mode to be active. it is also possible to set both in the same write. it is not possible to set dcu_mode to be active and then set it to 0 before the raster_en bit has been set. to disable the panel mcu_mode must be set to 0 in the same write as or befo re raster_en can be set to 0. it is not possible to set raster_en to 0 (dis able raster) before disabling the pixel clock. 12.4.5 layer configuration and blending users control the graphical content of the tft panel by manipulating the configurat ion of elements in the dcu called layers. ea ch layer has a control descriptor that defines the size, position, memory encoding, blending, and memory location of the graphic to be displayed. the dcu provides 16 inde pendent layers that are identical except that they have a fixed prio rity with respect to each other, and this affects how individual pixels are blended when layers overlap. the blending setting on each layer allo ws the pixels on that layer to be opaque, partially transparent, or fu lly transparent, which allows them to combine with pixels on other layers that they overlap. 12.4.5.1 blending pr iority of layers the 16 layers available in the dcu are each fixed in priority order, with layer 0 being the highest priority, layer 1 being the second highest priority, and so on until layer 15, which is the lowest priority. the priority is used by the dcu to define how to blend individual pi xels within the layers. for example, if layer 0 is defined as not being blended with other layers and a pixel on layer 0 overlaps a pixel on layer 1 then the pixel on layer 0 will be visible on the panel unchanged by the pixel on layer 1. however, if layer 0 is defined as being partially transparen t, then the dcu will blend the overlapping pixel such that the result is a combination of the pixel on layer 0 and the pixel on layer 1. it is possible to blend up to four layers at each pixel position. as there is a maximum number of layers that can ble nded together, then any pixe l on a layer that is lower than the threshold priority will not be included in a ny blend. if a pixel is on a layer that has the lowest priority in any blending sche me, then the blending settings for that pi xel are ignored and th e pixel is treated as a background pixel. this means th at a lower priority layer may have some pixels completely obscured by those on higher priority layers on one part of the panel, and some ot her pixels visible or blended on other parts of the panel. figure 12-58 shows how the pixel blend takes place inside the dcu. the priori ty of the layers determines at which stage of the blend the pixe l enters. any pixels lower than the threshold priority are ignored and, as can be seen, the blend settings for the lowest pr iority pixel is also ignor ed. the maximum number of pixels in the blend is configured by the blend_iter bit field in th e dcu_mode regist er. as can be seen in the figure, the blending proces s is iterative so that four-pixel blending takes more dcu clock cycles than three-pixel blending, a nd three-pixel blending ta kes more dcu clock cycles than two-pixel blending.
pxd10 microcontroller reference manual, rev. 1 12-78 freescale semiconductor preliminary?subject to change without notice figure 12-58. pixel blending stack the blending algorithm used for eac h color component is shown in equation 12-56 . this priority concept is illustrated in figure 12-59 and figure 12-60 . in this case, there are five layers enabled, and each contains a graphi c that is a solid rectangular block of a single color. the size and shape of each layer is different. the background color of the pane l is set to grey and layers have been placed such that they overlap each other. figure 12-59 shows the individual source gr aphics and the case where no la yer has any blending enabled. here, the highest priori ty layer (in this case layer 0) is fully visible. layer 1 is visibl e where layer 0 does not overlap it. layer 2 is visible wh ere layer 1 does not over lap it. layer 3 is overl apped by layers 0 and 1 and so is only partiall y visible. layer 4 is partially obscured by all of the other layers. no te that layer 4 is higher priority than the background color. blend1 blend2 blend3 highest priority pixel next higher priority pixel higher priority pixel lowest priority pixel two-plane blending result three-plane blending result four-plane blending note: all blend stages use the blending settings defined for the upper pixel.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-79 preliminary?subject to change without notice figure 12-59. example of layer placement with no blending figure 12-60 shows the same layer c onfiguration except that, in this case , the layers have been made 50% transparent and the depth of the pixel blend is set to 3. the pixels in layer 0 are now blended with pixels in the underlying layers. in part icular, note region a where layer 0 is blended with layer 4 and the background color. this blending effect is repeated across all of the layers; however, note the pixels in region b. in this region the pixels from layer 0 are blended with those on layer 1 and layer 2; however, the pixels from layer 4 and the background color are not in cluded in this blend. this is because the dcu is configured to blend three layers onl y, and so the blend setting for laye r 2 is ignored for those pixels in region b.
pxd10 microcontroller reference manual, rev. 1 12-80 freescale semiconductor preliminary?subject to change without notice figure 12-60. example of layer placement with 3-layer blending all blending is performed using fu ll 8-bits-per-component colors. th e dcu automatically performs a color promotion on source data that is stored in less than rgb888 color. 12.4.5.2 control descriptors the control descriptor for each layer consists of seven regist ers, and all 16 control de scriptors are identical except the two highest priority layers, which have additional control bits for the safety mode. the control descriptors may be written to at any time, and the value presen t in the registers at the start of the next frame refresh cycle defines the content of the panel for that frame. to avoid coherency issues, ensure all control descriptor cha nges are made before the prog_end bi t in the int_status register is asserted. 12.4.5.3 layer size and positioning the size of each layer is defined by register 1 in the control descriptor fo r the layer (ctrldescln_1, where n is the layer number). the re gister contains two b it fields, height and wi dth, which determine the size and shape of the layer. both fields are e xpressed in terms of the number of pixels in each dimension. the height bit field may take any va lue; however, it may not be useful to define a value larger than the height of the panel. the width field has a restriction on the value it ca n take, depending on the data format of the graphic specified by the layer. this field must always be an integer multiple of the number of pixels that are represented by a 32-bit word except in the special case of 1 bit per pixel where the multiple is 16.. the data format can range from 1 bit per pixel to 32 bits per pixe l and so there is a range of multiples from 1 to 32. figure 12-53 shows the multiples for the width bit field and some correct values.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-81 preliminary?subject to change without notice if the width bit field is se t to an invalid multiple, then the layer configuration is inva lid, the layer cannot be made visible, and an error flag is set in the layer parameter error register (parr_err). the position of each layer on the panel is defined by re gister 2 in the control descriptor for the layer (ctrldescln_2, where n is the layer number). the re gister contains two bit fields, posy and posx, which determine the location of the upper left pixel of the layer in the x and y axes. both fields are expressed in terms of the numbe r of pixels in each axis. there are no restrictions on layer placement. any layer can be placed and moved to any panel position. if a layer is placed so that pixels would appear beyond the dimensions of the pane l, then the dcu displays the pixels on the panel and ignores the pixels off the panel. 12.4.5.4 graphics and data format the memory location of the graphic that is displayed on the layer is defined by register 3 in the control descriptor for the layer (ctrldes cln_3, where n is the layer number). this 32-bit value can contain the address of any memory location in the memory map of the mcu. the format of the data that describes the graphic is de fined by the bpp bit field in register 4 in the control descriptor for the layer (ctrldescl n_4, where n is the layer number). this value also influences the range of values for the width of the layer (see section 12.4.5.3, layer size and positioning ?). by choosing an appropriate format, it is possible to optim ize the memory required by the graphics in use. there are five formats where the rgb values of the pi xels are stored directly in the graphic. in these formats, the dcu treats the data as desc ribing a true rgb color. the formats are: ? argb8888, where the data defines 8-bit values for the red, gree n, blue, and alpha components of the image. ? rgb888, where the data defines 8- bit values for the red, green, a nd blue components of the image. ? rgb565 where the data defines 5-bi t values for the red and blue components, and 6-bit values for the green component of the image. ? argb1555 where the data de fines 5-bit values for the red, gree n, and blue components, and a 1-bit value for the alpha channel of the image. ? argb4444, where the data defines 4-bit values for the red, gree n, blue, and alpha components of the image. table 12-53. example of width multiples for different graphic data formats data format width multiples example values 1 bpp 16 16, 32, 48, 64, ? 2 bpp 16 16, 32, 48, 64, ? 4 bpp 8 8, 16, 24, 32, ? 8 bpp 4 4, 8, 12, 16, ? 16 bpp 2 2, 4, 6, 8, ? 24 bpp 4 (= 3 whole 32-bit words) 4, 8, 12, 16 32 bpp 1 1, 2, 3, 4, ?
pxd10 microcontroller reference manual, rev. 1 12-82 freescale semiconductor preliminary?subject to change without notice the three 16-bit formats (rgb 565, argb1555, and argb4444) are prom oted to full 8 bit per component format by shifting the bits left so that th e msb of the component in the 16-bit format becomes the msb of the 24/32 bpp (bit per pixel) format, and th e lsb is filled with the value of the msb. for example, an rgb565 value of 10000: 010000:11111 becomes 10000111:0100000000:11111111. there are four indexed color formats where the data in the graphic does not define the rgb color to display. instead, the data defines the entry in a colo r look-up table (clut) that contains a pa lette of rgb colors. the maximum number of colors in the clut is defined by the si ze of the data stor ed in the graphic. for 1 bpp graphics, there is a maximum of two colors in the clut . for 2 bpp, there is a maximum of four colors. for 4 bpp and 8 bpp data, the maximums are 16 and 256 colors, respectively. the address of the first value in the clut is defined in the luoffs bit field of register 4 and the clut is the ram block dedicated to the dcu wh ich is described in section 12.4.7, clut/tile ram ?. since the rgb values stored in the clut are 24-bit rgb, there is no need for furt her adjustment before blending. there are four additional formats de fined by the bpp bit field. these conf igure the graphic in transparency mode and luminance mode (see section 12.4.5.6, transparency mode and blending ? and section 12.4.5.7, luminance mode ? respectively). there is a set storage format for each data format provided by the dcu. these formats can be seen in table 12-54 to table 12-60 . for 32 bpp format, data expected in the memory is in the form argb8888. for 24 bpp format, data expected in the memory is in the form rgb888. for 16 bpp, data expected is in the form of rgb565, argb1555 or argb4444. table 12-54. data layout for 32 bpp address offset [7:0] [15:8] [23:16] [31:24] 0x00 b0 g0 r0 a0 0x04 b1 g1 r1 a1 0x08 b2 g2 r2 a2 table 12-55. data layout for 24 bpp address offset [7:0] [15:8] [23:16] [31:24] 0x00 b0 g0 r0 b1 0x04 g1 r1 b2 g2 0x08 r2 b3 g3 r3 table 12-56. data layout for 16 bpp address offset [7:0] [15:8] [23:16] [31:24] 0x00 pixel0[15:8] pixel0[7:0] pixel1[15:8] pixel1[7:0] 0x04 pixel2[15:8] pixel2[7:0] pixel3[15:8] pixel3[7:0] 0x08 pixel4[15:8] pixel4[7:0] pixel5[15:8] pixel5[7:0]
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-83 preliminary?subject to change without notice for 8 bpp, data is in the form shown in table 12-57 . for 4 bpp, data is in the form shown in table 12-58 . for 2 bpp, data is in the form shown in table 12-59 . for 1 bpp, data is in the form shown in table 12-60 . the dcu includes a flag that indicates when it ha s completed fetching graphics from memory for the current frame refresh. if required, this flag (dma_trans_finish in the int_status register) can be used to determine when changes can be made to the source graphic content. 12.4.5.5 alpha and chroma-key blending the blending configuration of each layer is defined by the bb, ab, and tr ans bit fields in register 4 in the control descriptor for the layer (ctrldescln_4, wh ere n is the layer number). the pixels affected by the blending configuration can be further selected by registers 5 and 6 in the control descriptor (ctrldescln_4 and ctrldescln_5). depending on the priority and placement of the layer (see table 12-57. data layout for 8 bpp address offset [7:0] [15:8] [23:16] [31:24] 0x00 pixel0[7:0] pixel1[7:0] pixel2[7:0] pixel3[7:0] 0x04 pixel4[7:0] pixel5[7:0] pixel6[7:0] pixel7[7:0] 0x08 pixe8[7:0] pixel9[7:0 ] pixel10[7:0] pixel11[7:0] table 12-58. data layout for 4 bpp address offset [3:0] [7:4] [11:8] [15:12] [19:16] [23:20] [27:24] [31:28] 0x00 pixel1[3:0] pixel0[3:0] pixel3[3:0] pixel2[3:0] pixel5[3:0] pixel4[3:0] pixel7[3:0] pixel6[3:0] 0x04 pixel9[3:0] pixel8[3:0] pixel11[3:0 ] pixel10[3:0 ] pixel13[3:0 ] pixel12[3:0 ] pixel15[3:0 ] pixel14[3:0 ] 0x08 pixel17[3:0 ] pixel16[3:0 ] pixel19[3:0 ] pixel18[3:0 ] pixel21[3:0 ] pixel20[3:0 ] pixel23 pixel22 table 12-59. data layout for 2bpp address offset [3:0] [7:4] [11:8] [15:12] [19:16] [23:20] [27:24] [31:28] 0x00 [pix3,pix2] [pix1,pix0] [pix7,pix6] [pix5,pix4] [p ix11,pix10] [pix9,pix8] [pi x15,pix14] [pix13,pix12] 0x04 [pix19,pix18] pix17,pix16] [pix23,p ix22] [pix21,pix20] [pix27,pix26] [pix 25,pix24] pix31,pix30] [pix29,pix28] table 12-60. data layout for 1 bpp address offset [7:0] [15:8] [23:16] [31:24] 0x00 pixel7-pixel0 pixel15-pixel8 pixel23-pixel16 pixel31-pixel24 0x04 pixel39-pixel32 pixel47-pixel40 pixel55-pixel48 pixel63-pixel56
pxd10 microcontroller reference manual, rev. 1 12-84 freescale semiconductor preliminary?subject to change without notice section 12.4.5.1, blending priority of layers ?), these bit fields and regist ers define how pixels from different layers are blended together. the ab and bb bit fields define whether blending is active and whethe r the whole graphic or a selected portion is blended. registers 5 and 6 define the range of rgb colors that define the selected pixels. the trans bit field defines the transp arency of the selected pixels. the bb bit field defines wh ether the whole graphic, or only certain pixels, should be blended. when this bit is set, pixels that have an rg b value that falls into the range defi ned by registers 5 a nd 6 are considered to be selected and treated differentl y to the non-selected pixels in the graphic. this is a process known as chroma-keying since it is the color of the pixel that defines the selection. the selected pixels must be within the range defined by each color component of registers 5 and 6. see table 12-61 for examples of pixels that are selected and not selected when the given range is defined as 0x0080c0 to 0x0fb0ff. the ab bit field defines how any se lected and non-selected pixels are blended. by combining this control with the bb bit field it is possible to define 11 unique ways of blending the pixels on a layer dependent on the type of layer. depending on the configuration defined by the ab and bb bit fields, th e trans bit field combines the two pixels in every blend stage using the alpha value of the upper pi xel (which has the effect of making this pixel more or le ss transparent and revealing more or less of the lower pixel). the result of each blend stage is calculated for all three color components as shown in equation 12-56 . a = (lpixel*(255 - alpha)) + (hpixel * alpha) eqn. 12-56 where: ? a is a 16-bit value ? lpixel is the lower priority pixel in the blend ? hpixel is the higher priority pixel in the blend ? alpha is the alpha value of the higher priority pixel the value of a is then normalized back to an 8-bit value by the approximation shown in equation 12-57 : bpixel = a>>8 + 1 eqn. 12-57 where bpixel is the blended pixel output. the output value for each of the rgb components is theref ore obtained by right-shi fting a by 8 and then adding 1 to the result. the blend can apply to pixels with no alpha channel (rgb) or with an alpha channel (argb) in different ways. table 12-61. example of how chroma-key range selects pixels source pixel red 00?0f green 80?b0 blue c0?ff comment 0x000000 p x x not selected 0x08c0c0 p x p not selected 0x08a0c0 p p p pixel is selected
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-85 preliminary?subject to change without notice table 12-62 defines how the set tings of the bb and ab bi t fields affect the pixels in the layer; rgb modes are 1 bpp, 2 bpp, 4 bpp, 8 bpp, rgb565, and rgb888; argb modes are argb1555, argb4444, and argb8888. figure 12-61 to figure 12-69 illustrate the effect of the cases identified in table 12-62 . in all cases there is a single active layer and a white background color. table 12-62. blend options for bb and ab configurations case bb ab[1:0] format function 1 0 00 rgb no blending, underlying pixels are obscured 2 1 00 rgb selected pixels are completely removed 3 0 01 rgb the value in trans becomes the alpha channel of all pixels on the layer 4 1 01 rgb the value in trans becomes the alpha channel of the selected pixels on the layer 5 0 10 rgb same as case 3 6 1 10 rgb selected pixels are completely removed and the value in trans becomes the alpha channel of the non-selected pixels on the layer 7 0 11 rgb reserved 8 1 11 rgb reserved 9 0 00 argb no blending, pixel alpha is ignored and underlying pixels are obscured 10 1 00 argb selected pixels are complete ly removed, pixel alpha is ignored 11 0 01 argb pixel alpha is used to blend layer with underlying pixels. value in trans is ignored. 12 1 01 argb uses the pixel alpha of the selected pixels only to blend layer with underlying pixels. value in trans is ignored. 13 0 10 argb the value in trans is multiplied with the pixel alpha value and the resultant alpha is used to blend all the pixels 14 1 10 argb selected pixels are completely removed, the value in trans is multiplied with the pixel alpha value and the resultant alpha is used to blend the non-selected pixels on the layer 15 0 11 argb reserved 16 1 11 argb reserved
pxd10 microcontroller reference manual, rev. 1 12-86 freescale semiconductor preliminary?subject to change without notice figure 12-61. case 1 example (no blend) figure 12-62. case 2 example (remove selected pixels)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-87 preliminary?subject to change without notice figure 12-63. case 3 example (all pixels transparent) figure 12-64. case 4 example (selected pixels transparent)
pxd10 microcontroller reference manual, rev. 1 12-88 freescale semiconductor preliminary?subject to change without notice figure 12-65. case 6 example (selected pixels removed, others transparent) figure 12-66. case 9 example ( no blend, pixel alpha ignored)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-89 preliminary?subject to change without notice figure 12-67. case 10 example (selected pixels removed, pixel alpha ignored) figure 12-68. case 13 example (pixel and layer alpha used in blend)
pxd10 microcontroller reference manual, rev. 1 12-90 freescale semiconductor preliminary?subject to change without notice figure 12-69. case 14 example (selected pixels removed, pixel and layer alpha used in blend) 12.4.5.6 transparency mode and blending transparency mode is a special case for the graphic data format and is defined by the bpp bit field in register 4 in the control descriptor for the laye r (ctrldescln_4, where n is the layer number). this value also influences the range of values for the width of the layer (see section 12.4.5.3, layer size and positioning ?). by choosing an appropriate format, it is possible to optimize the memory required by the graphics in use. in transparency mode, the source gr aphic does not contain a ny direct or indexed co lor information. instead, the graphic data represents the alpha channel of the graphic. the dcu creates the final graphic by pre-blending a foreground colo r and background color using the alpha va lue of each pixel. the result of this pre-blend can then be blended with pixels on other layers using the normal blending process. each layer has dedicated registers to contain the foreground and background colors for this mode. these are fgn_fcolor and fgn_bcolor, wh ere n is the layer number. transparency mode is typically used when a graphi c must blend smoothly into the underlying layers, but where a rich color palette is not re quired. examples include te xt where this mode allo ws the text to blend smoothly with any background ? th is is known as anti-aliasing. there are two transparency modes available: 4 bpp a nd 8 bpp. the result of the pre-blend can be treated as an rgb888 graphic and ble nded in a similar way to prev iously described, or it can be treated as a special case of argb with only the foregr ound color visible in the final blend. table 12-63 describes the blend options for transparency mode.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-91 preliminary?subject to change without notice figure 12-70 ? figure 12-73 illustrate the effect of the cases identified in table 12-63 . in all cases there is a single active transparency layer and a white background color. figure 12-70. case 1 example (no blend) table 12-63. blend options for transparency mode case bb ab[1:0] mode function 1 0 00 transparency no blending, underlying pixels are obscured 2 1 00 transparency reserved 3 0 01 transparency the value in trans becomes the alpha channel of all pixels on the layer 4 1 01 transparency the value in trans becomes the alpha channel of the selected pixels on the layer 5 0 10 transparency same as case 3 6 1 10 transparency background color is igno red, selected pixels are completely removed, the value in trans is multiplied with the graphic data value (alpha) and the resultant alpha is used to blend the non-selected pixels on the layer 7 0 11 transparency reserved 8 1 11 transparency reserved transparency graphic foreground color background color panel
pxd10 microcontroller reference manual, rev. 1 12-92 freescale semiconductor preliminary?subject to change without notice figure 12-71. case 3 example (all pixels transparent) figure 12-72. case 4 example (selected pixels transparent)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-93 preliminary?subject to change without notice figure 12-73. case 6 example (only foreground color blended) 12.4.5.7 luminance mode luminance mode is a special case for the graphic da ta format and is defined by the bpp bit field in register 4 in the control descriptor for the laye r (ctrldescln_4, where n is the layer number). this value also influences the range of values for the width of the layer (see section 12.4.5.3, layer size and positioning ?). by choosing an appropriate format, it is possible to optimize the memory required by the graphics in use. in luminance mode, the data in the source graphic does not contain any di rect or indexed color information or alpha information. the data values in a layer in luminance mode modify the values of the pixels on underlying layers only. there are two luminance modes available: 4 bpp and 8 bpp. in both cases, the data values behave as signed integers that are added to each component of the underlyi ng pixel. the 4 bpp mode is left-shifted to form a signed 8 bpp integer. the re sults of the addition are pr evented from overflowing, so that any result greater than 0xff is set to 0xff and any result less than 0x00 is set to 0x00. the result of a blend with a luminance layer is that the intensity of the underlyi ng pixel's color will be increased or decreased. in this way, luminance mode can be used to hi ghlight or dim pixels on the panel without having to modify the source graphic data. table 12-64 describes the effect of luminance blends on an underlying pixel. 12.4.5.8 tile mode tile mode is a special case for the la yer and is enabled by the tile_en bit field in register 4 in the control descriptor for the layer (ctrldescl n_4, where n is the layer number). in this mode the layer size register (ctrldescln_1, wh ere n is the layer number) defines the size of the layer; however, the size of the graphic is defined in control register 7 (c trldescln_7, where n is the table 12-64. example of a blend with a luminance mode layer pixel value luminance value resultant pixel 0xff8040 0x40 0xffc080 0xff8040 0xc0 0x3f0000
pxd10 microcontroller reference manual, rev. 1 12-94 freescale semiconductor preliminary?subject to change without notice layer number). the size of th e graphic must be less than or equal to the size of the laye r. when tile mode is enabled, the graphic is repeated horizontally and vert ically until it fills the whole layer. the horizontal size of the tile is defined by the ti le_hor_size bit field and is restricted to be a multiple of 16 pixels. the vertical size of the tile is de fined by the tile_ver_size bit field. the graphic data for the tile mode can be fetched ei ther from the system memo ry or from the internal clut/tile memory. this is defined by the data_sel bit field in register 4 in th e control descriptor for the layer. if the graphic is fetched from clut/tile memory then it must be in the clut/tile ram direct color format. otherwise the gra phic can be in any previously described data format. see figure 12-74 for an example of a la yer in tile mode. figure 12-74. tile mode when data_sel is set (to use clut/tile ram) the luoffs bitfield defines the start address of the tile graphic. 12.4.6 hardware cursor in addition to the 16 layers, the dcu also provides a special layer intended for use as a cursor. this cursor operates in 1 bpp mode and includes it s own ram area to store the graphi c. the cursor may be placed at any location on the pane l and includes an automatic blink option. the hardware cu rsor is conf igured using a dedicated control descriptor a nd its visible pixels always overl ay any other layer on the panel.. the size of the cursor is defined by register 1 in the control descriptor for the cursor (ctrldesccursor_1). the register contains two bit fields, height and width, which determine the size and shape of the layer. both fields are e xpressed in terms of the number of pixels in each tile size - 64x64 pixels display size- 320 x240 (qvga) layer size - 192 x 128 pixels
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-95 preliminary?subject to change without notice dimension. the height is limited to a maximum of 256 pixels, and the total number of pixels cannot exceed the number of bits in the cursor ram (8192 bits). bits in the cursor ram that are 0 become transparent on the panel. bits that are 1 become fully opaque in the color defined in register 3 in the control descriptor for the cursor (ctrldesccursor_3). the default_cursor_color bit field is in rgb888 format. there are restrictions on the arrangement of bits in the curs or ram depending on how the height and width bit fields are configured. ? the rightmost bit in the cursor ram (bit 31) represents the leftmost pixel on the display. ? when the cursor size is less than 32 bits, each row of th e cursor is contained in a single 32-bit word of cursor ram. the other bits in each row must be filled with zeros. ? when the cursor width is an intege r multiple of 32 bits, the pixels in each row roll from one word in the ram to the next one. the ri ghtmost bit in the first word in the ram is the t op leftmost pixel on the display. the leftmost bit in the word repres ents a pixel that is adjacent to the rightmost bit in the next word (in the same row). the leftmost pixel on the next row is the rightmost bit in the first word after n words that describe the first row. ? when the cursor is greater than 32 bits but not an integer multiple of 32, the pixels in each row roll from one word into the next one such that the ri ghtmost bit in the first word of the row is the leftmost bit on the display. in the fina l word of the row there are unused bits. the position of the cursor on the panel is defined by re gister 2 in the control descriptor for the cursor (ctrldesccursor _2). the register contains two bit fields, posy and posx, which determine the location of the upper left pixel of the cursor in the x and y axes. both fields are expressed in terms of the number of pixels in each axis. placing the cursor beyond the panel area is not allowed. the cursor can be configured to blink at a part icular rate when it is enabled. the en_blink, hwc_blink_on, and hwc_blink_off b it fields define the blink beha vior. these are in register 4 in the control descriptor for the cursor (ctr ldesccursor_4). en_blink enables blinking. the blinking time is based on the frame rate, and the on and off times are inde pendently configurable. hwc_blink_on configures the numbe r of frame refresh cycles for which the cursor is visible. hwc_blink_off configures the number of frame refresh cycles for which the cursor is not visible. for a frame refresh rate of 64 hz, the hwc_blink_ on and hwc_blink_off counters give a range of on/off times up to 4 seconds. the cursor is enabled by setting the cur_en bit field in register 3 in the control descriptor for the cursor (ctrldesccursor_3). visible pixels in the cursor graphic operate independently from the normal layer blend process and alwa ys replace any other pixel at the same panel location. this has the effect of making the cursor the highest priority layer on the panel when it is enab led and where it contains visible pixels. if the dcu detects an invalid confi guration in the cursor control descri ptor, then the cursor configuration is invalid and it cannot be made visible. in addition, the error flag hwc_err is set in the layer parameter error register (parr_err). the cursor ram may be written at an y time when the tft lcd panel is not being driven with data. this means that the ram can be modified when the dcu is not enabled and during the vertical blanking period.
pxd10 microcontroller reference manual, rev. 1 12-96 freescale semiconductor preliminary?subject to change without notice 12.4.7 clut/tile ram the internal tile memory and color look up table (c lut) memory share a commo n block of ram internal to the dcu. color information in this ram is always stored as aligned 32-bit words where the most-significant byte is always 0x00, the next byte contains the red component, the next the green component and the least significant byt e the blue component (0x00rrggbb). this memory block can be used to st ore either color look-up tables or gra phics for use as a tile on a layer. the content of the ram at a specific address is defined by the control de scriptor of a la yer. the luoffs bit field in the layer control descri ptor defines the starting address of the area, and the bpp and tile_en bit fields define what t ype of use th e ram area has. in figure 12-75 three areas of the ram are de fined for different purposes. area a is used by layer 1 as a clut for its 4 bpp graphic. area b is use by layer 5 as a store for its tile graphic. area c is used by layers 2, 7, and 9 as a clut for their 8 bpp graphics. figure 12-75. an example of use for the clut/tile ram the clut/tile ram is mapped in the dcu 16k me mory space from address 0x2000 to 0x3fff. this gives 2048 entries, which provides up to eight full cluts for 8 bpp layers. the clut/tile ram may be written at any time when the tft lcd panel is not being driven with data. this means that the ram can be m odified when the dcu is not enable d and during the ve rtical blanking period. 16 palette entries 64 pixel entries for 8 x 8 tile 256 palette entries clut/tile ram a b c
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-97 preliminary?subject to change without notice 12.4.8 gamma correction the gamma table allows the user to define an arbi trary transfer function at the output of each color component. the function ( equation 12-58 ) is applied to each pixel afte r all blending is complete and before the data is driven to the tft lcd panel. gamma corr ection is optional and can be used to adjust the color output values to match the gamut of a particular tft lcd panel, or to perform da ta inversion or data length reduction on each component. output_color_component = gamma_table[input_color_component] eqn. 12-58 the table is arranged as th ree separate memory blocks within the dcu memory map; one for each of the three color components. each memory block has one entry for every possible 8-bit value and the entries are stored at 32-bit a ligned addresses. this means that the upper 24 bits are not used while reading/writing the gamma memories. see figure 12-76 for details of the memory arrangement. figure 12-76. gamma correction table organization the gamma table can only be read or written when the dcu is not en abled or during the vertical blanking period. 12.5 timing, error and interrupt management the dcu can detect and raise status and error flags when the status of the system changes and when configuration or operationa l errors are detected. 0x0800 blended pixel gamma adjusted pixel 0x0c00 0x1000 red green blue
pxd10 microcontroller reference manual, rev. 1 12-98 freescale semiconductor preliminary?subject to change without notice 12.5.1 synchronizing to panel frame rate since the dcu fetches data directly from memory independently of the cp u, there is the possibility that changes to the dcu layer configurat ion or content can create incoherent content on the panel. to help avoid this situa tion there are five timing control flags that define when the dcu recognizes and locks changes to its configuration. these can be used to ma nage changes to control descriptors, clut or tile memory, or source graphics and so avoid coherency problems on the pane l. all the timing flags are in the int_status register and can be used to generate interrupts from the dcu. the dcu configuration is completely open during the vertical blanking period and control descriptors and some other registers may also be programmed at a ny time. the configuration present one hsync before the end of the vertical blanking pe riod is the configuration used by the dcu for the panel refresh phase. the vs_blank and ls_bf_vs flags give indication of the start of the vertical blanking period. the vs_blank flag is set at the begi nning of the vertical bl anking period. the ls_bf_vs flag is set a given number of horizontal lines before the start of the vert ical blanking period; the gi ven number of lines is defined by the ls_bf_vs bit fiel d in the threshold register. the prog_end flag indicates that the dcu has locked the contents of its confi guration registers for the new panel refresh period. no further changes are accepted to the dcu configuration after this flag is set (until the next vert ical blanking period). the dma_trans_finish flag indicates that the dcu has completed fetching all data from memory in the current panel refresh cycle. this normally precedes the vertical blanki ng period and indicates that it is possible to change the contents of a memory that contains graphics used by the dcu. the vsync flag indicates th at the dcu has begun the ne xt panel refresh period. 12.5.2 managing the dcu fifos and dma activity the dcu fetches graphic data direct ly from internal and external me mory using a dedicated dma system and manages the output of data to the tft lcd panel such that the panel always receives the pixel information when expected. since the panel is sharing access to memo ry with the system dma and cpu it cannot depend on the required data always being available at all times. it therefore it uses input and output fifos to temporarily store incoming and outgoing data until required and thus reduces the opportunity for the panel to be starved of pixel data. the dcu manages the supply of graphic data to its format conversion and ble nding stages using input fifos that are 256 x 32 bits in size. the data that is driven to pane l is managed using an output fifo that is 128 pixels in size. see figure 12-1 for a diagram of the input fifo and output fifo operation in the dcu the input fifos are not accessible to the user but it is possible to se t thresholds that control the dcu behavior when the fifos are becoming full or empt y and observe when the lower and higher thresholds are reached. this can help detect and avert situations where the dc u is running out of data to send to the panel. the fifo thresholds are set in the threshold_in put_buf_1/2 registers. the upper thresholds are set by the inp_buf_pm_hi bit fields (where m is the position of the pixel in the blend stack) and these
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-99 preliminary?subject to change without notice set the point at which the dcu pa uses fetching data from memory. the maximum si ze of any dma burst is fixed to 16 pixels and so is dependent on the graphic encoding. the lower thresholds are set by the inp_buf_pm_lo bit fields. each of the four input fi fos has two flags that indicate whether the fifo has reache d its upper or lower threshold. the pm_fifo_hi_flag flags (where m is the position of the pixel in the blend stack) indicates that the input fifo has reached the upper threshold. the pm_fifo_lo_flag indicates that the input fifo has less data than its low threshold. depending on when the low threshold is reached this may indicate a number of scenarios ? the expected graphical data is not available for the dcu to load ? the dcu is reaching the end of a frame and does not need to load any more data ? the blend stack does not need pixels of this priority in the situation where the data is not available to th e dcu then there may or may not be an impact to the data visible on the panel. in the situation where the output fifo is full then it is possible for the dcu to accept a delay before it require s to use the incoming data. the output fifo is not accessible to the user but it is possible to set thresholds that control the dcu behavior when the fifo is becoming full or empty and obser ve the lower threshold. this can help detect and avert situations where the dcu is r unning out of data to send to the panel. the buffer thresholds are set in the threshol d register. the upper threshold is set by the out_buf_high bit field and this indicat es that sufficient data exists in the output buffer and processing should stop until the dcu uses some of the values in the fifo. if this value is set too low then the possibility of the dcu running out of data to drive the panel is increased. the lo wer threshold is set by the out_buf_low bit field. when the output fifo has emptied below its low threshold (out_buf_low bit field) it sets the undrun bit. in an under run situation there may or may not be an im pact to the data visible on the panel. the impact depends on whether the dcu is reaching th e end of a frame and how close to running out the threshold is set. the best guide to indicate whether the dcu is able to supply the requi red pixel information to the panel is the output buffer. if the output is indicating that it is r unning out of data then the input fifos may help identify the areas of memory that ar e restricting the supply of data. usi ng these indicators can help to set the dcu thresholds and ensure that the data throughput on the mcu is balanced correctly for all master devices. finally, note that the number of dcu clock cycles to fetch and blend ea ch pixel increases with the depth of the blend stack. however, the time taken to proc ess the pixel data is fixed by the timing requirements of the panel. therefore, for full performance across all color encodi ngs the ratio between the dcu clock and the pixel clock must increase as the blend stack depth increases. for two-pi xel blending, the minimum dcu clock must be twice the tft pixel clock. for three-pixel ble nding, the minimum dcu clock must be three times the tft pi xel clock. for four-pixel blending, the mi nimum dcu clock must be four times the tft pixel clock.
pxd10 microcontroller reference manual, rev. 1 12-100 freescale semiconductor preliminary?subject to change without notice 12.5.3 error detection the dcu asserts error flags when errors are detected in its configuration or wh en the user attempts to modify the configuration at an invalid point in the pa nel refresh period or when it is unable to access the required source data. the error flags may raise an interru pt if enabled to do so by the related mask bit in the corresponding mask register. error flags are stored in the parr_er r_status and int_status registers. errors in the dcu configuration are collecte d in the parr_err_status register. the flags ln_parr_err (where n is the layer number) indicate an error in the c onfiguration of the layer which can be either an invalid tile mode size or a layer with a horizont al dimension that is sm aller than the minimum size defined by the layer encoding (see section 12.4.5.3, layer size and positioning ?). the disp_err flag indicates that the vsync and hsync pulse widths are configured to the invalid value of 0. the hwc_err flag indicates that the hardwa re cursor is either larger than the available memory or is placed in an off-panel position. the sig_err indicates that the signature calculation specifies an area that extends beyond the panel size. reads of clut/tile ram during the period when the tft lcd panel is being updated do not return the clut/tile ram content. errors caused when the dcu is unable to access its requi red source data are collected in the int_status register. these errors are indicat ed by the undrun flag and the pm_f ifo_lo_flag flags (where m is the postion in the blend stack) 12.5.4 interrupt generation the dcu generates interrupt through four lines that are controlled by the contents of six registers: ? int_status ? int_mask ? pdi_status ? mask_pdi_status ? parr_err status ? mask_parr_err status there are four interrupt status lines de fined.these lines are grouped as follows ? timing based interrupts: ?vsync ?ls_bf_vs ? vs_blank ?prog_end ? dma_trans_finish ? functional interrupts: ? undrun ? crc_ready
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-101 preliminary?subject to change without notice ? crc_overflow ? p1_fifo_hi_flag ? p1_fifo_lo_flag ? p2_fifo_lo_flag ? p2_fifo_hi_flag ? p3_fifo_hi_flag ? p3_fifo_low_flag ? p4_fifo_hi_flag ? p4_fifo_low_flag ?ipm_error ? parameter error interrupts ?layer error ? signature calculator error ? display error ? hwc_error ? pdi-related interrupts (pdi_int) ? this includes pdi related interrupts. see section 12.8.2.7, pdi-re lated interrupts,? for a description. when any interrupt occurs, the host can identify wh ich type of interrupt has occurred by reading the interrupt status register /pdi status register/par r_err status register. 12.6 register protection there is a customized register protection scheme on the dcu that is different to the protection scheme implemented elsewhere on the mcu. th e scheme provides a mechanism to protect certain registers in the dcu from being written. 12.6.1 operation of scheme the register protection scheme provides a two-step protection scheme for the protected register. firstly, each register has an associat ed soft lock bit (slb) that prevents further writes to the register when it is set. each slb has a correspondi ng write enable (wen) bit that must be set in the same write operation as the slb. the slb can be set or cl eared by writing a '1' or '0 ' to it while its wen bi t is set. the slb bits are in the soft lock registers l0 and l1, di sp_size, hsync/vsync_para, pol, l0_transp and l1_transp registers. secondly, there is a hard lock bit (hlb) in the globa l protection register which prevents all changes to soft lock bits. the hlb can only be cleared by a system reset. if a write is made to a register whose slb is set th en a transfer error occurs that generates an ivor2 exception on the cpu. similarly if the hlb is set then any write to the slb registers causes a transfer error.
pxd10 microcontroller reference manual, rev. 1 12-102 freescale semiconductor preliminary?subject to change without notice 12.6.2 list of protected registers the register protection scheme a pplies to the following registers: ? all layer 0 control descriptor s ctrldescl0_1 to ctrldescl0_7 ? all layer 1 control descriptor s ctrldescl1_1 to ctrldescl1_7 ? layer 0 foreground and background register s for transparency mode fg0_fcolor and fg0_bcolor ? layer 1 foreground and background register s for transparency mode fg1_fcolor and fg1_bcolor ? all control descriptors & tran sparency registers for layer1 ? disp_size ? hsync_para ? vsync_para ? syn_pol 12.7 safety mode safety layers are used in a multi- layer dcu environment for the purpose of guaranteeing that the content is visible on the display regardless of the setting of remaining layers and the pixel mani pulation algorithms of the dcu.safety feature is a require ment from qualification institutes to be able to reach a safety level of sil2 or asilb.the safety layers (layer 0 and la yer 1) have the highest priority and use chroma key for complex area description.when a layer has safe ty mode enabled and layer format is 32 bpp or luminance mode, the layer is disabl ed as this is a wrong setting.also alpha blending for the layer is disabled if layer has safety mode enabled. a signature calculator module is impl emented in the dcu that calculates the signature (value and position) for a predefined area of the frame. dcu specifies a set of registers which define the wi ndow/area of the pixels for which crc needs to be calculated. the application sets thes e registers. the signature calculator starts to calculate the signature after the first vertical (frame) sync after activation a nd when first pixel in the selected area is activeness tagged). it is also possible to calcula te the crc value for all pixels if th e tag_en bit in the register is set to 0. the pixels in the region of the la yer on which signature needs to be calculated are tagged by the dcu. all the pixels for the safety layer enabled layer are tagged and then depending on the chroma keying operation, pixels with tagged values are passe d along with the original data (2 4 bpp rgb + 1 bit safety pixel tag). the crc value for these tagged pixels are th en calculated by the signature calculator. once crc calculation is done on all the pixels in the window of interest, an interrupt crc_ready is generated for the processor to compare the crc valu e with a precomputed value. signature calculator would continue to calculate crc for the next frame. if the interrupt is not processed within one frame time period, then crc overflow interrupt is issued. the sign ature calculator calculates the content signature and position signature.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-103 preliminary?subject to change without notice if the user has set neg bit for dcu which indicates that the pixels fed to the displa y are inverted of output pixels, value crc would be calculated on non inverted values. the position crc how ever remains as it is. in case a pixel has fg0 and fg1 as tw o highest priority layers with safe ty mode enabled in layer 1, normal arbitration takes place. the polynomial used for crc calculation is (x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1) figure 12-77. safety mode block diagram 12.7.1 crc area description 12.7.1.1 relationship between various input signals 1. crc is calculated when safety mode is enabled. 2. crc can be calculated over full screen as shown in figure 12-78 . here tag bit (generated internal to dcu and flow along the datapath) is set low. da ta enable is coming for green color portion given in figure 12-78 . data enable is not affect ed by chroma keying. tag_en re gister bit is low in this case. format converter blending/ chroma key gamma correc. display drive display fgplane bgplane 1-32 bpp 1-32 bpp 24 bpp 24 bpp 24 bpp 24 bpp format converter gamma correction display drive display fgplane fg1plane 1-24 bpp 1-24 bpp 25 bpp 25 bpp 25 bpp 24 bpp signature calculator normal mode operation safety mode optional chroma key optional sync tag 25 bpp = 24 bpp rgb + 1 bit safety pixel tag optional external signature checker result interrupt calculator fg2plane 1-24 bpp bgplane 1-24 bpp
pxd10 microcontroller reference manual, rev. 1 12-104 freescale semiconductor preliminary?subject to change without notice this scenario can also be used in debug mode to ca lculate the data of the si ngle layer. for such case cpu has to just enable the single concerned laye r and disable all the math ematical function on the same. 3. crc can be calculated for the pa rt of the screen as shown in figure 12-78 . here tag bit is set low.data enable is coming for green color portion given in figure 12-78 . data enable is not effected by chroma keying. tag_en register is low for this case. this can also be used in debug mode. figure 12-78. safety mode enabled for part of the screen 4. crc can be calculated only for the safety layers. layer 0 and 1 can only act as a safety layer. both of them have a separate control bits. in calculates the crc over the intersection of both as shown (dark pink) in figure 12-79 . here tag bit set high for all the bi ts corresponding to the layer 0 and 1 as shown by pink color (both dark and light) as shown in figure 12-79 . also data is affected by chroma keying.tag bit is cleared for the pixel removed by chroma keying.as shown in figure 12-79 data enable is controlled by the region s hown in green color and tag is controlled by the pink region. crc is calculated over region in dark pink. lenx startx starty area of concern leny note: enable to crc is sent for the green portion
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-105 preliminary?subject to change without notice figure 12-79. safety mode with tag bit high 5. layer 0 and 1 (i.e., safety layer) in safety m ode does not supports blendi ng or luminance offset. 12.7.2 features ? sc support area modes mentioned in table 12-65 ? supports calculation of crc on the pixel value only ? crc is calculated with the initial value as 32?h000000000 ? crc does not support: ? any modification of input bytes ? any modification of the output crc value before reporting. ? when pdi is enabled with the layer 0 and 1 (safet y enabled) in a single sector, then pdi would act as bg layer and layer 0 as a fg layer.cr c would be calculated over a single l0 layer. table 12-65. supported area area tag value note full 1?b0 startx = 0 starty = 0 lenx = screen size leny = screen height area of interest crc layer (intersection of both area of interest and safety layer) safety layers/tag note: enable to crc is sent for the dark pink portion
pxd10 microcontroller reference manual, rev. 1 12-106 freescale semiconductor preliminary?subject to change without notice 12.7.3 programming for debug mode 1. program the only debug layer as fg laye r. no layer is programmed as bg layer. 2. set startx, starty, width and le ngth as full layer parameters. 3. program safety mode as 1?b1. 4. check the crc when crc calculation inte rrupt is raised for particular screen. 12.7.4 programming of tag mode 1. program the safety layers. 2. set startx, starty, width and le ngth as full layer parameters. 3. tag bit as 1?b1. 4. set program safety mode as 1?b1. 5. check the crc when crc calculation inte rrupt is raised for particular screen. 12.8 parallel data interface (camera interface) figure 12-80. camera interface block diagram part 1?b0 all the parameter have value other the one mentioned above as shown in figure 12-78 safety layer (layer 0 and 1 only) 1?b1 part of the safety layer would depend on ? part lying within the area of concern defined by the startx starty lenx leny ? part deleted by the chroma keying functionality table 12-65. supported area (continued) area tag value note video dcu display digital rgb/mono/ycbcr digital digital digital rgb/mono/ycbcr rgb rgb dcu display fpga ccir656 rgb proprietary lv d s source
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-107 preliminary?subject to change without notice 12.8.1 itu-r bt.656 sync information extraction according to itu-r bt.656 recommendation, the incoming digital video will have a pdi_clk signal and 8 data bits. the data bits can cont ain both the video data and the ti ming reference signals (vsync and hsync). the timing signals are encoded at th e start and end of each line by ti ming reference codes known as start of active video (sav) and end of active video (eav ). the sav and eav codes are idnetified by their preamble of three bytes (0xff, 0x00, 0x00). due to th is, neither 0x00 or 0xff can be used during the active video data. the preamble is followed by the xy status word which cont ains a field bit (f), a vertical blanking bit (v), a horizont al blanking bit (h), and four pr otection bits for single-bit error correction and detection. the h bit is set to one to denote an eav. that is the end of a line, and the beginning of the horizontal blanking period. the v bit is set to 1 to denote the beginning of the ve rtical blanking pe riod. the f bit is used for interlaced video to denote if the forthcoming line is odd or even. the remaining 4 bits make up the protection bits fo r single-bit error correcti on and detection. f and v fields are only allowed to change as part of ea v sequences i.e during tran sitions from h=0 to h=1. an entire line of video comprise s active video + horizontal blanki ng (from the start of the eav code until the end of the sav code) and vert ical blanking (the space where v = 1). figure 12-81. itu-r bt.656 8 bit parallel data format for 525 video system note only 8-bit video is supported on this device. only non-interlaced video is supported on this device. the field (f) value is ignored. f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y video data active eav code sav code blanking h control signal start of digital line start of digital active line next line
pxd10 microcontroller reference manual, rev. 1 12-108 freescale semiconductor preliminary?subject to change without notice figure 12-82. control byte sequence for 8-bit video the bit definitions for the st atus word xy are given in table 12-68 . figure 12-83. pdi input data mode figure 12-83 represents the scenario in which data from an itu-r bt.6 56 compliant video source is fed into the pdi interface. the incoming data includes code s that trigger the start a nd end of the active video and blanking fields. an activity det ector checks for the transitions on the pdi bus. it samples the values on the pdi bus and once it has detected valid activity, se ts a flag in the status register and can optionally trigger an interrupt. the pdi interface has a state machine which extracts the control information from the video data. the machine checks the video data for the preamble field (0xff,0x00,0x00) and then depending on the status bits xy decides if it has received a valid control signal. 12.8.2 pdi interface description 12.8.2.1 introduction this block takes pixel info rmation from the video sour ce and passes to the dcu block to display the pixel information to the tft/lcd screen. it can also be used in the slave mode i.e. it takes only timing info from external chip/fpga and display pixel info from memory to tft screen at the timing provided. data t bit firstword secondword thirdword fourthword (ff) (00) (00) (xy) d9(msb) d8 d7 d6 d5 d4 d3 d2 d1 d0(lsb) 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 f v h p3 p2 p1 p0 0 0 video source with embedded itu656 timing clk embedded control pdi_clk activity detector ready data with pdi interface logic
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-109 preliminary?subject to change without notice 12.8.2.2 pdi interaction with other modules figure 12-84. pdi interacting directly with the external sensor in figure 12-84 , pdi directly accepts th e data from the extern al video source. extern al device must support the interface mentioned in the document. figure 12-85. pdi interacting with fpga in between as shown in figure 12-85 , pdi would not directly interface to the video source or any existing image processor chip. fpga sits in between. in normal mode, pdi clock frequency should be equal to pixel cloc k frequency desired for the tft display driver. in narrow mode, pdi cloc k frequency is double the desired pi xel clock frequency. the incoming clock does not have to bear any re lation to the dcu clock. prior to the lock condition the dcu will run on the internal dcu clock. after lock has been achiev ed, the dcu will switch to the clock from the pdi stream. pdi clock would be used to send data a nd timing signal to tft/lcd display driver. video source video source fed directly to pdi other layer data to mix with pdi (bg layer) pdi dcu display driver/ screen data being sent at pdi rate pdi output in format required by dcu pxd10 video source output fed directly to fpga, other layer data to mix with pdi (bg layer) pdi dcu display driver/ screen pdi output in format required by dcu video source fpga which converts the data to a format required by the pdi. data being sent at pdi rate pxd10
pxd10 microcontroller reference manual, rev. 1 12-110 freescale semiconductor preliminary?subject to change without notice in all cases, the resolution of the incoming stream and the hsync and vsync fre quency must be the same as that of the tft scree n. all the horizontal paramete r (front porch width, back porch width, pulse width) and vertical parameter (front porch width, back porch width, pulse width) should be same as that of tft screen. if pdi is the background layer, no other layer can be a background layer for that pa rticular frame. one and only background layer is possible i.e. pdi layer when pdi is enabled. 12.8.2.3 features the pdi supports the following: ? rgb565, rgb666, 8 bit monochr ome format,ycbcr422 mode ? max input frequency of 32 mh z in 8/16/18 normal mode input ? max input frequency of 64 mhz in 8 bit muxed (narrow) mode. ? external synchronization usi ng hsync, vsync, and pdi_clk ? external synchronization using hs ync, vsync, dataen and pdi_clk ? internal synchronization using pdi_datain and pdi_clk is s upported for rgb565 and ycbcr422 muxed mode only. 12.8.2.4 normal and narrow mode in normal mode, pdi support maximum input freque ncy of 32 mhz. in narrow mode, pdi supports maximum input frequency of 64 mhz. table 12-66. supported rgb format and sync format rgb format data input bus 8-bit monochrome 8 bit rgb565 16 bit rgb666 18 bit rgb565 muxed 8 bit ycbcr 8 bit sync format pin used internal sync (valid only for rgb565 muxed mode) pclk external sync hsync, vsync, pclk external sync (with data en) hsync, vsync, pclk, de
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-111 preliminary?subject to change without notice figure 12-86. data transfer in normal and narrow mode the byte transferred first (msb or lsb) depends on the configuration re gister as shown in figure 12-86 .this would not effect the sync preamble sequence in case in ternal sync mode. on this device, the incoming rgb data is mapped onto the pdi pins as described in table 12-67 . table 12-67. mapping of rgb data onto pdi pins mode mapping normal (full 18-bit pdi inte rface) pdi[17:12] = r[5:0] pdi[11:6] = g[5:0] pdi[5:0] = b[5:0] normal (rgb565 16-bit pdi in terface) pdi[15:11] = r[4:0] pdi[[10:5] = g[5:0] pdi[4:0] = b[4:0] narrow (8-bit pdi interface) rgb565: in first clock cycle, pdi[7: 0] = { r[4:0], g[5:3] } in second clock cycle, pdi[ 7:0] = { g[2:0], b[4:0] } ycbcr: in first clock cycle, pd i[7:0] = { cb[7:0] } in second clock cycle, pdi[7:0] = { y0[7:0] } in third clock cycle, pdi[7:0] = { cr[7:0] } in forth clock cycle, pdi[7:0] = { y1[7:0] } 0x01 0x00 0x03 0x02 0x05 0x04 0x07 0x06 0x09 0x08 0x0b 0x0a 0x0d 0x0c 0x0f 0x0e 0x0100 0x0302 0x0504 0x0706 0x0908 0x0b0a 0x0d0c 0x0f0e pdi_data [15:0] rgb565 normal mode (pdi_clk = 64 mhz max) lsb pdi_data [7:0] pdi_clk pdi_clk rgb565 narrow mode (pdi_clk = 64 mhz max) lsb transferred first rgb565 narrow mode (pdi_clk = 64 mhz max) msb transferred first pdi_data [7:0] 0x01 0x00 0x03 0x02 0x05 0x04 0x07 0x06 0x09 0x08 0x0b 0x0a 0x0d 0x0c 0x0f 0x0e
pxd10 microcontroller reference manual, rev. 1 12-112 freescale semiconductor preliminary?subject to change without notice 12.8.2.5 modes of operation based on sync extraction 12.8.2.5.1 pdi input data (external sync mode) in external sync mode the timing signals (hsync , vsync and, optionally, da te enable) are provided the timing pins by the external video source. external sync mode can be used in both normal mode and 8-bit narrow mode. in the instance that external sync and narrow mode is selecte d, the external signals are used, a nd any timing information (eav/sav) embedded in the data stream is ignored. as in figure 12-88 , pdi data enable (pdi_de) should be low during vsync and hsync pulse, vsync front porch (fp_v) and back porch (bp_v) , hsync front porch (fp_h) and back porch (bp_h). this is valid for data enable mode when the pdi_de_en bit is set in the dcu_mode register (i.e. mode with hsync, vsync, data enable and pdi_clk as pin signals). pulse width, front and back porch va lues should be picked from those programmed in dcu registers. in order to achieve lock, it must have same value as that of tft screen. front porch and back porch value can be zero. pulse width and tft sc reen size parameters ca nnot be zero. in case th ey are programmed as zero, it might lead to malfunctioni ng of the validation state machine. as in figure 12-87 hsync must be coming during the vsync and v blanking period. gap between 2 hsync should be same during vsync and v blanki ng as during active line period. as in figure 12-87 positive edge of the hsync and vsync should be aligned. as in figure 12-87 the positive edge of the hsync and start of the vertical fr ont/back porch should be aligned. polarity of hsync and vsync are selectable. figure 12-87. relation between hsync and vsync in external synchronization pdi_hsync pdi_vsync end of last active line posedge of vsync and hsync are aligned start of first active line fp_v (vertical front porch) value = 2 (no of hsync) value = 2 (no of hsync) value = 2 (no of hsync) pw_v (vertical pulse width) bp_v (vertical back porch) vertical blanking period
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-113 preliminary?subject to change without notice figure 12-88. occurrence of hsync and vsync and dataen for the entire frame 12.8.2.5.2 pdi input data (i nternal sync extraction mode) in internal sync mode the timing pa rameters (horizontal and vertical bl anking) are encoded into the data stream. internal sync mode can only be used in 8-bit narrow mode. in figure 12-89 , xy is used to decode the vert ical and horizontal blanking period. table 12-68. xyh value bit value description 7 1'b1 always 1'b1. this is checked while decoding sync preamble 6 f not considered in the state machine logic 5 v 1'b1 during vertical blanking 1'b0 elsewhere 4 h 1'b0 for start of active video 1'b1 for end of active video invalid data 1 2 3 4 delta x invalid data pdi_clk pdi_datain pdi_hsync pdi_de data enable high during active data bp_h fp_h data enable in the horizontal resolution fp_h and bp_h is programmable through register pdi_clk invalid data 1 2 3 4 delta x invalid data pdi_datain pdi_vsync bp_v fp_v pdi_de
pxd10 microcontroller reference manual, rev. 1 12-114 freescale semiconductor preliminary?subject to change without notice figure 12-89. location of sync preamble in narrow mode sync preamble would come continuously for 4 clock cycles as shown in figure 12-89 . it would not depend upon which byte is coming first in data (msb or lsb) . sync extraction is done using pdi_datain [7:0]. sync extraction identifies the horizon tal and vertical blanki ng period using h and v field of the 'xyh' data as mentioned in table 12-68 . itu 656 sync preamble pattern (ffh 00h 00h) has to be masked out in the rgb and ycbcr data. the data stream must not include ffh 00h 00h as the valid pixel data to avoid malfunction by the validation state machine. horizontal blanking period must be coming during the vertical blanki ng period. gap between 2 horizontal blanking should be same during vert ical blanking period as during line active. all vertical and horizontal parameter values are validated against the dcu regi sters programmed by the user. polarity of hsync and vsync are selectable. horizontal blanking and vertical blanking must be aligned as shown in figure 12-90 . during blanking period it would ch eck for the 80h 10h 80h 10h sequence. this sequence would be present both during horizontal (line) blanking and vertical (frame) blanking period. framing bit (f field in xyh) w ould be ignored during extraction. ex traction is valid for rgb565 and ycbcr422 muxed mode. ecc error is only detected not corrected. it would be calculated using protection bits in table 12-68 same as external sync mode, value of front and back porche can be zero but pulse width and tft screen parameter cannot be zero. 3 2 1 0 p3 p2 p1 p0 protection bits (used to detect ecc errors). it would not be used for bit correction. table 12-68. xyh value (continued) bit value description ff 00 00 xy pdi_data [7:0] pdi_clk 16-bit rgb (narrow mode) with internal sync (representation ?1) note: preamble sequence is independent of data sequence
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-115 preliminary?subject to change without notice figure 12-90. relationship between hbla nk and vblank in internal sync 12.8.2.5.3 pdi ycbcr mode in this mode, the pdi ex tracts the itu656 sync (ff-00-00), and sends the video to the processing functions.the first processing function converts the 422 stream to a 444 stream, by providing interpolation on the chroma components of the stream depending on pdi_interpol _en bit. the se cond processing function converts the stream to rgb888/rgb565. the rgb pixel value is computed using following equations: eqn. 12-59 eqn. 12-60 eqn. 12-61 note that the first multiplication (i.e (y-16) *ycoeff) is unsigned, the two others are signed. the register values after reset are as follows: yred = 10?h254 (596/512 = 1.16) crred = 11?h331 (817/512 = 1.6) cbred = 12?h000 line 1 frame of image data line 480 frame blanking period sav 80 eav 9d eav b6 sav ab line blanking period note: the sav and eav bytes are included as part of the blanking period. red y16 ? ?? yred ? 512 ------------------------------------ - cr 128 ? ?? crred 512 ----------------------------------------- cb 128 ? ?? cbred 512 ------------------------------------------- ++ = green y16 ? ?? ygreen ? 512 -------------------------------------------- - cr 128 ? ?? crgreen 512 ----------------------------------------------- - cb 128 ? ?? cbgreen 512 ------------------------------------------------- - ++ = blue y16 ? ?? yblue ? 512 --------------------------------------- - cr 128 ? ?? crblue 512 -------------------------------------------- cb 128 ? ?? cbblue 512 ---------------------------------------------- ++ =
pxd10 microcontroller reference manual, rev. 1 12-116 freescale semiconductor preliminary?subject to change without notice ygreen = 10?h254(596/512 = 1.16) crgreen = 11?h660(-416/512 = -0.812) cbgreen = 12?hf38(-200/512 = -0.39) yblue = 10?h254(596/512 = 1.16) crblue = 11?h000 cbblue = 12?h409(1033/512 = 2.017) figure 12-91. ycbc r timing diagram 12.8.2.6 mode of operation depending on pdi_datain pdi supports following modes (other than the slave mode): ? 8-bit monochrome (8-bit input data, each pixel info is coming in 1 clocks) ? 16-bit - rgb565 (16-bit i nput data, each pixel info is coming in 1 clocks) ? 18-bit - rgb666 (18-bit i nput data, each pixel info is coming in 1 clocks) ? 16-bit - rgb565 (8-bit input data, each pixel info is coming in 2 clocks) ? 16-bit - ycbcr422 (8-bit input data, info for 2 co-sited pixels coming in 4 clocks) pdi_data [7:0] pdi_clk cb 0 y 0 cr 0 y 1 y 2 y 4 y 5 y 6 cb 1 y 3 cb 2 cb 3 cr 1 cr 2 cr 3 y 0 y 1 y 2 y 4 y 3 cb 0 ? cb 1 ? cb 2 ? cb 3 ? cb 4 ? cr 0 ? cr 1 ? cr 2 ? cr 3 ? cr 4 ? cb n ? = cb n/2 y_data[7:0] cb_data[7:0] cr_data[7:0] (cb (n-1)/2 ? + cb (n+1)/2 )/2 cr n ? = cr n/2 (cr (n-1)/2 ? + cr (n+1)/2 )/2 rgb888 ycbcr_pulse rgb_valid for even n for even n for odd n for odd n
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 12-117 preliminary?subject to change without notice data info extraction is given in table 12-69 . the 8-bit monochrome image is equivalent to 8-bi t grayscale images. for c onverting 8-bit monochrome data to rgb data, each of the r/g/b components will have a value equal to the 8-bit monochrome value. rgb extraction starts when pdi is enabled (from the next falling edge of va lidated vertical blanking period) 12.8.2.7 pdi-related interrupts pdi can be configured to trigger an interrupt when synchronization is achieved i.e. it receives the prespecified numbers of fr ames without error. pdi w ould also give an interrupt when synchronization is lost i.e. it receives any error in frame there after. this interrupt is raised when hsync/vsync is lost. correctable ecc error interrupts fo r errors during extraction of pream bles. no error correction is done. non-correctable ecc error interrupt for the preamble errors that cannot be corrected. blanking sequence error is received in case 80h 10h is not found in vert ical and line blanking period during internal synchronization. activity detection interrupt for clk detection. hsync activity detection interrupts. it would be generated from the state machine. vsync activity detection interrupts. it would also be generated from the state machine. activity detection interrupt for data enable. activity lost interrupt for clk ? for clk lost interrupt, it is assumed that ipg_clk would be active for entire duration, if pdi_clk_frequency is less than or equal to ipg clock frequency/32, then the interrupt is trigge red. (i.e. if ipg_clk freq. max = 64 mhz then the pdi_clk_lost flag will be set if pdi clk freq. min < 2 mhz). all interrupts are rw1c (w rite one to clear). all interrupts are maskable. pdi must reset to show the latest status of the clock activity detect interrupt. 12.9 dcu initialization the following steps describe a t ypical approach to initializing the dcu for use in an application. 1. after reset configure the dcu peripheral to be active using the mode entr y module and configure the dcu clock source in the mc_cgm. table 12-69. data extraction in all possible modes pdi mode narrow mode pins rgb data notes 8-bit monochrome mode 1'b0 8 bit pdi_datain ? rgb565 1'b0 16 bit pdi_datain ? rgb666 1'b0 18 bit pdi_datain ? rgb565 muxed 1'b1 8 bit pdi_datain data from two clocks are combined. ycbcr422 1?b1 8 bit pdi_datain data from four clocks are combined for two pixels.
pxd10 microcontroller reference manual, rev. 1 12-118 freescale semiconductor preliminary?subject to change without notice 2. configure the output ports in the siul as required. 3. configure the timing registers to match the tft lcd panel in use ( section 12.4.2, tft lcd panel configuration ?). 4. set the background color as required. 5. load the initial tile or palette colors into the clut/tile memory 6. configure the control descriptors for the layers and cursor that are to be used initially 7. enable the dcu in the appropriate m ode (dcu_mode and raster_en bit fields). 12.10 glossary table 12-70. glossary argb a data format where the pixel values are stor ed using four components: alpha, red, green and blue. dcu supports different variations of this fo rmat where different numbers of bits can be used to represent each of the components component part of a pixel that contains a single color (red, green or blue) clut color look-up table. the table that contains the palette used by an indexed-color graphic direct color the full 18-bit value actually written to a pixel to create a color frame the collection of all pixels on a panel gamut the set of colors that a panel can display. in most cases a panel cannot display the full gamut of colors visible to the human eye. indexed color an index into a table containing direct-colors. usually smaller in size than the direct color; the dcu provides 1, 2, 4, and 8 bits per pixel options palette the list of colors used by a graphic when an indexed colors format is used. the palette is stored in a color look up table and can be from one color up to the maximum of the size of the clut. panel a tft lcd containing an array of colored pixels. pixel the basic graphical element on a tft lcd panel. can display a range of colors depending on the value of the red, green and blue values written to it. normally arranged in a rectangular array. ram fifo a 16-entry buffer that allows writes to the dcu rams during the tft lcd panel refresh period rgb a data format where the pixel values are stor ed using three components: red, green and blue. dcu supports different variations of this format where different numbers of bits can be used to represent each of the components vertical blanking period a time during the tft lcd panel refresh cycle when no data is bei ng written to the panel
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 13-1 preliminary?subject to change without notice chapter 13 dma channel mux (dmachmux) 13.1 introduction 13.1.1 overview the dmachmux controls the routing of multiple dma peripheral sources (called slots) to 16 dma channels. this is illustrated in figure 13-1 . figure 13-1. dmachmux block diagram 13.1.2 features the dmachmux provide s these features: ? 48 peripheral slots + 4 always-on slots can be routed to 16 channels ? 16 independently-selectabl e dma channels routers ? the first 4 channels additionally provide a trigger functionality source #1 source #2 source #3 dma channel #1 dma channel #0 dmachmux always #1 trigger #1 dma channel # 15 trigger # 4 always # 4 source #63
pxd10 microcontroller reference manual, rev. 1 13-2 freescale semiconductor preliminary?subject to change without notice ? each channel router can be assigned to one of 48 possible peri pheral dma slots or to one of the 4 always-on slots. 13.1.3 modes of operation the following operation modes are available: ? disabled mode in this mode, the dma channel is disabled. sinc e disabling and enabling of dma channels is done primarily via the dma conf iguration registers, this mode is us ed mainly as the reset state for a dma channel in the dma channel mux. it may al so be used to temporarily suspend a dma channel while reconfiguration of the system takes place (e.g. changing the period of a dma trigger). ? normal mode in this mode, a dma source (such as dspi transmit or dspi rece ive for example) is routed directly to the specified dma channel. the operation of the dma mux in this mode is completely transparent to the system. ? periodic trigger mode in this mode, a dma source may only request a dma transfer (such as when a transmit buffer becomes empty or a receive buffer becomes full) periodically. conf iguration of th e period is done in the registers of the periodic in terrupt timer (pit). this mode is only available fo r channels 0-4. 13.2 external signal description 13.2.1 overview the dma channel mux has no external pins. 13.3 memory map and register definition this section provides a detailed description of al l memory-mapped registers in the dma channel mux. table 13-1 shows the memory map for the dma channel m ux. note that all addresses are offsets; the absolute address may be computed by adding the specified offset to th e base address of the dma channel mux. table 13-1. module memory map address use access location base + 0x00 channel #0 configuration (chconfig0) r/w on page 3 base + 0x01 channel #1 configuration (chconfig1) r/w on page 3 .. .. .. .. base + 0x #n-1 channel #n configuration (chconfig #n-1 ) 1 1 in the table n refers to the number of channels - 1 r/w on page 3
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 13-3 preliminary?subject to change without notice all registers are accessible via 8-bit, 16-bit or 32-bit accesses. ho wever, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. as an example, chconfig0 through chconfig3 are accessible by a 32-bit read/write to address ?base + 0x00?, but performing a 32-bit access to address ?base + 0x01? is illegal. 13.3.1 register descriptions the following memory-mapped registers are available in the dma channel mux. 13.3.1.1 channel configuration registers each of the dma channels can be independently enab led/disabled and associat ed with one of the dma slots (peripheral slots or alwa ys-on slots) in the system. address: base + #n access: user read/write 01234567 r enbl trig source w reset00000000 figure 13-2. channe l configuration re gisters (chconfig #n ) table 13-2. chconfig xx field descriptions field description enbl dma channel enable. enbl enables the dma channel 0 dma channel is disabled. this mode is primarily used during configuration of the dma mux. the dma has separate channel enables/disables, which should be used to disable or re-configure a dma channel. 1 dma channel is enabled trig dma channel trigger enable (for triggered channels only). trig enables the periodic trigger capability for the dma channel 0 triggering is disabled. if triggering is disabled, and the enbl bit is set, the dma channel will simply route the specified source to the dma channel. 1 triggering is enabled source dma channel source (slot). source specifies whic h dma source, if any, is routed to a particular dma channel. please check your soc-guide for further details about the peripherals and their slot numbers. table 13-3. channel and trigger enabling enbl trig function mode 0 x dma channel is disabled disabled mode 1 0 dma channel is enabled with no triggering (transparent) normal mode 1 1 dma channel is enabled with triggering periodic trigger mode
pxd10 microcontroller reference manual, rev. 1 13-4 freescale semiconductor preliminary?subject to change without notice note setting multiple chconfig registers with the same source value will result in unpredictable behavior. note before changing the trigger or sour ce settings a dma ch annel must be disabled via the chconfig[ #n ].enbl bit. table 13-4. dmachmux request assignments dma requesting module dmachmux source number (ipd_ref_peripher[n periphs :1]) channel disable 1 0 dspi_0 tx 1 dspi_0 rx 2 dspi_1 tx 3 dspi_1 rx 4 quadspi_0 tfff 5 quadspi_0 rfdf / rbdf 6 i2c_0_tx 7 i2c_0_rx 8 i2c_1_tx 9 i2c_1_rx 10 i2c_2_tx 11 i2c_2_rx 12 i2c_3_tx 13 i2c_3_rx 14 emios200_0_flag_f0 15 emios200_0_flag_f1 16 emios200_0_flag_f2 17 emios200_0_flag_f3 18 emios200_0_flag_f4 19 emios200_0_flag_f5 20 emios200_0_flag_f6 21 emios200_0_flag_f7 22 emios200_0_flag_f8 23 emios200_0_flag_f9 24 emios200_0_flag_f10 25
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 13-5 preliminary?subject to change without notice emios200_0_flag_f11 26 emios200_0_flag_f12 27 emios200_0_flag_f13 28 emios200_0_flag_f14 29 emios200_0_flag_f15 30 emios200_1_flag_f0 31 emios200_1_flag_f1 32 emios200_1_flag_f2 33 emios200_1_flag_f3 34 emios200_1_flag_f4 35 emios200_1_flag_f5 36 emios200_1_flag_f6 37 emios200_1_flag_f7 38 reserved 39 reserved 40 reserved 41 reserved 42 reserved 43 reserved 44 reserved 45 reserved 46 siu_eisr_eif1 47 siu_eisr_eif2 48 siu_eisr_eif3 49 siu_eisr_eif4 50 adc 51 reserved 52 dcu 53 reserved 54 reserved 55 always requestors 56 always requestors 57 table 13-4. dmachmux request assignments (continued) dma requesting module dmachmux source number (ipd_ref_peripher[n periphs :1])
pxd10 microcontroller reference manual, rev. 1 13-6 freescale semiconductor preliminary?subject to change without notice 13.4 functional description this section provides a functional description of the dma channel mux. the primary purpose of the dma channel mux is to provide flex ibility in the system?s use of th e available dma channels. as such, configuration of the dma mux is intended to be a static procedure done duri ng execution of the system boot code. however, if the procedure outlined in section 13.5.2, enabling and configuring sources , is followed, the configuration of th e dma channel mux may be changed during the normal operation of the system. functionally, the dma channel mux channels may be divided into two classes: channels, which implement the normal routing functionality plus periodic triggering capability, and channels, which implement only the normal routing functionality. 13.4.1 dma channels with peri odic triggering capability besides the normal routing functionalit y, the first 4 channels of the dma mux provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames or packets at fixed intervals without the need for pr ocessor intervention. the trigger is generated by the periodic interrupt timer (pit); as such, the configuration of the peri odic triggering interval is done via configuration registers in the pit. please refer to chapter 27, periodic interrupt timer (pit), for more information on this topic. table 13-5 shows the mapping of pit channels to dma channels for triggering. always requestors 58 always requestors 59 always requestors 60 always requestors 61 always requestors 62 always requestors 63 1 configuring a dma channel to select source 0 or any reserved sources will disable that dma channel. table 13-5. pit-dma channel mapping pit channel number dmachmux channel number for triggering 00 11 22 33 table 13-4. dmachmux request assignments (continued) dma requesting module dmachmux source number (ipd_ref_peripher[n periphs :1])
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 13-7 preliminary?subject to change without notice note because of the dynamic nature of the system (i.e. dma ch annel priorities, bus arbitration, interrupt service routin e lengths, etc.), the number of clock cycles between a trigger and the actual dma transf er cannot be guaranteed. figure 13-3. dma mux triggered channels the dma channel triggering capability allows the syst em to ?schedule? regula r dma transfers, usually on the transmit side of certain periphe rals, without the intervention of th e processor. this trigger works by gating the request from the peripheral to the dma until a trigger event has been s een. this is illustrated in figure 13-4 . figure 13-4. dma mux channel triggering: normal operation dma channel #0 tr i g g e r # 1 tr i g g e r # 0 source #1 source #2 source #3 always #1 dma channel # 3 always # 4 trigger #3 source # 63 periph request tr i g g e r dma request
pxd10 microcontroller reference manual, rev. 1 13-8 freescale semiconductor preliminary?subject to change without notice once the dma request has been servic ed, the peripheral will negate its request, effectively resetting the gating mechanism until the periphe ral re-asserts its request and the next trigger event is seen. this means that if a trigger is seen, but the peripheral is not reque sting a transfer, that trigge red will be ignored. this situation is illustrated in figure 13-5 . figure 13-5. dma mux channel triggering: ignored trigger this triggering capability may be used with any periphe ral that supports dma transf ers, and is most useful for two types of situations: ? periodically polling external devices on a particular bus. as an exampl e, the transmit side of an spi is assigned to a dma channel with a trigger, as described above. once setup, the spi will request dma transfers (presumably from memory) as long as its transmit buffer is empty. by using a trigger on this channel, the spi transfer s can be automatically performed every 5 ? s (as an example). on the receive side of the spi, the spi and dma can be configured to transfer receive data into memory, effectively implementing a met hod to periodically read data from external devices and transfer the results into memory without processor intervention. ? using the gpio ports to drive or sample waveform s. by configuring the dma to transfer data to one or more gpio ports, it is possible to create complex waveforms using ta bular data stored in on-chip memory. conversely, using the dma to peri odically transfer data from one or more gpio ports, it is possible to sample co mplex waveforms and store the resu lts in tabular form in on-chip memory. a more detailed description of the capability of each trigger (i.e.-resolu tion, range of values, etc.) may be found in the periodic interrupt timer (pit) block guide. 13.4.2 dma channels with no triggering capability the other channels of the dma mux provide the normal routing functionali ty as described in section 13.1.3, modes of operation . 13.4.3 "always enabled" dma sources in addition to the peripherals that can be used as dma sources, there are 4 a dditional dma sources that are "always enabled". unlike the peri pheral dma sources, where the peripheral controls the flow of data during dma transfers, the "always enabled" sources pr ovide no such "throttling" of the data transfers. these sources are most useful in the following cases: ? doing dma transfers to/from gpio - moving data from/to one or more gpio pins, either un-throttled (i.e.-as fast as possible), or pe riodically (using the dma triggering capability). periph request tr i g g e r dma request
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 13-9 preliminary?subject to change without notice ? doing dma transfers from memory to memory - moving data from memory to memory, typically as fast as possible, sometimes with software activation. ? doing dma transfers from memory to the external bus (or vice-versa) - similar to memory to memory transfers, this is typi cally done as quickly as possible. ? any dma transfer that requires so ftware activation - any dma transf er that should be explicitly started by software. in cases where software s hould initiate the start of a dma transfer, a "always enabled" dma source can be used to provide maximum flexibility. when activating a dma channel via software, subsequent executions of the minor loop require a new "start" ev ent be sent. this can ei ther be a new software activation, or a transfer request from the dm a channel mux. the opti ons for doing this are: ? transfer all data in a si ngle minor loop. by configuring the dma to transfer all of the data in a single minor loop (i.e.-major loop counter = 1), no re-activation of the channel is necessary. the disadvantage to this option is the reduced granularity in determining the load that the dma transfer will incur on the system. for this option, the dma channel should be disabl ed in the dma channel mux. ? use explicit software re-activati on. in this option, the dma is confi gured to transfer the data using both minor and major loops, but the processor is re quired to re-activate the channel (by writing to the dma registers) after every minor loop . for this option, the dma channel should be disabled in the dma channel mux. ? use a "always enabled" dma source. in this opti on, the dma is configured to transfer the data using both minor and major loops, and the dma channel mux does the channel re-activation. for this option, the dma channe l should be enabled and pointing to an "always enabled" source. note that the re-activation of the chan nel can be continuous (dma trigge ring is disabled) or can use the dma triggering capability. in this manner, it is possible to execute periodic transfers of packets of data from one source to another, without processor intervention. 13.5 initialization/application information 13.5.1 reset the reset state of each individua l bit is shown within the regi ster description section (see section 13.3.1, register descriptions ). in summary, after reset, all channels ar e disabled and must be explicitly enabled before use. 13.5.2 enabling and configuring sources enabling a source with periodic triggering 1. determine with which dma channel the source will be associated. note th at only the first 4 dma channels have periodi c triggering capability. 2. clear the enbl and trig bits of the dma channel 3. ensure that the dma channel is properly conf igured in the dma. the dma channel may be enabled at this point
pxd10 microcontroller reference manual, rev. 1 13-10 freescale semiconductor preliminary?subject to change without notice 4. configure the corresponding timer 5. select the source to be routed to the dm a channel. write to the corresponding chconfig register, ensuring that the enbl and trig bits are set example 13-1. configure source #5 transmit for use with dma channel 2, with peri odic triggering capability 1. write 0x00 to chconfig2 (base address + 0x02) 2. configure channel 2 in the dm a, including enabling the channel 3. configure a timer for the desired trigger interval 4. write 0xc5 to chconfig2 (base address + 0x02) the following code example il lustrates steps #1 and #4 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8-bits */ volatile unsigned char *chconfig0 = (volatile unsigned char *) (dmamux_base_addr+0x0000); volatile unsigned char *chconfig1 = (volatile unsigned char *) (dmamux_base_addr+0x0001); volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); volatile unsigned char *chconfig3 = (volatile unsigned char *) (dmamux_base_addr+0x0003); volatile unsigned char *chconfig4 = (volatile unsigned char *) (dmamux_base_addr+0x0004); volatile unsigned char *chconfig5 = (volatile unsigned char *) (dmamux_base_addr+0x0005); volatile unsigned char *chconfig6 = (volatile unsigned char *) (dmamux_base_addr+0x0006); volatile unsigned char *chconfig7 = (volatile unsigned char *) (dmamux_base_addr+0x0007); volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); volatile unsigned char *chconfig9 = (volatile unsigned char *) (dmamux_base_addr+0x0009); volatile unsigned char *chconfig10= (volatile unsigned char *) (dmamux_base_addr+0x000a); volatile unsigned char *chconfig11= (volatile unsigned char *) (dmamux_base_addr+0x000b); volatile unsigned char *chconfig12= (volatile unsigned char *) (dmamux_base_addr+0x000c); volatile unsigned char *chconfig13= (volatile unsigned char *) (dmamux_base_addr+0x000d); volatile unsigned char *chconfig14= (volatile unsigned char *) (dmamux_base_addr+0x000e); volatile unsigned char *chconfig15= (volatile unsigned char *) (dmamux_base_addr+0x000f); in file main.c: #include "registers.h" : : *chconfig2 = 0x00; *chconfig2 = 0xc5; enabling a source without periodic triggering 1. determine with which dma channel the source will be associated. note th at only the first 4 dma channels have periodi c triggering capability. 2. clear the enbl and trig bits of the dma channel 3. ensure that the dma channel is properly conf igured in the dma. the dma channel may be enabled at this point 4. select the source to be routed to the dm a channel. write to the corresponding chconfig register, ensuring that the enbl is set and the trig bit is cleared
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 13-11 preliminary?subject to change without notice example 13-2. configure source #5 transmit for use with dma channel 2, with no periodic triggering capability. 1. write 0x00 to chconfig2 (base address + 0x02) 2. configure channel 2 in the dm a, including enabling the channel 3. write 0x85 to chconfig2 (base address + 0x02) the following code example il lustrates steps #1 and #3 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8-bits */ volatile unsigned char *chconfig0 = (volatile unsigned char *) (dmamux_base_addr+0x0000); volatile unsigned char *chconfig1 = (volatile unsigned char *) (dmamux_base_addr+0x0001); volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); volatile unsigned char *chconfig3 = (volatile unsigned char *) (dmamux_base_addr+0x0003); volatile unsigned char *chconfig4 = (volatile unsigned char *) (dmamux_base_addr+0x0004); volatile unsigned char *chconfig5 = (volatile unsigned char *) (dmamux_base_addr+0x0005); volatile unsigned char *chconfig6 = (volatile unsigned char *) (dmamux_base_addr+0x0006); volatile unsigned char *chconfig7 = (volatile unsigned char *) (dmamux_base_addr+0x0007); volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); volatile unsigned char *chconfig9 = (volatile unsigned char *) (dmamux_base_addr+0x0009); volatile unsigned char *chconfig10= (volatile unsigned char *) (dmamux_base_addr+0x000a); volatile unsigned char *chconfig11= (volatile unsigned char *) (dmamux_base_addr+0x000b); volatile unsigned char *chconfig12= (volatile unsigned char *) (dmamux_base_addr+0x000c); volatile unsigned char *chconfig13= (volatile unsigned char *) (dmamux_base_addr+0x000d); volatile unsigned char *chconfig14= (volatile unsigned char *) (dmamux_base_addr+0x000e); volatile unsigned char *chconfig15= (volatile unsigned char *) (dmamux_base_addr+0x000f); in file main.c: #include "registers.h" : : *chconfig2 = 0x00; *chconfig2 = 0x85; disabling a source a particular dma source may be disabled by not writing the correspon ding source value into any of the chconfig registers. additionally, some module spec ific configuration may be necessary. please refer to the appropriate section for more details. switching the source of a dma channel 1. disable the dma channel in the dma and re-configure the channel for the new source 2. clear the enbl and trig bits of the dma channel 3. select the source to be routed to the dm a channel. write to the corresponding chconfig register, ensuring that the enbl and trig bits are set example 13-3. switch dma channel 8 from source #5 transmit to source #7 transmit 1. in the dma configuration registers, disable dma channel 8 and re-con figure it to handle the transfers to peripheral slot 7. this example assu mes channel 8 doesn?t have triggering capability.
pxd10 microcontroller reference manual, rev. 1 13-12 freescale semiconductor preliminary?subject to change without notice 2. write 0x00 to chconfig8 (base address + 0x08) 3. write 0x87 to chconfig8 (base ad dress + 0x08). (in this example, setting the tr ig bit would have no effect, due to the assumption that ch annels 8 does not support the periodic triggering functionality). the following code example il lustrates steps #2 and #4 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8-bits */ volatile unsigned char *chconfig0 = (volatile unsigned char *) (dmamux_base_addr+0x0000); volatile unsigned char *chconfig1 = (volatile unsigned char *) (dmamux_base_addr+0x0001); volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); volatile unsigned char *chconfig3 = (volatile unsigned char *) (dmamux_base_addr+0x0003); volatile unsigned char *chconfig4 = (volatile unsigned char *) (dmamux_base_addr+0x0004); volatile unsigned char *chconfig5 = (volatile unsigned char *) (dmamux_base_addr+0x0005); volatile unsigned char *chconfig6 = (volatile unsigned char *) (dmamux_base_addr+0x0006); volatile unsigned char *chconfig7 = (volatile unsigned char *) (dmamux_base_addr+0x0007); volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); volatile unsigned char *chconfig9 = (volatile unsigned char *) (dmamux_base_addr+0x0009); volatile unsigned char *chconfig10= (volatile unsigned char *) (dmamux_base_addr+0x000a); volatile unsigned char *chconfig11= (volatile unsigned char *) (dmamux_base_addr+0x000b); volatile unsigned char *chconfig12= (volatile unsigned char *) (dmamux_base_addr+0x000c); volatile unsigned char *chconfig13= (volatile unsigned char *) (dmamux_base_addr+0x000d); volatile unsigned char *chconfig14= (volatile unsigned char *) (dmamux_base_addr+0x000e); volatile unsigned char *chconfig15= (volatile unsigned char *) (dmamux_base_addr+0x000f); in file main.c: #include "registers.h" : : *chconfig8 = 0x00; *chconfig8 = 0x87;
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 14-1 preliminary?subject to change without notice chapter 14 e200z0h core 14.1 overview the e200 processor family is a set of cpu core s that implement low-cost versions of the power architecture ? book e architecture. e200 processors are designed for deeply embedded control applications which require low cost solutions rather than maximum performance. the processors integrate an intege r execution unit, branch control unit, instruction fetch and load/store units, and a multi-ported register file capable of su staining three read and two write operations per clock. most integer instructions execute in a single clock cy cle. branch target prefet ching is performed by the branch unit to allow single-cycle branches in some cases. the e200z0h core is a single-issue, 32-bit powerpc book e vle-only design with 32-bit general purpose registers (gprs). all arithmetic inst ructions that execute in the core operate on data in the general purpose registers (gprs). instead of the base powerpc book e instruction se t support, the e200z0h core only implements the vle (variable-length encoding) apu, providing improved c ode density. the vle apu is further documented in the powerpc? vle apu definition , a separate document. 14.2 features the following is a list of some of the key features of the e200z0h core: ? 32-bit power architecture book e programmer?s model ? single issue, 32-bit cpu ? implements the vle apu for reduced code footprint ? in-order execution and retirement ? precise exception handling ? branch processing unit ? dedicated branch address calculation adder ? branch acceleration using br anch target buffer (btb) ? supports independent instruction and data accesse s to different memory subsystems, such as sram and flash memory via independent instru ction and data bus in terface units (bius). ? load/store unit ? 1 cycle load latency ? fully pipelined ? big-a and little-endian support ? misaligned access support ? zero load-to-use pipeline bu bbles for ali gned transfers ? power management
pxd10 microcontroller reference manual, rev. 1 14-2 freescale semiconductor preliminary?subject to change without notice ? low power design ? power saving modes: doze, nap, sleep, and wait ? dynamic power management of execution units ? testability ? synthesizeable, full muxd scan design ? abist/mbist for optional memory arrays 14.2.1 microarchitecture summary the e200z0h processor utilizes a four stage pipeline for instruction ex ecution. the instruction fetch (stage 1), instruction decode/reg ister file read/effective address ca lculation (stage 2), execute/memory access (stage 3), and regist er writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. the integer execution unit consists of a 32-bit arithmet ic unit (au), a logic unit (lu), a 32-bit barrel shifter (shifter), a mask-inserti on unit (miu), a condition regist er manipulation unit (cru), a count-leading-zeros unit (clz), a 32x32 hardware multiplier array, resu lt feed-forward hardware, and a hardware divider. arithmetic and logical operations are executed in a single cycle with the exception of the divide instructions. a count-leading-zeros uni t operates in a single clock cycle. the instruction unit contains a pc incrementer and a dedicated branch address a dder to minimize delays during change of flow operations. se quential prefetching is performed to ensure a supply of instructions into the execution pipeline. branch target prefetch ing from the btb is performed to accelerate certain taken branches in the e200z0h. prefetched instructions are placed into an instru ction buffer with 4 entries in e200z0h, each capable of holding a single 32-bit instruction or a pair of 16-b it instructions. conditional branches which are not ta ken execute in a single clock. br anches with successful target prefetching have an effectiv e execution time of one clock. allother taken branch es have an execution time of two clocks. memory load and store operations are provided for byte, halfword, and word (32-bi t) data with automatic zero or sign extension of byte and halfword load da ta as well as optional byte reversal of data. these instructions can be pipelined to allow effective single cycle throughput. load and store multiple word instructions allow low overhead context save and restore operations. the load /store unit contains a dedicated effective address adder to allow effective addres s generation to be optimi zed. also, a load-to-use dependency does not incur any pipeline bubbles for most cases. the condition register unit supports the condition regi ster (cr) and condition re gister operations defined by the powerpc? architecture. the condi tion register consists of eight 4-bit fields th at reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. vectored and autovectored interrupt s are supported by the cpu. vectored interrupt support is provided to allow multiple interrupt sources to have unique in terrupt handlers invoked with no software overhead.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 14-3 preliminary?subject to change without notice 14.2.1.1 block diagram figure 14-1. e200z0h block diagram 14.2.1.2 instruction unit features the features of the e200z0h instruction unit are: ? 32-bit instruction fetch path s upports fetching of one 32-bit inst ruction per clock, or up to two 16-bit vle instructions per clock ? instruction buffer with 4 entries in e200zh0, each holding a single 32-bit inst ruction, or a pair of 16-bit instructions cpu control logic load/ data nexus debug unit address store unit instruction unit branch unit pc unit instruction buffer gpr cr spr multiply unit data bus interface unit control 32 32 n once/nexus control logic interface control data (mtspr/mfspr) integer execution unit external spr ctr xer lr data address instruction bus interface unit control 32 32 n
pxd10 microcontroller reference manual, rev. 1 14-4 freescale semiconductor preliminary?subject to change without notice ? dedicated pc incrementer s upporting instruction prefetches ? branch unit with dedicated branch address adder, and small bran ch target buffer logic supporting single cycle of execution of certain branches, two cycles for all others 14.2.1.3 integer unit features the e200 integer unit supports single cycle ex ecution of most integer instructions: ? 32-bit au for arithmetic and comparison operations ? 32-bit lu for logical operations ? 32-bit priority encoder for count leading zero?s function ? 32-bit single cycle barrel sh ifter for shifts and rotates ? 32-bit mask unit for data masking and insertion ? divider logic for signed and uns igned divide in 5-34 clocks with minimized execution timing ? 32x32 hardware multiplier array supports 1 to 4 cycles 32x32->32 multiply (early out) 14.2.1.4 load/store unit features the e200 load/store unit supports lo ad, store, and the load multiple / store multiple instructions: ? 32-bit effective address adder fo r data memory address calculations ? pipelined operation supports throughput of one load or store operation per cycle ? 32-bit interface to memory (dedicated memory interface on e200z0h) 14.2.1.5 e200z0h system bus features the features of the e200z0h system bus interface are as follows: ? independent instruction and data buses ? amba ahb lite rev 2.0 specification w ith support for arm v6 amba extensions ? exclusive access monitor ? byte lane strobes ? cache allocate support ? 32-bit address bus plus attr ibutes and control on each bus ? 32-bit read data bus for instruction interface ? separate uni-directional 32-bit r ead data bus and 32-bit write data bus for data interface ? overlapped, in-order accesses 14.3 core registers and programmer?s model this section describes the register s implemented in the e200z0h core. it includes an overview of registers defined by the powerpc book e arch itecture, highlighting difference s in how these registers are implemented in the e200 core, and provides a detail ed description of e200- specific registers. full descriptions of the architecture -defined register set are provide d in the power architecture book e specification.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 14-5 preliminary?subject to change without notice the power architecture book e defines register-to-regi ster operations for all co mputational instructions. source data for these instructions are accessed from the on-chip registers or are provided as immediate values embedded in the opcode. the th ree-register instruction format allows specification of a target register distinct from the two s ource registers, thus preserving the original data for use by other instructions. data is transferred be tween memory and registers with expl icit load and store instructions only. figure 14-2 and figure 14-3 show the e200 register set including the registers which are accessible while in supervisor mode, and the registers which are acces sible in user mode. the number to the right of the special-purpose registers (spr s) is the decimal number used in the in struction syntax to access the register (for example, the integer except ion register (xer) is spr 1). note e200z0h is a 32-bit implementation of the power architecture book e specification. in this document, regist er bits are sometimes numbered from bit 0 (most significant bit) to 31 (lea st significant bit), rather than the book e numbering scheme of 32:63, thus register bit numbers for some registers in book e are 32 higher. where appropriate, the book e defi ned bit numbers are shown in parentheses.
pxd10 microcontroller reference manual, rev. 1 14-6 freescale semiconductor preliminary?subject to change without notice figure 14-2. e200z0h superviso r mode program model sprs spr general exception handling/control registers save and restore machine state msr pvr processor control registers sprg0 sprg1 spr 272 spr 273 srr0 srr1 csrr0 csrr1 dsrr0 1 dsrr1 1 spr 26 spr 27 spr 58 spr 59 spr 574 spr 575 processor id pir spr 286 interrupt vector prefix ivpr spr 63 debug registers 2 debug control dbcr0 dbcr1 dbcr2 dbcr3 1 spr 308 spr 309 spr 310 spr 561 instruction address compare iac1 iac2 iac3 iac4 spr 312 spr 313 spr 314 spr 315 data address compare dac1 dac2 spr 316 spr 317 1 - these e200-specific registers may not be supported by other powerpc processors 2 - optional registers defined by the powerpc book-e architecture 3 - read-only registers processor version hardware implementation dependent 1 hid0 hid1 spr 1008 spr 1009 cache registers spr 9 general-purpose registers count register ctr spr 8 link register lr condition register cr gpr0 gpr1 gpr31 spr 515 cache configuration (read-only) l1cfg0 spr 1 xer xer general registers spr 287 debug status dbsr spr 304 system version 1 svr spr 1023 esr spr 62 exception syndrome data exception address dear spr 61 machine check syndrome register mcsr spr 572 btb control 1 spr 1013 bucsr btb register memory management registers process id pid0 spr 48 configuration (read only) spr 1015 mmucfg dvc1 dvc2 spr 318 spr 319
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 14-7 preliminary?subject to change without notice figure 14-3. e200z0h user mode program model 14.3.1 unimplemented sprs and read-only sprs e200z0h fully decodes the spr field of the mfspr and mtspr instructions. if the sp r specified is undefined and not privileged, an ille gal instruction exception is generated. if the spr specified is undefined and privileged and the cpu is in user mode (msr[pr=1]), a privileged in struction exception is generated. if the spr specified is undefined and privileged and the co re is in supervisor mode (msr[pr=0]), an illegal instruction exception is generated. for the mtspr instruction, if the spr specified is read-onl y and not privileged, an illegal instruction exception is generated. if the spr specified is read-only and privileg ed and the core is in user mode (msr[pr=1]), a privileged instruct ion exception is generated. if th e spr specified is read-only and privileged and the core is in supervisor mode (msr[p r=0]), an illegal instruction exception is generated. 14.4 instruction summary e200z0h supports all vle instru ctions described in the powerpc? vle apu definition version 1.2 together with the additional instru ctions for context save/restore. user mode program model spr 515 cache configuration l1cfg0 cache register (read-only) spr 9 general-purpose registers count register ctr spr 8 link register lr condition register cr gpr0 gpr1 gpr31 spr 1 xer xer general registers
pxd10 microcontroller reference manual, rev. 1 14-8 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-1 preliminary?subject to change without notice chapter 15 enhanced direct memory access (edma) 15.1 introduction the dma (direct memory acce ss) is a second-generation platfo rm module capable of performing complex data transfers with minimal in tervention from a hos t processor via ? n ? programmable channels. intended for use as part of the st andard product platform (spp), the ha rdware microarchitecture includes a dma engine which performs source and destination address calculati ons, and the actual data movement operations, along with a loca l memory containing the transfer control descriptors (tcd) for the channels. this sram-based implementation is used to minimize the overall module size. figure 15-1 is a block diagram of the dma module. figure 15-1. dma block diagram j j+1 n-1 sram transfer control descriptor (tcd) dma engine addr_path data_path dma ips bus amba ahb ipd_req[n-1:0] dma_ipi_int[n-1:0] 0 c o n t r o l pmodel_charb addr wdata[31:0] rdata[31:0] hrdata[{63,31}:0] hwdata[{63,31}:0] haddr[31:0] bus 64 dma_ipd_done[n-1:0]
pxd10 microcontroller reference manual, rev. 1 15-2 freescale semiconductor preliminary?subject to change without notice 15.1.1 overview the dma is a highly-programmable da ta transfer engine, which has been optimized to minimize the required intervention from the host pro cessor. it is intended for use in a pplications where the data size to be transferred is st atically known, and is not defined within the data pack et itself. the dma hardware supports: ? single design supporting 16-, 32- and 64-channel implementati ons, dependent on size of the tcd memory and design parameters ? connections to the amba-ahb crossbar switch for bus mastering the da ta movement, slave bus for programming the module ? parameterized support for 32- and 64-bit amba-ahb datapath widths ? 32-byte transfer control descriptor per channel stored in local memory ? 32 bytes of data registers, used as te mporary storage to support burst transfers throughout this document, n is used to reference the channel numbe r. additionally, data sizes are defined as byte (8-bit), halfword (16-bit), word (32-bit) and doubleword (64-bit). 15.1.2 features the dma module supports the following features: ? 16 programmable channels ? all data movement via dual-address transfer s: read from source, write to destination ? programmable source, destinat ion addresses, transfer size, plus support for enhanced addressing modes ? transfer control descriptor organized to support two-deep, nested transfer operations ?an inner data transfer loop defined by a ?minor? byte transfer count ?an outer data transfer loop define d by a ?major? iteration count ? channel service request via one of three methods: ? explicit software initiation ? initiation via a channel-to-channel li nking mechanism for c ontinuous transfers ? independent channel linking at e nd of minor loop and/or major loop ? peripheral-paced hardware requests (one per channel) ? for all three methods, one service request per execution of the minor loop is required ? support for fixed-priority and round-robin channel arbitration ? channel completion reported vi a optional interrupt requests ? one interrupt per channel, optionally asse rted at completion of major iteration count ? error terminations are optionally enabled per ch annel, and logically summed together to form a small number of error interrupt outputs ? support for scatter/ga ther dma processing ? support for complex data structures ? support to cancel transfers via software or hardware
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-3 preliminary?subject to change without notice the structure of the transfer contro l descriptor is fundamental to the operation of the dma module. it is defined below in a ?c? pse udo-code specification, where int refers to a 32-bit variable (unless noted otherwise) and short is a 16-bit variable. note to compile these structures, change any periods '.' in the variable name to underscores '_'. typedef union { struct { /* citer.e_link = 1 */ unsigned short citer.linkch:6; /* link channel number, */ unsigned short citer:9; /* current (?major?) iteration count */ } minor_link_enabled; /* channel link at end of the minor loop */ struct { /* citer.e_link = 0 */ unsigned short citer:15; /* current (?major?) iteration count */ } minor_link_disabled; /* no linking at end of the minor loop */ } t_minor_link_citer; typedef union { struct { /* biter.e_link = 1 */ unsigned short biter.linkch:6; /* link channel number, */ unsigned short biter:9; /* beginning (?major?) iteration count */ } init_minor_link_enabled; /* channel link at end of the minor loop */ struct { /* biter.e_link = 0 */ unsigned short biter:15; /* beginning (?major?) iteration count */ } init_minor_link_disabled; /* no linking at end of the minor loop */ } t_minor_link_biter; typedef struct { unsigned intsaddr;/* source address */ unsigned intsmod:5;/* source address modulo */ unsigned intssize:3;/* source transfer size */ unsigned intdmod:5;/* destination address modulo */ unsigned intdsize:3;/* destination transfer size */ short soff; /* signed source address offset */ unsigned intnbytes;/* inner (?minor?) byte count */ int slast; /* last source address adjustment */ unsigned intdaddr;/* destination address */ unsigned shortciter.e_link:1;/* enable channel linking on minor loop */ t_minor_link_citerminor_link_citer;/* conditional current iteration count */ short doff; /* signed destination address offset */ int dlast_sga;/* last destination address adjustment, or scatter/gather address (if e_sg = 1) */ unsigned shortbiter.e_link:1;/* beginning channel link enable */ t_minor_link_biterminor_link_biter;/* beginning (?major?) iteration count */ unsigned intbwc:2;/* bandwidth control */ unsigned intmajor.linkch:6;/* link channel number */ unsigned intdone:1;/* channel done */ unsigned intactive:1;/* channel executing */ unsigned intmajor.e_link:1;/* enable channel linking on major loop*/ unsigned inte_sg:1;/* enable scatter/gather descriptor */ unsigned intd_req:1;/* disable ipd_req when done */ unsigned intint_half:1;/* interrupt on citer = (biter >> 1) */ unsigned intint_maj:1;/* interrupt on major loop completion */ unsigned intstart:1;/* explicit channel start */ } tcd /* transfer_control_descriptor */
pxd10 microcontroller reference manual, rev. 1 15-4 freescale semiconductor preliminary?subject to change without notice the basic operation of a channel is defined as: 1. the channel is initialized by software loading the transfer control descriptor into the dma?s programming model, memory-mappe d through the ips space, and implemented as local memory. 2. the channel requests service; either explicitly by software, a peripheral re quest or a linkage from another channel. note the major loop executes one iteration per service request. 3. the contents of the transfer cont rol descriptor for the activated cha nnel is read from the local memory and loaded into the dma engine?s internal register file. 4. the dma engine executes the data transfer defined by the transfer c ontrol descriptor, reading from the source and writing to the destinat ion. the number of iterations in the minor loop is automatically calculated by the dma engi ne. the number of iterations within the minor loop is a function of the number of bytes to transfer (nbytes), the source size (ssize) and the destinati on size (dsize). the completion of the minor loop is equal to one iteration of the major loop. 5. at the conclusion of the minor loop?s execution, certa in fields of the transfer control descriptor are written back to the local tcd memory. the process (steps 2-5) is repeated until the outer major loop?s itera tion count is exhausted. at that time, additional processing steps are comple ted, e.g., the optional asse rtion of an interrupt request signaling the transfer?s completion, final adjust ments to the source and destinati on addresses, etc. a more detailed description of the channel processing is listed in the pseudo-code below. this simplified example is intended to represent basic data transfers. detailed processing associated wi th the error handling is omitted. /* the given dmachannel is requesting service by the software assertion of the tcd[channel].start bit, the assertion of an enabled ipd_req from a device, or the implicit assertion of a channel-to-channel link */ /* begin by reading the transfer control descriptor from the local ram into the local dma_engine registers */ dma_engine = read_from_local_memory [channel]; dma_engine.active = 1; /* set active flag */ dma_engine.done = 0; /* clear done flag */ /* check the transfer control descriptor for consistency */ if (dma_engine.config_error == 0) { / * begin execution of the inner ?minor? loop transfers */ { /* convert the source transfer size into a byte count */ switch (dma_engine.ssize) { case 0: /* 8-bit transfer */ src_xfr_size = 1; break; case 1: /* 16-bit transfer */ src_xfr_size = 2; break;
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-5 preliminary?subject to change without notice case 2: /* 32-bit transfer */ src_xfr_size = 4; break; case 3: /* 64-bit transfer */ src_xfr_size = 8; break; case 4: /* 16-byte burst transfer */ src_xfr_size = 16; break; case 5: /* 32-byte burst transfer */ src_xfr_size = 32; break; } /* convert the destination transfer size into a byte count */ switch (dma_engine.dsize) { case 0: /* 8-bit transfer */ dest_xfr_size = 1; break; case 1: /* 16-bit transfer */ dest_xfr_size = 2; break; case 2: /* 32-bit transfer */ dest_xfr_size = 4; break; case 3: /* 64-bit transfer */ dest_xfr_size = 8; break; case 4: /* 16-byte burst transfer */ dest_xfr_size = 16; break; case 5: /* 32-byte burst transfer */ dest_xfr_size = 32; break; } /* determine the larger of the two transfer sizes, this value reflects */ /* the number of bytes transferred per read->write sequence. */ /* number of iterations of the minor loop = nbytes / xfer_size */ if (dma_engine.ssize < dma_engine.dsize) xfr_size = dest_xfer_size; else xfr_size = src_xfer_size; /* process the source address, read data into the buffer*/ /* read ?xfr_size? bytes from the source */ /* if the ssize < dsize, do multiple reads to equal the dsize */ /* if the ssize => dsize, do a single read of source data */ number_of_source_reads = xfer_size / src_xfer_size; for (number_of_source_reads) { dma_engine.data = read_from_amba-ahb (dma_engine.saddr, src_xfr_size); /* generate the next-state source address */ /* sum the current saddr with the signed source offset */ ns_addr = dma_engine.saddr + (int) dma_engine.soff; }
pxd10 microcontroller reference manual, rev. 1 15-6 freescale semiconductor preliminary?subject to change without notice /* if enabled, apply the power-of-2 modulo to the next-state addr */ if (dma_engine.smod != 0) address_select = (1 << dma_engine.smod) - 1; } else address_select = 0xffff_ffff; dma_engine.saddr = ns_addr & address_select | dma_engine.saddr & ~address_select; } } /* process the destination address, write data from buffer */ /* write ?xfr_size? bytes to the destination */ /* if the dsize < ssize, do multiple writes to equal the ssize */ /* if the dsize => ssize, do a single write of dest data */ number_of_dest_writes = xfer_size / dest_xfer_size; for (number_of_dest_writes) { write_to_amba-ahb (dma_engine.daddr, dest_xfr_size) = dma_engine.data; /* generate the next-state destination address */ /* sum the current daddr with the signed destination offset */ ns_addr = dma_engine.daddr + (int) dma_engine.doff; /* if enabled, apply the power-of-2 modulo to the next-state dest addr */ if (dma_engine.dmod != 0) address_select = (1 << dma_engine.dmod) - 1; else address_select = 0xffff_ffff; dma_engine.daddr = ns_addr & address_select | dma_engine.daddr & ~address_select; } if (cancel_transfer) break; /* check for a higher priority channel to service if: */ /* 1) preemption is enabled */ /* 2) in fixed arbitration mode */ /* 3) a higher priority channel is requesting service */ /* 4) not already servicing a preempting channel */ if ((dchprin.ecp = 1) & fixed_arbitration_mode higher_pri_request & ~current_channel_is_preempt) service_preempt_channel; /* the bandwidth control field determines when the next read/write occurs */ if (dma_engine.bwc > 1) stall_dma_engine (1 << dma_engine.bwc); /* decrement the minor loop byte count */ dma_engine.nbytes = dma_engine.nbytes - xfr_size; }while (dma_engine.nbytes > 0) /* end of minor inner loop */ dma_engine.citer--; /* decrement major loop iteration count */
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-7 preliminary?subject to change without notice /* if the major loop is not yet exhausted, update certain tcd values in the ram */ if (dma_engine.citer != 0) { write_to_local_memory [channel].saddr = dma_engine.saddr; write_to_local_memory [channel].daddr = dma_engine.daddr; write_to_local_memory [channel].citer = dma_engine.citer; /* if minor loop linking is enabled, make the channel link */ if (dma_engine.citer.e_link) tcd[citer.linkch].start = 1; /* specified channel service req */ /* check for interrupt assertion if half of the major iterations are done */ if (dma_engine.int_half && (dma_engine.citer == (dma_engine.biter >> 1))) generate_interrupt (channel); dma_engine.active = 0; /* clear the channel busy flag */ } else { /* major loop is complete, dma_engine.citer == 0 */ /* since the major loop is complete, perform the final address adjustments */ /* sum the current {src,dst} addresses with ?last? adjustment */ write_to_local_memory [channel].saddr = dma_engine.saddr + dma_engine.slast; write_to_local_memory [channel].daddr = dma_engine.daddr + dma_engine.dlast; /* restore the major iteration count to the beginning value */ write_to_local_memory [channel].citer = dma_engine.biter; /* check for interrupt assertion at completion of the major iteration */ if (dma_engine.int_maj) generate_interrupt (channel); /* check if the ipd_req is to be disabled at completion of the major iteration */ if (dma_engine.d_req) dmaerq [channel] = 0; /* check for a scatter/gather transfer control descriptor */ if (dma_engine.e_sg) { /* load new transfer control descriptor from the address defined by dlast_sga */ write_to_local_memory [channel] = read_from_amba-ahb(dma_engine.dlast_sga,32); } if (dma_engine.major.e_link) tcd[major.linkch].start = 1; /* specified channel service req */ dma_engine.active = 0; /* clear the channel busy flag */ dma_engine.done = 1; /* set the channel done flag */ } else { /* configuration error detected, abort the channel */ dma_engine.error_status = error_type; /* record the error */ dma_engine.active = 0; /* clear the channel busy flag */ /* check for interrupt assertion on error */ if (dma_engine.int_err) generate_interrupt (channel); }
pxd10 microcontroller reference manual, rev. 1 15-8 freescale semiconductor preliminary?subject to change without notice for more details, consult section 15.2.1, register descriptions, and section 15.3, functional description. 15.2 memory map/register definition the dma?s programming model is pa rtitioned into two sections, both mapped into the slave bus space: the first region defines a number of registers providing control f unctions, while the second region corresponds to the local transfer control descriptor memory. reading an unimplemented register bit or memory location will return the value of zero. write the value of zero to unimplemented register bits. any access to a reserved memory location will result in a bus error. reserved memory locations are indicated in the memory map. for 16- and 32-channel implementations, reserved memory also includes the high order "h " registers containing channels 63-32 data (i.e., dmaerqh, dmaeeih, dmainth, dmaerrh). many of the control registers have a bit width that matches the number of channels implemented in the module, i.e., 16-, 32- or 64- bits in size. registers a ssociated with a 64-channel design are implemented as two 32-bit registers, and include an ?h? and ?l? su ffixes, signaling the ?high? and ?low? portions of the control function. the descri ptions in this section define the 64-channel implementation. for 16- or 32-channel designs, the unused bits are not implemented: reads return zeroes, and writes are ignored. the dma module does not include any logic which pr ovides access control. rather, this function is supported using the standard access control logic provided by the pbridge controller. table 15-1 is a 32-bit view of the dma?s memory map. table 15-1. dma 32-bit memory map dma offset register 0x0000 dma control register (dmacr) 0x0004 dma error status (dmaes) 0x0008 dma enable request high (dmaerqh, channels 63-32) 0x000c dma enable request low (dmaerql, channels 31-00) 0x0010 dma enable error interrupt high (dmaeeih, channels 63-32) 0x0014 dma enable error interrupt low (dmaeeil, channels 31-00) 0x0018 dma set enable request (dmaserq) dma clear enable request (dmacerq) dma set enable error interrupt (dmaseei) dma clear enable error interrupt (dmaceei) 0x001c dma clear interrupt request (dmacint) dma clear error (dmacerr) dma set start bit (dmassrt) dma clear done status bit (dmacdne) 0x0020 dma interrupt request high (dmainth, channels 63-32) 0x0024 dma interrupt request low (dmaintl, channels 31-00) 0x0028 dma error high (dmaerrh, channels 63-32) 0x002c dma error low (dmaerrl, channels 31-00) 0x0030 dma hardware request status high (dmahrsh, channels 63-32) 0x0034 dma hardware request status low (dmahrsl, channels 31-00) 0x0038 dma general purpose output register (dmagpor) 0x003c-0x00fc reserved
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-9 preliminary?subject to change without notice 15.2.1 register descriptions 15.2.1.1 dma control register (dmacr) the 32-bit dmacr defines the basic ope rating configuratio n of the dma. the dma arbitrates channel serv ice requests in groups of 16 ch annels. the 64- and 32-channel configurations have four groups (3,2,1,0) and two groups (1,0), resp ectively; the 16 cha nnel configuration 0x0100 dma channel 0 priority (dchpri0) dma channel 1 priority (dchpri1) dma channel 2 priority (dchpri2) dma channel 3 priority (dchpri3) 0x0104 dma channel 4 priority (dchpri4) dma channel 5 priority (dchpri5) dma channel 6 priority (dchpri6) dma channel 7 priority (dchpri7) 0x0108 dma channel 8 priority (dchpri8) dma channel 9 priority (dchpri9) dma channel 10 priority (dchpri10) dma channel 11 priority (dchpri11) 0x010c dma channel 12 priority (dchpri12) dma channel 13 priority (dchpri13) dma channel 14 priority (dchpri14) dma channel 15 priority (dchpri15) 0x0110 dma channel 16 priority (dchpri16) dma channel 17 priority (dchpri17) dma channel 18 priority (dchpri18) dma channel 19 priority (dchpri19) 0x0114 dma channel 20 priority (dchpri20) dma channel 21 priority (dchpri21) dma channel 22 priority (dchpri22) dma channel 23 priority (dchpri23) 0x0118 dma channel 24 priority (dchpri24) dma channel 25 priority (dchpri25) dma channel 26 priority (dchpri26) dma channel 27 priority (dchpri27) 0x011c dma channel 28 priority (dchpri28) dma channel 29 priority (dchpri29) dma channel 30 priority (dchpri30) dma channel 31 priority (dchpri31) 0x0120 dma channel 32 priority (dchpri32) dma channel 33 priority (dchpri33) dma channel 34 priority (dchpri34) dma channel 35 priority (dchpri35) 0x0124 dma channel 36 priority (dchpri36) dma channel 37 priority (dchpri37) dma channel 38 priority (dchpri38) dma channel 39 priority (dchpri39) 0x0128 dma channel 40 priority (dchpri40) dma channel 41 priority (dchpri41) dma channel 42 priority (dchpri42) dma channel 43 priority (dchpri43) 0x012c dma channel 44 priority (dchpri44) dma channel 45 priority (dchpri45) dma channel 46 priority (dchpri46) dma channel 47 priority (dchpri47) 0x0130 dma channel 48 priority (dchpri48) dma channel 49 priority (dchpri49) dma channel 50 priority (dchpri50) dma channel 51 priority (dchpri51) 0x0134 dma channel 52 priority (dchpri52) dma channel 53 priority (dchpri53) dma channel 54 priority (dchpri54) dma channel 55 priority (dchpri55) 0x0138 dma channel 56 priority (dchpri56) dma channel 57 priority (dchpri57) dma channel 58 priority (dchpri58) dma channel 59 priority (dchpri59) 0x013c dma channel 60 priority (dchpri60) dma channel 61 priority (dchpri61) dma channel 62 priority (dchpri62) dma channel 63 priority (dchpri63) 0x0140-0x0ffc reserved 0x1000-0x11fc tcd00-tcd15 0x1200-0x13fc tcd16-tcd31 0x1400-0x15fc tcd32-tcd47 0x1600-0x17fc tcd48-tcd63 table 15-1. dma 32-bit memory map (continued) dma offset register
pxd10 microcontroller reference manual, rev. 1 15-10 freescale semiconductor preliminary?subject to change without notice has only one group (0). group 3 contains channe ls 63-48, group 2 contains channels 47-32, group 1 contains channels 31-16, and gr oup 0 contains channels 15-0. arbitration within a group can be conf igured to use either a fixed-prio rity or a round-robin selection. in fixed-priority arbitration, the highest priority cha nnel requesting service is selected to execute. the priorities are assigne d by the channel priority registers (see section 15.2.1.17, dma channel n priority (dchprin), n = 0,..., {15,31,63}? ). in round-robin arbitrat ion mode, the channel prio rities are ignored and the channels within each group are cycled through without regard to priority. the group priorities operate in a si milar fashion. in group fi xed-priority arbitrati on mode, channel service requests in the highest priority group are executed firs t where priority level 3 is the highest and priority level 0 is the lowest. the group prio rities are assigned in the grpnpri re gisters. all group priorities must have unique values prior to any channel service reque sts occur, otherwise a conf iguration error will be reported. unused group priority regi sters, per configuration, are unimp lemented in the dmacr. in group round-robin mode, the group prioriti es are ignored and the groups are cycled through without regard to priority. minor loop offsets are address offset values added to the fina l source address (saddr) or destination address (daddr) upon minor loop completion. wh en minor loop offsets are enable d, the minor loop offset (mloff) is added to the final source address (saddr), or the final destination address (da ddr), or both prior to the addresses being written back into the tcd. if the ma jor loop is complete, the minor loop offset is ignored and the major loop address offsets (slast and dlast_sga) are used to compute the next saddr and daddr values. when minor loop mapping is enabled (dmacr[emlm] = 1), tcdn word2 is redefined. a portion of tcdn word2 is used to specify multiple fields: an sour ce enable bit (smloe) to sp ecify the minor loop offset should be applied to the source a ddress (saddr) upon minor loop comple tion, an destination enable bit (dmloe) to specify the minor loop offset should be applied to the destinatio n address (daddr) upon minor loop completion, and the sign extended mi nor loop offset value (mloff). the same offset value (mloff) is used for both source and des tination minor loop offsets. when either minor loop offset is enabled (smloe set or dmloe set), the nbytes field is redu ced to 10 bits. when both minor l oop offsets are disabled (smloe cleared and dmloe cleared), the nbytes field is a 30-bit vector. when minor loop mapping is disabled (dmacr[emlm] = 0), all 32 bits of tcdn word2 are assigned to the nbytes field. see section 15.2.1.18, transfer cont rol descriptor (tcd),? for more details. see figure 15-2 and table 15-2 for the dmacr definition.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-11 preliminary?subject to change without notice figure 15-2. dma control register (dmacr) register address: dma_offset + 0x0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cx ecx w reset: 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r grp3pri grp2pri grp1pri grp0pri eml m clm halt hoe erg a erc a edb g ebw w reset: 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 = unimplemented table 15-2. dma control regist er (dmacr) field descriptions name description value cx cancel transfer 0 normal operation. 1 cancel the remaining data transfer. stop the executing channel and force the minor loop to be finished. the cancel takes effect after the last write of the current read/write sequence. the cxfr bit clears itself after the ca ncel has been honored. this cancel retires the channel normally as if the minor loop was completed. ecx error cancel transfer 0 normal operation. 1 cancel the remaining data transfer in the same fashion as the cx cancel transfer. stop the executing channel and force the minor loop to be finished. the cancel takes effect after the last write of the current read/write sequence. the ecx bit clears itself after the cancel cancel has been honored. in addition to cancelling the transfer, the ecx treats the cancel as an error condition; thus updating the dmaes regist er and generating an optional error interrupt (see section 15.2.1.2, dma error status (dmaes) ?). grp3pri channel group 3 priority group 3 priority level when fixed priority group arbitration is enabled. grp2pri channel group 2 priority group 2 priority level when fixed priority group arbitration is enabled. grp1pri channel group 1 priority group 1 priority level when fixed priority group arbitration is enabled. grp0pri channel group 0 priority group 0 priority level when fixed priority group arbitration is enabled.
pxd10 microcontroller reference manual, rev. 1 15-12 freescale semiconductor preliminary?subject to change without notice emlm enable minor loop mapping 0 minor loop mapping disabled. tcdn.word2 is defined as a 32-bit nbytes field. 1 minor loop mapping enabled. when set, tcdn.word2 is redefined to include individual enable fields, an offset field and the nbytes field. the individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. the nbytes field is reduced when either offset is enabled. clm continuous link mode 0 a minor loop channel link made to itself will go through channel arbitration before being activated again. 1 a minor loop channel link made to itself will not go through channel arbitration before being activated again. upon minor loop completion the channel will active again if that channel has has a minor loop channel link enabled and the link channel is itself. this effectively applies the minor loop offsets and restarts the next minor loop. halt halt dma operations 0 normal operation. 1 stall the start of any new channels. executing channels are allowed to complete. channel execution will resume when the halt bit is cleared. hoe halt on error 0 normal operation. 1 any error will cause the halt bit to be set. subsequently, all service requests will be ignored until the halt bit is cleared. erga enable round robin group arbitration 0 fi xed priority arbitration is used for selection among the groups. 1 round robin arbitration is used for selection among the groups. erca enable round robin channel arbitration 0 fixed priority arbitration is used for channel selection within each group. 1 round robin arbitration is used for channel selection within each group. edbg enable debug 0 the assertion of the ipg_debug input is ignored. 1 the assertion of the ipg_debug input causes the dma to stall the start of a new channel. executing channels are allowed to complete. channel execution will resume when either the ipg_debug input is negated or the edbg bit is cleared. ebw enable buffered writes 0 the buffer able write signal (hprot[2]) is not asserted during amba ahb writes. 1 the bufferable write signal (hprot[2]) is asserted on all amba ahb writes except for the last write sequence. table 15-2. dma control regist er (dmacr) field descriptions name description value
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-13 preliminary?subject to change without notice 15.2.1.2 dma error status (dmaes) the dmaes register provides informat ion concerning the last recorded ch annel error. channel errors can be caused by a configuration error (an illegal setting in the transfer contro l descriptor or an illegal priority register setting in fixed arbitration mode) or an error terminati on to a bus master re ad or write cycle. a configuration error is caused when the starting source or destinati on address, source or destination offsets, minor loop byte count and th e transfer size represent an incons istent state. the addresses and offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a multiple of the source and destinat ion transfer sizes. all source read s and destination writes must be configured to the natural boundary of the programmed transfer size respect ively. in fixed arbitration mode, a configuration error is caused by any two channel priorities being equal within a group, or any group priority levels being equa l among the groups. all channel priority le vels within a group must be unique and all group priority levels among th e groups must be unique when fixe d arbitration mode is enabled. if a scatter/gather operation is enab led upon channel completion, a configur ation error is reported if the scatter/gather address (dlast_sga) is not aligned on a 32-byte boundary . if minor loop channel linking is enabled upon channel completion, a conf iguration error is reported when the link is attempted if the tcd.citer.e_link bit does not equal the tcd.biter.e_ link bit. all configurati on error conditions except scatter/gather and minor loop link error are reported as th e channel is activated and assert an error interrupt request, if enabled. a scatter/gather configuration error is reported when the scatter/gather operation begins at major loop completion when properly enable d. a minor loop channel link configuration error is reported when the link operation is serviced at minor loop completion. if a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate bus error flag set. in this case, the state of the cha nnel?s transfer control desc riptor is updated by the dma engine with the current source addr ess, destination address and current iteration count at the point of the fault. when a system bus error occurs, the channel is terminated after the read or write transaction which is already pipelined after errant access, has complete d. if a bus error occurs on the last read prior to beginning the write sequence, the write will execute using the data cap tured during the bus error. if a bus error occurs on the last write prior to switching to the next read sequenc e, the read seque nce will execute before the channel is terminated due to the destination bus error. a transfer may be cancelled by software via the dmacr[cx ] bit or hardware via the dma_cancel_xfer input signal. when a cancel transfer request is recognized, the dma engine stops pr ocessing the channel. the current read-write sequence is allowed to finish. if the cancel occurs on th e last read-write sequence of a major or minor loop, the ca ncel request is discarded and the channel retires normally. the error cancel transfer is the sa me as a cancel transfer except the dmaes register is updated with the cancelled channel number and error cancel bit is set. the tcd of a cancelled channel has the source address and destination address of the last transfer saved in the tcd. it is the responsibility of the user to initialize the tcd again should the channel need to be restarted because the aforementioned fields have been modified by the dma engine and no longer repres ent the original parameters. when a transfer is cancelled via the error cancel tr ansfer mechanism (setting the dmacr[ecx] or asserting the dma_err_cancel_xfer input), the channel number is loaded into the errchn field and the ecx and vld bits are set are set in the dmae s register. in addition, an error inte rrupt may be gene rated if enabled. see section 15.2.1.14, dma error (dmaerrh, dmaerrl)? for error interrupt details.
pxd10 microcontroller reference manual, rev. 1 15-14 freescale semiconductor preliminary?subject to change without notice the occurrence of any type of error causes the dma engine to immediately stop, and the appropriate channel bit in the dma error register to be asserte d. at the same time, the details of the error condition are loaded into the dmaes register. the major loop complete indicators, sett ing the transfer control descriptor done flag and the possible a ssertion of an interrupt request, are not affected when an error is detected. see figure 15-3 and table 15-3 for the dmaes definition. figure 15-3. dma error status (dmaes) register register address: dma_offset + 0x0004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r vld 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ecx w reset: 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r gpe cpe errchn[0:5] sae soe dae doe nce sge sbe dbe w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented table 15-3. dma error status (dmaes) field descriptions name description value vld logical or of all dmaerrh and dmaerrl status bits. 0 no dmaerr bits are set. 1 at least one dmaerr bit is set indicating a valid error exists that has not been cleared. ecx transfer cancelled 0 no cancelled transfers. 1 the last recorded entry was a cancelled transfer via the error cancel transfer input. gpe group priority error 0 no group priority error. 1 the last recorded error was a configuration error among the group priorities. all group priorities are not unique. cpe channel priority error 0 no channel priority error. 1 the last recorded error was a configuration error in the channel priorities within a group. all channel priorities within a group are not unique. errchn[0:5] error channel number or cancelled channel number the channel number of the last recorded error (excluding gpe and cpe errors) or last recorded transfer that was error cancelled. sae source address error 0 no source address c onfiguration error. 1 the last recorded error was a configuration error detected in the tcd.saddr field. tcd.saddr is inconsistent with tcd.ssize. soe source offset error 0 no source offset configuration error. 1 the last recorded error was a configuration error detected in the tcd.soff field. tcd.soff is inconsistent with tcd.ssize.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-15 preliminary?subject to change without notice 15.2.1.3 dma enable request (dmaerqh, dmaerql) the dmaerq{h,l} registers provide a bit map fo r the implemented channels {16,32,64} to enable the request signal for each channel. dmaerqh supports channels 63-32, while dmae qrl covers channels 31-00. the state of any given ch annel enable is directly af fected by writes to this re gister; it is also affected by writes to the dmaserq and dmac erq registers. the dma{s,c}erq registers are provided so that the request enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the dmaerq{h,l} registers. both the dma request input signal and this enable re quest flag must be asse rted before a channel?s hardware service request is accepted. the st ate of the dma enable request flag does not affect a channel service request made explicitly through so ftware or a linked channel request. see figure 15-4 and table 15-4 for the dmaerq definition. dae destination address error 0 no destination address configuration error. 1 the last recorded error was a configuration error detected in the tcd.daddr field. tcd.daddr is inconsistent with tcd.dsize. doe destination offset error 0 no destination offset configuration error. 1 the last recorded error was a configuration error detected in the tcd.doff field. tcd.doff is inconsistent with tcd.dsize. nce nbytes/citer configuration error 0 no nbytes/citer configuration error. 1 the last recorded error was a configuration error detected in the tcd.nbytes or tcd.citer fields. tcd.nbytes is not a multiple of tcd.ssize and tcd.dsize, or tcd.citer is equal to zero, or tcd.citer.e_link is not equal to tcd.biter.e_link. sge scatter/gather configuration error 0 no scatter/gather configuration error. 1 the last recorded error was a configuration error detected in the tcd.dlast_sga field. this field is checked at the beginning of a scatter/gather operation after major loop completion if tcd.e_sg is enabled. tcd.dlast_sga is not on a 32 byte boundary. sbe source bus error 0 no source bus error. 1 the last recorded error was a bus error on a source read. dbe destination bus error 0 no destination bus error. 1 the last recorded error was a bus error on a destination write. table 15-3. dma error status (dmaes) field descriptions (continued) name description value
pxd10 microcontroller reference manual, rev. 1 15-16 freescale semiconductor preliminary?subject to change without notice figure 15-4. dma enable request (dmaerqh, dmaerql) registers as a given channel completes the processing of its majo r iteration count, there is a flag in the transfer control descriptor that may affect the ending state of the dm aerq bit for that channel. if the tcd.d_req bit is set, then the corresponding dm aerq bit is cleared, disabling the dma request; else if the d_req bit is cleared, the state of the dmaerq bit is unaffected. 15.2.1.4 dma enable error in terrupt (dmaeeih, dmaeeil) the dmaeei{h,l} registers provide a bit map for the implemented channels {16,32,64} to enable the error interrupt signal for each channel. dmaeei h supports channels 63-32, while dmaeeil covers channels 31-00. the state of any given channel?s error inte rrupt enable is directly af fected by writes to this register; it is also affected by writes to th e dmaseei and dmaceei regi sters. the dma{s,c}eei registers are provided so that the error interrupt enable for a single channel can easily be modified without the need to perform a read-modify-write sequence to the dmaeei{h,l} registers. register address: dma_offset + 0x0008 (dmaerqh), +0x000c (dmaerql) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r erq 63 erq 62 erq 61 erq 60 erq 59 erq 58 erq 57 erq 56 erq 55 erq 54 erq 53 erq 52 erq 51 erq 50 erq 49 erq 48 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r erq 47 erq 46 erq 45 erq 44 erq 43 erq 42 erq 41 erq 40 erq 39 erq 38 erq 37 erq 36 erq 35 erq 34 erq 33 erq 32 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r erq 31 erq 30 erq 29 erq 28 erq 27 erq 26 erq 25 erq 24 erq 23 erq 22 erq 21 erq 20 erq 19 erq 18 erq 17 erq 16 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r erq 15 erq 14 erq 13 erq 12 erq 11 erq 10 erq 09 erq 08 erq 07 erq 06 erq 05 erq 04 erq 03 erq 02 erq 01 erq 00 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented table 15-4. dma enable request (dmaerqh, dmaerql) field descriptions name description value erqn, n = 0,... 15 n = 0,... 31 n = 0,... 63 enable dma request n 0 the dma request signal for channel n is disabled. 1 the dma request signal for channel n is enabled.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-17 preliminary?subject to change without notice both the dma error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a given channel is asserted. see figure 15-5 and table 15-5 for the dmaeei definition. figure 15-5. dma enable error interr upt (dmaeeih, dmaeeil) registers table 15-5. dma enable error interrupt (dmaeeih, dmaeeil) field descriptions 15.2.1.5 dma set enable request (dmaserq) the dmaserq register provides a simple memory -mapped mechanism to set a given bit in the dmaerq{h,l} registers to enable the dma request fo r a given channel. the data value on a register write causes the corresponding bit in the dmaerq{h,l} register to be set. a data value of 64 to 127 (regardless of the number of impl emented channels) provides a global set function, forcing the entire contents of dmaerq{h,l} to be asse rted. if bit 7 is set, the command is ignored. this allows multiple byte registers to be writ ten as a 32-bit word. reads of this register return all zeroes. see figure 15-6 and table 15-6 for the dmaserq definition. register address: dma_offset + 0x0010 (dmaeeih), +0x0014 (dmaeeil) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r eei6 3 eei6 2 eei6 1 eei6 0 eei5 9 eei5 8 eei5 7 eei5 6 eei5 5 eei5 4 eei5 3 eei5 2 eei5 1 eei5 0 eei4 9 eei4 8 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eei4 7 eei4 6 eei4 5 eei4 4 eei4 3 eei4 2 eei4 1 eei4 0 eei3 9 eei3 8 eei3 7 eei3 6 eei3 5 eei3 4 eei3 3 eei3 2 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r eei3 1 eei3 0 eei2 9 eei2 8 eei2 7 eei2 6 eei2 5 eei2 4 eei2 3 eei2 2 eei2 1 eei2 0 eei1 9 eei1 8 eei1 7 eei1 6 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eei1 5 eei1 4 eei1 3 eei1 2 eei1 1 eei1 0 eei0 9 eei0 8 eei0 7 eei0 6 eei0 5 eei0 4 eei0 3 eei0 2 eei0 1 eei0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented name description value eein, n = 0,... 15 n = 0,... 31 n = 0,... 63 enable error interrupt n 0 the error signal for channel n does not generate an error interrupt. 1 the assertion of the error signal for channel n generate an error interrupt request.
pxd10 microcontroller reference manual, rev. 1 15-18 freescale semiconductor preliminary?subject to change without notice figure 15-6. dma set enable request (dmaserq) register table 15-6. dma set enable request (dmaserq) field descriptions 15.2.1.6 dma clear enable request (dmacerq) the dmacerq register provides a simple memory-m apped mechanism to clea r a given bit in the dmaerq{h,l} registers to disable the dma request fo r a given channel. the data value on a register write causes the corresponding bit in the dmaerq{h,l} re gister to be cleared. a data value of 64 to 127 (regardless of the number of impl emented channels) provides a global clear function, forcing the entire contents of the dmaerq{h,l} to be zeroed, disabli ng all dma request inputs. if bit 7 is set, the command is ignored. this allo ws multiple byte register s to be written as a 32- bit word. reads of this register return all zeroes. see figure 15-7 and table 15-7 for the dmacerq definition. figure 15-7. dma clear enable request (dmacerq) register table 15-7. dma clear enable request (dmacerq) field descriptions 15.2.1.7 dma set enable er ror interrupt (dmaseei) the dmaseei register provides a simple memory -mapped mechanism to set a given bit in the dmaeei{h,l} registers to enable the error interrupt for a given channel. the data value on a register write causes the corresponding bit in the dmaeei{h,l} register to be set. a data value of 64 to 127 (regardless of the number of impl emented channels) provides a global set function, forcing the entire register address: dma_offset + 0x0018 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop serq[0:6] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 serq[0:6] set enable request 0-63 set the corresponding bit in dmaerq{h,l} 64-127 set all bits in dmaerq{h,l} register address: dma_offset + 0x0019 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop cerq[0:6] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 cerq[0:6] clear enable request 0-63 clear corresponding bit in dmaerq{h,l} 64-127 clear all bits in dmaerq{h,l}
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-19 preliminary?subject to change without notice contents of dmaeei{h,l} to be asserted. if bit 7 is set, the command is ignor ed. this allows multiple byte registers to be writ ten as a 32-bit word. reads of this register return all zeroes. see figure 15-8 and table 15-8 for the dmaseei definition. figure 15-8. dma set enable er ror interrupt (dmaseei) register table 15-8. dma set enable error interrupt (dmaseei) field descriptions 15.2.1.8 dma clear enable error interrupt (dmaceei) the dmaceei register provides a simple memory-m apped mechanism to clear a given bit in the dmaeei{h,l} registers to disable the error interrupt for a given channel. the data value on a register write causes the corresponding bit in the dmaeei{h,l} register to be cleared. a data va lue of 64 to 127 (regardless of the number of impl emented channels) provides a global clear function, forcing the entire contents of the dmaeei{h,l} to be zeroed, disabling all dma request inputs. if bit 7 is set, the command is ignored. this allows multi ple byte registers to be writ ten as a 32-bit word. reads of this register return all zeroes. see figure 15-9 and table 15-9 for the dmaceei definition. figure 15-9. dma clear enable er ror interrupt (dmaceei) register table 15-9. dma clear enable error interrupt (dmaceei) field descriptions register address: dma_offset + 0x001a 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop seei[0:6] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 seei[0:6] set enable error interrupt 0-63 set the corresponding bit in dmaeei{h,l} 64-127 set all bits in dmaeei{h,l} register address: dma_offset + 0x001b 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop ceei[0:6] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 ceei[0:6] clear enable error in terrupt 0-63 clear corresponding bit in dmaeei{h,l} 64-127 clear all bits in dmaeei{h,l}
pxd10 microcontroller reference manual, rev. 1 15-20 freescale semiconductor preliminary?subject to change without notice 15.2.1.9 dma clear interrupt request (dmacint) the dmacint register provides a simple memory-mapped mechanism to clear a given bit in the dmaint{h,l} registers to disable th e interrupt request for a given channel. the gi ven value on a register write causes the corresponding bit in the dmaint{h,l} register to be cleared. a da ta value of 64 to 127 (regardless of the number of impl emented channels) provides a global clear function, forcing the entire contents of the dmaint{h,l} to be zeroed, disabling all dma interrupt requests. if bit 7 is set, the command is ignored. this allo ws multiple byte register s to be written as a 32- bit word. reads of this register return all zeroes. see figure 15-10 and table 15-10 for the dmacint definition. figure 15-10. dma clear interrupt request (dmacint) fields table 15-10. dma clear interrupt request (dmacint) field descriptions 15.2.1.10 dma clear error (dmacerr) the dmaceer register provides a simple memory-mapped mechanism to clear a given bit in the dmaerr{h,l} registers to disable the error conditi on flag for a given channel. the given value on a register write causes the corresponding bit in the dmaerr{h,l} register to be cleared. a data value of 64 to 127 (regardless of the number of implemented channels) provides a global clear function, forcing the entire contents of the dmaerr{h,l} to be zeroed, clearing all ch annel error indicators. if bit 7 is set, the command is ignored. this allo ws multiple byte register s to be written as a 32- bit word. reads of this register return all zeroes. see figure 15-11 and table 15-11 for the dmacerr definition. figure 15-11. dma clear error (dmacerr) register register address: dma_offset + 0x001c 0 1 2 3 4 5 6 7 r 00000000 w nop cint[0:6] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 cint[0:6] clear interrupt request 0-63 clear the corresponding bit in dmaint{h,l} 64-127 clear all bits in dmaint{h,l} register address: dma_offset + 0x001d 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop cerr[0:6] reset: 0 0 0 0 0 0 0 = unimplemented
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-21 preliminary?subject to change without notice table 15-11. dma clear error (dmacerr) field descriptions 15.2.1.11 dma set start bit (dmassrt) the dmassrt register provides a simple memory-mapped mechanism to set the start bit in the tcd of the given channel. the data valu e on a register write causes the st art bit in the corresponding transfer control descriptor to be set. a data value of 64 to 127 (regardless of the numbe r of implemented channels) provides a global set func tion, forcing all start bits to be set. if bit 7 is set, the command is ignored. this allows multiple byte registers to be written as a 32-bit word. reads of th is register return all zeroes. see table 15-28 for the tcd start bit definition. figure 15-12. dma set star t bit (dmassrt) register table 15-12. dma set start bit (dmassrt) field descriptions 15.2.1.12 dma clear done status (dmacdne) the dmacdne register provides a s imple memory-mapped mechanism to clear the done bit in the tcd of the given channel. the data value on a regi ster write causes the done bit in the corresponding transfer control descriptor to be cleared. a data value of 64 to 127 (regardless of the number of implemented channels) provides a global clear function, forcing al l done bits to be clea red. if bit 7 is set, the command is ignored. this allows multiple byte regi sters to be written as a 32-bit word. reads of this register return all zeroes. see table 15-28 for the tcd done bit definition. figure 15-13. dma clear done status (dmacdne) register name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 cerr[0:6] clear error indicator 0-63 clear corresponding bit in dmaerr{h,l} 64-127 clear all bits in dmaerr{h,l} register address: dma_offset + 0x001e 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop ssrt[0:6] reset: 0 0 0 0 0 0 0 = unimplemented name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 ssrt[0:6] set start bit (channel service request) 0-63 set the corresponding channel?s tcd.start 64-127 set all tcd.start bits register address: dma_offset + 0x001f 0 1 2 3 4 5 6 7 r 0 0 0 0 0 0 0 0 w nop cdne[0:6] reset: 0 0 0 0 0 0 0 = unimplemented
pxd10 microcontroller reference manual, rev. 1 15-22 freescale semiconductor preliminary?subject to change without notice table 15-13. dma clear done stat us (dmacdne) field descriptions 15.2.1.13 dma interrupt request (dmainth, dmaintl) the dmaint{h,l} registers provide a bit map fo r the implemented cha nnels {16,32,64} signaling the presence of an interrupt request for each channel. dmainth supports channels 63-32 , while dmaintl covers channels 31-00. the dma e ngine signals the occurrence of a programmed interrupt upon the completion of a data transfer as defi ned in the transfer control descript or by setting the appropriate bit in this register. the outputs of this regi ster are directly routed to the pl atform?s interrupt controller. during the execution of the interrupt service routine associ ated with any given cha nnel, it is software?s responsibility to clear the appropriate bit, negati ng the interrupt request. typically, a write to the dmacint register in the interrupt serv ice routine is used for this purpose. the state of any given channel?s interr upt request is directly affected by wr ites to this register; it is also affected by writes to the dmacint register. on writ es to the dmaint, a one in any bit position clears the corresponding channel?s interrupt request. a zero in any bit position has no affect on the corresponding channel?s current interrupt status . the dmacint register is provided so the in terrupt request for a single channel can easily be cleared wi thout the need to perform a read-modify-write sequence to the dmaint{h,l} registers. see figure 15-14 and table 15-14 for the dmaint definition. name description value nop no operation 0 normal operation. 1 no operation, ignore bits 6-0 cdne[0:6] clear done status bit 0-63 clear the corresponding channel?s done bit 64-127 clear all tcd done bits
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-23 preliminary?subject to change without notice figure 15-14. dma interrupt request (dmainth, dmaintl) registers table 15-14. dma interrupt request (dmainth, dmaintl) field descriptions 15.2.1.14 dma error (dmaerrh, dmaerrl) the dmaerr{h,l} registers provide a bit map fo r the implemented channels {16,32,64} signaling the presence of an error for each channel. dmaerrh supports cha nnels 63-32, while dmaerrl covers channels 31-00. the dma engine signals the occurrence of a error condition by se tting the appropriate bit in this register. the outputs of this register are en abled by the contents of the dmaeei register, then logically summed across groups of 16, 32 and 64 channels to form several group error interrupt requests which is then routed to the platform?s interrupt c ontroller. during the executi on of the interrupt service routine associated with any dma errors, it is software?s responsibilit y to clear the appropr iate bit, negating the error interrupt request. typically, a write to the dm acerr register in the interrupt service routine is used for this purpose. recall the normal dma channel completion indicators, setti ng the transfer control descriptor done flag and the possible a ssertion of an interrupt request, are not affected when an error is detected. the contents of this register can also be polled a nd a non-zero value indicates th e presence of a channel error, regardless of the state of th e dmaeei register. the state of any given channel?s error indicators is register address: dma_offset + 0x0020 (dmainth), +0x0024 (dmaintl) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r int6 3 int6 2 int6 1 int6 0 int5 9 int5 8 int5 7 int5 6 int5 5 int5 4 int5 3 int5 2 int5 1 int5 0 int4 9 int4 8 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r int4 7 int4 6 int4 5 int4 4 int4 3 int4 2 int4 1 int4 0 int3 9 int3 8 int3 7 int3 6 int3 5 int3 4 int3 3 int3 2 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r int3 1 int3 0 int2 9 int2 8 int2 7 int2 6 int2 5 int2 4 int2 3 int2 2 int2 1 int2 0 int1 9 int1 8 int1 7 int1 6 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r int1 5 int1 4 int1 3 int1 2 int1 1 int1 0 int0 9 int0 8 int0 7 int0 6 int0 5 int0 4 int0 3 int0 2 int0 1 int0 0 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented name description value intn, n = 0,... 15 n = 0,... 31 n = 0,... 63 dma interrupt request n 0 the interrupt request for channel n is cleared. 1 the interrupt request for channel n is active.
pxd10 microcontroller reference manual, rev. 1 15-24 freescale semiconductor preliminary?subject to change without notice affected by writes to this register; it is also affected by writes to the dmacerr register. on writes to the dmaerr, a one in any bit position clears the corres ponding channel?s error status. a zero in any bit position has no affect on the corresponding channel?s current error status. the dmacerr register is provided so the error indicator for a single channel can easily be cleared. see figure 15-15 and table 15-15 for the dmaerr definition. figure 15-15. dma error (dmaerrh, dmaerrl) registers table 15-15. dma error (dmaerrh, dmaerrl) field descriptions 15.2.1.15 dma hardware request status (dmahrsh, dmahrsl) the dmahrs{h,l} registers provide a bit map fo r the implemented channels {16,32,64} to show the current hardware reques t status for each channel. dmahrsh supports channels 63-32, while dmahrsl covers channels 31-00. ha rdware request status reflects the current st ate of the registered and qualified (via the dmaerq field) ipd_req lines as seen by the dma2?s arbitration logi c. this view into the hardware request signals may be used for debug purposes. see figure 15-16 and figure 15-16 for the dmahrs definition. register address: dma_offset + 0x0028 (dmaerrh), +0x002c (dmaerrl) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r err 63 err 62 err 61 err 60 err 59 err 58 err 57 err 56 err 55 err 54 err 53 err 52 err 51 err 50 err 49 err 48 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r err 47 err 46 err 45 err 44 err 43 err 42 err 41 err 40 err 39 err 38 err 37 err 36 err 35 err 34 err 33 err 32 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r err 31 err 30 err 29 err 28 err 27 err 26 err 25 err 24 err 23 err 22 err 21 err 20 err 19 err 18 err 17 err 16 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r err 15 err 14 err 13 err 12 err 11 err 10 err 09 err 08 err 07 err 06 err 05 err 04 err 03 err 02 err 01 err 00 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented name description value errn, n = 0,... 15 n = 0,... 31 n = 0,... 63 dma error n 0 an error in channel n has not occurred. 1 an error in channel n has occurred.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-25 preliminary?subject to change without notice figure 15-16. dma hardware request st atus (dmahrsh, dmahrsl) registers table 15-16. dma hardware request status (dmahrsh, dmahrsl) field descriptions 15.2.1.16 dma general purpose output register (dmagpor) the optional dmagpor register pr ovides a general purpose register in the programmer?s model that ouputs the register contents. the dmagpor performs no functions within the dma2. this general purpose register is enabled when spp_dma2_enable_gpor is defined. this register may be used by the soc integrator to define and display configuration information. see figure 15-17 and table 15-17 for the dmagpor definition. register address: dma_offset + 0x0030 (dmahrsh), +0x0034 (dmahrsl) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r hrs 63 hrs 62 hrs 61 hrs 60 hrs 59 hrs 58 hrs 57 hrs 56 hrs 55 hrs 54 hrs 53 hrs 52 hrs 51 hrs 50 hrs 49 hrs 48 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hrs 47 hrs 46 hrs 45 hrs 44 hrs 43 hrs 42 hrs 41 hrs 40 hrs 39 hrs 38 hrs 37 hrs 36 hrs 35 hrs 34 hrs 33 hrs 32 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r hrs 31 hrs 30 hrs 29 hrs 28 hrs 27 hrs 26 hrs 25 hrs 24 hrs 23 hrs 22 hrs 21 hrs 20 hrs 19 hrs 18 hrs 17 hrs 16 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hrs 15 hrs 14 hrs 13 hrs 12 hrs 11 hrs 10 hrs 09 hrs 08 hrs 07 hrs 06 hrs 05 hrs 04 hrs 03 hrs 02 hrs 01 hrs 00 w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented name description value hrsn, n = 0,... 15 n = 0,... 31 n = 0,... 63 dma hardware request status n 0 a hardware service request for channel n is not present. 1 a hardware service request for channel n is present. note: the hardware request status reflects the state of the request as seen by the arbitration logic. therefore, this status is affected by the dmaerqn bit.
pxd10 microcontroller reference manual, rev. 1 15-26 freescale semiconductor preliminary?subject to change without notice figure 15-17. dma general purpose output register (dmagpor) table 15-17. dma general purpose output register (dmagpor) field descriptions 15.2.1.17 dma channel n priority (dchprin), n = 0,..., {15,31,63} when the fixed-priority channel ar bitration mode is enab led (dmacr[erca] = 0), th e contents of these registers define the unique priorities associated with each channel within a group. the channel priorities are evaluated by numeric value, i.e., 0 is the lowest pr iority, 1 is the next higher priority, then 2, 3, etc. software must program the channel priorities with unique values, otherwise a c onfiguration error will be reported. the range of the priority va lue is limited to the va lues of 0?15. when rea d, the grppri bits of the dchprin register reflect the cu rrent priority level of the group of channels in which the corresponding channel resides. grppri bits are not affected by write s to the dchprin registers. the group priority is assigned in the dmacr. see figure 15-2 and table 15-2 for the dmacr definition. channel preemption is enabled on a per channel basi s by setting the ecp bit in the dchprin register. channel preemption allows the executin g channel?s data transfers to be temporarily suspended in favor of starting a higher priority channel. after the preempting channel has comp leted all of its minor loop data transfers, the preempted channel is restored and resumes execution. af ter the restored channel completes one read/write sequence, it is agai n eligible for preemption. if any hi gher priority channel is requesting service, the restored channel will be suspended and the higher priority channel will be serviced. nested preemption (attempting to preempt a preempting channel) is not su pported. after a preempting channel begins execution, it cannot be preempt ed. preemption is only available wh en fixed arbitration is selected for both group and channel arbitration modes. a channel?s ability to preempt a nother channel can be disabled by setting the dpa bit in the dchprin register. when a channel?s preempt ability is disa bled, that channel cannot suspend a lower priority channel?s data transfer; regardless of the lower priority channel?s ecp setting. this allo ws for a pool of low priority, large data moving channels to be define d. these low priority channe ls can be configured to not preempt each other, thus preven ting a low priority channel from c onsuming the preempt slot normally available a true, high priority channel. see figure 15-18 and table 15-18 for the dchprin definition. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r gpor[0:15] w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r gpor[16:31] w reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = unimplemented name description value gpor[0:31] dma general purpose output register the c ontents of this register is exported out of the dma2.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-27 preliminary?subject to change without notice figure 15-18. dma channel n priority (dchprin) register table 15-18. dma channel n priority (dchprin) field descriptions 15.2.1.18 transfer control descriptor (tcd) each channel requires a 32-byte tr ansfer control descriptor for de fining the desired data movement operation. the tcd structure was previously discussed in detail in section 15.1.2, features.? the channel descriptors are stored in the local memory in sequential order: ch annel 0, channel 1, ... channel [n-1]. the definitions of the tcd are pres ented as eight 32-bit values. table 15-19 is a 32-bit view of the basic tcd structure. register address: dma_offset + 0x100 + n 0 1 2 3 4 5 6 7 r ecp dpa grppri[0:1] chpri[0:3] w reset: 0 0 * * * * * * = unimplemented, * = defaults to channel number (n) after reset name description value ecp enable channel preemption 0 channel n cannot be suspended by a higher priority channel?s service request. 1 channel n can be temporarily suspended by the service request of a higher priority channel. dpa disable preempt ability 0 channel n can suspend a lower priority channel. 1 channel n cannot suspend any channel, regardless of channel priority. grppri[0:1] channel n current group priority gr oup priority assigned to this channel group when fixed-priority arbitration is enabled. these two bits are read only; writes are ignored. chpri[0:3] channel n arbitration priority channel priority when fixed-priority arbitration is enabled. table 15-19. tcdn 32-bit memory structure dma offset tcdn field 0x1000 + (32 x n) + 0x00 source address (saddr) 0x1000 + (32 x n) + 0x04 transfer attributes (smod, ssize, dmod, dsize) signed source address offset (soff) 0x1000 + (32 x n) + 0x08 signed minor loop offset (smloe, dmloe, mloff) inner ?minor? byte count (nbytes) 0x1000 + (32 x n) + 0x0c last source address adjustment (slast) 0x1000 + (32 x n) + 0x10 destination address (daddr) 0x1000 + (32 x n) + 0x14 current ?major? iteration co unt (citer) signed destinat ion address offset (doff) 0x1000 + (32 x n) + 0x18 last destination addre ss adjustment/scatter gath er address (dlast_sga)
pxd10 microcontroller reference manual, rev. 1 15-28 freescale semiconductor preliminary?subject to change without notice figure 15-19 and table 15-20 define word 0 of the tcdn structure, the saddr field. figure 15-19. tcdn word 0 (tcdn.saddr) field table 15-20. tcdn word 0 (tcdn.saddr) field description figure 15-20 and table 15-21 define word 1 of the tcdn structure, the soff and transfer attribute fields. figure 15-20. tcdn word 1 (tcdn.{soff,smod,ssize,dmod,dsize}) fields 0x1000 + (32 x n) + 0x1c beginning ?major? iteration count (biter) channel control/status (bwc, major.linkch, done, active, major.e_link, e_sg, d_req, int_half, int_maj, start) register address: dma_offset + 0x1000 + (32 x n) + 0x00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r saddr[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r saddr[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented name description value saddr[[0:31] source address memory address pointing to the source data. register address: dma_offset + 0x1000 + (32 x n) + 0x04 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r smod[0:4] ssize[0:2] dmod[0:4] dsize[0:2] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r soff[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented table 15-19. tcdn 32-bit memory structure (continued)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-29 preliminary?subject to change without notice figure 15-21 and table 15-22 define word 2 of the tcdn structure, the nbytes field. table 15-21. tcdn word 1 (tcdn.{smod,ssize,dmod,dsize,soff}) field descriptions name description value smod[0:4] source address modulo 0 sourc e address modulo feature is disabled. non-0 the value defines a specific address bit which is selected to be either the value after saddr + soff calculation is performed or the original register value. this feature provides the ability to easily implement a circular data queue. for data queues requiring power-of-2 ?size? bytes, the queue should be based at a 0-modulo-size address and the smod field set to the appropriate value to freeze the upper address bits. the bit select is defined as ((1 << smod[4:0]) - 1) where a resulting 1 in a bit location selects the next state address for the corresponding address bit location and a 0 selects the original register value for the corresponding address bit location. for this application, the soff is typically set to the transfer size to implement post-increment addressing with the smod function constraining the addresses to a 0-modulo-size range. ssize[0:2] source data transfer size 000 8-bit 001 16-bit 010 32-bit 011 64-bit 100 16-byte (32-bit ahb bus, wrap4 burst) 100 reserved (64-bit ahb bus, reserved) 101 32-byte (if supported by the platform) 110 reserved 111 reserved the attempted specification of a 64-bit source size in a 32-bit amba ahb bus implementation produces a configuration error. likewise, the attempted specification of a 16-byte source size in a 64-bit amba ahb bus implementation generates a configuration error. the attempted specification of a 32-byte burst on platforms that do not support such a transfer type will result in a configuration error. dmod[0:4] destination address modul o see the smod[5:0] definition. dsize[0:2] destination data transfer size see the ssize[2:0] definition. soff[16:31] source address signed offset sign-extended offset applied to the current source address to form the next-state value as each source read is completed.
pxd10 microcontroller reference manual, rev. 1 15-30 freescale semiconductor preliminary?subject to change without notice figure 15-21. tcdn word 2 (tcdn.nbytes) field (dmacr[emlm] = 0) table 15-22. tcdn word 2 (tcdn.nbytes) field description when minor loop mapping (dmacr[emlm] = 1) is enab led, tcd word2 is redefi ned as four fields: a source minor loop offset enable, a destination minor loop offset enable, a minor loop offset field and a nbytes field. register address: dma_offset + 0x1000 + (32 x n) + 0x08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r nbytes[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r nbytes[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented name description value nbytes[0:31] inner ?minor? byte transfer count nu mber of bytes to be transferred in each service request of the channel. as a channel is activat ed, the contents of the appropriate tcd is loaded into the dma engine, and the appropriate reads and wr ites performed until the complete byte transfer count has been transferred. this is an indivisible operation and cannot be stalled or halted. after the minor count is exhausted, the current values of the saddr and daddr are written back into the local memory, the major iteration count is decremented and restored to the local memory. if the major iteration count is completed, additional processing is performed. the nbytes value 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4 gb transfer.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-31 preliminary?subject to change without notice figure 15-22. tcdn word 2 (tcdn.nbytes) field (dmacr[emlm] = 1) register address: dma_offset + 0x1000 + (32 x n) + 0x08 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r smlo e dmlo e mloff[0:13] or nbytes[0:13] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mloff[14:19] or nbytes[14:19] nbytes[20:29] w reset: - - - - - - - - - - - - - - - - = unimplemented table 15-23. tcdn word 2 (tcdn.nbytes) field descriptions name description value smloe source minor loop offset enable this flag selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 the minor loop offset is not applied to the saddr. 1 the minor loop offset is applied to the saddr. dmloe destination minor loop offset enable this flag selects whether the minor loop offset is applied to the destination address upon minor loop completion. 0 the minor loop offset is not applied to the daddr. 1 the minor loop offset is applied to the daddr. nbytes[0:19] or mloff[0:19] inner ?minor? byte transfer count or minor loop offset if both smloe and dmloe are cleared, this field is part of the byte transfer count. if either smloe or dmloe are set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop is completed. nbytes[0:9] inner ?minor? byte transfer count numb er of bytes to be transferred in each service request of the channel. as a channel is activat ed, the contents of the appropriate tcd is loaded into the dma engine, and the appropriate reads and wr ites performed until the complete byte transfer count has been transferred. this is an indivisible operation and cannot be stalled or halted. once the minor count is exhausted, the current values of the saddr and daddr are written back into the local memory, the major iteration count is decremented and restored to the local memory. if the major iteration count is completed, additional processing is performed. this field is extended to 30 bits when both smloe and dmloe are cleared (disabled).
pxd10 microcontroller reference manual, rev. 1 15-32 freescale semiconductor preliminary?subject to change without notice figure 15-23 and table 15-24 define word 3 of the tcdn structure, the slast field. figure 15-23. tcdn word 3 (tcdn.slast) field table 15-24. tcdn word 3 (tcdn.slast) field descriptions figure 15-24 and table 15-25 define word 4 of the tcdn structure, the daddr field. figure 15-24. tcdn word 4 (tcdn.daddr) field table 15-25. tcdn word 4 (tcdn.daddr) field description figure 15-25 and table 15-26 define word 5 of the tcdn stru cture, the citer and doff fields. register address: dma_offset + 0x1000 + (32 x n) + 0x0c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r slast[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r slast[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented name description value slast[0:31] last source address adjustment adjust ment value added to the source address at the completion of the outer major iteration count. this value can be applied to ?restore? the source address to the initial value, or adjust the address to reference the next data structure. register address: dma_offset + 0x1000 + (32 x n) + 0x10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r daddr[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r daddr[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented name description value daddr[0:31] destination address memory addr ess pointing to the destination data.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-33 preliminary?subject to change without notice figure 15-25. tcdn word 5 (tcdn.{citer,doff}) fields register address: dma_offset + 0x1000 + (32 x n) + 0x14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r citer. e_link citer[0:5] or citer.linkch[0:5] citer[6:14] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r doff[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented table 15-26. tcdn word 5 (tcdn.{doff,citer}) field descriptions name description value citer.e_link enable channel-to-channel linking on minor loop complete as the channel completes the inner minor loop, this flag enables the linking to another channel, defined by citer.linkch[5:0]. the link target channel initiates a channel service request via an internal mechanism that sets the tcd.start bit of the specified channel. if channel linking is disabled, the citer value is extended to 15 bits in place of a link channel number. if the "major" loop is exhausted, this link mechanism is suppressed in favor of the major.e_link channel linking. this bit must be equal to the biter.e_link bit otherwise a configuration error will be reported. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. citer[0:5] or citer.linkch[0:5] current ?major? iteration count or link channel number if (tcd.citer.e_link = 0) then no channel-to-channel linking (or chaining) is performed after the inner "minor" loop is exhausted. tcd word 5, bits [30:25] are used to form a 15 bit citer field. else after the "minor" loop is exhausted, the dma engine initiates a channel service request at the channel defined by citer.linkch[5:0] by setting that channel?s tcd.start bit. the value contained in citer.linkch[5:0] must not exceed the number of implemented channels.
pxd10 microcontroller reference manual, rev. 1 15-34 freescale semiconductor preliminary?subject to change without notice figure 15-26 and table 15-27 define word 6 of the tcdn structure, the dlast_sga field. figure 15-26. tcdn word 6 (tcdn.dlast_sga) field citer[6:14] current ?major? iterat ion count this 9 or 15-bit count represents the current major loop count for the channel. it is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. once the major iteration count is exhausted, the channel performs a number of operations (e.g., final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the citer field from the beginning iteration count (biter) field. when the citer field is initially loaded by software, it must be set to the same value as that contained in the biter field. if the channel is configured to execute a single service request, the initial values of biter and citer should be 0x0001. doff[16:31] destination address signed offset sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. register address: dma_offset + 0x1000 + (32 x n) + 0x18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r dlast_sga[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dlast_sga[16:31] w reset: - - - - - - - - - - - - - - - - = unimplemented table 15-26. tcdn word 5 (tcdn.{doff,citer}) field descriptions (continued) name description value
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-35 preliminary?subject to change without notice table 15-27. tcdn word 6 (tcdn.dlast_sga) field description figure 15-27 and table 15-28 define word 7 of the tcdn structure, the biter and control/status fields. figure 15-27. tcdn word 7 (tcdn.{biter,control/status}) fields name description value dlast_sga[31:0 0:31] last destination address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel (scatter/gather) if (tcd.e_sg = 0) then adjustment value added to the destination address at the completion of the outer major iteration count. this value can be applied to ?restore? the destination address to the initial value, or adjust the address to reference the next data structure. else this address points to the beginning of a 0-modulo-32 region containing the next transfer control descriptor to be loaded into this channel. this channel reload is performed as the major iteration count completes. the scatter/gather address must be 0-modulo-32, else a configuration error is reported. register address: dma_offset + 0x1000 + (32 x n) + 0x1c 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r biter[0:15] w reset: - - - - - - - - - - - - - - - - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bwc major.linkch[0:5] done active major. e_link e_sg d_req int_ha lf int_m aj start w reset: - - - - - - - - 0 0 - - - - - 0 = unimplemented table 15-28. tcdn word 7 (tcdn.{biter, control/status}) field descriptions name description value biter.e_link enable channel-to-channel linking on minor loop complete this is the initial value copied into the citer.e_link field when the major loop is completed. the citer.e_link field controls channel linking during channel execution. this bit must be equal to the citer.e_link bit otherwise a configuration error will be reported. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled.
pxd10 microcontroller reference manual, rev. 1 15-36 freescale semiconductor preliminary?subject to change without notice biter[0:5] or biter.linkch[0:5] beginning ?major? iteration count or beginning link channel number this is the initial value copied into the citer field or citer.linkch field when the major loop is completed. the citer fields controls the iteration count and linking during channel execution. if (tcd.biter.e_link = 0) then no channel-to-channel linking (or chaining) is performed after the inner "minor" loop is exhausted. tcd word 5, bits [30:25] are used to form a 15 bit biter field. else after the "minor" loop is exhausted, the dma engine initiates a channel service request at the channel defined by biter.linkch[5:0] by setting that channel?s tcd.start bit. the value contained in biter.linkch[5:0] must not exceed the number of implemented channels. biter[6:14] beginning ?major? iteration count this is the initial value copied into the citer field or citer.linkch field when the major loop is completed. the citer fields controls the iteration count and linking during channel execution. this 9- or 15-bit count represents the beginning major loop count for the channel. as the major iteration count is exhausted, the contents of the entire 16-bit biter entry is reloaded into the 16-bit citer entry. when the biter field is initially loaded by software, it must be set to the same value as that contained in the citer field. if the channel is configured to execute a single service request, the initial values of biter and citer should be 0x0001. table 15-28. tcdn word 7 (tcdn.{biter, control/status}) field descriptions (continued) name description value
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-37 preliminary?subject to change without notice bwc[0:1] bandwidth control this two-bit fi eld provides a mechanism to effectively throttle the amount of bus bandwidth consumed by the dma. in general, as the dma processes the inner minor loop, it continuously generates read/write, read/write, ... sequences until the minor count is exhausted. this field forces the dma to stall after the completion of each read/write access to control the bus request bandwidth seen by the platform?s cross-bar arbitration switch. to minimize start-up latency, bandwidth control stalls are suppressed for the first two ahb bus cycles a nd after the last write of each minor loop. the dynamic priority elevation setting elevates the priority of the dma as seen by the cross-bar arbitration switch for the executing channel. dynamic priority elevation is suppressed during the first two ahb bus cycles. 00 no dma engine stalls 01 dynamic priority elevation 10 dma engine stalls for 4 cycles after each r/w 11 dma engine stalls for 8 cycles after each r/w major.linkch[0:5] link channel number if (tcd.major.e_link = 0) then no channel-to-channel linking (or chaining) is performed after the outer "major" loop counter is exhausted. else after the "major" loop counter is exhausted, the dma engine initiates a channel service request at the channel defined by major.linkch[5:0] by setting that channel?s tcd.start bit. the value contained in major.linkch[5:0] must not exceed the number of implemented channels. done channel done this flag indicates the dma has completed the outer major loop. it is set by the dma engine as the citer count reaches zero; it is cleared by software, or the hardware when the channel is activated. this bit must be cleared in order to write the major.e_link or e_sg bits. active channel active this flag signals the channel is currently in execution. it is set when channel service begins, and is cleared by the dma engine as the inner minor loop completes or if any error condition is detected. table 15-28. tcdn word 7 (tcdn.{biter, control/status}) field descriptions (continued) name description value
pxd10 microcontroller reference manual, rev. 1 15-38 freescale semiconductor preliminary?subject to change without notice major.e_link enable channel-to-channel linking on major loop complete as the channel completes the outer major loop, this flag enables the linking to another channel, defined by major.linkch[5:0]. the link target channel initiates a channel service request via an internal mechanism that sets the tcd.start bi t of the specified channel. to support the dynamic linking coherency model, this field is forced to zero when written to while the tcd.done bit is set. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. e_sg enable scatter/gather processing as the channel completes the outer major loop, this flag enables scatter/gather processing in the current channel. if enabled, the dma engine uses dlast_sga as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure which is loaded as the transfer control descriptor into the local memory. to support the dynamic scatter/gather coherency model, this field is forced to zero when written to while the tcd.done bit is set. 0 the current channel?s tcd is ?normal? format. 1 the current channel?s tcd specifies a scatter gather format. the dlast_sga field provides a memory pointer to the next tcd to be loaded into this channel after the outer major loop completes its execution. d_req disable request if this flag is set, the dma hardware automatically clears the corresponding dmaerq bit when the current major iteration count reaches zero. 0 the channel?s dmaerq bit is not affected. 1 the channel?s dmaerq bit is cleared when the outer major loop is complete. int_half enable an interrupt when major counter is half complete if this flag is set, the channel generates an interrupt request by setting the appropriate bit in the dmaint register when the current major iteration count reaches the halfway poi nt. specifically, the comparison performed by the dma engine is (citer == (biter >> 1)). this halfway point interrupt request is provided to support double-buffered schemes or other types of data movement where the processor needs an early indication of the transfer?s progress. the halfway complete interrupt is disabled when biter values are less than two. 0 the half-point interrupt is disabled. 1 the half-point interrupt is enabled. table 15-28. tcdn word 7 (tcdn.{biter, control/status}) field descriptions (continued) name description value
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-39 preliminary?subject to change without notice 15.3 functional description this section provides an overview of the microarchitecture and func tional operation of the dma module. 15.3.1 dma microarchitecture the dma module is partitioned into two major m odules: the dma engine and the transfer control descriptor local memory. additionall y, the dma engine is further partitioned into four submodules, which are detailed below. ? dma engine ? addr_path : this module implements registered vers ions of two channel transfer control descriptors: channel "x" and channel ?y?, and is responsible for all the master bus address calculations. all the implemen ted channels provide the exact same functionality. this hardware structure allows the data transfers asso ciated with one channel to be preempted after the completion of a read/write sequence if a highe r priority channel service request is asserted while the first channel is active. once a channel is activated, it runs until the minor loop is completed unless preempted by a higher prio rity channel. this capability provides a mechanism (optionally enabled by dchprin[ecp ]) where a large data move operation can be preempted to minimize the time anothe r channel is blocke d from execution. when any other channel is activated, the contents of its transfer control descriptor is read from the local memory and loaded into the regist ers of the other addr _path.channel_{x,y}. once the inner minor loop completes execut ion, the addr_path hardware wr ites the new values for the tcdn.{saddr, daddr, citer} back into the loca l memory. if the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the tcdn.citer field, a nd a possible fetch of the next tc dn from memory as part of a scatter/gather operation. ? data_path : this module implements the actual bus ma ster read/write datapath. it includes 32 bytes of register storage (match ing the maximum transfer size) and the necessary mux logic to support any required data alignm ent. the amba-ahb read data bus is the primary input, and int_maj enable an interrupt when major iteration count completes if this flag is set, the channel generates an interrupt request by setting the appropriate bit in the dmaint register when the current major iteration count reaches zero. 0 the end-of-major loop interrupt is disabled. 1 cthe end-of-major loop interrupt is enabled. start channel start if this flag is set, the channel is requesting service. the dma hardware automatica lly clears this flag after the channel begins execution. 0 the channel is not explicitly started. 1 the channel is explicitly started via a software initiated service request. table 15-28. tcdn word 7 (tcdn.{biter, control/status}) field descriptions (continued) name description value
pxd10 microcontroller reference manual, rev. 1 15-40 freescale semiconductor preliminary?subject to change without notice the ahb write data bus is the primary output. the addr_ and data_path modules directly support the 2-stage pipelined amba-ahb bus. the addr_path module represents the 1st stage of th e bus pipeline (the address phase), while the data_path module implements the 2nd stag e of the pipeline (the data phase). ? pmodel_charb : this module implements the first s ection of dma?s programming model as well as the channel arbitration logic. the pr ogramming model registers are connected to the ips bus (not shown). the ipd_req[n] inputs and dma_ipi_int[n] outputs are also connected to this module (via the control logic). ? control : this module provides all the control functi ons for the dma engine. for data transfers where the source and destination sizes are equal, the dma engine performs a series of source read, destination write ope rations until the number of bytes specified in the inner ?minor loop? byte count has been moved. for de scriptors where the sizes are not equal, multiple access of the smaller size data are required for each refere nce of the larger size. as an example, if the source size references 16-bit data and the des tination is 32-bit data, two reads are performed, then one 32-bit write. ? transfer_control_descriptor local memory ? memory controller : this logic implements the require d dual-ported controller, handling accesses from both the dma engine as well as references from the ips bus. as noted earlier, in the event of simultaneous acce sses, the dma engine is given pr iority and the ips transaction is stalled. the hooks to a bist controller for the local tcd memory are included in this module. ? memory array : the tcd is implemented using a single-ported, synchr onous compiled ram memory array 15.3.2 dma basic data flow the basic flow of a data transfer can be pa rtitioned into three se gments. as shown in figure 15-28 , the first segment involves the channel service request. in the diagram, this example uses the assertion of the ipd_req[n] signal to request service for channel n. channel service re quest via software and the tcdn.start bit follows the same basic flow as an ipd_req. the ipd_req[n] input signal is registered internally and then routed to through the dma engine, first through the control module, then into the programming model/channel arbitration (pmodel_char b) module. in the next cycle, th e channel arbitration is performed, either using the fixed-priority or round-robin algorithm. after the arb itration is complete, the activated channel number is sent through the a ddress path (addr_path) and convert ed into the required address to access the tcd local memory. next, the tcd memory is accessed and the required descriptor read from the local memory and loaded into the dma_engi ne.addr_path.channel_{x,y} regi sters. the tcd memory is organized 64-bits in width to mi nimize the time needed to fetch the activated channel?s descriptor and load it into the dma_engine .addr_path.channel_{x,y} registers.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-41 preliminary?subject to change without notice figure 15-28. dma operation, part 1 in the second part of the basic data flow as shown in figure 15-29 , the modules associated with the data transfer (addr_path, data_path a nd control) sequence through the requi red source reads and destination writes to perform the actual data movement. the source reads are in itiated and the fetched data is temporarily stored in the data_pa th module until it is gated on to the amba-ahb bus during the destination write. this source re ad/destination write pro cessing continues until th e inner minor byte count has been transferred. the dma_ipd_done[n ] signal is asserted at the end of the minor byte count transfer. j j+1 n-1 sram transfer control descriptor (tcd) dma engine addr_path data_path dma ips bus amba bus ipd_req[n-1:0] dma_ipi_int[n-1:0] 0 c o n t r o l pmodel_charb addr wdata[31:0] rdata[31:0] hrdata[{63,31}:0] hwdata[{63,31}:0] haddr[31:0] dma_ipd_done[n-1:0]
pxd10 microcontroller reference manual, rev. 1 15-42 freescale semiconductor preliminary?subject to change without notice figure 15-29. dma operation, part 2 once the inner minor byte count has been moved, the fina l phase of the basic data flow is performed. in this segment, the addr_path logic performs the required updates to ce rtain fields in the channel?s tcd, e.g., saddr, daddr, citer. if the outer ma jor iteration count is exhausted, th en there are additional operations which are performed. these in clude the final addr ess adjustments and reloading of the biter field into the citer. additionally, asserti on of an optional interrupt request occurs at this time, as doe s a possible fetch of a new tcd from memory using the s catter/gather address poi nter included in the descriptor. the updates to the tcd memory and the assertion of an interrupt request are shown in figure 15-30 . j j+1 n-1 sram transfer control descriptor (tcd) dma engine addr_path data_path dma ips bus amba bus ipd_req[n-1:0] dma_ipi_int[n-1:0] 0 c o n t r o l pmodel_charb addr wdata[31:0] rdata[31:0] hrdata[{63,31}:0] hwdata[{63,31}:0] haddr[31:0] dma_ipd_done[n-1:0]
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-43 preliminary?subject to change without notice figure 15-30. dma operation, part 3 15.3.3 dma performance this section addresses the performance of the dma module, focusing on two sepa rate metrics. in the traditional data movement context, pe rformance is best expressed as the peak data transfer rates achieved using the dma. in most im plementations, this transfer rate is limited by the speed of the source and destination address spaces. in a s econd context where device-paced m ovement of single data values to/from peripherals is dominant, a me asure of the requests which can be se rviced in a fixed time is a more interesting metric. in this environment, the speed of the source and destination address spaces remains important, but the microarchitectur e of the dma also factors signifi cantly into the resulting metric. the peak transfer rates for several different source and destination tr ansfers are shown in table 15-29 . the following assumptions apply to table 15-29 and table 15-30 : ? platform sram can be accessed with zero wait-states when viewed from the amba-ahb data phase j j+1 n-1 sram transfer control descriptor (tcd) dma engine addr_path data_path dma ips bus amba bus ipd_req[n-1:0] dma_ipi_int[n-1:0] 0 c o n t r o l pmodel_charb addr wdata[31:0] rdata[31:0] hrdata[{63,31}:0] hwdata[{63,31}:0] haddr[31:0] dma_ipd_done[n-1:0]
pxd10 microcontroller reference manual, rev. 1 15-44 freescale semiconductor preliminary?subject to change without notice ? all ips reads require two wait-states, and ips wr ites three wait-states, again viewed from the system bus data phase ? all ips accesses are 32 bits in size table 15-29 presents a peak transfer rate comparison, measured in megabyte s per second. in this table, the platform_sram-to-platform_sram tran sfers occur at the native platform datapath width, i.e., either 32- or 64-bits per access. for a ll transfers involving the ips bus, 32-bit transfer sizes are used. in all cases, the transfer rate includes the time to read the s ource plus the time to write the destination. the second performance metric is a measure of the number of dma reque sts which can be serviced in a given amount of time. for this metric, it is assumed the peripheral request cause s the channel to move a single ips-mapped operand to/from the platform sram. the same timing assumptions used in the previous example apply to this calculation. in partic ular, this metric also re flects the time required to activate the channel. the dma design supports the following hardware service request sequence: ? cycle 1: ipd_req[n] is asserted ? cycle 2: the ipd_req[n] is registered locally in the dma module and qualified (tcd.start bit initiated requests start at this point with th e registering of the ip s write to tcd word7) ? cycle 3: channel arbitration begins ? cycle 4: channel arbitration completes. the tran sfer control descriptor local memory read is initiated. ? cycle 5 - 6: the first two parts of the activated channel?s tcd is read from the local memory. the memory width to the dma engine is 64 bits, so the entire descriptor can be accessed in four cycles. ? cycle 7: the first amba-ahb read cycle is initiated, as the third pa rt of the channe l?s tcd is read from the local memory. depending on the state of the platform?s cros sbar switch, arbi tration at the system bus may insert an ad ditional cycle of delay here. ? cycle 8 - ?: the last part of the tcd is read in. this cycle represen ts the 1st data phase for the read, and the address phase for the destination write. the exact timing from this point is a function of the response ti mes for the channel?s read and write accesses. in this case of an ips read and a plat form sram write, the comb ined data phase time is 4 cycles. for an sram read a nd ips write, it is 5 cycles. table 15-29. dma peak transfer rates [mb/s] platform speed, width platform sram-to- platform sram 32-bit ips-to- platform sram platform sram-to- 32-bit ips 66.7 mhz, 32-bit 133.3 66.7 53.3 66.7 mhz, 64-bit 266.7 66.6 53.3 83.3 mhz, 32-bit 166.7 83.3 66.7 83.3 mhz, 64-bit 333.3 83.3 66.7 100.0 mhz, 32-bit 200.0 100.0 80.0 100.0 mhz, 64-bit 400.0 100.0 80.0 133.3 mhz, 32-bit 266.7 133.3 106.7 133.3 mhz, 64-bit 533.3 133.3 106.7 150.0 mhz, 32-bit 300.0 150.0 120.0 150.0 mhz, 64-bit 600.0 150.0 120.0
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-45 preliminary?subject to change without notice ? cycle ?+1: this cycle represents the da ta phase of the last destination write ? cycle ?+2: the dma engine completes the executi on of the inner minor loop and prepares to write back the required tcdn fields in to the local memory. tcd word7 is read and checked for channel linking or scatter/gather requests. ? cycle ?+3: the appropriate fields in the first pa rt of the tcdn are written back into the local memory ? cycle ?+4: the fields in the second part of the tcdn are written back into the local memory. this cycle coincides with the next channel arbitration cycle start. ? cycle ?+5: the next channel to be activated performs the read of th e first part of its tcd from the local memory. this is equivalent to cycle 4 for the first channel?s service request. assuming zero wait states on the ahb system bus, dma requests can be processed every 9 cycles. assuming an average of the access times associated with ips-to-sram (4 cycles) and sram-to-ips (5 cycles), dma requests can be processed every 11.5 cycles (4 + (4+5) ? 2 + 3). this is the time from cycle 4 to cycle ??+5?. the resulting peak request rate, as a function of the platform frequency, is shown in table 15-30 . this metric represents millions of requests per second. a general formula to compute the peak re quest rate (with overl apping requests) is: peakreq = freq ? [ entry + (1 + read_ws) + (1 + write_ws) + exit ] where: peakreq - peak request rate freq - platform frequency entry - channel startup (4 cycles) read_ws - wait states seen during the system bus read data phase write_ws - wait states seen duri ng the system bus write data phase exit - channel shutdown (3 cycles) for example: consider a platform with the following characteristics: table 15-30. dma peak request rate [mreq/sec] platform speed request rate (zero wait state) request rate (with wait states) 66.6 mhz 7.4 5.8 83.3 mhz 9.2 7.2 100.0 mhz 11.1 8.7 133.3 mhz 14.8 11.6 150.0 mhz 16.6 13.0
pxd10 microcontroller reference manual, rev. 1 15-46 freescale semiconductor preliminary?subject to change without notice ? platform sram can be accessed with one wait-state when view ed from the amba-ahb data phase ? all ips reads require two wait-states, and ips wr ites three wait-states, again viewed from the system bus data phase ? platform operates at 150 mhz for an sram to ips transfer: peakreq = 150 mhz ? [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 mreq/sec for an ips to sram transfer: peakreq = 150 mhz ? [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 mreq/sec assuming an even distribution of the two transfer types, the average peak request rate would be: peakreq = (11.5 mreq/sec + 12.5 mreq/sec) ? 2 = 12.0 mreq/sec the minimum number of cycles to pe rform a single read/write, zero wait states on the system bus, from a cold start (where no channel is executing, dma is idle) are: ? 11 cycles for a software (tcd.start bit) request ? 12 cycles for a hardware (ipd_req signal) request two cycles account for the arbitratio n pipeline and one extra cycle on th e hardware request resulting from the internal registering of the ipd_re q signals. for the peak request rate calculations above, the arbitration and request registering is absorbed in or overlap the previous executing channel. note when channel linking or scatter/gather is enabled, a two cycle delay is imposed on the next channel selecti on and startup. this allows the link channel or the scatter/gather channel to be eligible and considered in the arbitration pool for ne xt channel selection. 15.4 initialization/application information 15.4.1 dma initialization a typical initialization of the dma is: 1. write the dmacr register if a configuration other than the default is desired. 2. write the channel priority levels into the dchp rin registers if a conf iguration other than the default is desired. 3. enable error interrupts in the dmaeei registers if so desired. 4. write the 32 byte tcd for each ch annel that may request service. 5. enable any hardware service requests via the dmaerq register.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-47 preliminary?subject to change without notice 6. request channel service by either software (setting the tcd.start bit) or by hardware (slave device asserting its ipd_req signal). after any channel requests service, a channel is select ed for execution based on th e arbitration and priority levels written into the programmer' s model. the dma engine will read the entire tcd for the selected channel into its internal address path module. as the tc d is being read, the first transfer is initiated on the ahb bus unless a configuration erro r is detected. transfers from th e source (as defined by the source address, tcd.saddr) to the destinat ion (as defined by the destination address, tcd.daddr ) continue until the specified number of bytes (tcd.nbytes) have been transferred. when the transfer is complete, the dma engine's local tcd.saddr, tcd .daddr, and tcd.citer are written ba ck to the main tcd memory and any minor loop channe l linking is performed, if enabled. if the major loop is exhausted, further post processing is executed, i.e. interrupt s, major loop channel li nking, and scatter/gather operations, if enabled. 15.4.2 dma programming errors the dma performs various tests on the transfer control descriptor to verify cons istency in the descriptor data. most programming errors are reported on a per ch annel basis with the excep tion of two errors; group priority error and channel priority error, gp e and cpe in the dmaes register respectively. for all error types other than group or channel priori ty errors, the channel number causing the error is recorded in the dmaes register. if the error source is not removed before th e next activation of the problem channel, the error will be detected and recorded again. the sequence listed below is correct. for item 2, th e dma_ipd_ack{done} lines will assert only if the selected channel is requesti ng service via the ipd_req signa l. i think the typical application will enable error interrupts for all channels. so the user will get an error interrupt , but the channel num ber for the dmaerr register and the error interrupt re quest line may be wrong because th ey reflect the selected channel. channel priority errors are identifi ed within a group after that group has been selected as the active group. for example: 1. the dma is configured for fixed gro up and fixed channel arbitration modes. 2. group3 is the highest priority and al l channels are unique in that group. 3. group2 is the next highest priority and has two channels with the same priority level. 4. if group3 has any service requests, those requests will be executed. 5. once all of group3 requests have complete d, group2 will be the next active group. 6. if group2 has a service request, then an undefined channel in group2 will be selected and a channel priority error will occur. 7. this will repeat until the all of group2 reque sts have been removed or a higher priority group3 request comes in. a group priority error is globa l and any request in any group wi ll cause a group priority error. in general, if priority levels are not unique, the highe st (channel/group) priority that has an active request will be selected, but the lowest num bered (channel/group) with that priori ty will be select ed by arbitration
pxd10 microcontroller reference manual, rev. 1 15-48 freescale semiconductor preliminary?subject to change without notice and executed by the dma engine. the hardware servi ce request handshake signals, error interrupts and error reporting will be associat ed with the selected channel. 15.4.3 dma arbitration mode considerations 15.4.3.1 fixed group arbitration, fixed channel arbitration in this mode, the channel service request from the hi ghest priority channel in the highest priority group will be selected to execute. if the dma is programmed so the channels within one group use "fixed" priorities, and that group is assigned the highest "fixed " priority of all groups, it is possible for that group to take all the bandwidth of the dma controller ? i.e. no other groups will be serv iced if there is always at least one dma request pending on a ch annel in the highest priority gro up when the controller arbitrates the next dma request. the advantage of this scenario is that latency can be small for channels that need to be serviced quickly. preemption is available in this scenario only. 15.4.3.2 round-robin grou p arbitration, fixed channel arbitration the occurrence of one or more dma requests from one or more gr oups, the channel with the highest priority from a specific group will be serviced first. groups are serviced starting with the highest group number with an service request and rotating thr ough to the lowest group number containing a service request. once the channel request is serviced, the group round robin algorithm will se lect the highest pending request from the next group in the round robin sequence. servicing cont inues round robin, always servicing the highest priority channel in the next gr oup in the sequence, or just skipping a group if it has no pending requests. if a channel requests service at a ra te that equals or exceeds the round ro bin service rate, then that channel will always be serviced before lower priority cha nnels in the same group, and thus the lower priority channels will never be serviced. the advantage of this scenario is that no one group uses all the dma bandwidth. the highest priority channel sel ection latency is potentially great er than fixed/fixed arbitration. excessive request rates on high priority channels can prevent the servicing of lower priority channels in the same group. 15.4.3.3 round-robin group arbitration, round-robin channel arbitration groups will be servic ed as described in section 15.4.3.2, round -robin group arbitration, fixed channel arbitration,? but this time channels will be serviced in channel number order. only one channel is serviced from each requesting group for each round robin pass through the groups. within each group, channels are serv iced starting with the highest ch annel number and rotating through to the lowest channel number without re gard to channel priority levels.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-49 preliminary?subject to change without notice because channels are serviced in round robin manner, any channel that generates dma reque sts faster than a combination of the group round robin service rate and the channel service ra te for its group will not prevent the servicing of other channels in its group. any dma requests that are not serviced are simply lost, but at least one channel will be serviced. this scenario ensures that all channe ls will be guaranteed se rvice at some point, regardless of the request rates. however, the potential latency could be quite high. all channels are treated equally. priority leve ls are not used in r ound robin/round robin mode. 15.4.3.4 fixed group arbitration, round-robin channel arbitration the highest priority group with a requ est will be serviced. lo wer priority groups will be serviced if no pending requests exist in th e higher priority groups. within each group, channels are serv iced starting with the highest ch annel number and rotating through to the lowest channel number without regard to the channel priority levels assigned within the group. this scenario could cause the same bandwid th consumption problem as indicated in section 15.4.3.1, fixed group arbitration, fi xed channel arbitration,? but all the channels in the highest priority group will be serviced. service latency will be short on the highest priori ty group, but can become much longer as the group priority decreases. 15.4.4 dma transfer 15.4.4.1 single request to perform a simply transfer of ?n? bytes of data w ith one activation, set the major loop to one (tcd.citer = tcd.biter = 1). the data transf er will begin after the channel serv ice request is acknowledged and the channel is selected to exec ute. once the transfer is co mplete, the tcd.done bit will be set and an interrupt will be generated if properly enabled. for example, the following tcd entry is configured to transfer 16 byte s of data. the dm a is programmed for one iteration of the major loop transferring 16 bytes per iteration. the source memory has a byte wide memory port located at 0x1000. the destination memory has a word wide port located at 0x2000. the address offsets are programmed in increments to matc h the size of the transfer; one byte for the source and four bytes for the destination. the fi nal source and destinati on addresses are adjusted to return to their beginning values. tcd.citer = tcd.biter = 1 tcd.nbytes = 16 tcd.saddr = 0x1000 tcd.soff = 1 tcd.ssize = 0
pxd10 microcontroller reference manual, rev. 1 15-50 freescale semiconductor preliminary?subject to change without notice tcd.slast = -16 tcd.daddr = 0x2000 tcd.doff = 4 tcd.dsize = 2 tcd.dlast_sga= -16 tcd.int_maj = 1 tcd.start = 1 (tcd.word7 should be written last after all other fields have been initialized) all other tcd fields = 0 this generates the following sequence of events: 1. ips write to the tcd.start bit requests channel service 2. the channel is selected by arbitration for servicing 3. dma engine writes: tcd.done = 0, tcd.start = 0, tcd.active = 1 4. dma engine reads: channel tcd data from local memory to internal register file 5. the source to destination transfers are executed as follows: a. read_byte(0x1000), rea d_byte(0x1001), read_byte( 0x1002), read_byte(0x1003) b. write_word(0x2000) -> first iteration of the minor loop c. read_byte(0x1004), rea d_byte(0x1005), read_byte( 0x1006), read_byte(0x1007) d. write_word(0x2004) -> second iteration of the minor loop e. read_byte(0x1008), rea d_byte(0x1009), read_byte(0 x100a), read_byte(0x100b) f. write_word(0x2008) -> third iteration of the minor loop g. read_byte(0x100c), r ead_byte(0x100d), read_byte (0x100e), read_byte(0x100f) h. write_word(0x200c) -> last iteration of the minor loop -> major loop complete 6. dma engine writes: tcd.saddr = 0x1000, tcd.daddr = 0x2000, tcd.citer = 1 (tcd.biter) 7. dma engine writes: tcd.active = 0, tcd.done = 1, dmaint[n] = 1 8. the channel retires the dma goes idle or se rvices next channel. 15.4.4.2 multiple requests the next example is the sa me as the previous example, with the exception of transfer ring 32 bytes via two hardware requests. the only fields that change are the major loop iteration count and the final address offsets. the dmais programmed for two iterations of the major loop transferri ng 16 bytes per iteration. after the channel?s hardware requests is enabled in the dmaerq register, channel service requests are initiated by the slave device.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-51 preliminary?subject to change without notice tcd.citer = tcd.biter = 2 tcd.slast = -32 tcd.dlast_sga = -32 this would generate the fo llowing sequence of events: 1. first hardware (ipd_req) request for channel service 2. the channel is selected by arbitration for servicing 3. dma engine writes: tcd.done = 0, tcd.start = 0, tcd.active = 1 4. dma engine reads: channel tcd data from local memory to internal register file 5. the source to destination transfers are executed as follows: a. read_byte(0x1000), rea d_byte(0x1001), read_byte( 0x1002), read_byte(0x1003) b. write_word(0x2000) -> first iteration of the minor loop c. read_byte(0x1004), rea d_byte(0x1005), read_byte( 0x1006), read_byte(0x1007) d. write_word(0x2004) -> second iteration of the minor loop e. read_byte(0x1008), rea d_byte(0x1009), read_byte(0 x100a), read_byte(0x100b) f. write_word(0x2008) -> third iteration of the minor loop g. read_byte(0x100c), r ead_byte(0x100d), read_byte (0x100e), read_byte(0x100f) h. write_word(0x200c) -> last iteration of the minor loop 6. dma engine writes: tcd.saddr = 0x1010, tcd.daddr = 0x2010, tcd.citer = 1 7. dma engine writes: tcd.active = 0 8. the channel retires -> one iteration of the major loop the dma goes idle or se rvices next channel. 9. second hardware (ipd_req) requests channel service 10. the channel is selected by arbitration for servicing 11. dma engine writes: tcd.done = 0, tcd.start = 0, tcd.active = 1 12. dma engine reads: channel tcd data from local memory to internal register file 13. the source to destination transfers are executed as follows: a. read_byte(0x1010), rea d_byte(0x1011), read_byte( 0x1012), read_byte(0x1013) b. write_word(0x2010) -> first iteration of the minor loop c. read_byte(0x1014), rea d_byte(0x1015), read_byte( 0x1016), read_byte(0x1017) d. write_word(0x2014) -> second iteration of the minor loop e. read_byte(0x1018), rea d_byte(0x1019), read_byte(0 x101a), read_byte(0x101b) f. write_word(0x2018) -> third iteration of the minor loop g. read_byte(0x101c), r ead_byte(0x101d), read_byte (0x101e), read_byte(0x101f)
pxd10 microcontroller reference manual, rev. 1 15-52 freescale semiconductor preliminary?subject to change without notice h. write_word(0x201c) -> last iteration of the minor loop -> major loop complete 14. dma engine writes: tcd.saddr = 0x1000, tcd.daddr = 0x2000, tcd.citer = 2 (tcd.biter) 15. dma engine writes: tcd.active = 0, tcd.done = 1, dmaint[n] = 1 16. the channel retires -> major loop complete the dma goes idle or services the next channel. 15.4.5 tcd status 15.4.5.1 minor loop complete there are two methods to test for minor loop completi on when using software init iated service requests. the first method is to read the tcd.citer field and test for a change. anothe r method may be extracted from the sequence shown below. the second method is to test the tcd.start bit an d the tcd.active bit. the minor loop complete condition is indicated by both bits reading zer o after the tcd.start was written to a one. polling the tcd.active bit may be inconclusi ve because the active status may be missed if the channel execution is short in duration. the tcd status bits execute the following sequence for a software activated channel: 1. tcd.start = 1, tcd.active = 0, tcd.done = 0 (channel service request via software) 2. tcd.start = 0, tcd.active = 1, tc d.done = 0 (channel is executing) 3. tcd.start = 0, tcd.active = 0, tc d.done = 0 (channel has complete d the minor loop and is idle) or tcd.start = 0, tcd.active = 0, tc d.done = 1 (channel has complete d the major loop and is idle) the best method to test for minor loop completion wh en using hardware initiate d service requests is to read the tcd.citer field and test for a change. the hardware request and acknowledge handshakes signals are not visible in the programmer?s model. the tcd status bits execute the following sequence for a hardware activated channel: 1. ipd_req asserts (channel se rvice request via hardware) 2. tcd.start = 0, tcd.active = 1, tc d.done = 0 (channel is executing) 3. tcd.start = 0, tcd.active = 0, tc d.done = 0 (channel has complete d the minor loop and is idle) or tcd.start = 0, tcd.active = 0, tc d.done = 1 (channel has complete d the major loop and is idle) for both activation types, the major loop complete stat us is explicitly indica ted via the tcd.done bit. the tcd.start bit is cleared automatically when th e channel begins execution regardless of how the channel was activated.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-53 preliminary?subject to change without notice 15.4.5.2 active channel tcd reads the dma will read back the 'true' tcd.saddr, tcd.daddr, and tcd.nbytes values if read while a channel is executing. the 'true' values of the saddr, daddr, and nbytes are the va lues the dma engine is currently using in its internal register file and not the values in the tcd local memory for that channel. the addresses (saddr and daddr) and nbyt es (decrements to zero as the tr ansfer progresses) can give an indication of the progress of the tr ansfer. all other values are read back from the tcd local memory. 15.4.5.3 preemption status preemption is only available when fixed arbitration is selected for both group and channel arbitration modes. a preempt-able situ ation is one in which a preempt-ena bled channel is running and a higher priority request be comes active. when the dma engine is not operating in fixed group, fixed channel arbitration mode, the determination of the relative priority of the actively running and the outstanding requests become undefined. channel a nd/or group priorities are treated as equal (constantly rotating) when round-robin arbitration mode is selected. the tcd.active bit for the preempted channel remain s asserted throughout the preemption. the preempted channel is temporarily suspended wh ile the preempting channel executes one iteration of the major loop. two tcd.active bits set at the same time in the overa ll tcd map indicates a high er priority channel is actively preempting a lo wer priority channel. the worst case latency when switching to a preempt channel is the summation of: ? arbitration latency (2 cycles) ? bandwidth control stalls (if enabled) ? the time to execute two read/write sequences (including ahb bus holds ; a system dependency driven by the slave devices or the crossbar) 15.4.6 channel linking channel linking (or chaining) is a m echanism where one channel sets the tcd.start bit of another channel (or itself) thus initiating a service request for that channel. this operation is automatically performed by the dma engine at the conclusion of the ma jor or minor loop when properly enabled. the minor loop channel linking occurs at the completio n of the minor loop (or one iteration of the major loop). the tcd.citer.e_link field are used to determ ine whether a minor loop link is requested. when enabled, the channel link is made after each iterati on of the major loop except for the last. when the major loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be made. for example, with the initial fields of: tcd.citer.e_link = 1 tcd.citer.linkch = 0xc tcd.citer value = 0x4 tcd.major.e_link = 1 tcd.major.linkch = 0x7
pxd10 microcontroller reference manual, rev. 1 15-54 freescale semiconductor preliminary?subject to change without notice will execute as: 1. minor loop done -> set channel 12 tcd.start bit 2. minor loop done -> set channel 12 tcd.start bit 3. minor loop done -> set channel 12 tcd.start bit 4. minor loop done, major loop done -> set channel 7 tcd.start bit when minor loop linking is enabled (t cd.citer.e_link = 1), the tcd.citer field uses a nine bit vector to form the current iteration count. when minor loop linking is disabled (t cd.citer.e_link = 0), the tcd.citer fi eld uses a 15 bit vector to form the current iteration count. the bits associated with the tcd.citer.linkch field are concatenated onto the citer value to increase the range of the citer. note the tcd.citer.e_link bit and the tcd .biter.e_link bit must equal or a configuration error will be reported. th e citer and biter vector widths must be equal to calculate the major loop, half-way done interrupt point. 15.4.7 dynamic programming this section provides recommended methods to cha nge the programming model during channel execution. 15.4.7.1 dynamic priority changing the following two options are r ecommended for dynamically changing channel priority levels: 1. switch to round-robin channel arbi tration mode, change the channel priorities, then switch back to fixed arbitration mode. 2. disable all the channels within a group, then change the channel prio rities within that group only, then enable the appropriate channels. the following two options are av ailable for dynamically changing group priority levels: 1. switch to round-robin group arbitr ation mode, change the group priorities, then switch back to fixed arbitration mode. 2. disable all channels, change the group priori ties, then enable the appropriate channels. 15.4.7.2 dynamic channel linki ng and dynamic scatter/gather dynamic channel linking and dynamic scatter/gather is the process of changing the tcd.major.e_link or tcd.e_sg bits during channel execution. these bits are read from the tcd local memory at the end of channel execution thus allowing the user to en able either feature dur ing channel execution. because the user is allowed to change the configur ation during execution, a c oherency model is needed. consider the scenario where the user attempts to execute a dynamic channel link by enabling the tcd.major.e_link bit at the same time the dma engi ne is retiring the channel. the tcd.major.e_link would be set in the programmer?s m odel, but it would be unclear whet her the actual link was made before the channel retired.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 15-55 preliminary?subject to change without notice the following coherency model is recommended when executing a dynamic channel link or dynamic scatter/gather request: 1. set the tcd.major.e_link bit. 2. read back the tcd.major.e_link bit. 3. test the tcd.major.e_link request status: a. if the bit is set, the dynamic link attempt was successful. b. if the bit is cleared, the attempted dynami c link did not succeed, the channel was already retiring. this same coherency model is tr ue for dynamic scatter/gather opera tions. for both dynamic requests, the tcd local memory controller forces the tcd.major.e_ link and tcd.e_sg bits to zero on any writes to a channel?s tcd.word7 after that channel?s tcd.done bit is set indicating the major loop is complete. note the user must clear the tcd.done bi t before writing th e tcd.major.e_link or tcd.e_sg bits. the tcd.done bit is cleared automatically by the dma engine after a channel begins execution. 15.4.8 hardware request release timing this section provides a timing di agram for deasserting the ipd_r eq hardware request signal. figure 15-31 shows two read write sequen ces with grey indicating the release of the ipd_req hardware request signal. figure 15-31. ipd_req hardware handshake rd1 wr1 rd2 wr2 hclk htrans ahb_ap ipd_req ipd_ack ipd_done hwrite rd1 wr1 rd2 wr2 ahb_dp done_lw ipd_complete note: ipd_req must de-assert in this cycle unless another service request is intended
pxd10 microcontroller reference manual, rev. 1 15-56 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 16-1 preliminary?subject to change without notice chapter 16 error correction status module (ecsm) 16.1 introduction the error correction status module (e csm) provides a myriad of miscel laneous control functions for the device including program-visible info rmation about configuration and revision levels, a reset status register, wakeup control for exiting low-power mode s, and optional features such as information on memory errors reported by error-correcting codes. the register prot ection module (see appendix a, register s under protection ) provides access protection for slave modules intc, ecsm, mpu, stm, and swt. 16.2 overview the error correction status module is mapped into the ips space and s upports a number of miscellaneous control functions for the device. 16.3 features the ecsm includes these features: ? program-visible information on th e device configurat ion and revision ? optional registers for capturing information on memory errors if error-correcting codes (ecc) are implemented ? optional registers to specify the generation of si ngle- and double-bit memory data inversions for test purposes if error-correcting codes are implemented ? axbs_lite priority functions, including fo rcing round robin and high priority enabling ? spp_ips_reg_protection provides privileged-only ac cess to selected on-plat form slave devices: intc, ecsm, mpu, stm, and swt. 16.4 memory map and register description this section details the programming model for the error correction status module. this is a 128-byte space mapped to the region serviced by an ips bus controller. 16.4.1 memory map the error correction status module does not include a ny logic which provides acces s control. rather, this function is supported using the standard access control logic pr ovided by the ips controller. table 16-1 is a 32-bit view of the ecsm?s memory map.
pxd10 microcontroller reference manual, rev. 1 16-2 freescale semiconductor preliminary?subject to change without notice 16.4.2 register description attempted accesses to reserved addresses result in an error termination, while attempted writes to read-only registers are ignored and do not terminate with an error. unle ss noted otherwise, writes to the table 16-1. ecsm memory map ecsm offset register 0x00 processor core type (pct) revision (rev) reserved 0x08 reserved 0x0c reserved misc reset status (mrsr) 0x10 reserved misc wakeup control (mwcr) 0x14 reserved 0x18 reserved 0x1c reserved misc interrupt (mir) 0x20 reserved 0x24 miscellaneous user-defined control register (mudcr) 0x28 reserved 0x2c - 0x3c reserved 0x40 reserved ecc configuration (ecr) 0x44 reserved ecc status (esr) 0x48 reserved ecc error generation (eegr) 0x4c reserved 0x50 flash ecc address (fear) 0x54 reserved flash ecc master (femr) flash ecc attributes (feat) 0x58 reserved 0x5c flash ecc data (fedr) 0x60 ram ecc address (rear) 0x64 reserved ram ecc syndrome (resr) ram ecc master (remr) ram ecc attributes (reat) 0x68 reserved 0x6c ram ecc data (redr) 0x70 - 0x7c reserved
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 16-3 preliminary?subject to change without notice programming model must match the size of the register, e.g., an n-bit re gister only supports n-bit writes, etc. attempted writes of a different size than the re gister width produce an erro r termination of the bus cycle and no change to the targeted register. 16.4.2.1 processor core type (pct) register the pct is a 16-bit read-onl y register specifying the architecture of the processor core in the device. the state of this register is define d by a module input signal; it can onl y be read from the ips programming model. any attempted write is ignored. see figure 16-1 and table 16-2 for the processor core type definition. 16.4.2.2 revision (rev) register the rev is a 16-bit read-only regist er specifying a revision number that can only be read from the ips programming model. any atte mpted write is ignored. see figure 16-2 and table 16-3 for the revision definition. register address: ecsm base + 0x00 0123456789101112131415 r pct[0:15] w reset:1110000000010010 = unimplemented figure 16-1. processor core type (pct) register table 16-2. processor core type (pct) field descriptions name description 0-15 pct[0:15] processor core type 0xe012 identifies the e200z0h powe r architecture processor core. register address: ecsm base + 0x02 0123456789101112131415 r rev[0:15] w reset: rev[0:15] = unimplemented figure 16-2. revision (rev) register
pxd10 microcontroller reference manual, rev. 1 16-4 freescale semiconductor preliminary?subject to change without notice 16.4.2.3 miscellaneous reset status register (mrsr) the mrsr contains a bit for each of the reset sources to the device. an asserted bit indica tes the last type of reset that occurred. only one bit is set at any time in the mrsr , reflecting the cause of the most recent reset as signalled by device rese t input signals. the mrsr can only be read from the ips programming model. any attempted write is ignored. see figure 16-3 and table 16-4 for the miscellaneous reset status register definition. 16.4.2.4 miscellaneous wakeup control register (mwcr) implementation of low-power modes and exit from th ese modes via an interrupt require communication between the ecsm, the interru pt controller and external logic typically associated with phase-locked loop clock generation circuitry. the miscellaneous wakeup control regi ster (mwcr) provides an 8-bit register controlling entry into thes e types of low-power modes as well as definition of the interrupt level needed to exit the mode. the following sequence of oper ations is generally needed to enable this functionality. note that the exact details are likely to be system-specific. 1. the processor core loads the a ppropriate data value into the mwcr, setting the enbwcr bit and the desired interrupt priority level. table 16-3. revision (rev) field descriptions name description 0-15 rev[0:15] revision the rev[0:15] field is specified by an input signal to define a software-visible revision number. register address: ecsm base + 0x0f 01234567 rpordir000000 w reset:* *000000 = unimplemented figure 16-3. miscellaneous reset status (mrsr) register table 16-4. miscellaneous reset status (mrsr) field descriptions name description 0 por power-on reset 1 = last recorded event was caused by a power-on reset (based on a device input signal) 1 di r device input reset 1 = last recorded event was a reset caused by a device input reset.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 16-5 preliminary?subject to change without notice 2. at the appropriate time, the pr ocessor ceases execution. the exac t mechanism varies by processor core. in some cases, a processor- is-stopped status is signaled to th e ecsm and external logic. this assertion, if properly enabled by mwcr[en bwcr], causes the ecsm output signal ?enter_low_power_mode? to be set. this, in tur n, causes the selected external, low-power mode, to be entered, and the appropriate clock signals disabled. in most implementations, there are multiple low-power modes, where the exact clocks to be disabled vary acro ss the different modes. 3. after entering the low-power mode , the interrupt controller enables a special combinational logic path which evaluates all unmasked interrupt requests. the device remains in this mode until an event which generates an unmasked interrupt request with a priority level greater than the value programmed in the mwcr[prilvl] occurs. 4. once the appropriately-high interrupt request leve l arrives, the interrupt controller signals its presence, and the ecsm responds by asse rting an ?exit_low_power_mode? signal. 5. the external logic senses the assertion of the ?e xit? signal, and re-enabl es the appropriate clock signals. 6. with the processor core clocks enabled, th e core handles the pending interrupt request. see figure 16-4 and table 16-5 for the miscellaneous wakeup control register definition. 16.4.2.5 miscellaneous interrupt register (mir) all interrupt requests associated with ecsm are collected in the mir re gister. this includes the processor core system bus fault interrupt. register address: ecsm base + 0x13 01234567 r enbwcr 0 0 0 prilvl[0:3] w reset:00000000 = unimplemented figure 16-4. miscellaneous wakeup control (mwcr) register table 16-5. wakeup control (mwcr) field descriptions name description 0 enbwcr enable wcr 0 = mwcr is disabled. 1 = mwcr is enabled. 4-7 prilvl[0:3] interrupt priority level the interrupt priority level is a core-specific definition. it specifies the interrupt priority level needed to exit the low-power mode. specifically, an unmasked interrupt request of a priority level greater than the prilvl value is required to exit the mode. certain interrupt controller implementations include logic associated with this priority level that restricts the data value contained in this field to a [0, maximum - 1] range. see the specific interrupt controller module for details.
pxd10 microcontroller reference manual, rev. 1 16-6 freescale semiconductor preliminary?subject to change without notice during the appropriate interrupt serv ice routine handling these requests, the interrupt source contained in the mir must be explicitly cleared. see figure 16-5 and table 16-6 . 16.4.2.6 miscellaneous user-defined control register (mudcr) the mudcr provides a program-v isible register for user-defined contro l functions. it typi cally is used as configuration control for miscellane ous device-level modules. the conten ts of this register is simply output from ecsm to other modules where the user -defined control functions are implemented. see figure 16-6 and table 16-7 for the miscellaneous user-defin ed control register definition. register address: ecsm base + 0x1f 01234567 r fb0ai fb0si fb1ai fb1si 0 0 0 0 w w1c w1c w1c w1c reset:00000000 = unimplemented figure 16-5. miscellaneous interrupt (mir) register table 16-6. miscellaneous interrupt (mir) field descriptions name description 0 fb0ai flash bank 0 abort interrupt 0: a flash bank 0 abort has not occurred. 1: a flash bank 0 abort has occurred. the interrupt reque st is negated by writing a 1 to this bit. writing a 0 has no effect. 1 fb0si flash bank 0 stall interrupt 0: a flash bank 0 stall has not occurred. 1: a flash bank 0 stall has occurred. the interrupt request is negated by writing a 1 to this bit. writing a 0 has no effect. 2 fb1ai flash bank 1 abort interrupt 0: a flash bank 1 abort has not occurred. 1: a flash bank 1 abort has occurred. the interrupt reque st is negated by writing a 1 to this bit. writing a 0 has no effect. 3 fb1si flash bank 1 stall interrupt 0: a flash bank 1 stall has not occurred. 1: a flash bank 1 stall has occurred. the interrupt request is negated by writing a 1 to this bit. writing a 0 has no effect.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 16-7 preliminary?subject to change without notice 16.4.2.6.1 axbs_lite force_ round_robin bit (mudcr[31]) when the axbs_lite is included on the platform, this bit is used to dr ive the force_round_robin bit of the axbs_lite. this will force the slaves into round robin mode of arbitrati on rather than fixed mode. unless a master is using priority elevation, wh ich forces the desi gn back into fixed mode re gardless of this bit. by defining the ?define enable_round_robin_ reset, this bit will reset to 1. 16.4.2.7 ecc registers for designs including error- correcting code (ecc) impl ementations to improve th e quality and reliability of memories, there are a number of program-visible registers for the so le purpose of reporting and logging of memory failures. these optional registers include: ? ecc configurati on register (ecr) ? ecc status register (esr) ? ecc error generation register (eegr) ? flash ecc address register (fear) ? flash ecc master number register (femr) ? flash ecc attributes register (feat) ? flash ecc data register (fedr) ? ram ecc address register (rear) ? ram ecc syndrome register (resr) register address: ecsm base + 0x24 0123456789101112131415 r mudcr[0:15] w reset:0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mudcr[16:31] w reset:0000000000000000 = unimplemented figure 16-6. miscellaneous user-d efined control (mudcr) register table 16-7. miscellaneous user-defined control register (mudcr) field descriptions name description mudcr user-defined control register 0 = the control associated with this mudcr bit is disabled. 1 = the control associated with this mudcr bit is enabled.
pxd10 microcontroller reference manual, rev. 1 16-8 freescale semiconductor preliminary?subject to change without notice ? ram ecc master number register (remr) ? ram ecc attributes register (reat) ? ram ecc data register (redr) the details on the ecc registers are provided in th e subsequent sections. if the design does not include ecc on the memories, these addresses are reserved locations within the ecsm?s programming model. 16.4.2.8 ecc configuration register (ecr) the ecc configuration register is an 8-bit control register for specifying which t ypes of memory errors are reported. in all systems with ecc, the occurrence of a non-correctable error causes the current access to be terminated with an error condition. in many cases , this error termination is reported directly by the initiating bus master. however, there are certain si tuations where the occurrence of this type of non-correctable error is not reported by the master. examples include speculative instruction fetches which are discarded due to a change-of-f low operation, and buffered operand wr ites. the ecc reporting logic in the ecsm provides an optional error interrupt mechanism to signal all non-correctable memory errors. in addition to the interrupt generation, the ecsm captures specific inform ation (memory address, attributes and data, bus master number, etc.) which may be useful for subsequent failure analysis. the reporting of single-bit memory corrections can only be enabled vi a a an soc-configurable module input signal. while not direc tly accessible to a user, this capability is viewed as important for error logging and failure analysis. see figure 16-7 and table 16-8 for the ecc configurat ion register definition. register address: ecsm base + 0x43 01234567 r0 0 er1br ef1br 00 erncr efncr w reset:00000000 = unimplemented figure 16-7. ecc configuration (ecr) register table 16-8. ecc configuration (ecr) field descriptions name description 2 er1br enable ram 1-bit reporting 0 = reporting of single-bit ram corrections is disabled. 1 = reporting of single-bit ram corrections is enabled. this bit can only be set if the soc-configurable in put enable signal is asserted. the occurrence of a single-bit ram correction generates a ecsm ecc interrupt request as signalled by the assertion of esr[r1bc]. the address, attributes and data are al so captured in the rear, resr, remr, reat and redr registers.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 16-9 preliminary?subject to change without notice 16.4.2.9 ecc status register (esr) the ecc status register is an 8-bit control regist er for signaling which types of properly-enabled ecc events have been detected. the es r signals the last, prope rly-enabled memory event to be detected. ecc interrupt generation is separated in to single-bit error detection/correc tion, uncorrectable error detection and the combination of the two as defined by the following boolean equations. in these equations, ?&? refers to a bitwise and operator an d ?|? refers to a bitw ise or operator; bitwis e and has precedence of bitwise or. bitwise and has precedence of bitwise or. ecsm_ecc1bit_irq = ecr[er1br] & esr[ r1bc]// ram, 1-bit correction | ecr[ef1br] & esr[f1bc]// flash, 1-bit correction ecsm_eccrncr_irq = ecr[erncr] & esr[rn ce]// ram, noncorrectable error ecsm_eccfncr_irq = ecr[efncr] & esr[fn ce]// flash, noncorrectable error 3 ef1br enable flash 1-bit reporting 0 = reporting of single-bit flash corrections is disabled. 1 = reporting of single-bit flash corrections is enabled. this bit can only be set if the soc-configurable in put enable signal is asserted. the occurrence of a single-bit flash correction generates a ecsm ecc inte rrupt request as signalled by the assertion of esr[f1bc]. the address, attributes and data are al so captured in the fear, femr, feat and fedr registers. 6 erncr enable ram non-correctable reporting 0 = reporting of non-correctable ram errors is disabled. 1 = reporting of non-correctable ram errors is enabled. the occurrence of a non-correctable multi-bit ram error generates a ecsm ecc interrupt request as signalled by the assertion of esr[rnce]. the faulting address, attributes and data are also captured in the rear, resr, remr, reat and redr registers. 7 efncr enable flash non-correctable reporting 0 = reporting of non-correctable flash errors is disabled. 1 = reporting of non-correctable flash errors is enabled. the occurrence of a non-correctable multi-bit flash error generates a ecsm ecc interrupt request as signalled by the assertion of esr[fnce]. the faulting ad dress, attributes and data are also captured in the fear, femr, feat and fedr registers. table 16-8. ecc configuration (ecr) field descriptions (continued) name description
pxd10 microcontroller reference manual, rev. 1 16-10 freescale semiconductor preliminary?subject to change without notice ecsm_ecc2bit_irq = ecsm_eccrncr_irq/ / ram, noncorrectable error | ecsm_eccfncr_irq// flash, noncorrectable error ecsm_ecc_irq = ecsm_ecc1bit_irq // 1-bit correction | ecsm_ecc2bit_irq// noncorrectable error where the combination of a properly-enabled categor y in the ecr and the dete ction of the corresponding condition in the esr produces the interrupt request. the ecsm allows a maximum of one b it of the esr to be asserted at any given time. this preserves the association between the esr and the corresponding addr ess and attribute registers, which are loaded on each occurrence of an properly-enabled ecc event. if there is a pending ecc interrupt and another properly-enabled ecc event occurs, the ecsm ha rdware automatically handles the esr reporting, clearing the previous data and loading the new state and thus gua ranteeing that only a single flag is asserted. to maintain the coherent software view of the reported event, the fo llowing sequence in the ecsm error interrupt service routine is suggested: 1. read the esr and save it. 2. read and save all the address and attribute reporting registers. 3. re-read the esr and verify the current contents matches the original contents. if the two values are different, go back to step 1 and repeat. 4. when the values are identical, write a 1 to the a sserted esr flag to negate the interrupt request. see figure 16-8 and table 16-9 for the ecc status register definition. register address: ecsm base + 0x47 01234567 r 0 0 r1bc f1bc 0 0 rnce fnce w w1c w1c w1c w1c reset:00000000 = unimplemented figure 16-8. ecc status (esr) register
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 16-11 preliminary?subject to change without notice in the event that multiple status flags are signale d simultaneously, ecsm records the event with the r1bc as highest priority, then f1bc, then rnce, and finally fnce. 16.4.2.10 ecc error gene ration register (eegr) the ecc error generation register is a 16-bit control register used to force the generati on of single- and double-bit data inversions in the memo ries with ecc, most notably the ram. this capability is provided for two purposes: ? it provides a software-controlled mechanism for ?injecting? errors into the memories during data writes to verify the integrity of the ecc logic. ? it provides a mechanism to allow testing of the so ftware service routines associated with memory error logging. it should be noted that while the eeg r is associated with th e ram, similar capabiliti es exist for the flash, i.e., the ability to program the non- volatile memory with single- or double-bit errors is supported for the same two reasons previously identified. table 16-9. ecc status (esr) field descriptions name description 2 r1bc ram 1-bit correction 0 = no reportable single-bit ram correction has been detected. 1 = a reportable single-bit ram correction has been detected. this bit can only be set if ecr[epr1br] is asserted. the occurrence of a properly-enabled single-bit ram correction generates a ecsm ecc interrupt requ est. the address, attributes and data are also captured in the rear, resr, remr, reat and redr regi sters. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. 3 f1bc flash 1-bit correction 0 = no reportable single-bit flash correction has been detected. 1 = a reportable single-bit flash correction has been detected. this bit can only be set if ecr[epf1br] is assert ed. the occurrence of a properly-enabled single-bit flash correction generates a ecsm ecc interrupt re quest. the address, attributes and data are also captured in the fear, femr, feat and fedr registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. 6 rnce ram non-correctable error 0 = no reportable non-correctable ram error has been detected. 1 = a reportable non-correctable ram error has been detected. the occurrence of a properly-enabled non-correct able ram error generates a ecsm ecc interrupt request. the faulting address, attributes and data ar e also captured in the rear, resr, remr, reat and redr registers. to clear this interrupt flag, wr ite a 1 to this bit. writing a 0 has no effect. 7 fnce flash non-correctable error 0 = no reportable non-correctable flash error has been detected. 1 = a reportable non-correctable flash error has been detected. the occurrence of a properly-enabled non-correctab le flash error generates a ecsm ecc interrupt request. the faulting address, attributes and data are also captured in the fear, femr, feat and fedr registers. to clear this interrupt flag, wr ite a 1 to this bit. writing a 0 has no effect.
pxd10 microcontroller reference manual, rev. 1 16-12 freescale semiconductor preliminary?subject to change without notice for both types of memories (ram and flash), the intent is to generate er rors during data write cycles, such that subsequent reads of the corrupt ed address locations generate ecc ev ents, either singl e-bit corrections or double-bit noncorrectable errors that are terminated with an error response. the enabling of these error generation modes requires the same soc-configurable input enable signal (as that used to enable single-bit correction reporting) be asserted. see figure 16-9 and table 16-10 for the ecc configura tion register definition. register address: ecsm base + 0x4a 0123456789101112131415 r 00frc1 bi fr11 bi 00frcn ci fr1 nci 0errbit[0:6] w reset: 0000000000000000 = unimplemented figure 16-9. ecc error generation (eegr) register table 16-10. ecc error generation (eegr) field descriptions name description 2 frc1bi force ram continuous 1-bit data inversions 0 = no ram continuous 1-bit data inversions are generated. 1 = 1-bit data inversions in t he ram are continuously generated. the assertion of this bit forces the ram controller to create 1-bit data inversions, as defined by the bit position specified in errbit[0:6], co ntinuously on every write operation. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit is inverted to in troduce a 1-bit ecc event in the ram. after this bit has been enabled to generate another co ntinuous 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. this bit can only be set if the same soc configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. note: the only allowable values for the 4 control bit enables {fr11bi, frc1bi, frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0 ,0,1,0} and {0,0,0,1}. all other values result in undefined behavior.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 16-13 preliminary?subject to change without notice 3 fr11bi force ram one 1-bit data inversion 0 = no ram single 1-bit data inversion is generated. 1 = one 1-bit data inversion in the ram is generated. the assertion of this bit forces the ram controller to create one 1-bit data inversion, as defined by the bit position specified in errb it[0:6], on the first write oper ation after this bit is set. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit is inverted to in troduce a 1-bit ecc event in the ram. after this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. this bit can only be set if the same soc configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. note: the only allowable values for the 4 control bit enables {fr11bi, frc1bi, frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0 ,0,1,0} and {0,0,0,1}. all other values result in undefined behavior. 6 frcnci force ram continuous noncorrectable data inversions 0 = no ram continuous 2-bit data inversions are generated. 1 = 2-bit data inversions in t he ram are continuously generated. the assertion of this bit forces the ram controller to create 2-bit data inversions, as defined by the bit position specified in errbit[0:6] and the overall odd parity bit, continuously on every write operation. after this bit has been enabled to generate another c ontinuous noncorrectable data inversion, it must be cleared before being set again to properly re-enable the error generation logic. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are inverted to introduce a 2-bit ecc error in the ram. note: the only allowable values for the 4 control bit enables {fr11bi, frc1bi, frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0 ,0,1,0} and {0,0,0,1}. all other values result in undefined behavior. 7 fr1nci force ram one noncorrectable data inversions 0 = no ram single 2-bit data inversions are generated. 1 = one 2-bit data inversion in the ram is generated. the assertion of this bit forces the ram controller to create one 2-bit data inversion, as defined by the bit position specified in errbit[0:6] and the overall odd parity bit, on the first write operation after this bit is set. the normal ecc generation takes place in the ram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are inverted to introduce a 2-bit ecc error in the ram. after this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly re-enable the error generation logic. note: the only allowable values for the 4 control bit enables {fr11bi, frc1bi, frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0 ,0,1,0} and {0,0,0,1}. all other values result in undefined behavior. table 16-10. ecc error generation (eeg r) field descriptions (continued) name description
pxd10 microcontroller reference manual, rev. 1 16-14 freescale semiconductor preliminary?subject to change without notice if an attempt to force a non-correctable invers ion (by asserting eegr[f rcnci] or eegr[frc1nci]) and eegr[errbit] equals 64, then no data inversion will be generated. 16.4.2.11 flash ecc address register (fear) the fear is a 32-bit register for cap turing the address of the last, prope rly-enabled ecc event in the flash memory. depending on the state of th e ecc configuration regi ster, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the fear, femr, feat and fedr registers, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 16-10 and table 16-11 for the flash ecc address register definition. 9-15 errbit [0:6] error bit position the vector defines the bit position which is complemented to create the data inversion on the write operation. for the creation of 2-bit data inversions, the bi t specified by this field plus the odd parity bit of the ecc code are inverted. the ram controller follows a vector bit ordering sc heme where lsb=0. errors in the ecc syndrome bits can be generated by setting this field to a value greater than the ram width. for example, consider a 32-bit ram implementation. the 32-bit ecc approach requires 7 code bits for a 32 -bit word. for pram data width of 32 bits, the actual sram (32b data + 7b for ecc) = 39 bits. the following association between the errbit field and the corrupted memory bit is defined: if errbit = 0, then ram[0] of the odd bank is inverted if errbit = 1, then ram[1] of the odd bank is inverted ... if errbit = 31, then ram[31] of the odd bank is inverted if errbit = 64, then ecc parity[0] of the odd bank is inverted if errbit = 65, then ecc parity[1] of the odd bank is inverted ... if errbit = 70, then ecc parity[6] of the odd bank is inverted for errbit values of 32 to 63 and greater than 70, no bit position is inverted. table 16-10. ecc error generation (eeg r) field descriptions (continued) name description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 16-15 preliminary?subject to change without notice 16.4.2.12 flash ecc master number register (femr) the femr is a 4-bit register for capturing the axbs bus master number of the last, properly-enabled ecc event in the flash memory. depending on the state of the ecc configuration register, an ecc event in the flash causes the address, attri butes and data associated with the access to be loaded into the fear, femr, feat and fedr registers, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 16-11 and table 16-12 for the flash ecc master number register definition. register address: ecsm base + 0x50 0123456789101112131415 r fear[0:15] w reset:xxxxxxxxxxxxxxxx 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fear[16:31] w reset:xxxxxxxxxxxxxxxx = unimplemented figure 16-10. flash ecc address (fear) register table 16-11. flash ecc address (fear) field descriptions name description 0-31 fear[0:31] flash ecc address register this 32-bit register contains the faulting acce ss address of the last, properly-enabled flash ecc event. register address: ecsm base + 0x56 01234567 r 0 0 0 0 femr[0:3] w reset: 0 0 0 0 - - - - = unimplemented figure 16-11. flash ecc master number (femr) register
pxd10 microcontroller reference manual, rev. 1 16-16 freescale semiconductor preliminary?subject to change without notice 16.4.2.13 flash ecc attributes (feat) register the feat is an 8-bit register for capturing the axbs bus master attributes of the last, properly-enabled ecc event in the flash memory. depe nding on the state of the ecc conf iguration register, an ecc event in the flash causes the address, attri butes and data associated with the access to be loaded into the fear, femr, feat and fedr registers, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 16-12 and table 16-13 for the flash ecc attri butes register definition. 16.4.2.14 flash ecc data register (fedr) the fedr is a 32-bit regist er for capturing the data associated wi th the last, properly-enabled ecc event in the flash memory. depending on th e state of the ecc configuration re gister, an ecc event in the flash causes the address, attributes and data associated with the access to be loaded into the fear, femr, table 16-12. flash ecc master number (femr) field descriptions name description 4-7 femr[0:3] flash ecc master number register this 4-bit register contains the axbs bus master number of the faulti ng access of the last, properly-enabled flash ecc event. register address: ecsm base + 0x57 01234567 r write size[0:2] protection[0:3] w reset:xxxxxxxx = unimplemented figure 16-12. flash ecc attributes (feat) register table 16-13. flash ecc attributes (feat) field descriptions name description 0 write amba-ahb hwrite 0 = amba-ahb read access 1 = amba-ahb write access 1-3 size[0:2] amba-ahb hsize[0:2] 0b000 = 8-bit amba-ahb access 0b001 = 16-bit amba-ahb access 0b010 = 32-bit amba-ahb access 0b1xx = reserved 4-7 protection[0:3] amba-ahb hprot[0:3] protection[3]: cacheable 0 = non-cacheable,1 = cacheable protection[2]: bufferable0 = non-bufferable,1 = bufferable protection[1]: mode 0 = user mode, 1 = supervisor mode protection[0]: type 0 = i-fetch, 1 = data
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 16-17 preliminary?subject to change without notice feat and fedr registers, and the appropriate flag (f1bc or fnce) in the ecc status register to be asserted. the data captured on a multi-bit non- correctable ecc error is undefined. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 16-13 and table 16-14 for the flash ecc data register definition. 16.4.2.15 ram ecc address register (rear) the rear is a 32-bit register for capturing the addr ess of the last, properly-enabled ecc event in the ram memory. depending on the stat e of the ecc configuration regi ster, an ecc event in the ram causes the address, attributes and data associated with the access to be loaded into the rear, resr, remr, reat and redr registers, a nd the appropriate flag (r1bc or rn ce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 16-14 and table 16-15 for the ram ecc address register definition. register address: ecsm base +0x5c 0123456789101112131415 r fedr[0:15] w reset:xxxxxxxxxxxxxxxx 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fedr[16:31] w reset:xxxxxxxxxxxxxxxx = unimplemented figure 16-13. flash ecc data (fedr) register table 16-14. flash ecc data (fedr) field descriptions name description 0-31 fedr[0:31] flash ecc data register this 32-bit register contains the data associated with the faulting access of the last, properly-enabled flash ecc event. the register contains the data value taken directly from the data bus.
pxd10 microcontroller reference manual, rev. 1 16-18 freescale semiconductor preliminary?subject to change without notice 16.4.2.16 ram ecc syndrome register (resr) the resr is an 8-bit register for capturing the error syndrome of the last, properly-enabled ecc event in the ram memory. depending on the stat e of the ecc configuration regi ster, an ecc event in the ram causes the address, attributes and data associated with the access to be loaded into the rear, resr, remr, reat and redr registers, a nd the appropriate flag (r1bc or rn ce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 16-15 and table 16-16 for the ram ecc syndrome register definition. register address: ecsm base + 0x60 0123456789101112131415 r rear[0:15] w reset:xxxxxxxxxxxxxxxx 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rear[16:31] w reset:xxxxxxxxxxxxxxxx = unimplemented figure 16-14. ram ecc ad dress (rear) register table 16-15. ram ecc address (rear) field descriptions name description 0-31 rear[0:31] ram ecc address register this 32-bit register contains the faulting acce ss address of the last, properly-enabled ram ecc event. register address: ecsm base + 0x65 01234567 r resr[0:7] w reset:xxxxxxxx = unimplemented figure 16-15. ram ecc syndrome (resr) register
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 16-19 preliminary?subject to change without notice note: ta b l e 1 6 - 1 6 associates the upper 7 bits of the ecc syndrome with the exact data bit in error for single-bit correctable codewords. this table follows the bit vectoring notation wher e the lsb=0. note that the syn drome value of 0x01 implies no error condition but this value is not readable when the presr is read for the no error case. table 16-16. ram ecc syndrome (resr) field descriptions name description 0-7 resr[0:7] ram ecc syndrome register this 8-bit syndrome field includes 6 bits of hamming decoded parity plus an odd-parity bit for the entire 39-bit (32-bit data + 7 ecc) code word. the upper 7 bits of the syndrome specify the exact bit position in error for single-bit correctable codewords, and the combination of a non-zero 7-bit syndrome plus overall incorrect parity bit signal a multi-bit, non-correctable error. for correctable single-bit errors, the mapping shown in table 16-16 associates the upper 7 bits of the syndrome with the data bit in error. table 16-17. ram syndrome mapping for single-bit correctable errors resr[0:7] data bit in error 0x00 ecc odd[0] 0x01 no error 0x02 ecc odd[1] 0x04 ecc odd[2] 0x06 data odd bank[31] 0x08 ecc odd[3] 0x0a data odd bank[30] 0x0c data odd bank[29] 0x0e data odd bank[28] 0x10 ecc odd[4] 0x12 data odd bank[27] 0x14 data odd bank[26] 0x16 data odd bank[25] 0x18 data odd bank[24] 0x1a data odd bank[23] 0x1c data odd bank[22] 0x50 data odd bank[21] 0x20 ecc odd[5] 0x22 data odd bank[20] 0x24 data odd bank[19] 0x26 data odd bank[18] 0x28 data odd bank[17] 0x2a data odd bank[16 0x2c data odd bank[15] 0x58 data odd bank[14] 0x30 data odd bank[13] 0x32 data odd bank[12] 0x34 data odd bank[11] 0x64 data odd bank[10]
pxd10 microcontroller reference manual, rev. 1 16-20 freescale semiconductor preliminary?subject to change without notice 16.4.2.17 ram ecc master number register (remr) the remr is a 4-bit register for capturing the axbs bus master number of the last, properly-enabled ecc event in the ram memory. depending on the state of the ecc configuration register, an ecc event in the ram causes the address, attributes and data associ ated with the access to be loaded into the rear, resr, remr, reat and redr regist ers, and the appropriate flag (r 1bc or rnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 16-16 and table 16-18 for the ram ecc master number register definition. 0x38 data odd bank[9] 0x62 data odd bank[8] 0x70 data odd bank[7] 0x60 data odd bank[6] 0x40 ecc odd[6] 0x42 data odd bank[5] 0x44 data odd bank[4] 0x46 data odd bank[3] 0x48 data odd bank[2] 0x4a data odd bank[1] 0x4c data odd bank[0] 0x03,0x05........0x4d m ultiple bit error > 0x4d multiple bit error register address: ecsm base + 0x66 01234567 r 0 0 0 0 remr[0:3] w reset: 0 0 0 0 x x x x = unimplemented figure 16-16. ram ecc master number (remr) register table 16-18. ram ecc master number (remr) field descriptions name description 4-7 remr[0:3] ram ecc master number register this 4-bit register contains the axbs bus master number of the faulting access of the last, properly-enabled ram ecc event. table 16-17. ram syndrome mapping for single-bit correctable errors (continued) resr[0:7] data bit in error
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 16-21 preliminary?subject to change without notice 16.4.2.18 ram ecc attributes (reat) register the reat is an 8-bit register for capturing the axbs bus master attributes of the last, properly-enabled ecc event in the ram memory. depe nding on the state of the ecc conf iguration register, an ecc event in the ram causes the address, attributes and data as sociated with the access to be loaded into the rear, resr, remr, reat and redr regist ers, and the appropriate flag (r 1bc or rnce) in the ecc status register to be asserted. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 16-17 and table 16-19 for the ram ecc attributes register definition. 16.4.2.19 ram ecc data register (redr) the redr is a 32-bit register for capturing the data associated with the last, properly-enabled ecc event in the ram memory. depending on the state of the e cc configuration register , an ecc event in the ram causes the address, attributes an d data associated with the access to be loaded into the rear, resr, remr, reat and redr registers, a nd the appropriate flag (r1bc or rn ce) in the ecc status register to be asserted. the data captured on a multi-bit non- correctable ecc error is undefined. this register can only be read from the ips programming model; a ny attempted write is ignored. see figure 16-18 and table 16-20 for the ram ecc data register definition. register address: ecsm base + 0x67 01234567 r write size[0:2] protection[0:3] w reset:xxxxxxxx = unimplemented figure 16-17. ram ecc attributes (reat) register table 16-19. ram ecc attributes (reat) field descriptions name description 0 write amba-ahb hwrite 0 = amba-ahb read access 1 = amba-ahb write access 1-3 size[0:2] amba-ahb hsize[0:2] 0b000 = 8-bit amba-ahb access 0b001 = 16-bit amba-ahb access 0b010 = 32-bit amba-ahb access 0b1xx = reserved 4-7 protection[0:3] amba-ahb hprot[0:3] protection[3]: cacheable 0 = non-cacheable, 1 = cacheable protection[2]: bufferable 0 = non-bufferable,1 = bufferable protection[1]: mode 0 = user mode, 1 = supervisor mode protection[0]: type 0 = i-fetch, 1 = data
pxd10 microcontroller reference manual, rev. 1 16-22 freescale semiconductor preliminary?subject to change without notice 16.4.3 high priority enables e200 processors can be configured to support criti cal and/or external interrupts. furthermore, each processor can be configured to em ploy priority elevation on critical and/or external interrupt events. critical interrupts come from outside the platform, and are routed dire ctly to the processor?s critical interrupt input. external interrupts are routed through th e interrupt controller. in addition to the interrupt notification signals, va rious processor-specific c onfiguration flags from the processor?s machine check register (mcr[ee,ce]) and the hard ware implementation re gister (hid1) are sent to the ecsm to determine when interrupt servicing is enabled and when high-priority elevation should be enabled. if the corresponding processor is configured to allow high-priority elevation on critical interrupt events, the ecsm generates the high-priority signal upon critical interrupt detection and holds it active throughout the duration of interrupt servicing. if the correspondi ng processor is configured to allow hi gh-priority elevation on external interrupt even ts, the ecsm generates the high-priority signal upon external interrupt detection and holds it active throughout the duration of interrupt servicing. during interrupt servicing the processor status output, p_stat, is monitored fo r indication of a return from interrupt (rfi). great care needs to be taken when using the priority el evation as it can enable a master to starve the rest of the masters in the system. please see chapter 10, crossbar switch (xbar),? for information on priority elevation. register address: ecsm base +0x6c 0123456789101112131415 r redr[0:15] w reset:xxxxxxxxxxxxxxxx 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r redr[16:31] w reset:xxxxxxxxxxxxxxxx = unimplemented figure 16-18. ram ecc data (redr) register table 16-20. ram ecc data (redr) field descriptions name description 0-31 redr[0:31] ram ecc data register this 32-bit register contains the data asso ciated with the faulting access of the last, properly-enabled ram ecc event. the register co ntains the data value taken directly from the data bus.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 16-23 preliminary?subject to change without notice 16.4.4 spp_ips_reg_protection the spp_ips_reg_protection logic prov ides hardware enforcement of s upervisor mode access protection for five on-platform ips modules: intc, ecsm, mpu, stm, and swt. this logic resides between the on-platform bus sourced by the aips bus controller and the individual sl ave modules. it monitors the bus access type (supervisor or user) and if a user access is attempted, the tran sfer is terminated with an error and inhibited from reaching the slave module. identical logic is replicated for each of the five, targeted slave modules. a block diagram of the s pp_ips_reg_protection m odule is shown in figure 16-19 . figure 16-19. spp_ips_reg_protection block diagram aips_lite intc ips_supervisor_access ips_module_en[4:0] spp_ips_reg_protection qual_ips_mod_en[0] ips_xfr_wait[0] ips_xfr_err[0] ecsm qual_ips_mod_en[1] ips_xfr_wait[1] ips_xfr_err[1] stm qual_ips_mod_en[3] ips_xfr_wait[3] ips_xfr_err[3] mpu qual_ips_mod_en[2] ips_xfr_wait[2] ips_xfr_err[2] swt qual_ips_mod_en[4] ips_xfr_wait[4] ips_xfr_err[4] final_ips_xfr_wait[4:0] final_ips_xfr_err[4:0]
pxd10 microcontroller reference manual, rev. 1 16-24 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-1 preliminary?subject to change without notice chapter 17 flash memory 17.1 introduction the flash memory comprises a platform flash controller (pflash) interf ace and three flash memory arrays: two arrays of up to 512 kb for code (cflash) and one array of 64 kb fo r data (dflash). the flash memory architecture of this device is illustrated in figure 17-1 . see table 2-1 in chapter 2, memory map, for exact memory sizes of each family member. figure 17-1. pxd10 flash memory architecture 17.2 program flash memory (cod e flash 0 and code flash 1) 17.2.1 introduction the primary function of the program flash module is to serve as electr ically programmable and erasable non-volatile memory. non-volatile memory may be used for instruction and/or data storage. xbar 512k 4x128 p-buffer pflash controller 64k code flash data flash 512k code flash (2x16k 3x32k 3x128k) (4x128k) array 0 (4x16k) array 1 array 0 (for eee) via port splitter 4x128 p-buffer 1x128 p-buffer 4x128 p-buffer 4x128 p-buffer 1x128 p-buffer 128 128 128 (bank 0) (bank 1) (bank 2)
pxd10 microcontroller reference manual, rev. 1 17-2 freescale semiconductor preliminary?subject to change without notice the module is a non-volatile solid-stat e silicon memory device consisting of blocks (called also sectors) of single transistor storage elements, an electric al means for selectively adding (programming) and removing (erasing) charge from these elements, and a means of selectively sensing (reading) the charge stored in these elements. the flash module is arranged as two functional units: the flash core a nd the memory interface. the flash core is composed of arrayed non-volatile storage elements , sense amplifiers, row decoders, column decoders and charge pumps. the arrayed storage elements in th e flash core are subdivided into physically separate units referred to as blocks (or sectors). the memory interface contains the registers and logi c which control the operati on of the flash core. the memory interface is also the interface between the flash module and a bus interface unit (biu) and contains the ecc logic and redundancy logic. a biu connects the flash module to a system bus, and contains all sy stem level customization required for the soc application. 17.2.2 main features ? high read parallelism (128 bits) ? error correction code (sec-ded ) to enhance data retention ? double word program (64 bits) ? sector erase ? double bank (code flash 0 and code flash 1): allows one bank to be read while the other bank is being modified ? erase suspend available (pr ogram suspend not available) ? software programmable program/erase pr otection to avoid unwanted writings ? censored mode against piracy ? usable as main code memory of the soc ? shadow sector available ? "otp" area in test flash block 17.2.3 block diagram each bank contains one flas h macrocell comprising one matrix module, normally used for code storage. no read-while-modify operations ar e possible within the same bank. the modify operations are managed by an embedded flash program/erase cont roller (fpec). commands to the fpec are given through a user registers interface. the read data bus is 128 bits wide, while the flash registers are on a se parate bus 32 bits wide addressed in user memory map. the high voltages needed for program/era se operations are in ternally generated.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-3 preliminary?subject to change without notice figure 17-2. bank 0 flash macrocell structure 17.2.4 functional description 17.2.4.1 macrocell structure the flash module is addressable by word (32 bits) or doubl e word (64 bits) for program, and page (128 bits) for read. reads done to the fl ash always return 128 bits, although read page buffering may be done in the platform biu. each read of the flash module retrieves a page, or 4 consecutive words (128 bits) of information. the address for each word retrieved within a page differ from the other a ddresses in the page only by address bits (3:2). the flash module supports fault tole rance through error correction code (ecc) and/or error detection. the ecc implemented within the fl ash module will correct single bi t failures and detect double bit failures. the flash module uses an embedde d hardware algorithm implemented in the memory interface to program and erase the flash core. control logic that works with the software block enab les, and software lock mechanisms, is included in the embedded hardware algorithm to gua rd against accident al program/erase. the hardware algorithm perform the steps necessary to ensure that th e storage elements are programmed and erased with sufficient margin to guarantee data integr ity and reliability. a programmed bit in the flash module reads as logic level 0 (or low). an erased bit in the flash module reads as logic level 1 (or high). 512 kb + 16kb test flash hv generator flash controller flash matrix registers program/erase registers interface flash bank 0 interface + 16kb shadow
pxd10 microcontroller reference manual, rev. 1 17-4 freescale semiconductor preliminary?subject to change without notice program and erase of the flas h module requires multi ple system clock cycles to complete. the erase sequence may be suspended. the program and erase sequences may be aborted. 17.2.4.2 flash modul e sectorization bank 0 (code flash 0) of the flas h module supports up to 512 kb of us er memory, plus 16 kb of test memory (a portion of which is one- time programmable by the user). an extra 16 kb sector is available as shadow space usable for us er option bits or censorship. bank 1 (data flash 0) of the flash module supports 64 kb of user memory, plus 16 kb of test memory (a portion of which is one-ti me programmable by the user). bank 2 (code flash 1) of the flas h module supports up to 512 kb of us er memory, plus 16 kb of test memory (a portion of which is on e-time programmable by the user). the sectorization of the flash module is shown in table 17-1 . table 17-1. flash module sectorization ap size [kb] 5602s 5604s 5606s sector region start address end address on chip flash memories (code flash) 0x00000000 0x00007fff 32 yes yes yes 1 b0f0 code flash array 0 0x00008000 0x0000bfff 16 yes yes yes 1 b0f1 code flash array 0 0x0000c000 0x0000ffff 16 yes yes yes 1 b0f2 code flash array 0 0x00010000 0x00017fff 32 yes yes yes 1 b0f3 code flash array 0 0x00018000 0x0001ffff 32 yes yes yes 1 b0f4 code flash array 0 0x00020000 0x0003ffff 128 yes yes yes 1 b0f5 code flash array 0 0x00040000 0x0005ffff 128 no yes yes 1 b0f6 code flash array 0 0x00060000 0x0007ffff 128 no yes yes 1 b0f7 code flash array 0 0x00080000 0x0009ffff 128 no no yes 1 b2f0 code flash array 1 0x000a0000 0x000bffff 128 no no yes 1 b2f1 code flash array 1 0x000c0000 0x000dffff 128 no no yes 1 b2f2 code flash array 1 0x000e0000 0x000fffff 128 no no yes 1 b2f3 code flash array 1 0x00100000 0x001fffff 1024 ? ? ? ? reserved on chip flash memories (shadow for code flash) 0x00200000 0x00203fff 16 yes yes yes ? code flash array 0 shadow sector 0x00204000 0x003fffff 2032 ? ? ? ? reserved on chip flash memories (test for code flash)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-5 preliminary?subject to change without notice the flash module is divided into blocks also to implement independent er ase/program protection. a software mechanism is provided to independently lock/unlock each block (as reported in table 17-1 ) against program and erase. 17.2.4.2.1 test flash block the test flash block exists outside the normal addr ess space and is programme d and read independently of the other blocks. the independent test flash block is included also to support systems which require non-volatile memory for security and/or to store system initialization information. a section of the test flash is reserved to store the non-volatile information related to redundancy, configuration and protection. the ecc is applied also to test flash. the usage of reserved test flash sect or is detailed in the following table. 0x00400000 0x00403fff 16 yes yes yes ? co de flash array 0 test sector 0x00404000 0x0047ffff 496 ? ? ? ? reserved 0x00480000 0x00483fff 16 no no yes ? code flash array 1 test sector 0x00484000 0x007fffff 3568 ? ? ? ? reserved on chip flash memories (data flash) 0x00800000 0x00803fff 16 yes yes ye s b1f0 data flash array 0 0x00804000 0x00807fff 16 yes yes ye s b1f1 data flash array 0 0x00808000 0x0080bfff 16 yes yes yes b1f2 data flash array 0 0x0080c000 0x0080ffff 16 yes yes yes b1f3 data flash array 0 0x00810000 0x00bfffff 4032 ? ? ? ? reserved on chip flash memories (test for data flash) 0x00c00000 0x00c03fff 16 yes yes yes ? d ata flash array 0 test sector 0x00c04000 0x00ffffff 2032 ? ? ? ? reserved 1 flash sector can be accessed via both slave ports. arbitrat ion logic required in case tw o different masters do access the same address at the same time. table 17-2. test flash structure for code flash 0 (block 0) name description addresses size user otp area 0x400000 to 0x401fff 8192 byte reserved 0x402000 to 0x403cff 7424 byte user reserved 0x403d00 to 0x403de7 232 byte table 17-1. flash module sectorization (continued) ap size [kb] 5602s 5604s 5606s sector region start address end address
pxd10 microcontroller reference manual, rev. 1 17-6 freescale semiconductor preliminary?subject to change without notice erase of test flash block is always locked. program of the test flash bl ock has similar restri ction as the array in terms of how ecc is calculated. only one program is allowed per 64-bit ecc segment. the first 8 kb of test flash block ma y be used for user defined functions (possibly to stor e serial numbers, other configuration words or factory process codes). locations of the test flash othe r than the first 8 kb of otp area cannot be program med by the user application. nvlml non-volatile low/mid address space block locking register 0x403de8 to 0x403def 8 byte nvhbl non-volatile high address space block locking register 0x403df0 to 0x403df7 8 byte nvsll non-volatile secondary low/mid add space block lock register 0x403df8 to 0x403dff 8 byte user reserved 0x403e00 to 0x403eff 256 byte reserved 0x403f00 to 0x403fff 256 byte table 17-3. test flash structure for data flash 0 (block 1) name description addresses size user otp area 0xc00000 to 0xc01fff 8192 byte reserved 0xc02000 to 0xc03cff 7424 byte user reserved 0xc03d00 to 0xc03de7 232 byte nvlml non-volatile low/mid address space block locking register 0xc03de8 to 0xc03def 8 byte nvhbl non-volatile high address space block locking register 0xc03df0 to 0xc03df7 8 byte nvsll non-volatile secondary low/mid add space block lock register 0xc03df8 to 0xc03dff 8 byte user reserved 0xc03e00 to 0xc03eff 256 byte reserved 0xc03f00 to 0xc03fff 256 byte table 17-4. test flash structure for code flash 1 (block 2) name description addresses size user otp area 0x480000 to 0x481fff 8192 byte reserved 0x482000 to 0x483cff 7424 byte user reserved 0x483d00 to 0x483de7 232 byte nvlml non-volatile low/mid address space block locking register 0x483de8 to 0x483def 8 byte nvhbl non-volatile high address space block locking register 0x483df0 to 0x483df7 8 byte nvsll non-volatile secondary low/mid add space block lock register 0x483df8 to 0x483dff 8 byte user reserved 0x483e00 to 0x483eff 256 byte reserved 0x483f00 to 0x483fff 256 byte table 17-2. test flash structure for code flash 0 (block 0) (continued) name description addresses size
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-7 preliminary?subject to change without notice 17.2.4.2.2 shadow block a shadow block is present in code flash 0 (block 0). the shadow block can be enabled by the biu. when the shadow space is enabled, all the operations are mapped to the shadow block. user mode program and erase of the shadow block are enabled only wh en mcr.peas is high. the shadow block may be locked/unlocked agains t program or erase by using the lml.tslk and sll.stslk registers. program of the shadow bloc k has similar restriction as the array in terms of how ecc is calculated. only one program is allowed per 64-b it ecc segment between erases. erase of the shadow block is done similarly as an sectors erase. the shadow block contains specified data that are needed for user features. the user area of shadow block may be used for user define d functions (possibly to store boot code, other configuration words or factory process codes). the usage of shadow sector is detailed in the following table: 17.2.5 user mode operation in user mode the flash module may be read and written (register writes and interlock writes), programmed or erased. the default state of the flash module is read. the main, shadow and test address space can be read only in the read state. the flash registers are always avai lable for read, also when the modul e is in power-down mode (except few documented registers). table 17-5. shadow sector structure name description addresses size nvsrc non-volatile system reset confi guration register 0x200000 to 0x200007 8 byte user area 0x200008 to 0x203dcf 15816 byte reserved 0x203dd0 to 0x203dd7 8 byte nvpwd0-1 non-volatile private censorship password 0-1 registers 0x203dd8 to 0x203ddf 8 byte nvsci0-1 non-volatile system censorship information 0-1 registers 0x203de0 to 0x203de7 8 byte reserved 0x203de8 to 0x203dff 24 byte nvbiu2-3 non-volatile bus interface unit 2-3 registers 0x203e00 to 0x203e0f 16 byte reserved 0x203e10 to 0x203e17 8 byte nvusro non-volatile user options register 0x203e18 to 0x203e1f 8 byte reserved 0x203e20 to 0x203fff 480 byte
pxd10 microcontroller reference manual, rev. 1 17-8 freescale semiconductor preliminary?subject to change without notice the flash module enters th e read state on reset. the module is in the read stat e under two sets of conditions: ? the read state is active when the module is enabled (user mode read) ? the read state is active when mcr.ers and mcr.esus are high and mcr.pgm is low (erase suspend). notice that no read-while-modify is available. flash core reads return 128 bits (1 page = 2 double words). registers reads return 32 bits (1 word). flash core reads are done through the bus interface unit. registers reads to unmapped register address space will return all 0?s. registers writes to unmapped register address space will have no effect. array reads attempted to invalid locations will result in indeterminate data. i nvalid locations occur when addressing is done to blocks that do not exist in non 2 n array sizes. interlock writes attempted to invali d locations, will result in an in terlock occurring, but attempts to program these blocks will not occur since they are for ced to be locked. erase will occur to selected and unlocked blocks even if the interloc k write is to an invalid location. simultaneous read cycle on the fl ash matrix and read/write cycl es on the registers are possible . on the contrary registers read/write acce sses simultaneous to a flash matr ix interlock write are forbidden. 17.2.5.1 reset a reset is the highest priority operation for the flash module and terminates all other operations. the flash module uses reset to init ialize register and status bits to their default reset values. if the flash module is executing a program or eras e operation (mcr.pgm = 1 or mcr.ers = 1) and a reset is issued, the operatio n will be aborted and the module will disable the high voltage logic without damage to the high vo ltage circuits. reset aborts all operations and forces the flash module into user mode ready to receive accesses. reset and power-off must not be used systematically to terminate a program or erase operation. after reset is negated, read register access may be done , although it should be noted that registers that require updating from shadow info rmation, or other inputs, may not read updated values until mcr.done transitions. mcr.done may be polled to determine if the flash module has transitioned out of reset. notice that the registers cannot be written until mcr.done is high. 17.2.5.2 power-down mode the power-down mode turns off all flash dc current sources, so that power dissipation is due only to leakage. in power-down mode no reads from or write to the module are possible.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-9 preliminary?subject to change without notice the user may not read so me registers (umisr0-4, ut 1-2 and part of ut0) un til the power-down mode is exited. on the contrary write access is lo cked on all the registers in power-down mode. when enabled the flash memory module returns to its previous state in all cases unle ss it was in the process of executing an erase high voltage operation at the time of entering power-down mode. if the flash memory module enters power-down mode during an eras e operation, the mcr[esus] bit is set. the user may resume the erase operation when the module exits power-down mode by clearing the mcr[esus] bit. mcr[ehv] must be high to resume the erase operation. if the flash memory module is configured to en ter power-down mode duri ng a program operation, the operation will be completed and th e power-down mode will be ente red only after the programming ends. if the flash memory module is put in power-down m ode and the vector table re mains mapped in the flash address space, the user must take care that the flash memory module will strongly incr ease the interrupt response time by adding several wait states. it is forbidden to enter low power mode when the power-down mode is active. 17.2.5.3 low power mode the low power mode turns off most of the dc current sources within the flash module. the module (flash core and register s) is not accessible for read or wr ite after entering low power mode. the wake-up time from low power mode is faster than the wake-up time from power-down mode. the user may not read some regist ers (umisr0-4, ut1-2 and part of ut 0) until the low power mode is exited. write access is locked on all the registers in low power mode. when exiting from low powe r mode the flash memory module returns to its previous state in all cases unless it was in the process of ex ecuting an erase high-voltage operati on at the time of entering low power mode. if the flash memory module enters low power mode during an erase ope ration, the mcr[esus] bit is set. the user may resume the erase operation when th e module exits low power mode by clearing the mcr[esus] bit. the mcr[ehv] bit must be high to resume the erase operation. if the flash memory module is configured to en ter low power mode during a program operation, the operation will be completed and the low power mode will be entered only after the programming ends. it is forbidden to enter power-down mode when the low power mode is active. 17.2.6 register description the flash user register s mapping is shown in table 17-6 . table 17-6. flash 528 kb single bank registers register name address offset location module configuration register (mcr) 0x0000 on page 11
pxd10 microcontroller reference manual, rev. 1 17-10 freescale semiconductor preliminary?subject to change without notice in the following some non-volatile registers are describe d. please notice that such entities are not flip-flops, but locations of test flash or shadow sectors with a special meaning. during the flash initialization phase, the fpec reads these non-volatile registers and update their related volatile registers. when the fpec detects ecc double errors in these sp ecial locations, it behaves in the following way: ? in case of a failing system locations (confi gurations, device options , redundancy, embalgo firmware), the initialization phase is in terrupted and a fatal error is flagged. ? in case of failing user locations (protections, censorship, biu, ...), the volatile registers are filled with all ?1?s and the flash initializat ion ends setting low the peg bit of mcr. in this section, the follow ing abbreviations are used low/mid address space block locking register (lml) 0x0004 on page 16 high address space block locking register (hbl) 0x0008 on page 18 secondary low/mid address space block lock register (sll) 0x000c on page 19 low/mid address space block select register (lms) 0x0010 on page 22 high address space block select register (hbs) 0x0014 on page 23 address register (adr) 0x0018 on page 24 bus interface unit register 0 (biu0) 0x001c on page 25 bus interface unit register 1 (biu1) 0x0020 on page 26 bus interface unit register 2 (biu2) 0x0024 on page 26 reserved 0x0028 reserved 0x002c reserved 0x0030 reserved 0x0034 reserved 0x0038 user test register 0 (ut0) 0x003c on page 28 user test register 1 (ut1) 0x0040 on page 30 user test register 2 (ut2) 0x0044 on page 30 user multiple input signatur e register 0 (umisr0) 0x0048 on page 31 user multiple input signatur e register 1 (umisr1) 0x004c on page 32 user multiple input signatur e register 2 (umisr2) 0x0050 on page 32 user multiple input signatur e register 3 (umisr3) 0x0054 on page 33 user multiple input signatur e register 4 (umisr4) 0x0058 on page 34 table 17-6. flash 528 kb single bank registers (continued) register name address offset location
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-11 preliminary?subject to change without notice 17.2.6.1 module configur ation register (mcr) the module configuration regi ster is used to enable and monitor al l the modify operations of the flash module. table 17-7. abbreviations case abbreviation description read/write rw the software can read and write to these bits. read/clear rc the software can read and clear to these bits. read-only r the software can only read these bits. write-only w the software should only write to these bits. address offset: 0x0000 reset value: 0x0220_0600 (code flash 0) 0x0210_0600 (code flash 1) 0123456789101112131415 edc 0 0 0 0 size2 size1 size0 0 las2 las1 las0 0 0 0 mas rc/0 r/0 r/0 r/0 r/0 r/0 r/1 r/0 r/0 r/0 r/1 r/0 r/0 r/0 r/0 r/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 eer rwe 0 0 peas done peg 0 0 0 0 pgm psus ers esus ehv rc/0 rc/0 r/0 r/0 r/0 r/1 r/1 r/0 r/0 r/0 r/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-3. module configuration register (mcr) table 17-8. mcr field descriptions field description 0 edc: ecc data correction (read/clear) edc provides information on previous reads. if a e cc single error detection and correction occurred, the edc bit will be set to 1. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to 1 by the user. in the event of a ecc double error detection, this bit will not be set. if edc is not set, or remains 0, this indicates that a ll previous reads (from the la st reset, or clearing of edc) were not corrected through ecc. since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. a write of 0 will have no effect. the function of this bit is soc dependent and it can be configured to be disabled. 0: reads are occurring normally. 1: an ecc single error occurred and was corrected during a previous read. 1:4 reserved (read only) write these bits has no effect a nd read these bits always outputs 0. 5:7 size2-0: array space size 2-0 (read only) the value of size field is dependent upon the size of the flash module, according to table 17-9 . 8 reserved (read only). write this bit has no effect and read this bit always outputs 0.
pxd10 microcontroller reference manual, rev. 1 17-12 freescale semiconductor preliminary?subject to change without notice 9:11 las2-0: low address space 2- (read only) the value of the las field correspond to the config uration of the low address space, according to table 17-10 . 12:14 reserved (read only) write these bits has no effect a nd read these bits always outputs 0. 15 mas: mid address space (read only) the value of the mas field correspond to the confi guration of the mid address space, according to table 17-11 . 16 eer: ecc event error (read/clear) eer provides information on previous reads. if a ecc double error detection occurred, the eer bit will be set to 1. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to 1 by the user. in the event of a ecc single error detection and correction, this bit will not be set. if eer is not set, or remains 0, this indicates that a ll previous reads (from the last reset, or clearing of eer) were correct. since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. a write of 0 will have no effect. 0: reads are occurring normally. 1: an ecc double error occurred during a previous read. 17 rwe: read-while-write event error (read/clear) rwe provides information on previous reads when a modify operation is on going. if a rww error occurs, the rwe bit will be set to 1. read-while-write erro r means that a read access to the flash matrix has occurred while the fpec was performing a program or erase operation or an array integrity check. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to 1 by the user. if rwe is not set, or remains 0, this indicates that all previous rww reads (from the last reset, or clearing of rwe) were correct. since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. a write of 0 will have no effect. 0: reads are occurring normally. 1: a rww error occurred during a previous read. 18:19 reserved (read only) write these bits has no effect a nd read these bits always outputs 0. 20 peas: program/erase access space (read only) peas is used to indicate which space is valid for program and erase operations: main array space or shadow/test space. peas=0 indicates that the main address space is active for all flash module program and erase operations. peas=1 indicates that th e test or shadow addr ess space is active for program and erase. the value in peas is captured and held with the first inte rlock write done for modify operations. the value of peas is retained between sampling events (i.e. subsequent first interlock writes). 0: shadow/test address space is disabled fo r program/erase and main address space enabled. 1: shadow/test address space is enabled for program/erase and main address space disabled. table 17-8. mcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-13 preliminary?subject to change without notice 21 done: modify operation done (read only) done indicates if the flash module is performing a high voltage operation. done is set to 1 on termination of the flash module reset. done is cleared to 0 immediately after a 0 to 1 transi tion of ehv, which initiates a high voltage operation, or after resuming a suspended operation. done is set to 1 at the end of program and erase high voltage sequences. done is set to 1 (within t pabt or t eabt , equal to p/e abort latency) after a 1 to 0 transition of ehv, which aborts a high voltage program/erase operation. done is set to 1 (within t esus , time equals to erase suspend latency) after a 0 to 1 transition of esus, which suspends an erase operation. 0: flash is executing a high voltage operation. 1: flash is not executing a high voltage operation. 22 peg: program/erase good (read only) the peg bit indicates the completion status of the la st flash program or erase sequence for which high voltage operations were initiated. the value of peg is updated automatically during the program and erase high voltage operations. aborting a program/erase high voltage operation will cause peg to be cleared to 0, indicating the sequence failed. peg is set to 1 when the flash module is reset, unless a flash initialization error has been detected. the value of peg is valid only when pgm=1 and/or ers=1 and after done transitions from 0 to 1 due to an abort or the completion of a program/erase operation. peg is valid until pgm/ers makes a 1 to 0 transition or ehv makes a 0 to 1 transition. the value in peg is not valid after a 0 to 1 transition of done caused by esus being set to logic 1. if program or erase are attempted on blocks that ar e locked, the response will be peg=1, indicating that the operation was successful, and the content of the block were properly protected from the program or erase operation. if a program operation tries to program at ?1? bits t hat are at ?0?, the program operation is correctly executed on the new bits to be programmed at ?0?, bu t peg is cleared, indica ting that the requested operation has failed. in array integrity check or margin mode peg is set to 1 when the operation is completed, regardless of the occurrence of any error. the presence of e rrors can be detected only by comparing the checksum value stored in umirs0-1. aborting an array integrity check or a margin mode operation will cause peg to be cleared to 0, indicating the sequence failed. 0: program or erase operation failed. 1: program or erase operation successful. 23:26 reserved (read only) write these bits has no effect a nd read these bits always outputs 0. 27 pgm: program (read/write) pgm is used to setup the flas h module for a program operation. a 0 to 1 transition of pgm initiates a program sequence. a 1 to 0 transition of pgm ends the program sequence. pgm can be set only under user mode read (ers is low and ut0.aie is low). pgm can be cleared by the user on ly when ehv is low and done is high. pgm is cleared on reset. 0: flash is not executing a program sequence. 1: flash is executing a program sequence. 28 psus: program suspend (read/write) write this bit has no effect, but the written data can be read back. table 17-8. mcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 17-14 freescale semiconductor preliminary?subject to change without notice 29 ers: erase (read/write) ers is used to setup the flash module for an erase operation. a 0 to 1 transition of ers initiates an erase sequence. a 1 to 0 transition of ers ends the erase sequence. ers can be set only under user mode read (pgm is low and ut0.aie is low). ers can be cleared by the user only when esus and ehv are low and done is high. ers is cleared on reset. 0: flash is not executing an erase sequence. 1: flash is executing an erase sequence. 30 esus: erase suspend (read/write) esus is used to indicate that the flash module is in erase suspend or in the process of entering a suspend state. the flash module is in erase suspend when esus=1 and done=1. esus can be set high only when ers and ehv are high and pgm is low. a 0 to 1 transition of esus starts the sequence which sets done and places the flash in erase suspend. the flash module enters suspend within t esus of this transition. esus can be cleared only when done and ehv are high and pgm is low. a 1 to 0 transition of esus with ehv=1 starts the sequence which clears done and returns the module to erase. the flash module cannot exit erase suspend and clear done while ehv is low. esus is cleared on reset. 0: erase sequence is not suspended. 1: erase sequence is suspended. 31 ehv: enable high voltage (read/write) the ehv bit enables the flash module for a high voltage program/erase operation. ehv is cleared on reset. ehv must be set after an interlock write to start a program/erase sequence. ehv may be set under one of the following conditions: erase (ers=1, esus=0, ut0.aie=0) program (ers=0, esus=0, pgm=1, ut0.aie=0) in normal operation, a 1 to 0 transition of ehv with done high and esus low terminates the current program/erase high voltage operation. when an operation is aborted, there is a 1 to 0 tr ansition of ehv with done low and the eventual suspend bit low. an abort causes the value of peg to be cleared, indicating a failing program/erase; address locations being operated on by the aborted ope ration contain indeterminate data after an abort. a suspended operation cannot be aborted. aborting a high voltage operation will leave the flash module addresses in an undeterminate data state. this may be recovered by executing an erase on the affected blocks. ehv may be written during suspend. ehv must be high to exit suspend. ehv may not be written after esus is set and before done transitions high. ehv ma y not be cleared after esus is cleared and before done transitions low. 0: flash is not enabled to perform an high voltage operation. 1: flash is enabled to perform an high voltage operation. table 17-9. array space size size2-0 array space size 000 128kb 001 256kb 010 512kb table 17-8. mcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-15 preliminary?subject to change without notice a number of mcr bits are protected agai nst write when another bit, or set of bits, is in a specific state. these write locks are covered on a bit by bit basis in the preceding description, but those locks do not consider the effects of trying to wr ite two or more bits simultaneously. the flash module does not allow the user to write bits simultaneously which would put the device into an illegal state. this is implemente d through a priority mech anism among the bits. the bit changing priorities are detailed in the following table. 011 reserved (1024kb) 100 reserved (1536kb) 101 reserved (2048kb) 110 64kb 111 reserved table 17-10. low address space configuration las2-0 low address space sectorization 000 reserved 001 2 ? 128 kb 010 32 kb + 2 ? 16 kb + 2 ? 32 kb + 128 kb 011 reserved 100 reserved 101 reserved 110 4 x 16kb 111 reserved table 17-11. mid address space configuration mas mid address space sectorization 02 ? 128 kb or 0 kb 1 reserved table 17-12. mcr bits set/clear priority levels priority level mcr bits 1ers 2pgm 3ehv 4 esus table 17-9. array space size (continued) size2-0 array space size
pxd10 microcontroller reference manual, rev. 1 17-16 freescale semiconductor preliminary?subject to change without notice if the user attempts to write two or more mcr bits simultaneously then only the bit with the lowest priority level will be written. 17.2.6.2 low/mid address space block locking register (lml) address offset: 0x0004 reset value: 0x00xxxxxx, initially determin ed by nvlml value from test sector. 17.2.6.3 non-volatile low/mid address sp ace block locking register (nvlml) the low/mid address space block locking register provides a means to protect blocks from being modified. these bits, along wi th bits in the sll register, determine if the block is locked from program or erase. an ?or? of lml and sll determine the final lock status. the lml register has a related n on-volatile low/mid address space bl ock locking register located in test flash that contains the default reset value fo r lml: the nvlml register is read during the reset phase of the flash module and loaded into the lml. the nvlml register is a 64-bit register, the 32 most significative bits of whic h (bits 63-32) are ?don?t care? and eventually used to manage ecc codes. address offset: 0x403de8 delivery value: 0xffffffff 0123456789101112131415 lme0000000000tslk00mlk1mlk0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/x r/0 r/0 rw/x rw/x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 llk15 llk14 llk13 llk12 llk11 llk10 llk9 llk8 llk7 llk6 llk5 llk4 llk3 llk2 llk1 llk0 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x figure 17-4. non-volatile low/mid address space block locking register (nvlml) table 17-13. lml field descriptions field description 0 lme : low/mid address space block enable (read only) this bit is used to enable the lock registers (tslk, ml k1-0 and llk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bi t is to write a password, and if the password matches, the lme bit will be set to reflect the status of enab led, and is enabled until a reset operation occurs. for lme the password 0xa1a11111 must be written to the lml register. 0: low address locks are disabled: tslk, mlk1-0 and llk15-0 cannot be written. 1: low address locks are enabled: tslk, mlk1-0 and llk15-0 can be written. 1:10 reserved (read only). write these bits has no effect and read these bits always outputs 0.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-17 preliminary?subject to change without notice 11 tslk : test/shadow address space block lock (read/write) this bit is used to lock the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the tslk register signifies that the test/shadow block is locked for program and erase. a value of 0 in the tslk register signifies that the test/shadow block is available to receive program and erase pulses. the tslk register is not writable once an interloc k write is completed until mcr.done is set at the completion of the requested operation. likewise, the tslk register is not writable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the tslk register. the tslk bit may be written as a register. reset will cause the bit to go back to its test flash block value. the default value of the tslk bit (assuming erased fuses) would be locked. tslk is not writable unless lme is high. 0: test/shadow address space block is unlocked and can be modified (if also sll.stslk=0). 1: test/shadow address space block is locked and cannot be modified. 12:13 reserved (read only). write these bits has no effect and read these bits always outputs 0. 14:15 mlk1-0 : mid address space block lock 1-0 (read/write) these bits are used to lock the blocks of mid address space from program and erase. for code flash 0, mlk1-0 are relat ed to sectors b0f7 -6, respectively. for code flash 1, mlk1-0 are relat ed to sectors b2f3 -2, respectively. a value of 1 in a bit of the mlk register signifie s that the corresponding block is locked for program and erase. a value of 0 in a bit of the mlk register signifies that the corresponding block is available to receive program and erase pulses. the mlk register is not writable once an interloc k write is completed until mcr.done is set at the completion of the requested operation. likewise, the mlk register is not writable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the mlk registers. the mlk bits may be written as a register. reset will cause the bits to go back to their test flash block value. the default value of the mlk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to config uration or total memory size), the mlk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the test flash block), and register writes will have no effect. mlk is not writable unless lme is high. 0: mid address space block is unlocked and can be modified (if also sll.smlk=0). 1: mid address space block is locked and cannot be modified. table 17-13. lml field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 17-18 freescale semiconductor preliminary?subject to change without notice 17.2.6.4 high address space block locking register (hbl) address offset: 0x0008 reset value: 0x000000xx, initially determined by nvhbl, located in test sector. 17.2.6.5 non-volatile high address space block locking register (nvhbl) the high address space block locking register provides a means to protect blocks from being modified. the hbl register has a related non- volatile high address space block lo cking register located in test flash that contains the default rese t value for hbl: the nvhbl register is read during th e reset phase of the flash module and loaded into the hbl. 16:31 llk15-0 : low address space block lock 15-0 (read/write) these bits are used to lock the blocks of low address space from program and erase. for code flash 0, llk5-0 are related to sectors b0f5-0, respectively. llk15-6 are not used for code flash 0. for code flash 1, llk1-0 are related to to sectors b2f1-0, respectively. llk15-2 are not used for for code flash 1. a value of 1 in a bit of the llk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the llk register signifies that the corresponding block is available to receive program and erase pulses. the llk register is not writable once an interlock write is completed until mcr.done is set at the completion of the requested operation. likewise, the llk register is not writable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the llk registers. the llk bits may be written as a register. reset will cause the bits to go back to their test flash block value. the default value of the llk bits (assuming erased fuses) would be locked. in the event that blocks are not pres ent (due to configuration or total me mory size), the llk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the test flash block), and register writes will have no effect. in code flash 0 bits llk15-6 are read-only and locked at 1. in code flash 1 bits llk15-2 are read-only and locked at 1. llk is not writable unless lme is high. 0: low address space block is unlocked and can be modified (if also sll.slk=0). 1: low address space block is locked and cannot be modified. address offset: 0x403df0 delivery value: 0xffffffff 0123456789101112131415 hbe000000000000000 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0000000000hlk5hlk4hlk3hlk2hlk1hlk0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/x rw/x rw/x rw/x rw/x rw/x figure 17-5. non-volatile high address space block locking register (nvhbl) table 17-13. lml field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-19 preliminary?subject to change without notice the nvhbl register is a 64-bit register, the 32 most significative bits of which (bits 63-32) are ?don?t care? and eventually used to manage ecc codes. 17.2.6.6 secondary low/mid address sp ace block locking register (sll) address offset: 0x000c reset value: 0x00xxxxxx, initially determined by nvsll, located in test sector. table 17-14. hbl field descriptions field description 0 high address space block enable (read only) this bit is used to enable the lock registers (hlk 5-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bit is to write a password, and if the password matches, the hbe bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for hbe the password 0xb2b22222 must be written to the hbl register. 0: high address locks are disabled: hlk5-0 cannot be written. 1: high address locks are enabled: hlk5-0 can be written. 1:25 reserved (read only). write these bits has no effect and read these bits always outputs 0. 26:31 hlk5-0 : high address space block lock 5-0 (read/write) these bits are used to lock the blocks of high address space from program and erase. all the hlk5-0 are not used for both code flash 0 and 1 that are all mapped in mid and low address space. a value of 1 in a bit of the hlk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the hlk register signifies that the corresponding block is available to receive program and erase pulses.the hlk register is not writable once an interlock write is completed until mcr.done is set at the completion of the requested operation. likewise , the hlk register is not writable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the hlk registers. the hlk bits may be written as a register. reset will cause the bits to go ba ck to their test flash block value. the default value of the hlk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configur ation or total memory size), the hlk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the test flash block), and register writes will have no effect. in both code flash 0 and 1, bits hlk5-0 are read-only and locked at 1. hlk is not writable unless hbe is high. 0: high address space block is unlocked and can be modified. 1: high address space block is locked and cannot be modified.
pxd10 microcontroller reference manual, rev. 1 17-20 freescale semiconductor preliminary?subject to change without notice 17.2.6.7 non-volatile secondary low/ mid address space block locking reg (nvsll) the secondary low/mid address spac e block locking register provides an alternative means to protect blocks from being modified. these bits, along with bits in the lml register, determine if the block is locked from program or erase. an ?or? of lml and sll determine the final lock status. the sll register has a related n on-volatile secondary low/mid addre ss space block locking register located in test flash that contains the default reset value for sll: the nvsll re gister is read during the reset phase of the flash module and loaded into the sll. the nvsll register is a 64-bit regist er, the 32 most significative bits of which (bits 63-32) are ?don?t care? and eventually used to manage ecc codes. address offset: 0x403df8 delivery value: 0xffffffff 0123456789101112131415 sle0000000000stslk00smk1smk0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/x r/0 r/0 rw/x rw/x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 slk15 slk14 slk13 slk12 slk11 slk10 slk9 slk8 slk7 slk6 slk5 slk4 slk3 slk2 slk1 slk0 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x figure 17-6. non-volatile secondary low/mid address space block locking reg (nvsll) table 17-15. sll field descriptions field description 0 sle : secondary low/mid address space block enable (read only) this bit is used to enable the lock registers (stslk , smk1-0 and slk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bi t is to write a password, and if the password matches, the sle bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle the password 0xc3c33333 must be written to the sll register. 0: secondary low/mid address locks are disabled: stslk, smk1-0 and slk 15-0 cannot be written. 1: secondary low/mid address locks are enabled: stslk, smk1-0 and slk15-0 can be written. 1:10 reserved (read only). write these bits has no effect and read these bits always outputs 0.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-21 preliminary?subject to change without notice 11 stslk : secondary test/shadow address space block lock (read/write) this bit is used as an alternate means to lock t he block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the stslk register signifies that the test/shadow block is locked for program and erase. a value of 0 in the stslk register signifies that the test/shadow block is available to receive program and erase pulses. the stslk register is not writable once an interloc k write is completed until mcr.done is set at the completion of the requested operation. likewise, the stslk register is not writable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the stslk register. the stslk bit may be written as a register. reset will cause the bit to go back to its test flash block value. the default value of the stslk bit (assuming erased fuses) would be locked. stslk is not writable unless sle is high. 0: test/shadow address space block is unlocked and can be modified (if also lml.tslk=0). 1: test/shadow address space block is locked and cannot be modified. 12:13 reserved (read only). write these bits has no effect and read these bits always outputs 0. 14:15 smk1-0 : secondary mid address space block lock 1-0 (read/write) these bits are used as an alternate means to lock the blocks of mid address space from program and erase. for code flash 0, smk1-0 are related to sectors b0f7-6, respectively. for code flash 1, smk1-0 are related to sectors b2f3-2, respectively. a value of 1 in a bit of the smk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the smk register signifies that the corresponding block is available to receive program and erase pulses. the smk register is not writable once an interlock write is completed until mcr.done is set at the completion of the requested operation. likewise, the smk register is not writable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the smk registers. the smk bits may be written as a register. reset will cause the bits to go bac k to their test flash block value. the default value of the smk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configur ation or total memory size), the smk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the test flash block), and register writes will have no effect. smk is not writable unless sle is high. 0: mid address space block is unlocked and can be modified (if also lml.mlk=0). 1: mid address space block is locked and cannot be modified. table 17-15. sll field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 17-22 freescale semiconductor preliminary?subject to change without notice 17.2.6.8 low/mid address space block select register (lms) the low/mid address space block sel ect register provides a means to se lect blocks to be operated on during erase. 16:31 slk15-0 : secondary low address space block lock 15-0 (read/write) these bits are used as an alternate means to lock the blocks of low address space from program and erase. for code flash 0, slk5-0 are related to sectors b0f5-0, respectively. for code flash 1, slk1-0 are related to sectors b2f1-0, respectively. a value of 1 in a bit of the slk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the slk register signifies that the corresponding block is available to receive program and erase pulses. the slk register is not writable once an interlock write is completed until mcr.done is set at the completion of the requested operation. likewise, the slk register is not writable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the slk registers. the slk bits may be written as a register. reset will cause the bits to go bac k to their test flash block value. the default value of the slk bits (assuming erased fuses) would be locked. in the event that blocks are not pres ent (due to configuration or total me mory size), the slk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the test flash block), and register writes will have no effect. in code flash 0 bits slk15-6 are read-only and locked at 1. in code flash 1, bits slk15-2 are read-only and locked at 1. slk is not writable unless sle is high. 0: low address space block is unlocked and can be modified (if also lml.llk=0). 1: low address space block is locked and cannot be modified. address offset: 0x00010 reset value: 0x00000000 0123456789101112131415 00000000000000msl1msl0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsl15 lsl14 lsl13 lsl12 lsl11 lsl10 lsl9 lsl8 lsl7 lsl6 lsl5 lsl4 lsl3 lsl2 lsl1 lsl0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-7. low/mid address space block select register (lms) table 17-16. lms field descriptions field description 0:13 reserved (read only). write these bits has no effect and read these bits always outputs 0. table 17-15. sll field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-23 preliminary?subject to change without notice 17.2.6.9 high address space bl ock select register (hbs) the high address space block select register provides a means to se lect blocks to be operated on during erase. 14:15 msl1-0 : mid address space block select 1-0 (read/write) a value of 1 in the select register signi fies that the block is selected for erase. a value of 0 in the select register signifies that the block is not selected for erase. the reset value for the select register is 0, or unselected. for code flash 0, msl1-0 are related to sectors b0f7-6, respectively. for code flash 1, msl1-0 are related to sectors b2f3-2, respectively. the blocks must be selected (or unselected) before do ing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not pres ent (due to configuration or total memory size), the corresponding msl bits will default to unselected, and will not be writable. the reset value will always be 0, and register writes will have no effect. 0: mid address space block is unselected for erase. 1: mid address space block is selected for erase. 16:31 lsl15-0 : low address space block select 15-0 (read/write) a value of 1 in the select register signi fies that the block is selected for erase. a value of 0 in the select register signifies that the block is not selected for erase. the reset value for the select register is 0, or unselected. for code flash 0, lsl5-0 are related to sectors b0f5-0, respectively. for code flash 1, lsl1-0 are related to sectors b2f1-0, respectively. the blocks must be selected (or unselected) before do ing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not pres ent (due to configuration or total memory size), the corresponding lsl bits will default to unselected, and will not be writable. the reset value will always be 0, and register writes will have no effect. in code flash 0, bits lsl15-6 are read-only and locked at 0. in code flash 1 bits lsl15-2 are read-only and locked at 0. 0: low address space block is unselected for erase. 1: low address space block is selected for erase. address offset: 0x00014 reset value: 0x00000000 0123456789101112131415 0000000000000000 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0000000000hsl5hsl4hsl3hsl2hsl1hsl0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/0rw/0rw/0rw/0rw/0rw/0 figure 17-8. high address space block select register (hbs) table 17-16. lms field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 17-24 freescale semiconductor preliminary?subject to change without notice 17.2.6.10 address register (adr) the address register provi des the first failing address in the even t module failures (ecc, rww or fpec) or the first address at which a ecc single error correction occurs. table 17-17. hbs field descriptions field description 0:25 reserved (read only). write these bits has no effect and read these bits always outputs 0. 26:31 hsl5-0 : high address space block select 5-0 (read/write) a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not select ed for erase. the reset value for the select register is 0, or unselected. all the hsl5-0 are not used for both code flash 0 and 1 that are all mapped in mid and low address space. the blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not present (due to config uration or total memory size), the corresponding hsl bits will default to unselected, and will not be writable. the reset value will always be 0, and register writes will have no effect. in both code flash 0 and 1, bits hs l5-0 are read-only and locked at 0. 0: high address space block is unselected for erase. 1: high address space block is selected for erase. address offset: 0x00018 reset value: 0x00000000 0123456789101112131415 000000000ad22ad21ad20ad19ad18ad17ad16 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 0 0 0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 figure 17-9. address register (adr) table 17-18. adr field descriptions field description 0:8 reserved (read only). write these bits has no effect and read these bits always outputs 0.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-25 preliminary?subject to change without notice 17.2.6.11 bus interface unit 0 register (biu0) the bus interface unit 0 register provides a mean for biu specific in formation, or biu configuration information to be stored. please see section 17.4.3.2.1, platform flash configuration register 0 (pfcr0),? for more information about register description. this register is present only in code flash 0. 9:28 ad22-3 : address 22-3 (read only) the address register provides the first failing addre ss in the event of ecc error (mcr.eer set) or the first failing address in the event of rww error (mcr.rw e set), or the address of a failure that may have occurred in a fpec operation (mcr. peg cleared). the address register provides also the first address at which a ecc single error correction occurs (mcr.e dc set), if the soc is configured to show this feature. the ecc double error detection takes the highest priority, followed by the rww error, the fpec error and the ecc single error correction. when accessed a dr will provide the address related to the first event occurred with the highest priority. the priorities bet ween these 4 possible events is summarized in the following table. this address is always a double word address that selects 64 bits. in case of a simultaneous ecc double error detection on both double words of the same page, bit ad3 will output 0. the same is valid for a simultaneous ecc single error correction on both double words of the same page. in user mode the address register is read only. 29:31 reserved (read only). write these bits has no effect and read these bits always outputs 0. table 17-19. adr content: priority list priority level error flag adr content 1 mcr.eer = 1 address of first ecc double error 2 mcr.rwe = 1 address of first rww error 3 mcr.peg = 0 address of first fpec error 4 mcr.edc = 1 address of first ecc single error correction address offset: 0x0001c reset value: 0xxxxxxxxx 0123456789101112131415 bi031 bi030 bi029 bi028 bi027 bi026 bi025 bi024 bi023 bi022 bi021 bi020 bi019 bi018 bi017 bi016 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bi015 bi014 bi013 bi012 bi011 bi010 bi009 bi008 bi007 bi006 bi005 bi004 bi003 bi002 bi001 bi000 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x figure 17-10. bus interface unit 0 register (biu0) table 17-18. adr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 17-26 freescale semiconductor preliminary?subject to change without notice note on this device, biu0 and pfcr0 are th e same register. your software may refer to either register. for clarity, however, it is recommended that you use pfcr0. 17.2.6.12 bus interface unit 1 register (biu1) the bus interface unit 1 register provides a mean for biu specific in formation, or biu configuration information to be stored. please see section 17.4.3.2.2, platform flash configuration register 1 (pfcr1),? for more information about register description. this register is present only in code flash 0. note on this device, biu1 and pfcr1 are th e same register. your software may refer to either register. for clarity, however, it is recommended that you use pfcr1. 17.2.6.13 bus interface unit 2 register (biu2) address offset: 0x00024 reset value: 0xxxxxxxxx table 17-20. biu0 field descriptions field description 0:31 bi031-00 : bus interface unit 0 31-00 (read/write) the writability of the bits in this register can be locked. address offset: 0x00020 reset value: 0xxxxxxxxx 0123456789101112131415 bi131 bi130 bi129 bi128 bi127 bi126 bi125 bi124 bi123 bi122 bi121 bi120 bi119 bi118 bi117 bi116 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bi115 bi114 bi113 bi112 bi111 bi110 bi109 bi108 bi107 bi106 bi105 bi104 bi103 bi102 bi101 bi100 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x figure 17-11. bus interface unit 1 register (biu1) table 17-21. biu1 field descriptions field description 0:31 bi131-00 : bus interface unit 1 31-00 (read/write) the writability of the bits in this register can be locked. the use of this bus is soc specific.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-27 preliminary?subject to change without notice 17.2.6.14 non-volatile bus interface unit 2 register (nvbiu2) the bus interface unit 2 register provides a mean for biu specific in formation, or biu configuration information to be stored. please see section 17.4.3.2.3, platform flash access protection register (pfapr),? for more information a bout register description. this register is present only in code flash 0. the biu2 register has a related non- volatile bus interface unit 2 register located in shadow sector that contains the default reset value for biu2: the nvbiu2 register is read during the reset phase of the flash module and loaded into the biu2. the nvbiu2 register is a 64-bit regi ster, the 32 most significative bits of which (bits 63-32) are ?don?t care? and eventually used to manage ecc codes. note on this device, biu2 and pfapr are th e same register. y our software may refer to either register. for clarity, however, it is recommended that you use pfapr. address offset: 0x203e00 delivery value: 0xxxxxxxxx 0123456789101112131415 bi231 bi230 bi229 bi228 bi227 bi226 bi225 bi224 bi223 bi222 bi221 bi220 bi219 bi218 bi217 bi216 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bi215 bi214 bi213 bi212 bi211 bi210 bi209 bi208 bi207 bi206 bi205 bi204 bi203 bi202 bi201 bi200 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x figure 17-12. non-volatile bus interface unit 2 register (nvbiu2) table 17-22. biu2 field descriptions field description 0:31 bi231-00 : bus interface unit 2 31-00 (read/write) the bi231-00 generic registers are reset bas ed on the information stored in nvbiu2. the writability of the bits in this register can be locked. the use of this bus is soc specific.
pxd10 microcontroller reference manual, rev. 1 17-28 freescale semiconductor preliminary?subject to change without notice 17.2.6.15 user test 0 register (ut0) the user test feature gives the user of the flash m odule the ability to perform test features on the flash. the user test 0 register allows to control th e way in which the flas h content check is done. bits mre, mrv, ais, eie and dsi7-0 of the us er test 0 register are not accessible whenever mcr.done or ut0.aid are low: reading returns i ndeterminate data while writing has no effect. address offset: 0x0003c reset value: 0x00000001 0123456789101112131415 ute0000000dsi7dsi6dsi5dsi4dsi3dsi2dsi1dsi0 rw/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/0rw/0rw/0rw/0rw/0rw/0rw/0rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 000000000xmremrveieaisaieaid r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/0rw/0rw/0rw/0rw/0rw/0 r/1 figure 17-13. user test 0 register (ut0) table 17-23. ut0 field descriptions field description 0 ute : user test enable (read/clear) this status bit gives indication when user test is enabled. all bits in ut0-2 and umisr0-4 are locked when this bit is 0. this bit is not writeable to a 1, bu t may be cleared. the reset value is 0. the method to set this bit is to provide a password, and if the password matches, the ute bit is set to reflect the status of enabled, and is enabled until it is cleared by a register write. for ute the password 0xf9f99999 must be written to the ut0 register. 1:7 reserved (read only). write these bits has no effect a nd read these bits always outputs 0. 8:15 dsi7-0 : data syndrome input 7-0 (read/write) these bits represent the input of syndrome bits of ecc logic used in the ecc logic check. the dsi7-0 correspond to the 8 syndrome bits on a double word. these bits are not accessible whenever mcr.done or ut0.aid are low: read ing returns indeterminate data while writing has no effect. 0: the syndrome bit is forced at 0. 1: the syndrome bit is forced at 1. 16:24 reserved (read only). write these bits has no effect a nd read these bits always outputs 0. 25 reserved (read/write). this bit can be written and its value can be re ad back, but there is no function associated. this bit is not accessible whenever mcr.done or ut 0.aid are low: reading returns indeterminate data while writing has no effect.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-29 preliminary?subject to change without notice 26 mre : margin read enable (read/write) mre enables margin reads to be done. this bit, combined with mrv, enables regular user mode reads to be replaced by margin reads. margin reads are only active during array integrity checks; normal user reads are not affected by mre. this bit is not accessible whenever mcr.done or ut 0.aid are low: reading returns indeterminate data while writing has no effect. 0: margin reads are not enabled, all reads are user mode reads. 1: margin reads are enabled. 27 mrv : margin read value (read/write) if mre is high, mrv selects the margin level that is being checked. margin can be checked to an erased level (mrv=1) or to a programmed level (mrv=0). this bit is not accessible whenever mcr.done or ut 0.aid are low: reading returns indeterminate data while writing has no effect. 0: zero?s (programmed) margin reads are requested (if mre=1). 1: one?s (erased) margin reads are requested (if mre=1). 28 eie : ecc data input enable (read/write) eie enables the ecc logic check operation to be done. this bit is not accessible whenever mcr.done or ut 0.aid are low: reading returns indeterminate data while writing has no effect. 0: ecc logic check is not enabled. 1: ecc logic check is enabled. 29 ais : array integrity sequence (read/write) ais determines the address sequence to be used during array integrity checks or margin mode. the default sequence (ais=0) is meant to replicate sequences normal user code follows, and thoroughly checks the read propagation paths. this sequence is proprietary. the alternative sequence (ais=1) is just logically sequential. it should be noted that the time to run a sequential sequence is significantly shorter than the time to run the proprietary sequence. only the sequential mode is allowed in margin mode. this bit is not accessible whenever mcr.done or ut 0.aid are low: reading returns indeterminate data while writing has no effect. 0: array integrity sequence is proprietary sequence. 1: array integrity sequence or margin mode sequence is sequential. 31 aie : array integrity enable (read/write) aie set to 1 starts the array integrity check done on all selected and unlocked blocks. the pattern is selected by ais, and the misr (umisr0- 4) can be checked after the operation is complete, to determine if a correct signature is obtained. aie can be set only if mcr.ers, mcr.pgm and mcr.ehv are all low. 0: array integrity checks, margin mode, and ecc logic checks are not enabled. 1: array integrity checks, margin mode, and ecc logic checks are enabled. 31 aid : array integrity done (read only) aid will be cleared upon an array integrity check being enabled (to signify the operation is on-going). once completed, aid will be set to indicate that the array integrity check is complete. at this time the misr (umisr0-4) can be checked. 0: array integrity check is on-going. 1: array integrity check is done. table 17-23. ut0 field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 17-30 freescale semiconductor preliminary?subject to change without notice 17.2.6.16 user test 1 register (ut1) the user test 1 register allows to enable the check s on the ecc logic related to the 32 lsb of the double word. the user test 1 register is not accessible whenev er mcr.done or ut0.aid are low: reading returns indeterminate data whil e writing has no effect. 17.2.6.17 user test 2 register (ut2) the user test 2 register allows to enable the check s on the ecc logic related to the 32 msb of the double word. the user test 2 register is not accessible whenev er mcr.done or ut0.aid are low: reading returns indeterminate data whil e writing has no effect. address offset: 0x00040 reset value: 0x00000000 0123456789101112131415 dai31 dai30 dai29 dai28 dai27 dai26 dai25 dai24 dai23 dai22 dai21 dai20 dai19 dai18 dai17 dai16 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dai15 dai14 dai13 dai12 dai11 dai10 dai09 dai08 dai07 dai06 dai05 dai04 dai03 dai02 dai01 dai00 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-14. user test 1 register (ut1) table 17-24. ut1 field descriptions field description 0:31 dai31-00 : data array input 31-0 (read/write) these bits represent the input of even word of ec c logic used in the ecc logic check. the dai31-00 correspond to the 32 array bits representing word 0 within the double word. 0: the array bit is forced at 0. 1: the array bit is forced at 1. address offset: 0x00044 reset value: 0x00000000 0123456789101112131415 dai63 dai62 dai61 dai60 dai59 dai58 dai57 dai56 dai55 dai54 dai53 dai52 dai51 dai50 dai49 dai48 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dai47 dai46 dai45 dai44 dai43 dai42 dai41 dai40 dai39 dai38 dai37 dai36 dai35 dai34 dai33 dai32 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-15. user test 2 register (ut2)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-31 preliminary?subject to change without notice 17.2.6.18 user multiple input signature register 0 (umisr0) the multiple input signature register provide s a mean to evaluate the array integrity. the user multiple input signature re gister 0 represents the bits 31-0 of the whole 144 bits word (2 double words including ecc). the umisr0 register is not accessible whenever mcr.done or ut0.aid ar e low: reading returns indeterminate data whil e writing has no effect. table 17-25. ut2 field descriptions field description 0:31 dai63-32 : data array input 63-32 (read/write) these bits represent the input of odd word of e cc logic used in the ecc logic check. the dai63-32 correspond to the 32 array bits representing word 1 within the double word. 0: the array bit is forced at 0. 1: the array bit is forced at 1. address offset: 0x00048 reset value: 0x00000000 0123456789101112131415 ms031 ms030 ms029 ms028 ms027 ms026 ms025 ms024 ms023 ms022 ms021 ms020 ms019 ms018 ms017 ms016 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ms015 ms014 ms013 ms012 ms011 ms010 ms009 ms008 ms007 ms006 ms005 ms004 ms003 ms002 ms001 ms000 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-16. user multiple input signature register 0 (umisr0) table 17-26. umsir0 field descriptions field description 0:31 ms031-000 : multiple input signature 031-000 (read/write) these bits represent the misr value obtained accumu lating the bits 31-0 of all the pages read from the flash memory. the ms can be seeded to any value by writing the umisr0 register.
pxd10 microcontroller reference manual, rev. 1 17-32 freescale semiconductor preliminary?subject to change without notice 17.2.6.19 user multiple input signature register 1 (umisr1) the multiple input signature register provide s a mean to evaluate the array integrity. the user multiple input signature register 1 represents the bits 63- 32 of the whole 144 bits word (2 double words including ecc). the umisr1 register is not accessible whenever mcr.done or ut0.aid ar e low: reading returns indeterminate data whil e writing has no effect. 17.2.6.20 user multiple input signature register 2 (umisr2) the multiple input signature register provide s a mean to evaluate the array integrity. the user multiple input signature register 2 represents the bits 95- 64 of the whole 144 bits word (2 double words including ecc). address offset: 0x0004c reset value: 0x00000000 0123456789101112131415 ms063 ms062 ms061 ms060 ms059 ms058 ms057 ms056 ms055 ms054 ms053 ms052 ms051 ms050 ms049 ms048 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ms047 ms046 ms045 ms044 ms043 ms042 ms041 ms040 ms039 ms038 ms037 ms036 ms035 ms034 ms033 ms032 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-17. user multiple input signature register 1 (umisr1) table 17-27. umisr1 field descriptions field description 0:31 ms063-032 : multiple input signature 063-032 (read/write) these bits represent the misr value obtained accumulati ng the bits 63-32 of all the pages read from the flash memory. the ms can be seeded to any value by writing the umisr1 register. address offset: 0x00050 reset value: 0x00000000 0123456789101112131415 ms095 ms094 ms093 ms092 ms091 ms090 ms089 ms088 ms087 ms086 ms085 ms084 ms083 ms082 ms081 ms080 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ms079 ms078 ms077 ms076 ms075 ms074 ms073 ms072 ms071 ms070 ms069 ms068 ms067 ms066 ms065 ms064 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-18. user multiple input signature register 2(umisr2)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-33 preliminary?subject to change without notice the umisr2 register is not accessible whenever mcr.done or ut0.aid ar e low: reading returns indeterminate data whil e writing has no effect. 17.2.6.21 user multiple input signature register 3 (umisr3) the multiple input signature register provide s a mean to evaluate the array integrity. the user multiple input signature register 3 represents the bits 127- 96 of the whole 144 bits word (2 double words including ecc). the umisr3 register is not accessible whenever mcr.done or ut0.aid ar e low: reading returns indeterminate data whil e writing has no effect. table 17-28. umisr2 field descriptions field description 0:31 ms095-064 : multiple input signature 095-064 (read/write) these bits represent the misr value obtained accumulati ng the bits 95-64 of all the pages read from the flash memory. the ms can be seeded to any value by writing the umisr2 register. address offset: 0x00054 reset value: 0x00000000 0123456789101112131415 ms127 ms126 ms125 ms124 ms123 ms122 ms121 ms120 ms119 ms118 ms117 ms116 ms115 ms114 ms113 ms112 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ms111 ms110 ms109 ms108 ms107 ms106 ms105 ms104 ms103 ms102 ms101 ms100 ms099 ms098 ms097 ms096 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-19. user multiple input signature register 3(umisr3) table 17-29. umisr3 field descriptions field description 0:31 ms127-096 : multiple input signature 127-096 (read/write) these bits represent the misr value obtained accumula ting the bits 127-96 of all the pages read from the flash memory. the ms can be seeded to any value by writing the umisr3 register.
pxd10 microcontroller reference manual, rev. 1 17-34 freescale semiconductor preliminary?subject to change without notice 17.2.6.22 user multiple input signature register 4 (umisr4) the multiple input signature register provide s a mean to evaluate the array integrity. the user multiple input signature register 4 represen ts the ecc bits of the whole 144 bits word (2 double words including ecc): bits 8-15 are ecc bits for the odd double word and bits 24-31 are the ecc bits for the even double word; bits 4-5 and 20-21 of misr are respectively the double and single ecc error detection for odd and even double word. the umisr4 register is not accessible whenever mcr.done or ut0.aid ar e low: reading returns indeterminate data whil e writing has no effect. 17.2.6.23 non-volatile private censorship password 0 register (nvpwd0) address offset: 0x00058 reset value: 0x00000000 0123456789101112131415 ms159 ms158 ms157 ms156 ms155 ms154 ms153 ms152 ms151 ms150 ms149 ms148 ms147 ms146 ms145 ms144 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ms143 ms142 ms141 ms140 ms139 ms138 ms137 ms136 ms135 ms134 ms133 ms132 ms131 ms130 ms129 ms128 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-20. user multiple input signature register 4(umisr4) table 17-30. umisr4 field descriptions field description 0:31 ms159-128 : multiple input signature 159-128 (read/write) these bits represent the misr value obtained accumulating: the 8 ecc bits for the even double word (on ms135-128); the single ecc error detection for even double word (on ms138); the double ecc error detection for even double word (on ms139); the 8 ecc bits for the odd double word (on ms151-144); the single ecc error detection for odd double word (on ms154); the double ecc error detection for odd double word (on ms155). the ms can be seeded to any value by writing the umisr4 register. address offset: 0x203dd8 reset value: 0xfeedface 0123456789101112131415 pwd31 pwd30 pwd29 pwd28 pwd27 pwd26 pwd25 pwd24 pwd23 pwd22 pwd21 pwd20 pwd19 pwd18 pwd17 pwd16 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 pwd15 pwd14 pwd13 pwd12 pwd11 pwd10 pwd09 pwd08 pwd07 pwd06 pwd05 pwd04 pwd03 pwd02 pwd01 pwd00 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x figure 17-21. non-volatile private censorship password 0 register (nvpwd0)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-35 preliminary?subject to change without notice the non-volatile private censorship password 0 regist er contains the 32 lsb of the password used to validate the censorship information contained in nvsci0-1 registers. 17.2.6.24 non-volatile private censorship password 1 register (nvpwd1) the non-volatile private censorship password 1 regi ster contains the 32 msb of the password used to validate the censorship information contained in nvsci0-1 registers. 17.2.6.25 non-volatile system censor ing information 0 register (nvsci0) the non-volatile system censoring in formation 0 register stores the 32 lsb of the censorship control word of the soc. table 17-31. nvpwd0 field descriptions field description 0:31 pwd31-00 : password 31-00 (read/write) the pwd31-00 registers represent the 32 ls b of the private censorship password. address offset: 0x203ddc reset value: 0xcafebeef 0123456789101112131415 pwd63 pwd62 pwd61 pwd60 pwd59 pwd58 pwd57 pwd56 pwd55 pwd54 pwd53 pwd52 pwd51 pwd50 pwd49 pwd48 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 pwd47 pwd46 pwd45 pwd44 pwd43 pwd42 pwd41 pwd40 p wd39 pwd38 pwd37 pwd36 pwd35 pwd34 pwd33 pwd32 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x figure 17-22. non-volatile private censorship password 1 register (nvpwd1) table 17-32. nvpwd1 field descriptions field description 0:31 pwd63-32 : password 63-32 (read/write) the pwd63-32 registers represent the 32 m sb of the private censorship password. address offset: 0x203de0 delivery value: 0x55aa55aa 0123456789101112131415 sc15 sc14 sc13 sc12 sc 11 sc10 sc9 sc8 sc7 sc6 sc5 sc4 sc3 sc2 sc1 sc0 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x figure 17-23. non-volatile system censoring information 0 register (nvsci0)
pxd10 microcontroller reference manual, rev. 1 17-36 freescale semiconductor preliminary?subject to change without notice the nvsci0 is a non-volatile register located in shadow sector: it is read during the reset phase of the flash module and the protection mech anisms are activated consequently. the parts are delivered uncensored to the user. 17.2.6.26 non-volatile system censor ing information 1 register (nvsci1) the non-volatile system censoring in formation 1 register stores the 32 msb of the censorship control word of the soc. the nvsci1 is a non-volatile register located in shadow sector: it is read during the reset phase of the flash module and the protection mech anisms are activated consequently. the parts are delivered uncensored to the user. table 17-33. nvsci0 field descriptions field description 0:15 sc15-0 : serial censorship control word 15-0 (read/write) these bits represent the 16 lsb of the se rial censorship control word (sccw). if sc15-0 = 0x55aa and nvsci1 = n vsci0 the public access is disabled. if sc15-0 != 0x55aa or nvsci1 != nvsci0 the public access is enabled. 16:31 cw15-0 : censorship control word 15-0 (read/write) these bits represent the 16 lsb of the censorship control word (ccw). if cw15-0 = 0x55aa and nvsci1 = nvsci0 the censored mode is disabled. if cw15-0 != 0x55aa or nvsci1 != nvsci0 the censored mode is enabled. address offset: 0x203de4 delivery value: 0x55aa55aa 0123456789101112131415 sc31 sc30 sc29 sc28 sc27 sc26 sc25 sc24 sc23 sc22 sc21 sc20 sc19 sc18 sc17 sc16 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x figure 17-24. non-volatile system censoring information 1 register (nvsci1) table 17-34. nvsci1 field descriptions field description 0:15 sc32-16 : serial censorship control word 32-16 (read/write) these bits represent the 16 msb of the serial censorship control word (sccw). if sc15-0 = 0x55aa and nvsci1 = n vsci0 the public access is disabled. if sc15-0 != 0x55aa or nvsci1 != nvsci0 the public access is enabled. 16:31 cw32-16 : censorship control word 32-16 (read/write) these bits represent the 16 msb of the censorship control word (ccw). if cw15-0 = 0x55aa and nvsci1 = nvsci0 the censored mode is disabled. if cw15-0 != 0x55aa or nvsci1 != nvsci0 the censored mode is enabled.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-37 preliminary?subject to change without notice 17.2.6.27 non-volatile user options register (nvusro) the non-volatile user options regi ster contains configuration info rmation for the user application. the nvusro register is a 64-bit regi ster, the 32 most significative bits of which (bits 63-32) are ?don?t care? and eventually used to manage ecc codes. the availability of this register is soc dependent. address offset: 0x203e18 delivery value: 0xxxxxxxxx 0123456789101112131415 uo31 uo30 uo29 uo28 uo27 uo26 uo25 uo24 uo23 uo22 uo21 uo20 uo19 uo18 uo17 uo16 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 uo15 uo14 uo13 uo12 uo11 uo10 uo09 uo08 uo07 uo06 uo05 uo04 uo03 pa d 3 v 5 v oscillator_margin watchdog_en rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x figure 17-25. non-volatile us er options register (nvusro) table 17-35. nvusro field descriptions field description 0:28 uo31-03 : user options 31-03 (read/write) the uo31-03 generic registers are reset bas ed on the information stored in nvusro. the use of this bus is soc specific. 2 pad3v5v 0: high voltage supply is 5.0 v 1: high voltage supply is 3.3 v default manufacturing value before flash initialization is '1' (3.3 v) which should ensure correct min slope for boundary scan. 1 oscillator_margin 0: low consumption conf iguration (4 mhz / 8 mhz) 1: high margin configuration (4/16 mhz) default manufacturing value before flash initialization is '1' 0 watchdog_en 0: disable after reset 1: enable after reset default manufacturing value before flash initialization is '1' . if the device undergoes a non-destructive reset, the behavior of swt after reset will again be controlled by this field. any change in the value of this field will take effect only after the device goes through a phase 0 (destructive reset sequence).
pxd10 microcontroller reference manual, rev. 1 17-38 freescale semiconductor preliminary?subject to change without notice 17.2.7 programming considerations 17.2.7.1 modify operation all the modify operations of the flash module are managed through the flash user registers interface. all the sectors of the flas h module belong to the same partition (b ank), therefore when a modify operation is active on some sectors no read access is possibl e on any other sector (r ead-while-modify is not supported). during a flash modify operation any attempt to read any flash location will output invalid data and bit rwe of mcr will be automa tically set. this means th at the flash module is not fetchable when a modify operation is active and these commands must be execu ted from another memory (internal ram or another flash module). if during a modify operation a reset occurs, the operation is suddenly term inated and the macrocell is reset to read mode. the data integrity of the flash section where the modify operation has been terminated is not guaranteed ? the interrupted flash modify operation must be repeated. in general each modify operation is started through a sequence of 3 steps: ? the first instruction is used to select the desired operation by set ting its corresponding selection bit in mcr (pgm or ers) or ut0 (mre or eie). ? the second step is the definiti on of the operands: the address and the data for programming or the sectors for erase or margin read. ? the third instruction is used to start the modi fy operation, by setting e hv in mcr or aie in ut0. once selected, but not yet started, one operation can be canceled by rese tting the operation selection bit. a summary of the available flash modify operations are shown in the following table 17-36 . once bit mcr.ehv (or ut0.aie) is se t, all the operands can no more be modified until bit mcr.done (or ut0.aid) is high. in general each modify operation is co mpleted through a sequence of four steps: 1. wait for operation completion: wait fo r bit mcr.done (or ut0.aid) to go high. 2. check operation result: check bit mcr.peg (o r compare umisr0-4 with expected value). 3. switch-off fpec by resetting mcr.ehv (or ut0.aie). 4. deselect current operation by clear ing mcr.pgm/ers (or ut0.mre/eie). table 17-36. flash modify operations operation select bit operands start bit double word program mcr.pgm address and data by interlock writes mcr.ehv sector erase mcr.ers lms, hbs mcr.ehv array integrity check none lms, hbs ut0.aie margin read ut0.mre ut0.mrv + lms, hbs ut0.aie ecc logic check ut0.eie ut0.dsi, ut1, ut2 ut0.aie
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-39 preliminary?subject to change without notice if the device embeds more than one flash macrocell and a modify op eration is on-going on one of them, then it is forbidden to start any other m odify operation on the other flash macrocells. in the following all the possible modify operations are described and some examples of the sequences needed to activate them are presented. 17.2.7.1.1 double word program a flash program sequence operates on any double word within the flash core. up to 2 words within the double word ma y be altered in a single program operation. whenever you program, ecc bits also get programmed (unless the selected address belongs to a sector in which the ecc has been disa bled in order to allow bit manipulation). ecc is handled on a 64-bit boundary. thus, if only one word in any given 64-bit ecc se gment is programmed, the adjoining word (in that segment) should not be pr ogrammed since ecc calculat ion has already completed for that 64-bit segment. attempts to program the adjoining word will probabl y result in an operation failure. it is recommended that all programming operations be of 64 bits. the prog ramming operation should co mpletely fill selected ecc segments within the double word. programming changes the value stored in an array b it from logic 1 to logic 0 only. programming cannot change a stored logic 0 to a logic 1. addresses in locked/disabled blocks cannot be programmed. the user may program the values in any or all of 2 words, of a double word, with a single program sequence. double word-bound words have addresses which differ only in address bit 2. the program operation consists of the following sequence of events: 1. change the value in the mcr.pgm bit from 0 to 1. 2. ensure the block that contains the address to be programmed is unlocked. write the first address to be pr ogrammed with the program data. the flash module latches address bits (22:3) at this time. the flash module latches data written as well. this write is referred to as a program data interl ock write. an interlock wr ite may be as large as 64 bits, and as small as 32 bits (depending on the cpu bus). 3. if more than 1 word is to be programmed, write the additional address in the double word with data to be programmed. this is re ferred to as a program data write. the flash modules ignores address bits (22:3) for program data writes. the eventual unwritten data word default to 0xffffffff. 4. write a logic 1 to the mcr.ehv bit to start the internal program sequence or skip to step 9 to terminate. 5. wait until the mcr.done bit goes high. 6. confirm mcr.peg=1. 7. write a logic 0 to the mcr.ehv bit. 8. if more addresses are to be programmed, return to step 2.
pxd10 microcontroller reference manual, rev. 1 17-40 freescale semiconductor preliminary?subject to change without notice 9. write a logic 0 to the mcr.pgm bi t to terminate the program operation. program may be initiated with the 0 to 1 transition of the mcr.pgm bi t or by clearing the mcr.ehv bit at the end of a previous program. the first write after a progr am is initiated determines the page address to be programmed. this first write is referred to as an interlock write. the interlock wr ite determines if the shadow , test or norma l array space will be programmed by causing mcr.peas to be set/cleared. an interlock write must be performed before se tting mcr.ehv. the user may terminate a program sequence by clearing mcr.pgm prior to setting mcr.ehv. after the interlock write, additiona l writes only affect the data to be programmed at the word location determined by address bit 2. unwritten locations defaul t to a data value of 0xf fffffff. if multiple writes are done to the same location the data fo r the last write is used in programming. while mcr.done is low and mcr.e hv is high, the user may clear ehv, resulting in a program abort. a program abort forces the module to step 8 of the program sequence. an aborted program will result in mcr.peg bei ng set low, indicating a fa iled operation. mcr.done must be checked to know when the aborting command has completed. the data space being operated on befo re the abort will cont ain indeterminate data. this may be recovered by repeating the same program instruction or executing an erase of the affected blocks. example 17-1. double word program of data 0x55aa55aa at address 0x00aaa8 and data 0xaa55aa55 at address 0x00aaac. mcr = 0x00000010; /* set pgm in mcr: select operation */ (0x00aaa8) = 0x55aa55aa; /* latch address and 32 lsb data */ (0x00aaac) = 0xaa55aa55; /* latch 32 msb data */ mcr = 0x00000011; /* set ehv in mcr: operation start */ do /* loop to wait for done=1 */ { tmp = mcr; /* read mcr */ } while ( !(tmp & 0x00000400) ); status = mcr & 0x00000200; /* check peg flag */ mcr = 0x00000010; /* reset ehv in mcr: operation end */ mcr = 0x00000000; /* reset pgm in mcr: deselect operation */ 17.2.7.1.2 sector erase erase changes the value stored in all bits of the selected block(s) to logic 1. an erase sequence operates on any combination of blocks (sectors) in the low, mid or high address space, or the shadow block (if available) . the test block cannot be erased. the erase sequence is fully automated within the flash. the user only needs to select the blocks to be erased and initiate the erase sequence. locked/disabled blocks cannot be erased. if multiple blocks are selected fo r erase during an erase sequence, no specific operation order must be assumed.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-41 preliminary?subject to change without notice the erase operation cons ists of the following sequence of events: 1. change the value in the mcr.ers bit from 0 to 1. 2. select the block(s) to be erased by writing ?1 ?s to the appropriate re gister(s) in lms or hbs registers. if the shadow block is to be erased, this step may be ski pped, and lms and hbs are ignored. note that lock and select are i ndependent. if a block is selected and locked, no erase will occur. 3. write to any address in flash. this is referred to as an erase interlock write. 4. write a logic 1 to the mcr.ehv bit to start the internal erase sequence or skip to step 9 to terminate. 5. wait until the mcr.done bit goes high. 6. confirm mcr.peg=1. 7. write a logic 0 to the mcr.ehv bit. 8. if more blocks are to be erased, return to step 2. 9. write a logic 0 to the mcr.ers bi t to terminate the erase operation. after setting mcr.ers, one write, refe rred to as an interlock write, must be performed before mcr.ehv can be set to 1. data words written during erase sequence interlock writes are ignored. the user may terminate the erase seque nce by clearing ers before setting ehv. an erase operation may be aborted by clearing mc r.ehv assuming mcr.done is low, mcr.ehv is high and mcr.esus is low. an erase abort forces the module to step 8 of the erase sequence. an aborted erase will result in mcr.peg being set low, indicati ng a failed operation. mcr.done must be checked to know when the aborting command has completed. the block(s) being operated on before the abort cont ain indeterminate data. th is may be recovered by executing an erase on the affected blocks. the user may not abort an erase sequence while in erase suspend. example 17-2. erase of sectors b0f1 and b0f2. mcr = 0x00000004; /* set ers in mcr: select operation */ lms = 0x00000006; /* set lsl2-1 in lms: select sectors to erase */ (0x000000) = 0xffffffff; /* latch a flash address with any data */ mcr = 0x00000005; /* set ehv in mcr: operation start */ do /* loop to wait for done=1 */ { tmp = mcr; /* read mcr */ } while ( !(tmp & 0x00000400) ); status = mcr & 0x00000200; /* check peg flag */ mcr = 0x00000004; /* reset ehv in mcr: operation end */ mcr = 0x00000000; /* reset ers in mcr: deselect operation */
pxd10 microcontroller reference manual, rev. 1 17-42 freescale semiconductor preliminary?subject to change without notice erase suspend/resume the erase sequence may be suspended to allow read access to the flash core. it is not possible to program or to erase during an erase suspend. during erase suspend, all reads to blocks targ eted for erase return indeterminate data. an erase suspend can be initiated by changing the va lue of the mcr.esus bit from 0 to 1. mcr.esus can be set to 1 at any time wh en mcr.ers and mcr.ehv are high and mcr.pgm is low. a 0 to 1 transition of mcr.esus causes th e module to start the sequence whic h places it in erase suspend. the user must wait until mcr.done=1 before the module is suspe nded and further actions are attempted. mcr.done will go high no more than t esus after mcr.esus is set to 1. once suspended, the array may be read. flash core reads while mcr.esus=1 from the block(s) being erased return indeterminate data. example 17-3. sector erase suspend mcr = 0x00000007; /* set esus in mcr: erase suspend */ do /* loop to wait for done=1 */ { tmp = mcr; /* read mcr */ } while ( !(tmp & 0x00000400) ); notice that there is no need to clear mcr.ehv and mcr.ers in order to perf orm reads du ring erase suspend. the erase sequence is resumed by writing a logic 0 to mcr.esus. mcr.ehv must be set to 1 before mcr.esus can be cleared to resume the operation. the module continues the erase sequence from one of a se t of predefined points. this may extend the time required for the erase operation. example 17-4. sector erase resume mcr = 0x00000005; /* reset esus in mcr: erase resume */ 17.2.7.1.3 user test mode user test mode is a mode, that customers can put th e flash module in, to do specific tests to check the integrity of the flash module. three kinds of test can be performed: ? array integrity self check ? margin mode read ? ecc logic check the user test mode is equivalent to a modify opera tion: read accesses attempted by the user during user test mode generates a read-while -write error (rwe of mcr set). it is not allowed to perform user test operations on the test and shadow blocks.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-43 preliminary?subject to change without notice array integrity self check array integrity is checked using a predefined address sequence (pr oprietary), and this operation is executed on selected and unlocked bloc ks. once the operation is completed, the results of the reads can be checked by reading the misr value (stored in umisr0 -4), to determine if an incorrect read, or ecc detection was noted. the internal misr calculator is a 32-bit register. the 128-bit data, the 16 ecc data and the single and double ecc errors of the two double words are therefore captured by the misr through 5 diff erent read accesses at the same location. the whole check is done through five comple te scans of the memory address space: 1. the first pass will scan only bits 31-0 of each page. 2. the second pass will scan only bits 63-32 of each page. 3. the third pass will scan only bits 95-64 of each page. 4. the fourth pass will scan only bits 127-96 of each page. 5. the fifth pass will scan only the ecc bits (8 + 8) and the single and double ecc errors (2 + 2) of both double words of each page. the 128-bit data and the 16 ecc data are sampled be fore the eventual ecc correction, while the single and double error flags are samp led after the ecc evaluation. only data from existing and unlocke d locations are captured by the misr. the misr can be seeded to any value by writing the umisr0-4 registers. the array integrity self check consists of the following sequence of events: 1. set ute in ut0 by writing the related password in ut0. 2. select the block(s) to be checked by writing ?1?s to the appropriate register(s) in lms or hbs registers. note that lock and select are independent. if a block is select ed and locked, no array integrity check will occur. 3. set eventually ut0.ais bit for a sequential addressing only. 4. write a logic 1 to the ut0.aie bit to start the array integrity check. 5. wait until the ut0.aid bit goes high. 6. compare umisr0-4 content with the expected result. 7. write a logic 0 to the ut0.aie bit. 8. if more blocks are to be checked, return to step 2. it is recommended to leave ut0.ais at 0 and use th e proprietary address sequence that checks the read path more fully, although this sequence takes more time. during the execution of the array inte grity check operation it is forbidde n to modify the content of block select (lms, hbs) and lock (lml, sll, hbl) regi sters, otherwise the misr value can vary in an unpredictable way.
pxd10 microcontroller reference manual, rev. 1 17-44 freescale semiconductor preliminary?subject to change without notice while ut0.aid is low and ut0.aie is high, the user may clear aie, resulting in a array integrity check abort. ut0.aid must be checked to know when the aborting command has completed. example 17-5. array integrity check of sectors b0f1 and b0f2. ut0 = 0xf9f99999; /* set ute in ut0: enable user test */ lms = 0x00000006; /* set lsl2-1 in lms: select sectors */ ut0 = 0x80000002; /* set aie in ut0: operation start */ do /* loop to wait for aid=1 */ { tmp = ut0; /* read ut0 */ } while ( !(tmp & 0x00000001) ); data0 = umisr0; /* read umisr0 content*/ data1 = umisr1; /* read umisr1 content*/ data2 = umisr2; /* read umisr2 content*/ data3 = umisr3; /* read umisr3 content*/ data4 = umisr4; /* read umisr4 content*/ ut0 = 0x00000000; /* reset ute and aie in ut0: operation end */ margin read margin read procedure (either margin 0 or margin 1), can be run on unlocked blocks in order to unbalance the sense amplifiers, respect to standard read conditi ons, so that all the read accesses reduce the margin vs ?0? (ut0.mrv = ?0?) or vs ?1 ? (ut0.mrv = ?1?). locked sectors are ignored by misr calculation and ecc flagging. the results of the margin reads can be checked comparing checksum value in umisr0-4. since margin reads are done at voltages that differ th an the normal read voltage, lifetime expectancy of the flash macrocell is impacted by the execution of margin reads. doing margin reads repetitively results in degradati on of the flash array, and shorten expected lifetime experienced at normal read levels. for these reasons the margin read usage is allowed only in factory, while it is forbidden to use it inside the user application. in any case the charge losses detected through the marg in mode cannot be considered failures of the device and no failure analysis will be opened on them. the margin read setup operation consists of the following sequence of events: 1. set ute in ut0 by writing the related password in ut0. 2. select the block(s) to be checked by writing 1? s to the appropriate register(s) in lms or hbs registers. note that lock and select are independent. if a block is select ed and locked, no array integrity check will occur. 3. set eventually ut0.ais bit for a sequential addressing only. 4. change the value in the ut0.mre bit from 0 to 1. 5. select the margin level: ut0.mrv=0 fo r 0?s margin, ut0.mrv=1 for 1?s margin. 6. write a logic 1 to the ut0.aie bit to start the ma rgin read setup or skip to step 6 to terminate. 7. wait until the ut0.aid bit goes high.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-45 preliminary?subject to change without notice 8. compare umisr0-4 content with the expected result. 9. write a logic 0 to the ut0.a ie, ut0.mre and ut0.mrv bits. 10. if more blocks are to be checked, return to step 2. it is recommended to leave ut0.ais at 1 and use the linear address sequence that takes less time. during the execution of the margin m ode operation it is forbidden to m odify the content of block select (lms, hbs) and lock (lml, sll, hbl) register s, otherwise the misr value can vary in an unpredictable way. the read accesses will be done with the addition of a proper number of wait states to guarantee the correctness of the result. while ut0.aid is low and ut0.aie is high, the user may clear aie, re sulting in a array integrity check abort. ut0.aid must be checked to know when the aborting command has completed. example 17-6. margin read check versus ?1?s ut0 = 0xf9f99999; /* set ute in ut0: enable user test */ lms = 0x00000006; /* set lsl2-1 in lms: select sectors */ ut0 = 0x80000004; /* set ais in ut0: select operation */ ut0 = 0x80000024; /* set mre in ut0: select operation */ ut0 = 0x80000034; /* set mrv in ut0: select margin versus 1?s */ ut0 = 0x80000036; /* set aie in ut0: operation start */ do /* loop to wait for aid=1 */ { tmp = ut0; /* read ut0 */ } while ( !(tmp & 0x00000001) ); data0 = umisr0; /* read umisr0 content*/ data1 = umisr1; /* read umisr1 content*/ data2 = umisr2; /* read umisr2 content*/ data3 = umisr3; /* read umisr3 content*/ data4 = umisr4; /* read umisr4 content*/ ut0 = 0x80000034; /* reset aie in ut0: operation end */ ut0 = 0x00000000; /* reset ute, mre, mrv, ais in ut0: deselect op. */ ecc logic check ecc logic can be checked by forcing the input of ecc logic: the 64 bits of data and the 8 bits of ecc syndrome can be individually forced and they will drive simultane ously at the same value the ecc logic of the whole page (2 double words). the results of the ecc logic check can be verified by reading the misr value. the ecc logic check operatio n consists of the following sequence of events: 1. set ute in ut0 by writing the related password in ut0. 2. write in ut1.dai31-0 and ut2.dai63-32 the double word input value. 3. write in ut0.dsi7-0 the syndrome input value. 4. select the ecc logic check: wr ite a logic 1 to the ut0.eie bit.
pxd10 microcontroller reference manual, rev. 1 17-46 freescale semiconductor preliminary?subject to change without notice 5. write a logic 1 to the ut0.aie bit to start the ecc logic check. 6. wait until the ut0.aid bit goes high. 7. compare umisr0-4 content with the expected result. 8. write a logic 0 to the ut0.aie bit. notice that when ut0.aid is low umisr0-4, ut1-2 an d bits mre, mrv, eie, ais and dsi7-0 of ut0 are not accessible: reading returns undete rminate data and write has no effect. example 17-7. ecc logic check ut0 = 0xf9f99999; /* set ute in ut0: enable user test */ ut1 = 0x55555555; /* set dai31-0 in ut1: even word input data */ ut2 = 0xaaaaaaaa; /* set dai63-32 in ut2: odd word input data */ ut0 = 0x80ff0000; /* set dsi7-0 in ut0: syndrome input data */ ut0 = 0x80ff0008; /* set eie in ut0: select ecc logic check */ ut0 = 0x80ff000a; /* set aie in ut0: operation start */ do /* loop to wait for aid=1 */ { tmp = ut0; /* read ut0 */ } while ( !(tmp & 0x00000001) ); data0 = umisr0; /* read umisr0 content (expected 0x55555555) */ data1 = umisr1; /* read umisr1 content (expected 0xaaaaaaaa) */ data2 = umisr2; /* read umisr2 content (expected 0x55555555) */ data3 = umisr3; /* read umisr3 content (expected 0xaaaaaaaa) */ data4 = umisr4; /* read umisr4 content (expected 0x00ff00ff) */ ut0 = 0x00000000; /* reset ute, aie and eie in ut0: operation end */ 17.2.7.2 error correction code the flash macrocell provides a method to improve the reli ability of the data stored in flash: the usage of an error correction code. the wo rd size is fixed of 64 bits. at each double word of 64 bits there are associated 8 ecc bits that are progr ammed in such a way to guarantee a single error co rrection and a double erro r detection (sec-ded). 17.2.7.2.1 ecc algorithms the flash macrocell supports one ecc algorithm: ?all ?1?s no erro r?. a modified hamming code is used that ensures the all erased state (i.e . 0xffff.....ffff) data is a valid state, and will not cause an ecc error. this allows the user to perform a bla nk check after a sector erase operation. 17.2.7.3 protection strategy two kind of protections are availabl e: modify protection to avoid unwan ted program/erase in flash sectors and censored mode to avoid piracy. 17.2.7.3.1 modify protection the flash modify protection information is stored in non-volatile flash cells located in the test flash. this information is read once during the fl ash initialization phase following th e exit from reset and is stored in volatile registers th at act as actuators. the reset state of all the volatile modify protection registers is the protected state.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-47 preliminary?subject to change without notice all the non-volatile modify prot ection registers can be program med through a normal double word program operation at the relate d locations in test flash. the non-volatile modify protecti on registers cannot be erased. ? the non-volatile modify protection registers are phys ically located in test flash their bits can be programmed to ?0? only once and they can no more be restored to ?1?. ? the volatile modify protection re gisters are read/write registers wh ich bits can be written at ?0? or ?1? by the user application. a software mechanism is provided to independently lock/unlock each low, mid and high address space block against program and erase. software locking is done through th e lml (low/mid address space bloc k lock register) or hbl (high address space block lock register) registers. an alternate means to enable software locking for blocks of low address sp ace only is through the sll (secondary low/mid address space block lock register). all these registers have a non-volatile image stored in test flash (nvlml, nvhbl, nvsll), so that the locking information is kept on reset. on delivery the test flash non-volatile image is at all ?1?s, meaning all sectors are locked. by programming the non-volatile lo cations in test flash the sele cted sectors can be unlocked. being the test flash one time programmable (i.e. not erasable), once unlocked the sectors cannot be locked again. of course, on the contrary, all the vol atile registers can be written at 0 or 1 at any time, therefore the user application can lock and unlock sectors when desired. 17.2.7.3.2 censored mode the censored mode information is st ored in non-volatile flash cells lo cated in the shadow sector. this information is read once during the fl ash initialization phase following th e exit from reset and is stored in volatile registers that act as actuators. the reset state of all the volatile censored mode registers is the protected state. all the non-volatile censored mode registers can be programmed th rough a normal double word program operation at the related locations in the shadow sector. the non-volatile censored mode registers can be erased by erasing the shadow sector. ? the non-volatile censored mode registers are physically located in the shadow sector their bits can be programmed to ?0? and eventually rest ored to ?1? by erasing the shadow sector. ? the volatile censored mode registers are re gisters not accessible by the user application. the flash macrocell provides two leve ls of protection against piracy: ? if bits cw15-0 of nvsci0 are programmed at 0x55aa and nvsc1 = nvsci0 the censored mode is disabled, while al l the other possible values enable the censored mode.
pxd10 microcontroller reference manual, rev. 1 17-48 freescale semiconductor preliminary?subject to change without notice ? if bits sc15-0 of nvsci0 ar e programmed at 0x55aa and nvsc1 = nvsci0 the p ublic access is disabled, while all the other possi ble values enable the public access. the parts are delivered to the user with censored mode and public access disabled. the flash ecc algorithm allows to modify the censors hip status without erasi ng the shadow sector, as shown in table 17-37 . 17.3 data flash memory 17.3.1 introduction the primary function of the data flash module is to serve as electrically pr ogrammable and erasable non-volatile memory. non-volatile memory may be used for instruction and/or data storage. the module is a non-volatile solid-stat e silicon memory device consisting of blocks (called also sectors) of single transistor storage elements, an electric al means for selectively adding (programming) and removing (erasing) charge from these elements, and a means of selectively sensing (reading) the charge stored in these elements. the data flash module is arranged as two functiona l units: the flash core and the memory interface. the flash core is composed of arrayed non-volatile storage elements , sense amplifiers, row decoders, column decoders and charge pumps. the arrayed storage elements in th e flash core are subdivided into physically separate units referred to as blocks (or sectors). the memory interface contains the registers and logi c which control the operati on of the flash core. the memory interface is also the interface between the flash module and a bus interface unit (biu) and contains the ecc logic and redundancy logic. a biu connects the flash module to a system bus, and contains all sy stem level customization required for the soc application. table 17-37. bit manipulation: censorship management censored mode public access nvsci0 nvsci1 enabled enabled 0xffff_ffff 0xffff_ffff disabled enabled 0xfff f_55aa 0xffff_55aa enabled disabled 0x55aa_ffff 0x55aa_ffff disabled disabled 0x55aa_55aa 0x55aa_55aa enabled disabled 0x55aa_0000 0x55aa_0000 disabled enabled 0x0000_55aa 0x0000_55aa enabled enabled 0x0000_0000 0x0000_0000
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-49 preliminary?subject to change without notice 17.3.2 main features ? high read parallelism (128 bits) ? error correction code (sec-ded ) to enhance data retention ? double word program (64 bits) ? sector erase ? single bank: read-while-modify not available ? erase suspend available (pr ogram suspend not available) ? software programmable program/erase pr otection to avoid unwanted writings ? censored mode against piracy ? not usable as main code memory ? shadow sector not available ? "otp" area in test flash block 17.3.3 block diagram the flash macrocell contai ns one matrix module, composed by a single bank: bank 0, normally used for code storage. no read-while -modify operations are possible. the modify operations are managed by an embedded flash program/erase cont roller (fpec). commands to the fpec are given through a user registers interface. the read data bus is 128 bits wi de, while the flash registers are on a separate bus 32 bits wide. the high voltages needed for program/erase operations ar e internally generated addressed in user memory map. figure 17-26. flash macrocell structure 64 kb + 16kb test flash hv generator flash controller flash matrix registers program/erase registers interface flash bank 0 interface
pxd10 microcontroller reference manual, rev. 1 17-50 freescale semiconductor preliminary?subject to change without notice 17.3.4 functional description 17.3.4.1 macrocell structure the flash module is addressable by word (32 bits) or doubl e word (64 bits) for program, and page (128 bits) for read. reads done to the fl ash always return 128 bits, although read page buffering may be done in the platform biu. each read of the flash module retr ieves a page, or four consecutive words (128 bits) of information. the address for each word retrieved within a page differ from the other a ddresses in the page only by address bits (3:2). the flash module supports fault tole rance through error correction code (ecc) and/or error detection. the ecc implemented within the fl ash module will correct single bi t failures and detect double bit failures. the flash module uses an embedde d hardware algorithm implemented in the memory interface to program and erase the flash core. control logic that works with the software block enab les, and software lock mechanisms, is included in the embedded hardware algorithm to gua rd against accident al program/erase. the hardware algorithm perform the steps necessary to ensure that th e storage elements are programmed and erased with sufficient margin to guarantee data integr ity and reliability. a programmed bit in the flash module reads as logic level 0 (or low). an erased bit in the flash module reads as logic level 1 (or high). program and erase of the flas h module requires multi ple system clock cycles to complete. the erase sequence may be suspended. the program and erase sequences may be aborted. 17.3.4.2 flash modul e sectorization the data flash module suppor ts 64 kb of user memory, plus 16 kb of test me mory (a portion of which is one-time programmable by the user). the flash module is composed by a single bank (bank 0): read-while-modify is not supported. bank 0 of the 80 kb flash macrocell is divided in four sectors. bank 0 contains also a reserved sector named test flash in which some one ti me programmable user data are stored. the sectorization of the 80 kb matrix module is shown in table 17-38 . table 17-38. 80 kb flash module sectorization bank sector addresses size address space b1 b1f0 0x00800000 to 0x00803fff 16 kb low address space b1 b1f1 0x00804000 to 0x00807fff 16 kb low address space
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-51 preliminary?subject to change without notice the flash module is divided into blocks also to implement independent er ase/program protection. a software mechanism is provided to independently lo ck/unlock each block in low, mid and high address space against program and erase. 17.3.4.2.1 test flash block the test flash block exists outside the normal addr ess space and is programme d and read independently of the other blocks. the independent test flash block is included also to support systems which require non-volatile memory for security and/or to store system initialization information. a section of the test flash is reserved to store the non-volatile information related to redundancy, configuration and protection. the ecc is applied also to test flash. the usage of reserved test flash sect or is detailed in the following table. when the test space is enabled, all the operations are mapped to the test block. user mode program of the test bl ock are enabled only when mcr.peas is high, also if the shadow block is available. the test flash block may be locked/unlocked agai nst program by using the lml.tslk and sll.stslk registers. erase of test flash bloc k is always locked in user mode. program of the test flash bl ock has similar restri ction as the array in terms of how ecc is calculated. only one program is allowed per 64-bit ecc segment. b1 b1f2 0x00808000 to 0x0080bfff 16 kb low address space b1 b1f3 0x0080c000 to 0x0080ffff 16 kb low address space b1 reserved 0x00810000 to 0x00bfffff reserved b1 b1tf 0x00c00000 to 0x00c03fff 16 kb test address space table 17-39. test flash structure name description addresses size user otp area 0x400000 to 0x401fff 8192 byte reserved 0x402000 to 0x403cff 7424 byte user reserved 0x403d00 to 0x403de7 232 byte nvlml non-volatile low/mid address space block locking register 0x403de8 to 0x403def 8 byte nvhbl non-volatile high address space block locking register 0x403df0 to 0x403df7 8 byte nvsll non-volatile secondary low/mid add space block lock register 0x403df8 to 0x403dff 8 byte user reserved 0x403e00 to 0x403eff 256 byte reserved 0x403f00 to 0x403fff 256 byte table 17-38. 80 kb flash module sectorization (continued) bank sector addresses size address space
pxd10 microcontroller reference manual, rev. 1 17-52 freescale semiconductor preliminary?subject to change without notice the first 8 kb of test flash block may be used for user defined functions (po ssibly to store boot code, other configuration words or factory process codes). locations of th e test flash block marked as reserved cannot be programmed by the user application. 17.3.5 user mode operation in user mode the flash module may be read and written (register writes and interlock writes), programmed or erased. the default state of the flash module is read. the main and test address space can be read only in the read state. the flash registers are always avai lable for read, also when the modul e is in power-down mode (except few documented registers). the flash module enters th e read state on reset. the module is in the read stat e under two sets of conditions: ? the read state is active when the module is enabled (user mode read) ? the read state is active when mcr.ers and mcr.esus are high and mcr.pgm is low (erase suspend). notice that no read-while-modify is available. flash core reads return 128 bits (1 page = 2 double words). registers reads return 32 bits (1 word). flash core reads are done through the bus interface unit. registers reads to unmapped register address space will return all ?0?s. registers writes to unmapped register address space will have no effect. array reads attempted to invalid locations will result in indeterminate data. i nvalid locations occur when addressing is done to blocks that do not exist in non 2 n array sizes. interlock writes attempted to invali d locations, will result in an in terlock occurring, but attempts to program these blocks will not occur since they are for ced to be locked. erase will occur to selected and unlocked blocks even if the interloc k write is to an invalid location. simultaneous read cycle on the fl ash matrix and read/write cycl es on the registers are possible . on the contrary registers read/write acce sses simultaneous to a flash matr ix interlock write are forbidden. 17.3.5.1 reset a reset is the highest priority operation for the flash module and terminates all other operations. the flash module uses reset to init ialize register and status bits to their default reset values. if the flash module is executing a program or eras e operation (mcr.pgm = 1 or mcr.ers = 1) and a reset is issued, the operation will be terminated and the module will di sable the high voltage logic without
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-53 preliminary?subject to change without notice damage to the high vo ltage circuits. reset terminat es all operations and forces the flash module into user mode ready to receive accesses. reset and power-off must not be used systematically to terminate a program or erase operation. after reset is negated, read register access may be done , although it should be noted that registers that require updating from shadow info rmation, or other inputs, may not read updated values until mcr.done transitions. mcr.done may be polled to determine if the flash module has transitioned out of reset. notice that the registers cannot be written until mcr.done is high. 17.3.5.2 power-down mode the power-down mode turns off all flash memory dc current sources, so that power dissipation is due only to leakage. in power-down mode no reads from or write to the module are possible. the user may not read some regist ers (umisr0-4, ut1-2 and part of ut0) until the disable mode is exited. on the contrary write access is locked on all the registers in power-down mode. when enabled the flash module returns to its previous state in all cases unless in the process of executing an erase high voltage operation at th e time of entering power-down mode. if the flash memory module enters power-down mode during an eras e operation, the mcr[esus] bit is set. the user may resume the erase operation when the module exits power-down mode by clearing the mcr[esus] bit. mcr[ehv] must be high to resume the erase operation. if the flash memory module is configured to en ter power-down mode duri ng a program operation, the operation will be completed and th e power-down mode will be ente red only after the programming ends. if the flash memory module is put in power-down m ode and the vector table re mains mapped in the flash address space, the user must take care that the flash macrocell wi ll strongly increase the interrupt response time by adding several wait states. it is forbidden to enter low power mode when the power-down mode is active. 17.3.5.3 low power mode the low power mode turns off most of the dc current sources within the flash memory module. the module (flash core and registers) is not accessibl e for read or write after it enters low power mode. the wake-up time from low power mode is faster than the wake-up time from power-down mode. the user may not read some regist ers (umisr0-4, ut1-2 and part of ut 0) until the low power mode is exited. write access is locked on all the registers in low power mode. when exiting from low powe r mode the flash memory module returns to its previous state in all cases unless it was in the process of execu ting an erase high voltage operation at the time of entering low power mode.
pxd10 microcontroller reference manual, rev. 1 17-54 freescale semiconductor preliminary?subject to change without notice if the flash memory module enters low power mode during an erase ope ration, the mcr[esus] bit is set. the user may resume the erase operation when th e module exits low power mode by clearing the mcr[esus] bit. the mcr[ehv] bit must be high to resume the erase operation. if the flash memory module is configured to en ter low power mode during a program operation, the operation will be completed and the low power mode will be entered only after the programming ends. it is forbidden to enter power-down mode when the low power mode is active. 17.3.6 register description the flash user registers mapping is shown in the following table. in the following some non-volatile registers are describe d. please notice that such entities are not flip-flops, but locations of test fl ash sector with a special meaning. during the flash initialization phase, the fpec reads these non-volatile registers and update their related volatile registers. when the fpec detects ecc double errors in these sp ecial locations, it behaves in the following way: ? in case of a failing system locations (confi gurations, device options , redundancy, embalgo firmware), the initialization phase is in terrupted and a fatal error is flagged. ? in case of failing user locations (protections, censorship, biu, ...), the volatile registers are filled with all ?1?s and the flash initializat ion ends setting low the peg bit of mcr. table 17-40. flash 528 kb single bank registers register name address offset location module configuration register (mcr) 0x00 on page 55 low/mid address space block locking register (lml) 0x04 on page 59 high address space block locking register (hbl) 0x08 on page 61 secondary low/mid address space block lock register (sll) 0x0c on page 62 low/mid address space block select register (lms) 0x10 on page 65 high address space block select register (hbs) 0x14 on page 66 address register (adr) 0x18 on page 67 reserved 0x1c?0x3b ? user test register 0 (ut0) 0x3c on page 68 user test register 1 (ut1) 0x40 on page 70 user test register 2 (ut2) 0x44 on page 71 user multiple input signature register 0 (umisr0) 0x48 on page 72 user multiple input signature register 1 (umisr1) 0x4c on page 72 user multiple input signature register 2 (umisr2) 0x50 on page 73 user multiple input signature register 3 (umisr3) 0x54 on page 74 user multiple input signature register 4 (umisr4) 0x58 on page 74
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-55 preliminary?subject to change without notice in this section, the follow ing abbreviations are used 17.3.6.1 module configur ation register (mcr) the module configuration regi ster is used to enable and monitor al l the modify operations of the flash module. table 17-41. abbreviations case abbreviation description read/write rw the software can read and write to these bits. read/clear rc the software can read and clear to these bits. read-only r the software can only read these bits. write-only w the software should only write to these bits. address offset: 0x0000 reset value: 0x06600600 0123456789101112131415 edc 0 0 0 0 size2 size1 size0 0 las2 las1 las0 0 0 0 mas rc/0 r/0 r/0 r/0 r/0 r/1 r/1 r/0 r/0 r/1 r/1 r/0 r/0 r/0 r/0 r/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 eer rwe 0 0 peas done peg 0 0 0 0 pgm psus ers esus ehv rc/0 rc/0 r/0 r/0 r/0 r/1 r/1 r/0 r/0 r/0 r/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-27. module config uration register (mcr) table 17-42. mcr field descriptions field description 0 edc: ecc data correction (read/clear) edc provides information on previous reads. if a e cc single error detection and correction occurred, the edc bit will be set to 1. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to 1 by the user. in the event of a ecc double error detection, this bit will not be set. if edc is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of edc) were not corrected through ecc. since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. a write of 0 will have no effect. the function of this bit is soc dependent and it can be configured to be disabled. 0: reads are occurring normally. 1: an ecc single error occurred and was corrected during a previous read. 1:4 reserved (read only) write these bits has no effect and read these bits always outputs 0. 5:7 size2-0: array space size 2-0 (read only) 110 64 kb array space size 8 reserved (read only). write this bit has no effect and read this bit always outputs 0.
pxd10 microcontroller reference manual, rev. 1 17-56 freescale semiconductor preliminary?subject to change without notice 9:11 las2-0: low address space 2-0 (read only) 010 low address space sectorization is 32 kb + 2 ? 16 kb + 2 ? 32 kb + 128 kb 12:14 reserved (read only) write these bits has no effect and read these bits always outputs 0. 15 mas: mid address space (read only) 0 no mid address space 16 eer: ecc event error (read/clear) eer provides information on previous reads. if a ecc double error detection occurred, the eer bit will be set to 1. this bit must then be cleared, or a reset must occur bef ore this bit will return to a 0 state. this bit may not be set to 1 by the user. in the event of a ecc single error detection and correction, this bit will not be set. if eer is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of eer) were correct. since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. a write of 0 will have no effect. 0: reads are occurring normally. 1: an ecc double error occurred during a previous read. 17 rwe: read-while-write event error (read/clear) rwe provides information on previous reads when a modify operation is on going. if a rww error occurs, the rwe bit will be set to 1. read-while-write erro r means that a read access to the flash matrix has occurred while the fpec was performing a program or erase operation or an array integrity check. this bit must then be cleared, or a reset must occur bef ore this bit will return to a 0 state. this bit may not be set to 1 by the user. if rwe is not set, or remains 0, th is indicates that all previous rww reads (from the last reset, or clearing of rwe) were correct. since this bit is an error flag, it must be cleared to 0 by writing 1 to the register location. a write of 0 will have no effect. 0: reads are occurring normally. 1: a rww error occurred during a previous read. 18:19 reserved (read only) write these bits has no effect and read these bits always outputs 0. 20 peas: program/erase access space (read only) peas is used to indicate which space is valid for program and erase operati ons: main array space or shadow/test space. peas=0 indicates that the main address space is active for all flash module program and erase operations. peas=1 indicates that the test or shadow add ress space is active for program and erase. the value in peas is captured and he ld with the first interlock write do ne for modify operations. the value of peas is retained between sampling events (i.e. subsequent firs t interlock writes). 0: shadow/test address space is disabled for program/erase and main address space enabled. 1: shadow/test address space is enabled for pr ogram/erase and main address space disabled. table 17-42. mcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-57 preliminary?subject to change without notice 21 done: modify operation done (read only) done indicates if the flash module is performing a high voltage operation. done is set to 1 on termination of the flash module reset. done is cleared to 0 just after a 0 to 1 transition of ehv, which initiates a high voltage operation, or after resuming a suspended operation. done is set to 1 at the end of prog ram and erase high voltage sequences. done is set to 1 (within t pabt or t eabt , equal to p/e abort latency) after a 1 to 0 transition of ehv, which aborts a high voltage program/erase operation. done is set to 1 (within t esus , time equals to erase suspend latency) after a 0 to 1 transition of esus, which suspends an erase operation. 0 flash is executing a high voltage operation. 1 flash is not executing a high voltage operation. 22 peg: program/erase good (read only) the peg bit indicates the completion status of the last flash program or erase sequence for which high voltage operations were initiated. the value of peg is updated automatically during the program and erase high voltage operations. aborting a program/erase high voltage operation wil l cause peg to be cleared to 0, indicating the sequence failed. peg is set to 1 when the flash mo dule is reset, unless a flash initialization error has been detected. the value of peg is valid only when pgm=1 and/or ers=1 and after done transitions from 0 to 1 due to an abort or the completion of a program/erase ope ration. peg is valid until pgm/ers makes a 1 to 0 transition or ehv makes a 0 to 1 transition. the value in peg is not valid after a 0 to 1 transition of done caused by esus being set to logic 1. if program or erase are attempted on blocks that are locked, the response will be peg=1, indicating that the operation was successful, and the content of the block were properly protected from the program or erase operation. if a program operation tries to program at ?1? bits that are at ?0?, the program opera tion is correctly executed on the new bits to be programmed at ?0?, but peg is cleared, indicating that the requested operation has failed. in array integrity check or margin mode peg is set to 1 when the operation is completed, regardless the occurrence of any error. the presence of errors can be detected only comparing checksum value stored in umirs0-1. aborting an array integrity check or a margin mode operation will cause peg to be cleared to 0, indicating the sequence failed. 0 program or erase operation failed. 1 program or erase operation successful. 23:26 reserved (read only) write these bits has no effect and read these bits always outputs 0. 27 pgm: program (read/write) pgm is used to setup the flash module for a program operation. a 0 to 1 transition of pgm initiates a program sequence. a 1 to 0 transition of pgm ends the program sequence. pgm can be set only under user mode read (ers is low and ut0.aie is low). pgm can be cleared by the user only when ehv is low and done is high. pgm is cleared on reset. 0: flash is not executing a program sequence. 1: flash is executing a program sequence. 28 psus: program suspend (read/write) write this bit has no effect, but the written data can be read back. table 17-42. mcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 17-58 freescale semiconductor preliminary?subject to change without notice a number of mcr bits are protected agai nst write when another bit, or set of bits, is in a specific state. these write locks are covered on a bit by bit basis in the preceding description, but those locks do not consider the effects of trying to wr ite two or more bits simultaneously. the flash module does not allow the user to write bits simultaneously which would put the device into an illegal state. this is implemente d through a priority mech anism among the bits. the bit changing priorities are detailed in table 17-43 . 29 ers: erase (read/write) ers is used to setup the flash module for an erase operation. a 0 to 1 transition of ers initiates an erase sequence. a 1 to 0 transition of ers ends the erase sequence. ers can be set only under user mode read (pgm is low and ut0.aie is low). ers can be cleared by the user only when esus and ehv are low and done is high. ers is cleared on reset. 0: flash is not executing an erase sequence. 1: flash is executing an erase sequence. 30 esus: erase suspend (read/write) esus is used to indicate that the flash module is in erase suspend or in the process of entering a suspend state. the flash module is in erase suspend when esus=1 and done=1. esus can be set high only when ers and ehv are high and pgm is low. a 0 to 1 transition of esus starts the sequence whic h sets done and places the flash in erase suspend. the flash module enters suspend within t esus of this transition. esus can be cleared only when done and ehv are high and pgm is low. a 1 to 0 transition of esus with ehv=1 starts t he sequence which clears done and returns the module to erase. the flash module cannot exit erase suspend and clear done while ehv is low. esus is cleared on reset. 0: erase sequence is not suspended. 1: erase sequence is suspended. 31 ehv: enable high voltage (read/write) the ehv bit enables the flash module for a high voltage program/erase operation. ehv is cleared on reset. ehv must be set after an interlock write to start a program/erase sequence. ehv may be set under one of the following conditions: erase (ers=1, esus=0, ut0.aie=0) program (ers=0, esus=0, pgm=1, ut0.aie=0) in normal operation, a 1 to 0 transition of ehv with done high and esus low terminates the current program/erase high voltage operation. when an operation is aborted, there is a 1 to 0 transition of eh v with done low and the eventual suspend bit low. an abort causes the value of peg to be cleared, indicating a failing program/erase; address locations being operated on by the aborted operation contain indeterminate data after an abort. a suspended operation cannot be aborted. aborting a high voltage operation will leave the fl ash module addresses in an undeterminate data state. this may be recovered by executing an erase on the affected blocks. ehv may be written during suspend. ehv must be high to exit suspend. ehv may not be written after esus is set and before done transitions high. ehv may not be cleared after esus is cleared and before done transitions low. 0: flash is not enabled to perform an high voltage operation. 1: flash is enabled to perform an high voltage operation. table 17-42. mcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-59 preliminary?subject to change without notice if the user attempts to write two or more mcr bits simultaneously then only the bit with the lowest priority level will be written. 17.3.6.2 low/mid address space block locking register (lml) address offset: 0x0004 reset value: 0x00xxxxxx, initially determin ed by nvlml value from test sector. 17.3.6.3 non-volatile low/mid address sp ace block locking register (nvlml) the low/mid address space block locking register provides a means to protect blocks from being modified. these bits, along wi th bits in the sll register, determine if the block is locked from program or erase. an ?or? of lml and sll determine the final lock status. the lml register has a related non-volatile low/mid address space block locking register located in test flash that contains the default reset value fo r lml: the nvlml register is read during the reset phase of the flash module and loaded into the lml. the nvlml register is a 64-bit register, the 32 most significative bits of whic h (bits 63-32) are ?don?t care? and eventually used to manage ecc codes. table 17-43. mcr bits set/clear priority levels priority level mcr bits 1ers 2pgm 3ehv 4 esus address offset: 0x403de8 delivery value: 0xffffffff 0123456789101112131415 lme0000000000tslk00mlk1mlk0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/x r/0 r/0 rw/x rw/x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 llk15 llk14 llk13 llk12 llk11 llk10 llk9 llk8 llk7 llk6 llk5 llk4 llk3 llk2 llk1 llk0 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x figure 17-28. non-volatile low/mid address space block locking register (nvlml)
pxd10 microcontroller reference manual, rev. 1 17-60 freescale semiconductor preliminary?subject to change without notice table 17-44. nvlml field descriptions field description 0 lme : low/mid address space block enable (read only) this bit is used to enable the lock registers (tslk, ml k1-0 and llk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bi t is to write a password, and if the password matches, the lme bit will be set to reflect the status of enab led, and is enabled until a reset operation occurs. for lme the password 0xa1a11111 must be written to the lml register. 0: low address locks are disabled: tslk, mlk1-0 and llk15-0 cannot be written. 1: low address locks are enabled: tslk, mlk1-0 and llk15-0 can be written. 1:10 reserved (read only). write these bits has no effect and read these bits always outputs 0. 11 tslk : test/shadow address space block lock (read/write) this bit is used to lock the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the tslk register signifies that the test/shadow block is locked for program and erase. a value of 0 in the tslk register signifies that the test/shadow block is available to receive program and erase pulses. the tslk register is not writable once an interloc k write is completed until mcr.done is set at the completion of the requested operation. likewise, the tslk register is not writable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the tslk register. the tslk bit may be written as a register. reset will cause the bit to go back to its test flash block value. the default value of the tslk bit (assuming erased fuses) would be locked. tslk is not writable unless lme is high. 0: test/shadow address space block is unlocked and can be modified (if also sll.stslk=0). 1: test/shadow address space block is locked and cannot be modified. 12:13 reserved (read only). write these bits has no effect and read these bits always outputs 0. 14:15 mlk1-0 : mid address space block lock 1-0 (read/write) these bits are used to lock the blocks of mid address space from program and erase. all the mlk1-0 are not used for this memory cut that is all mapped in low address space. a value of 1 in a bit of the mlk register signifie s that the corresponding block is locked for program and erase. a value of 0 in a bit of the mlk register signifies that the corresponding block is available to receive program and erase pulses. the mlk register is not writable once an interloc k write is completed until mcr.done is set at the completion of the requested operation. likewise, the mlk register is not writable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the mlk registers. the mlk bits may be written as a register. reset will cause the bits to go back to their test flash block value. the default value of the mlk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to config uration or total memory size), the mlk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the test flash block), and register writes will have no effect. in the 80 kb flash macrocell bits mlk1-0 are read-only and locked at 1. mlk is not writable unless lme is high. 0: mid address space block is unlocked and can be modified (if also sll.smlk=0). 1: mid address space block is locked and cannot be modified.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-61 preliminary?subject to change without notice 17.3.6.4 high address space block locking register (hbl) address offset: 0x0008 reset value: 0x000000xx, initially determined by nvhbl, located in test sector. 17.3.6.5 non-volatile high address space block locking register (nvhbl) the high address space block locking register provides a means to protect blocks from being modified. the hbl register has a related non-volatile high addre ss space block locking regi ster located in test flash that contains the default rese t value for hbl: the nvhbl register is read during th e reset phase of the flash module and loaded into the hbl. the nvhbl register is a 64-bit register, the 32 most significative bits of which (bits 63-32) are ?don?t care? and eventually used to manage ecc codes. 16:31 llk15-0 : low address space block lock 15-0 (read/write) these bits are used to lock the blocks of low address space from program and erase. llk3-0 are related to sectors b1f3-0, respective ly. llk15-4 are not used for this memory cut. a value of 1 in a bit of the llk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the llk register signifies that the corresponding block is available to receive program and erase pulses. the llk register is not writable once an interlock write is completed until mcr.done is set at the completion of the requested operation. likewise, the llk register is not writable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the llk registers. the llk bits may be written as a register. reset will cause the bits to go back to their test flash block value. the default value of the llk bits (assuming erased fuses) would be locked. in the event that blocks are not pres ent (due to configuration or total me mory size), the llk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the test flash block), and register writes will have no effect. in the 80 kb flash macrocell bits llk15-4 are read-only and locked at 1. llk is not writable unless lme is high. 0: low address space block is unlocked and can be modified (if also sll.slk=0). 1: low address space block is locked and cannot be modified. address offset: 0x403df0 delivery value: 0xffffffff 0123456789101112131415 hbe000000000000000 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0000000000hlk5hlk4hlk3hlk2hlk1hlk0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/x rw/x rw/x rw/x rw/x rw/x figure 17-29. non-volatile high address space block locking register (nvhbl) table 17-44. nvlml field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 17-62 freescale semiconductor preliminary?subject to change without notice 17.3.6.6 secondary low/mid address sp ace block locking register (sll) address offset: 0x000c reset value: 0x00xxxxxx, initially determin ed by nvsll, located in test sector table 17-45. hbl field descriptions field description 0 high address space block enable (read only) this bit is used to enable the lock registers (hlk5-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bi t is to write a password, and if the password matches, the hbe bit will be set to reflect the status of enab led, and is enabled until a reset operation occurs. for hbe the password 0xb2b22222 must be written to the hbl register. 0: high address locks are disabled: hlk5-0 cannot be written. 1: high address locks are enabled: hlk5-0 can be written. 1:25 reserved (read only). write these bits has no effect and read these bits always outputs 0. 26:31 hlk5-0 : high address space block lock 5-0 (read/write) these bits are used to lock the blocks of high address space from program and erase. all the hlk5-0 are not used for this memory cut that is all mapped in low address space. a value of 1 in a bit of the hlk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the hlk register signifies that the corresponding block is available to receive program and erase pulses. the hlk register is not writable once an interlock write is completed until mcr.done is set at the completion of the requested operation. likewise, the hlk register is not wr itable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the hlk registers. the hlk bits may be written as a register. reset will cause the bits to go back to their test flash block value. the default value of the hlk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configur ation or total memory size), the hlk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the test flash block), and register writes will have no effect. in the 80 kb flash macrocell bits hlk5-0 are read-only and locked at 1. hlk is not writable unless hbe is high. 0: high address space block is unlocked and can be modified. 1: high address space block is locked and cannot be modified.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-63 preliminary?subject to change without notice 17.3.6.7 non-volatile secondary low/ mid address space block locking reg (nvsll) the secondary low/mid address spac e block locking register provides an alternative means to protect blocks from being modified. these bits, along with bits in the lml register, determine if the block is locked from program or erase. an ?or? of lml and sll determine the final lock status. the sll register has a related n on-volatile secondary low/mid addre ss space block locking register located in test flash that contains the default reset value for sll: the nvsll re gister is read during the reset phase of the flash module and loaded into the sll. the nvsll register is a 64-bit regist er, the 32 most significative bits of which (bits 63-32) are ?don?t care? and eventually used to manage ecc codes. address offset: 0x403df8 delivery value: 0xffffffff 0123456789101112131415 sle0000000000stslk00smk1smk0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/x r/0 r/0 rw/x rw/x 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 slk15 slk14 slk13 slk12 slk11 slk10 slk9 slk8 slk7 slk6 slk5 slk4 slk3 slk2 slk1 slk0 rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x rw/x figure 17-30. non-volatile secondary low/ mid address space block locking reg (nvsll) table 17-46. nvsll field descriptions field description 0 sle : secondary low/mid address space block enable (read only) this bit is used to enable the lock registers (sts lk, smk1-0 and slk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to set this bi t is to write a password, and if the password matches, the sle bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle the password 0xc3c33333 must be written to the sll register. 0: secondary low/mid address locks are disabled : stslk, smk1-0 and slk15-0 cannot be written. 1: secondary low/mid address locks are enable d: stslk, smk1-0 and slk15-0 can be written. 1:10 reserved (read only). write these bits has no effect and read these bits always outputs 0.
pxd10 microcontroller reference manual, rev. 1 17-64 freescale semiconductor preliminary?subject to change without notice 11 stslk : secondary test/shadow address space block lock (read/write) this bit is used as an alternate means to lock the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the stslk register signifies that the test/shadow block is locked for program and erase. a value of 0 in the stslk register signifies that the test/shadow block is available to receive program and erase pulses. the stslk register is not writable once an interloc k write is completed until mcr.done is set at the completion of the requested operation. likewise, the stslk register is not writable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the stslk register. the stslk bit may be written as a register. reset will cause the bit to go back to its test flash block value. the default value of the stslk bit (assuming erased fuses) would be locked. stslk is not writable unless sle is high. 0: test/shadow address space block is unlocked and can be modified (if also lml.tslk=0). 1: test/shadow address space block is locked and cannot be modified. 12:13 reserved (read only). write these bits has no effect and read these bits always outputs 0. 14:15 smk1-0 : secondary mid address space block lock 1-0 (read/write) these bits are used as an alternate means to lock the blocks of mid address space from program and erase. all the smk1-0 are not used for this memory cut that is all mapped in low address space. a value of 1 in a bit of the smk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the smk register signifies that the corresponding block is available to receive program and erase pulses. the smk register is not writable once an interlock write is completed until mcr.done is set at the completion of the requested operation. likewise, the smk register is not writable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the smk registers. the smk bits may be written as a register. reset will cause the bits to go back to their test flash block value. the default value of the smk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to confi guration or total memory size), the smk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the test flash block), and register writes will have no effect. in the 80 kb flash macrocell bits smk1-0 are read-only and locked at 1. smk is not writable unless sle is high. 0: mid address space block is unlocked and can be modified (if also lml.mlk=0). 1: mid address space block is locked and cannot be modified. table 17-46. nvsll field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-65 preliminary?subject to change without notice 17.3.6.8 low/mid address space block select register (lms) the low/mid address space block sel ect register provides a means to se lect blocks to be operated on during erase. 16:31 slk15-0 : secondary low address space block lock 15-0 (read/write) these bits are used as an alternate means to lo ck the blocks of low address space from program and erase. slk3-0 are related to sectors b1 f3-0, respectively. slk15-4 are not used for this memory cut. a value of 1 in a bit of the slk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the slk register signifies that the corresponding block is available to receive program and erase pulses. the slk register is not writable once an interlock write is completed until mcr.done is set at the completion of the requested operation. likewise, the slk register is not wr itable if a high voltage operation is suspended. upon reset, information from the test flash block is loaded into the slk registers. the slk bits may be written as a register. reset will cause the bits to go back to their test flash block value. the default value of the slk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configur ation or total memory size), the slk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the test flash block), and register writes will have no effect. in the 80 kb flash macrocell bits slk15-4 are read-only and locked at 1. slk is not writable unless sle is high. 0: low address space block is unlocked and can be modified (if also lml.llk=0). 1: low address space block is locked and cannot be modified. address offset: 0x00010 reset value: 0x00000000 0123456789101112131415 00000000000000msl1msl0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsl15 lsl14 lsl13 lsl12 lsl11 lsl10 lsl9 lsl8 lsl7 lsl6 lsl5 lsl4 lsl3 lsl2 lsl1 lsl0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-31. low/mid address space block select register (lms) table 17-47. lms field descriptions field description 0:13 reserved (read only). write these bits has no effect and read these bits always outputs 0. table 17-46. nvsll field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 17-66 freescale semiconductor preliminary?subject to change without notice 17.3.6.9 high address space bl ock select register (hbs) the high address space block select register provides a means to se lect blocks to be operated on during erase. 14:15 msl1-0 : mid address space block select 1-0 (read/write) a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not select ed for erase. the reset value for the select register is 0, or unselected. all the msl1-0 are not used for this memory cut that is all mapped in low address space. the blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not present (due to conf iguration or total memory size), the corresponding msl bits will default to unselected, and will not be writable. the reset value will always be 0, and register writes will have no effect. in the 80 kb flash macrocell bits msl1-0 are read-only and locked at 0. 0: mid address space block is unselected for erase. 1: mid address space block is selected for erase. 16:31 lsl15-0 : low address space block select 15-0 (read/write) a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not select ed for erase. the reset value for the select register is 0, or unselected. lsl3-0 are related to sectors b1 f3-0, respectively. lsl15-4 are not used for this memory cut. the blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not present (due to config uration or total memory size), the corresponding lsl bits will default to unselected, and will not be writable. the reset value will always be 0, and register writes will have no effect. in the 80 kb flash macrocell bits lsl15-4 are read-only and locked at 0. 0: low address space block is unselected for erase. 1: low address space block is selected for erase. address offset: 0x00014 reset value: 0x00000000 0123456789101112131415 0000000000000000 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0000000000hsl5hsl4hsl3hsl2hsl1hsl0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/0rw/0rw/0rw/0rw/0rw/0 figure 17-32. high address space block select register (hbs) table 17-47. lms field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-67 preliminary?subject to change without notice 17.3.6.10 address register (adr) the address register provi des the first failing address in the even t module failures (ecc, rww or fpec) or the first address at which a ecc single error correction occurs. table 17-48. hbs field descriptions field description 0:25 reserved (read only). write these bits has no effect and read these bits always outputs 0. 26:31 hsl5-0 : high address space block select 5-0 (read/write) a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not select ed for erase. the reset value for the select register is 0, or unselected. all the hsl5-0 are not used for this memory cut that is all mapped in low address space. the blocks must be selected (or unselected) before doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not present (due to config uration or total memory size), the corresponding hsl bits will default to unselected, and will not be writable. the reset value will always be 0, and register writes will have no effect. in the 80 kb flash macrocell bits hsl5-0 are read-only and locked at 0. 0: high address space block is unselected for erase. 1: high address space block is selected for erase. address offset: 0x00018 reset value: 0x00000000 0123456789101112131415 000000000ad22ad21ad20ad19ad18ad17ad16 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 0 0 0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 figure 17-33. address register (adr) table 17-49. adr field descriptions field description 0:8 reserved (read only). write these bits has no effect and read these bits always outputs 0.
pxd10 microcontroller reference manual, rev. 1 17-68 freescale semiconductor preliminary?subject to change without notice 17.3.6.11 user test 0 register (ut0) the user test feature gives the user of the flash m odule the ability to perform test features on the flash. the user test 0 register allows to control th e way in which the flas h content check is done. bits mre, mrv, ais, eie and dsi7-0 of the us er test 0 register are not accessible whenever mcr.done or ut0.aid are low: reading returns i ndeterminate data while writing has no effect. 9:28 ad22-3 : address 22-3 (read only) the address register provides the first failing addre ss in the event of ecc error (mcr.eer set) or the first failing address in the event of rww error (mcr.rw e set), or the address of a failure that may have occurred in a fpec operation (mcr. peg cleared). the address register provides also the first address at which a ecc single error correction occurs (mcr.e dc set), if the soc is configured to show this feature. the ecc double error detection takes the highest priority, followed by the rww error, the fpec error and the ecc single error correction. when accessed a dr will provide the address related to the first event occurred with the highest priority. the priorities bet ween these 4 possible events is summarized in the following table. this address is always a double word address that selects 64 bits. in case of a simultaneous ecc double error detection on both double words of the same page, bit ad3 will output 0. the same is valid for a simultaneous ecc single error correction on both double words of the same page. in user mode the address register is read only. 29:31 reserved (read only). write these bits has no effect and read these bits always outputs 0. table 17-50. adr content: priority list priority level error flag adr content 1 mcr.eer = 1 address of first ecc double error 2 mcr.rwe = 1 address of first rww error 3 mcr.peg = 0 address of first fpec error 4 mcr.edc = 1 address of first ecc single error correction address offset: 0x0003c reset value: 0x00000001 0123456789101112131415 ute0000000dsi7dsi6dsi5dsi4dsi3dsi2dsi1dsi0 rw/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/0rw/0rw/0rw/0rw/0rw/0rw/0rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 000000000xmremrveieaisaieaid r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 r/0 rw/0rw/0rw/0rw/0rw/0rw/0 r/1 figure 17-34. user test 0 register (ut0) table 17-49. adr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-69 preliminary?subject to change without notice table 17-51. ut0 field descriptions field description 0 ute : user test enable (read/clear) this status bit gives indication when user test is en abled. all bits in ut0-2 and umisr0-4 are locked when this bit is 0. this bit is not writeable to a 1, but may be cleared. the reset value is 0. the method to set this bit is to provide a password, and if the password matches, the ute bit is set to reflect the status of enabled, and is enabled until it is cleared by a register write. for ute the password 0xf9f99999 must be written to the ut0 register. 1:7 reserved (read only). write these bits has no effect and read these bits always outputs 0. 8:15 dsi7-0 : data syndrome input 7-0 (read/write) these bits represent the i nput of syndrome bits of ecc logic used in the ecc logic check. the dsi7-0 correspond to the 8 syndrome bits on a double word. these bits are not accessible when ever mcr.done or ut0.aid are lo w: reading returns indeterminate data while writing has no effect. 0: the syndrome bit is forced at 0. 1: the syndrome bit is forced at 1. 16:24 reserved (read only). write these bits has no effect and read these bits always outputs 0. 25 reserved (read/write). this bit can be written and its value can be r ead back, but there is no function associated. this bit is not accessible whenever mcr.done or ut0.aid are low: reading returns indeterminate data while writing has no effect. 26 mre : margin read enable (read/write) mre enables margin reads to be done. this bit, combined with mrv, enables regular user mode reads to be replaced by margin reads. this bit is not accessible whenever mcr.done or ut0.aid are low: reading returns indeterminate data while writing has no effect. 0: margin reads are not enabled, all reads are user mode reads. 1: margin reads are enabled. 27 mrv : margin read value (read/write) if mre is high, mrv selects the margin level that is being checked. margin can be checked to an erased level (mrv=1) or to a programmed level (mrv=0). this bit is not accessible whenever mcr.done or ut0.aid are low: reading returns indeterminate data while writing has no effect. 0: zero?s (programmed) margin reads are requested (if mre=1). 1: one?s (erased) margin reads are requested (if mre=1). 28 eie : ecc data input enable (read/write) eie enables the ecc logic check operation to be done. this bit is not accessible whenever mcr.done or ut0.aid are low: reading returns indeterminate data while writing has no effect. 0: ecc logic check is not enabled. 1: ecc logic check is enabled.
pxd10 microcontroller reference manual, rev. 1 17-70 freescale semiconductor preliminary?subject to change without notice 17.3.6.12 user test 1 register (ut1) the user test 1 register allows to enable the check s on the ecc logic related to the 32 lsb of the double word. the user test 1 register is not accessible whenev er mcr.done or ut0.aid are low: reading returns indeterminate data whil e writing has no effect. 29 ais : array integrity sequence (read/write) ais determines the address sequence to be used during array integrity checks or margin mode. the default sequence (ais=0) is meant to replicate sequences normal user code follows, and thoroughly checks the read propagation paths. this sequence is proprietary. the alternative sequence (ais=1) is just logically sequential. it should be noted that the time to run a sequential sequence is significantly shorter than the time to run the proprietary sequence. only the sequential mode is allowed in margin mode. this bit is not accessible whenever mcr.done or ut0.aid are low: reading returns indeterminate data while writing has no effect. 0: array integrity sequence is proprietary sequence. 1: array integrity sequence or margin mode sequence is sequential. 31 aie : array integrity enable (read/write) aie set to 1 starts the array integrity check done on all selected and unlocked blocks. the pattern is selected by ais, and the misr (umisr0- 4) can be checked after the operation is complete, to determine if a correct signature is obtained. aie can be set only if mcr.ers, mcr.pgm and mcr.ehv are all low. 0: array integrity checks, margin mode, and ecc logic checks are not enabled. 1: array integrity checks, margin mode, and ecc logic checks are enabled. 31 aid : array integrity done (read only) aid will be cleared upon an array integrity check being enabled (to signify the operation is on-going). once completed, aid will be set to in dicate that the array integrity chec k is complete. at this time the misr (umisr0-4) can be checked. 0: array integrity check is on-going. 1: array integrity check is done. address offset: 0x00040 reset value: 0x00000000 0123456789101112131415 dai31 dai30 dai29 dai28 dai27 dai26 dai25 dai24 dai23 dai22 dai21 dai20 dai19 dai18 dai17 dai16 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dai15 dai14 dai13 dai12 dai11 dai10 dai09 dai08 dai07 dai06 dai05 dai04 dai03 dai02 dai01 dai00 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-35. user test 1 register (ut1) table 17-51. ut0 field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-71 preliminary?subject to change without notice 17.3.6.13 user test 2 register (ut2) the user test 2 register allows to enable the check s on the ecc logic related to the 32 msb of the double word. the user test 2 register is not accessible whenev er mcr.done or ut0.aid are low: reading returns indeterminate data whil e writing has no effect. table 17-52. ut1 field descriptions field description 0:31 dai31-00 : data array input 31-0 (read/write) these bits represent the input of even word of ec c logic used in the ecc logic check. the dai31-00 correspond to the 32 array bits representing word 0 within the double word. 0: the array bit is forced at 0. 1: the array bit is forced at 1. address offset: 0x00044 reset value: 0x00000000 0123456789101112131415 dai63 dai62 dai61 dai60 dai59 dai58 dai57 dai56 dai55 dai54 dai53 dai52 dai51 dai50 dai49 dai48 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 dai47 dai46 dai45 dai44 dai43 dai42 dai41 dai40 dai39 dai38 dai37 dai36 dai35 dai34 dai33 dai32 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-36. user test 2 register (ut2) table 17-53. ut2 field descriptions field description 0:31 dai63-32 : data array input 63-32 (read/write) these bits represent the input of odd word of e cc logic used in the ecc logic check. the dai63-32 correspond to the 32 array bits representing word 1 within the double word. 0: the array bit is forced at 0. 1: the array bit is forced at 1.
pxd10 microcontroller reference manual, rev. 1 17-72 freescale semiconductor preliminary?subject to change without notice 17.3.6.14 user multiple input signature register 0 (umisr0) the multiple input signature register provide s a mean to evaluate the array integrity. the user multiple input signature re gister 0 represents the bits 31-0 of the whole 144 bits word (2 double words including ecc). the umisr0 register is not accessible whenever mcr.done or ut0.aid ar e low: reading returns indeterminate data whil e writing has no effect. 17.3.6.15 user multiple input signature register 1 (umisr1) the multiple input signature register provide s a mean to evaluate the array integrity. the user multiple input signature register 1 represents the bits 63- 32 of the whole 144 bits word (2 double words including ecc). address offset: 0x00048 reset value: 0x00000000 0123456789101112131415 ms031 ms030 ms029 ms028 ms027 ms026 ms025 ms024 ms023 ms022 ms021 ms020 ms019 ms018 ms017 ms016 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ms015 ms014 ms013 ms012 ms011 ms010 ms009 ms008 ms007 ms006 ms005 ms004 ms003 ms002 ms001 ms000 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-37. user multiple input signature register 0 (umisr0) table 17-54. umsir0 field descriptions field description 0:31 ms031-000 : multiple input signature 031-000 (read/write) these bits represent the misr value obtained accumu lating the bits 31-0 of a ll the pages read from the flash memory. the ms can be seeded to any value by writing the umisr0 register. address offset: 0x0004c reset value: 0x00000000 0123456789101112131415 ms063 ms062 ms061 ms060 ms059 ms058 ms057 ms056 ms055 ms054 ms053 ms052 ms051 ms050 ms049 ms048 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ms047 ms046 ms045 ms044 ms043 ms042 ms041 ms040 ms039 ms038 ms037 ms036 ms035 ms034 ms033 ms032 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-38. user multiple input signature register 1 (umisr1)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-73 preliminary?subject to change without notice the umisr1 register is not accessible whenever mcr.done or ut0.aid ar e low: reading returns indeterminate data whil e writing has no effect. 17.3.6.16 user multiple input signature register 2 (umisr2) the multiple input signature register provide s a mean to evaluate the array integrity. the user multiple input signature register 2 represents the bits 95- 64 of the whole 144 bits word (2 double words including ecc). the umisr2 register is not accessible whenever mcr.done or ut0.aid ar e low: reading returns indeterminate data whil e writing has no effect. table 17-55. umisr1 field descriptions field description 0:31 ms063-032 : multiple input signature 063-032 (read/write) these bits represent the misr value obtained accumulati ng the bits 63-32 of all the pages read from the flash memory. the ms can be seeded to any value by writing the umisr1 register. address offset: 0x00050 reset value: 0x00000000 0123456789101112131415 ms095 ms094 ms093 ms092 ms091 ms090 ms089 ms088 ms087 ms086 ms085 ms084 ms083 ms082 ms081 ms080 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ms079 ms078 ms077 ms076 ms075 ms074 ms073 ms072 ms071 ms070 ms069 ms068 ms067 ms066 ms065 ms064 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-39. user multiple input signature register 2 (umisr2) table 17-56. umisr2 field descriptions field description 0:31 ms095-064 : multiple input signature 095-064 (read/write) these bits represent the misr value obtained accumulati ng the bits 95-64 of all the pages read from the flash memory. the ms can be seeded to any value by writing the umisr2 register.
pxd10 microcontroller reference manual, rev. 1 17-74 freescale semiconductor preliminary?subject to change without notice 17.3.6.17 user multiple input signature register 3 (umisr3) the multiple input signature register provide s a mean to evaluate the array integrity. the user multiple input signature register 3 represents the bits 127- 96 of the whole 144 bits word (2 double words including ecc). the umisr3 register is not accessible whenever mcr.done or ut0.aid ar e low: reading returns indeterminate data whil e writing has no effect. 17.3.6.18 user multiple input signature register 4 (umisr4) the multiple input signature register provide s a mean to evaluate the array integrity. the user multiple input signature register 4 represen ts the ecc bits of the whole 144 bits word (2 double words including ecc): bits 8-15 are ecc bits for the odd double word and bits 24-31 are the ecc bits for the even double word; bits 4-5 and 20-21 of misr are respectively the double and single ecc error detection for odd and even double word. address offset: 0x00054 reset value: 0x00000000 0123456789101112131415 ms127 ms126 ms125 ms124 ms123 ms122 ms121 ms120 ms119 ms118 ms117 ms116 ms115 ms114 ms113 ms112 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ms111 ms110 ms109 ms108 ms107 ms106 ms105 ms104 ms103 ms102 ms101 ms100 ms099 ms098 ms097 ms096 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-40. user multiple input signature register 3 (umisr3) table 17-57. umisr3 field descriptions field description 0:31 ms127-096 : multiple input signature 127-096 (read/write) these bits represent the misr value obtained accumula ting the bits 127-96 of all the pages read from the flash memory. the ms can be seeded to any value by writing the umisr3 register. address offset: 0x00058 reset value: 0x00000000 0123456789101112131415 ms159 ms158 ms157 ms156 ms155 ms154 ms153 ms152 ms151 ms150 ms149 ms148 ms147 ms146 ms145 ms144 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 ms143 ms142 ms141 ms140 ms139 ms138 ms137 ms136 ms135 ms134 ms133 ms132 ms131 ms130 ms129 ms128 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 rw/0 figure 17-41. user multiple input signature register 4 (umisr4)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-75 preliminary?subject to change without notice the umisr4 register is not accessible whenever mcr.done or ut0.aid ar e low: reading returns indeterminate data whil e writing has no effect. 17.3.7 programming considerations 17.3.7.1 modify operation all the modify operations of th e flash module are managed through th e flash user registers interface. all the sectors of the flas h module belong to the same partition (b ank), therefore when a modify operation is active on some sectors no read access is possibl e on any other sector (r ead-while-modify is not supported). during a flash modify operation any attempt to read any flash location will output invalid data and bit rwe of mcr will be automa tically set. this means th at the flash module is not fetchable when a modify operation is active: the modify operation commands must be executed from another memory (internal ram or external memory). if during a modify operation a reset occurs, the operation is suddenly term inated and the macrocell is reset to read mode. the data integrity of the flash section where the modify operation has been terminated is not guaranteed: the interrupted flash modify operation mu st be repeated. in general each modify operation is started through a sequence of 3 steps: 1. the first instruction is used to select the desired operation by set ting its corresponding selection bit in mcr (pgm or ers) or ut0 (mre or eie). 2. the second step is the definiti on of the operands: the address and the data for programming or the sectors for erase or margin read. 3. the third instruction is used to start the modi fy operation, by setting e hv in mcr or aie in ut0. once selected, but not yet started, one operation can be canceled by rese tting the operation selection bit. a summary of the available flash modify operations are shown in the following table 17-36 . table 17-58. umisr4 field descriptions field description 0:31 ms159-128 : multiple input signature 159-128 (read/write) these bits represent the misr value obtained accumulating: the 8 ecc bits for the even double word (on ms135-128); the single ecc error detection for even double word (on ms138); the double ecc error detection for even double word (on ms139); the 8 ecc bits for the odd double word (on ms151-144); the single ecc error detection for odd double word (on ms154); the double ecc error detection for odd double word (on ms155). the ms can be seeded to any value by writing the umisr4 register. table 17-59. flash modify operations operation select bit operands start bit double word program mcr.pgm address and data by interlock writes mcr.ehv
pxd10 microcontroller reference manual, rev. 1 17-76 freescale semiconductor preliminary?subject to change without notice in general each modify operation is co mpleted through a sequence of four steps: 1. wait for operation completion: wait fo r bit mcr.done (or ut0.aid) to go high. 2. check operation result: check bit mcr.peg (o r compare umisr0-4 with expected value). 3. switch-off fpec by resetting mcr.ehv (or ut0.aie). 4. deselect current operation by clear ing mcr.pgm/ers (or ut0.mre/eie). if the device embeds more than one flash macrocell and a modify op eration is on-going on one of them, then it is forbidden to start any other m odify operation on the other flash macrocells. in the following all the possible modify operations are described and some examples of the sequences needed to activate them are presented. 17.3.7.2 double word program a flash program sequence operates on any double word within the flash core. up to two words within the double word ma y be altered in a single program operation. whenever you program, ecc bits also get programmed (unless the selected address belongs to a sector in which the ecc has been disa bled in order to allow bit manipulation). ecc is handled on a 64-bit boundary. thus, if only one word in any given 64-bit ecc se gment is programmed, the adjoining word (in that segment) should not be pr ogrammed since ecc calculat ion has already completed for that 64-bit segment. attempts to program the adjoining word will probabl y result in an operation failure. it is recommended that all programming operations be of 64 bits. the prog ramming operation should co mpletely fill selected ecc segments within the double word. programming changes the value stored in an array b it from logic 1 to logic 0 only. programming cannot change a stored logic 0 to a logic 1. addresses in locked/disabled blocks cannot be programmed. the user may program the values in any or all of two words, of a double word, with a single program sequence. double word-bound words have addresses which differ only in address bit 2. the program operation consists of the following sequence of events: 1. change the value in the mcr.pgm bit from 0 to 1. sector erase mcr.ers lms, hbs mcr.ehv array integrity check none lms, hbs ut0.aie margin read ut0.mre ut0.mrv + lms, hbs ut0.aie ecc logic check ut0.eie ut0.dsi, ut1, ut2 ut0.aie table 17-59. flash modify operations (continued) operation select bit operands start bit
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-77 preliminary?subject to change without notice 2. ensure the block that contains the address to be programmed is unlocked. write the first address to be pr ogrammed with the program data. the flash module latches address bits (22:3) at this time. the flash module latches data written as well. this write is referred to as a program data interl ock write. an interlock wr ite may be as large as 64 bits, and as small as 32 bits (depending on the cpu bus). 3. if more than 1 word is to be programmed, write the additional address in the double word with data to be programmed. this is re ferred to as a program data write. the flash modules ignores address bits (22:3) for program data writes. the eventual unwritten data word default to 0xffffffff. 4. write a logic 1 to the mcr.ehv bit to start the internal program sequence or skip to step 9 to terminate. 5. wait until the mcr.done bit goes high. 6. confirm mcr.peg=1. 7. write a logic 0 to the mcr.ehv bit. 8. if more addresses are to be programmed, return to step 2. 9. write a logic 0 to the mcr.pgm bi t to terminate the program operation. program may be initiated with the 0 to 1 transition of the mcr.pgm bi t or by clearing the mcr.ehv bit at the end of a previous program. the first write after a progr am is initiated determines the page address to be programmed. this first write is referred to as an interlock write. the interlock wr ite determines if the shadow , test or norma l array space will be programmed by causing mcr.peas to be set/cleared. an interlock write must be performed before se tting mcr.ehv. the user may terminate a program sequence by clearing mcr.pgm prior to setting mcr.ehv. after the interlock write, additiona l writes only affect the data to be programmed at the word location determined by address bit 2. unwritten locations defaul t to a data value of 0xf fffffff. if multiple writes are done to the same location the data fo r the last write is used in programming. while mcr.done is low and mcr.e hv is high, the user may clear ehv, resulting in a program abort. a program abort forces the module to step 8 of the program sequence. an aborted program will result in mcr.peg bei ng set low, indicating a fa iled operation. mcr.done must be checked to know when the aborting command has completed. the data space being operated on befo re the abort will cont ain indeterminate data. this may be recovered by repeating the same program instruction or executing an erase of the affected blocks. example 17-8. double word program of data 0x55aa55aa at address 0x00aaa8 and data 0xaa55aa55 at address 0x00aaac. mcr = 0x00000010; /* set pgm in mcr: select operation */ (0x00aaa8) = 0x55aa55aa; /* latch address and 32 lsb data */ (0x00aaac) = 0xaa55aa55; /* latch 32 msb data */ mcr = 0x00000011; /* set ehv in mcr: operation start */ do /* loop to wait for done=1 */ { tmp = mcr; /* read mcr */
pxd10 microcontroller reference manual, rev. 1 17-78 freescale semiconductor preliminary?subject to change without notice } while ( !(tmp & 0x00000400) ); status = mcr & 0x00000200; /* check peg flag */ mcr = 0x00000010; /* reset ehv in mcr: operation end */ mcr = 0x00000000; /* reset pgm in mcr: deselect operation */ 17.3.7.3 sector erase erase changes the value stored in all bits of the selected block(s) to logic 1. an erase sequence operates on any combination of blocks (sectors) in the low, mid or high address space, or the shadow block (if available) . the test block cannot be erased. the erase sequence is fully automated within the flash. the user only needs to select the blocks to be erased and initiate the erase sequence. locked/disabled blocks cannot be erased. if multiple blocks are selected fo r erase during an erase sequence, no specific operation order must be assumed. the erase operation cons ists of the following sequence of events: 1. change the value in the mcr.ers bit from 0 to 1. 2. select the block(s) to be erased by writing ?1 ?s to the appropriate re gister(s) in lms or hbs registers. if the shadow block is to be erased, this step may be ski pped, and lms and hbs are ignored. note that lock and select are i ndependent. if a block is selected and locked, no erase will occur. 3. write to any address in flash. this is referred to as an erase interlock write. 4. write a logic 1 to the mcr.ehv bit to start the internal erase sequence or skip to step 9 to terminate. 5. wait until the mcr.done bit goes high. 6. confirm mcr.peg=1. 7. write a logic 0 to the mcr.ehv bit. 8. if more blocks are to be erased, return to step 2. 9. write a logic 0 to the mcr.ers bi t to terminate the erase operation. after setting mcr.ers, one write, refe rred to as an interlock write, must be performed before mcr.ehv can be set to 1. data words written during erase sequence interlock writes are ignored. the user may terminate the erase seque nce by clearing ers before setting ehv. an erase operation may be aborted by clearing mc r.ehv assuming mcr.done is low, mcr.ehv is high and mcr.esus is low. an erase abort forces the module to step 8 of the erase sequence. an aborted erase will result in mcr.peg being set low, indicati ng a failed operation. mcr.done must be checked to know when the aborting command has completed. the block(s) being operated on before the abort cont ain indeterminate data. th is may be recovered by executing an erase on the affected blocks.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-79 preliminary?subject to change without notice the user may not abort an erase sequence while in erase suspend. example 17-9. erase of sectors b0f1 and b0f2. mcr = 0x00000004; /* set ers in mcr: select operation */ lms = 0x00000006; /* set lsl2-1 in lms: select sectors to erase */ (0x000000) = 0xffffffff; /* latch a flash address with any data */ mcr = 0x00000005; /* set ehv in mcr: operation start */ do /* loop to wait for done=1 */ { tmp = mcr; /* read mcr */ } while ( !(tmp & 0x00000400) ); status = mcr & 0x00000200; /* check peg flag */ mcr = 0x00000004; /* reset ehv in mcr: operation end */ mcr = 0x00000000; /* reset ers in mcr: deselect operation */ 17.3.7.3.1 erase suspend/resume the erase sequence may be suspended to allow read access to the flash core. it is not possible to program or to erase during an erase suspend. during erase suspend, all reads to blocks targ eted for erase return indeterminate data. an erase suspend can be initiated by changing the va lue of the mcr.esus bit from 0 to 1. mcr.esus can be set to 1 at any time wh en mcr.ers and mcr.ehv are high and mcr.pgm is low. a 0 to 1 transition of mcr.esus causes th e module to start the sequence whic h places it in erase suspend. the user must wait until mcr.done=1 before the module is suspe nded and further actions are attempted. mcr.done will go high no more than t esus after mcr.esus is set to 1. once suspended, the array may be read. flash core reads while mcr.esus=1 from the block(s) being erased return indeterminate data. example 17-10. sector erase suspend mcr = 0x00000007; /* set esus in mcr: erase suspend */ do /* loop to wait for done=1 */ { tmp = mcr; /* read mcr */ } while ( !(tmp & 0x00000400) ); notice that there is no need to clear mcr.ehv and mcr.ers in order to perf orm reads du ring erase suspend. the erase sequence is resumed by writing a logic 0 to mcr.esus. mcr.ehv must be set to 1 before mcr.esus can be cleared to resume the operation. the module continues the erase sequence from one of a se t of predefined points. this may extend the time required for the erase operation. example 17-11. sector erase resume mcr = 0x00000005; /* reset esus in mcr: erase resume */
pxd10 microcontroller reference manual, rev. 1 17-80 freescale semiconductor preliminary?subject to change without notice 17.3.7.4 user test mode user test mode is a mode, that customers can put th e flash module in, to do specific tests to check the integrity of the flash module. three kinds of test can be performed: ? array integrity self check ? margin mode read ? ecc logic check the user test mode is equivalent to a modify opera tion: read accesses attempted by the user during user test mode generates a read-while -write error (rwe of mcr set). it is not allowed to perform user test operations on the test and shadow blocks. 17.3.7.4.1 array integrity self check array integrity is checked using a predefined address sequence (pr oprietary), and this operation is executed on selected and unlocked bloc ks. once the operation is completed, the results of the reads can be checked by reading the misr value (stored in umisr0 -4), to determine if an incorrect read, or ecc detection was noted. the internal misr calculator is a 32-bit register. the 128 bit data, the 16 ecc data and the single and double ecc errors of the two double words are therefore captured by the misr through 5 diff erent read accesses at the same location. the whole check is done through five comple te scans of the memory address space: 1. the first pass will scan only bits 31-0 of each page. 2. the second pass will scan only bits 63-32 of each page. 3. the third pass will scan only bits 95-64 of each page. 4. the fourth pass will scan only bits 127-96 of each page. 5. the fifth pass will scan only the ecc bits (8 + 8) and the single and double ecc errors (2 + 2) of both double words of each page. the 128 bit data and the 16 ecc data are sampled be fore the eventual ecc correction, while the single and double error flags are samp led after the ecc evaluation. only data from existing and unlocke d locations are captured by the misr. the misr can be seeded to any value by writing the umisr0-4 registers. the array integrity self check consists of the following sequence of events: 1. set ute in ut0 by writing the related password in ut0. 2. select the block(s) to be checked by writing ?1?s to the appropriate register(s) in lms or hbs registers. note that lock and select are independent. if a block is select ed and locked, no array integrity check will occur.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-81 preliminary?subject to change without notice 3. set eventually ut0.ais bit for a sequential addressing only. 4. write a logic 1 to the ut0.aie bit to start the array integrity check. 5. wait until the ut0.aid bit goes high. 6. compare umisr0-4 content with the expected result. 7. write a logic 0 to the ut0.aie bit. 8. if more blocks are to be checked, return to step 2. it is recommended to leave ut0.ais at 0 and use th e proprietary address sequence that checks the read path more fully, although this sequence takes more time. during the execution of the array inte grity check operation it is forbidde n to modify the content of block select (lms, hbs) and lock (lml, sll, hbl) regi sters, otherwise the misr value can vary in an unpredictable way. while ut0.aid is low and ut0.aie is high, the user may clear aie, resulting in a array integrity check abort. ut0.aid must be checked to know when the aborting command has completed. example 17-12. array integrity check of sectors b0f1 and b0f2 ut0 = 0xf9f99999; /* set ute in ut0: enable user test */ lms = 0x00000006; /* set lsl2-1 in lms: select sectors */ ut0 = 0x80000002; /* set aie in ut0: operation start */ do /* loop to wait for aid=1 */ { tmp = ut0; /* read ut0 */ } while ( !(tmp & 0x00000001) ); data0 = umisr0; /* read umisr0 content*/ data1 = umisr1; /* read umisr1 content*/ data2 = umisr2; /* read umisr2 content*/ data3 = umisr3; /* read umisr3 content*/ data4 = umisr4; /* read umisr4 content*/ ut0 = 0x00000000; /* reset ute and aie in ut0: operation end */ 17.3.7.4.2 margin read margin read procedure (either margin 0 or margin 1), can be run on unlocked blocks in order to unbalance the sense amplifiers, respect to standard read conditi ons, so that all the read accesses reduce the margin vs ?0? (ut0.mrv = ?0?) or vs ?1 ? (ut0.mrv = ?1?). locked sectors are ignored by misr calculation and ecc flagging. the results of the margin reads can be checked comparing checksum value in umisr0-4. since margin reads are done at voltages that differ th an the normal read voltage, lifetime expectancy of the flash macrocell is impacted by th e execution of margin reads. doing margin reads repetitively results in degradation of the flash array, and shorten expect ed lifetime experienced at normal read levels. for these reasons the margin read usage is allowed only in factory, while it is forbidden to use it inside the user application. in any case the ch arge losses detected through the ma rgin mode cannot be considered failures of the device and no failur e analysis will be opened on them. the margin read setup operation consists of the following sequence of events: 1. set ute in ut0 by writing the related password in ut0.
pxd10 microcontroller reference manual, rev. 1 17-82 freescale semiconductor preliminary?subject to change without notice 2. select the block(s) to be checked by writing 1? s to the appropriate register(s) in lms or hbs registers. note that lock and select are independent. if a block is select ed and locked, no array integrity check will occur. 3. set eventually ut0.ais bit for a sequential addressing only. 4. change the value in the ut0.mre bit from 0 to 1. 5. select the margin level: ut0.mrv=0 fo r 0?s margin, ut0.mrv=1 for 1?s margin. 6. write a logic 1 to the ut0.aie bit to start the ma rgin read setup or skip to step 6 to terminate. 7. wait until the ut0.aid bit goes high. 8. compare umisr0-4 content with the expected result. 9. write a logic 0 to the ut0.a ie, ut0.mre and ut0.mrv bits. 10. if more blocks are to be checked, return to step 2. it is recommended to leave ut0.ais at 1 and use the linear address sequence that takes less time. during the execution of the margin m ode operation it is forbidden to m odify the content of block select (lms, hbs) and lock (lml, sll, hbl) register s, otherwise the misr value can vary in an unpredictable way. the read accesses will be done with the addition of a proper number of wait states to guarantee the correctness of the result. while ut0.aid is low and ut0.aie is high, the user may clear aie, re sulting in a array integrity check abort. ut0.aid must be checked to know when the aborting command has completed. example 17-13. margin read setup versus ?1?s ut0 = 0xf9f99999; /* set ute in ut0: enable user test */ lms = 0x00000006; /* set lsl2-1 in lms: select sectors */ ut0 = 0x80000004; /* set ais in ut0: select operation */ ut0 = 0x80000024; /* set mre in ut0: select operation */ ut0 = 0x80000034; /* set mrv in ut0: select margin versus 1?s */ ut0 = 0x80000036; /* set aie in ut0: operation start */ do /* loop to wait for aid=1 */ { tmp = ut0; /* read ut0 */ } while ( !(tmp & 0x00000001) ); data0 = umisr0; /* read umisr0 content*/ data1 = umisr1; /* read umisr1 content*/ data2 = umisr2; /* read umisr2 content*/ data3 = umisr3; /* read umisr3 content*/ data4 = umisr4; /* read umisr4 content*/ ut0 = 0x80000034; /* reset aie in ut0: operation end */ ut0 = 0x00000000; /* reset ute, mre, mrv, ais in ut0: deselect op. */ 17.3.7.4.3 ecc logic check ecc logic can be checked by forcing the input of ecc logic: the 64 bits of data and the 8 bits of ecc syndrome can be individually forced and they will drive simultane ously at the same value the ecc logic of the whole page (2 double words).
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-83 preliminary?subject to change without notice the results of the ecc logic check can be verified by reading the misr value. the ecc logic check operatio n consists of the following sequence of events: 1. set ute in ut0 by writing the related password in ut0. 2. write in ut1.dai31-0 and ut2.dai63-32 the double word input value. 3. write in ut0.dsi7-0 the syndrome input value. 4. select the ecc logic check: wr ite a logic 1 to the ut0.eie bit. 5. write a logic 1 to the ut0.aie bit to start the ecc logic check. 6. wait until the ut0.aid bit goes high. 7. compare umisr0-4 content with the expected result. 8. write a logic 0 to the ut0.aie bit. notice that when ut0.aid is low umisr0-4, ut1-2 an d bits mre, mrv, eie, ais and dsi7-0 of ut0 are not accessible: reading returns undete rminate data and write has no effect. example 17-14. ecc logic check ut0 = 0xf9f99999; /* set ute in ut0: enable user test */ ut1 = 0x55555555; /* set dai31-0 in ut1: even word input data */ ut2 = 0xaaaaaaaa; /* set dai63-32 in ut2: odd word input data */ ut0 = 0x80ff0000; /* set dsi7-0 in ut0: syndrome input data */ ut0 = 0x80ff0008; /* set eie in ut0: select ecc logic check */ ut0 = 0x80ff000a; /* set aie in ut0: operation start */ do /* loop to wait for aid=1 */ { tmp = ut0; /* read ut0 */ } while ( !(tmp & 0x00000001) ); data0 = umisr0; /* read umisr0 content (expected 0x55555555) */ data1 = umisr1; /* read umisr1 content (expected 0xaaaaaaaa) */ data2 = umisr2; /* read umisr2 content (expected 0x55555555) */ data3 = umisr3; /* read umisr3 content (expected 0xaaaaaaaa) */ data4 = umisr4; /* read umisr4 content (expected 0x00ff00ff) */ ut0 = 0x00000000; /* reset ute, aie and eie in ut0: operation end */ 17.3.8 error correction code the flash macrocell provides a method to improve the reli ability of the data stored in flash: the usage of an error correction code. the wo rd size is fixed of 64 bits. at each double word of 64 bits there are associated 8 ecc bits that are progr ammed in such a way to guarantee a single error co rrection and a double erro r detection (sec-ded). ecc circuitry provides correcti on of single bit faults and is used to achieve auto motive reliability targets. some units will experience single bit corrections th roughout the life of the product with no impact to product reliability. 17.3.8.1 ecc algorithm the flash macrocell supports one ecc algorithm: ?all ?1?s no error?. this algorithm detects as valid any double word read on a just erased sector (all the 72 bits are ?1?s).
pxd10 microcontroller reference manual, rev. 1 17-84 freescale semiconductor preliminary?subject to change without notice this option allows to perform a bla nk check after a sector erase operation. 17.3.8.2 bit manipulation the ecc algorithm allows some bit manipulations so that a double word can be rewritten several times without needing an erase of the sector. this allows to use a double word to store flags useful for the eeprom emulation. as an example the ecc algorithm allows to start from an all ?1?s double word value and rewrite whichever of its four 16-bits half-words to an all ?0?s content by keeping the same ecc value. table 17-60 shows a set of double words sharing the same ecc value. 17.3.8.3 eeprom emulation when some flash sectors are used to perform an eeprom emulation, it is reccomended for safety reasons to reserve at least 3 sectors to this purpose. 17.3.9 protection strategy two kind of protections are availabl e: modify protection to avoid unwan ted program/erase in flash sectors and censored mode to avoid piracy. table 17-60. bit manipulation: double words with the same ecc value double word ecc 0xffff_ffff_ffff_ffff 0xff 0xffff_ffff_ffff_0000 0xffff_fff f_0000_ffff 0xffff_0000_ ffff_ffff 0x0000_ffff_ ffff_ffff 0xffff_ffff_0000_0000 0xffff_0000_ffff_0000 0x0000_ffff_ffff_0000 0xffff_0000_0000_ffff 0x0000_ffff_0000_ffff 0x0000_0000_ffff_ffff 0xffff_0000_0000_0000 0x0000_ffff_0000_0000 0x0000_0000_0000_0000
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-85 preliminary?subject to change without notice 17.3.9.1 modify protection the flash modify protection information is stored in non-volatile flash cells located in the test flash. this information is read once during the fl ash initialization phase following th e exit from reset and is stored in volatile registers th at act as actuators. the reset state of all the volatile modify protection registers is the protected state. all the non-volatile modify prot ection registers can be program med through a normal double word program operation at the relate d locations in test flash. the non-volatile modify protecti on registers cannot be erased. ? the non-volatile modify protection registers are phys ically located in test flash their bits can be programmed to ?0? only once and they can no more be restored to ?1?. ? the volatile modify protection re gisters are read/write registers wh ich bits can be written at ?0? or ?1? by the user application. a software mechanism is provided to independently lock/unlock each low, mid and high address space block against program and erase. software locking is done through th e lml (low/mid address space bloc k lock register) or hbl (high address space block lock register) registers. an alternate means to enable software locking for blocks of low address sp ace only is through the sll (secondary low/mid address space block lock register). all these registers have a non-volatile image stored in test flash (nvlml, nvhbl, nvsll), so that the locking information is kept on reset. on delivery the test flash non-volatile image is at all ?1?s, meaning all sectors are locked. by programming the non-volatile lo cations in test flash the sele cted sectors can be unlocked. being the test flash one time programmable (i.e. not erasable), once unlocked the sectors cannot be locked again. of course, on the contrary, all the vol atile registers can be written at 0 or 1 at any time, therefore the user application can lock and unlock sectors when desired. 17.3.9.2 censored mode the 80k flash macrocell does not cont ain a shadow sector a nd all the associated features to manage the censored mode. these must theref ore be managed by the associated code flash macrocell embedded in the same soc.
pxd10 microcontroller reference manual, rev. 1 17-86 freescale semiconductor preliminary?subject to change without notice 17.4 platform flash controller (pflash2p_lca) 17.4.1 introduction this section provides an introduction to the 2-port platform flash controller (pflash2p_lca). the pflash2p_lca acts as the interface between two sy stem bus master ports (ahb-lite 2.v6) and up to three banks of integrated low-cost 90-nm flash memory arrays. it in telligently converts the protocols between the system bus ports and th e dedicated flash array interfaces. a block diagram of the e 200z0h power architecture reduced produc t platform (rpp) reference design is shown below in figure 17-42 with the pflash2p_lca module and its attached off-platform flash memory arrays highlighted. figure 17-42. power architecture e200z0 h rpp reference platform block diagram as shown in this block diagram, there are a number of baseline and optional modules (shaded) supported. the module list includes: ? power architecture e200z0h core wi th nexus1 or optional nexus2+ debug xbar memarray edma mem s0 s2 m0 s7 memarray pram pflash2p ips/apb intc ahb biu branch unit load/store i-fetcher dispatch gpr integer unit e200z0h core p_i_h* p_d_h* m1 m2 mpu on-platform irqs off-platform irqs debug unit nexus1, nexus2+ off-platform master m3 stm ips bus ips+apb bus flash regs ips+apb slave modules memarray flash regs bank0 bank1 ecsm swt s1 memarray flash regs bank2
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-87 preliminary?subject to change without notice ? optional 16-channel 2nd-generati on direct memory access (dma) ? optional off-platform bus master, e.g., flexray ? ahb crossbar switch (xbar) ? optional memory protection unit (mpu) ? 2-port platform flash memory controller (pflas h2p_lca) with connections to 3 memory banks ? platform ram memory controller (pram) ? ahb-to-{ips/apb} bus controller (aips-lite) for access to on- and off-platform slave modules ? interrupt controller (intc) ? 4-channel system timers (stm) ? software watchdog timer (swt) ? error correction status module (ecsm) the resulting 32-bit power architect ure e200z0h platform represents a reference design , where a single design description can be configured to generate multiple im plementations by including/excluding various platform modules as require d by a specific application. throughout this document, several im portant terms are used to descri be the pflash2p_lca module and its connections. these terms are defined here: ? port ? this is used to descri be the amba-ahb c onnection(s) into the pflash2p_lca. this flash controller supports 2 ahb por ts. for these platform designs, the pflash2p_lca p0 port is always connected to the processor core and the p1 port is conn ected to the non-core bus masters . ? bank ? this term is used to de scribe the attached flash memo ries. from the pflash2p_lca?s perspective, there may be two or three attached banks of flash memory. there are two ?code flash? arrays required and they are at tached to banks 0 and 2. the pfl ash2p_lca treats banks 0 and 2 in a common manner with various configuration fields of the programming model shared across the two banks. additionally, ther e may be a ?data fl ash? attached to bank1. the pflash2p_lca interface supports three separate c onnections, one to each memory bank. ? array ? within each memory bank, ther e are one (or more) flash arra y instantiations. recall the maximum capacity of the low-cost array is 512 kb, so devices with larger flash memory bank sizes require multiple instantiations of the array. within a bank, the array in stantiations are named array0, array1, etc. since the pflash2p_lca m odule supports interface signals for each bank, it is the responsibility of the soc design to provide the required address decoding, control generation and read data muxing when ther e are multiple arrays within a bank. regardless of the number of array instantiations or the number of populated banks, the operating configuration of the pflash2p_lca is defined by the regist er values contained in bank0 array0. ? page ? this value defines the number of bits read fr om the flash array in a single access. for this controller and memory, the page size is 128 bits (16 bytes). the nomenclature ?page buffers and ?line buffers? are used interchangeably. from an architectural and programming model persp ective, there are two ?c onfiguration variables? associated with the pflash2p_lca. these variables define the 2 ahb input ports (p0 and p1) initiating transactions and the three destination flash memory banks (b0, optional b1, b2). the following abbreviations for these variable s are used throughout the document:
pxd10 microcontroller reference manual, rev. 1 17-88 freescale semiconductor preliminary?subject to change without notice p0 ahb port 0 p1 ahb port 1 b0, bk0 flash memory bank0 b1, bk1 flash memory bank1 (optional) b2, bk2 flash memory bank2 b02 flash memory banks 0 and 2 finally since the page buffe rs and temporary holding regi sters are associated with both an ahb input port and a flash bank, they use a bx_py nomenclature. for example, the b0_p0 page buffer refers to the bank0, port 0 storage elements. 17.4.1.1 overview the pflash2p_lca supports a 32-bit data bus width at th e two ahb ports and c onnections to 128-bit read data interfaces from three memory banks , where each bank contains one (or more) instantiations of the low-cost flash memory array. typically, flash bank0 is connected to the first code flash memory, bank2 is connected to a second code flas h memory, and bank1 is connected to the optional data flash memory. the memory controller capabilities vary between the banks with each bank?s f unctionality optimized for the typical use cases associated with the attached flash memory. as an ex ample, the pflash2p_lca logic associated with ba nk0 contains 2 four-entry ?page? buffers, one for each ahb input port, where each buffer entry contains 128 bits of data (1 flash page) plus an asso ciated controller which prefetches sequential lines of data from the fl ash array into the buffer. this stru cture is repeated for bank2, providing a total of four copies of the 4-en try page buffer. the cont roller logic associated wi th bank1 is simpler and only supports two 128-bit re gisters (again, one for e ach ahb port) which serve as temporary page holding registers and no support of a ny prefetching. prefetch buffe r hits from any of the pa ge buffers or temporary holding registers support zero-wait ah b data phase responses. ahb read requests which miss the buffers generate the needed flash array access and the read data is forwarded to the ahb port upon completion, typically incurring two wait-states at an operating frequenc y of 60 - 64 mhz. the logic of the pflash2p_lca is structured to s upport simultaneous ahb accesses from the two ports fully in parallel when the references are targeted to different memory banks. if simultaneous ahb accesses reference the same bank, then arbitratio n logic within the pflash2p_lca determ ines the order the references are granted access to the bank. this memory controller is optimi zed for applications where a cachel ess processor core, such as the e200z0h, is connected through the platform to on- chip memories, e.g., flash and ram, where the processor and platform operate at the same fre quency. for these applicati ons, the 2-stage pipeline amba-ahb system bus is effectivel y mapped directly into stages of the processor?s pipeline and zero wait-state responses for most me mory accesses are critical for provi ding the required level of system performance. 17.4.1.2 features the following list summarizes the key features of the pflash2p_lca: ? triple bank interfaces support up to a total of 16 mbytes of flas h memory, partitioned as two 4 mbyte code banks (0, 2) and a sepa rate optional 8 m byte data bank (1)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-89 preliminary?subject to change without notice ? dual ahb input port interfaces support a 32-bit data bus. all ahb aligned and unaligned reads within the 32-bit container are supported. only aligned word writes are supported. ? array interfaces s upport a 128-bit read data bus and a 64-bit write data bus for each of the 3 banks ? internal hardware structure supports fully concur rent accesses from the du al ahb input ports when accessing different flash banks ? if the ahb ports reference the sa me flash bank, there is arbitrat ion logic which determines the order the accesses are gr anted access to the bank ? programmable arbitration allo ws the user to select fi xed priority or round-robin ? total flash page storage in the pflash2p_lc a includes four 4-entry page buffers (b0_p0, b0_p1, b2_p0, b2_p1) and two 128-bit temporar y holding registers (b1_p0, b1_p1). ? each ahb input port provides configurable and independent read buffering and page prefetch support for banks 0 and 2 ? each ahb input port includes f our page read buffers (each 128 bits wide) and a prefetch controller to support single-cycle read responses (zero ahb data phase wa it-states) for hits in the buffers. the buffers implement a least-r ecently-used replacement algorithm to maximize performance. ? each ahb input port inte rfaces to the optional data flash (b ank1) includes a 128-bit register to temporarily hold a single flash page. this l ogic supports single-cycle read responses (zero ahb data phase wait-states) for accesses that hit in the holding register. there is no support for prefetching associated with this bank. ? programmable response for read-while-write se quences including support for stall-while-write, optional stall notification interr upt, optional flash operation abort, and optional abort notification interrupt ? separate and independent configurable access ti ming (common settings for banks 0 and 2, separate settings for bank1) to support use across a wide range of platforms and frequencies ? support of address-based read access timing for emulati on of other memory types ? support for reporting of single- and multi-bit flash ecc events ? typical operating configuration loaded into programming model by system reset figure 17-43 shows a simplified block diagram of the pflash2p_lca memory controller.
pxd10 microcontroller reference manual, rev. 1 17-90 freescale semiconductor preliminary?subject to change without notice figure 17-43. pflash2p_lca memo ry controller block diagram platform flash controller (pflash2p_lca) ahb-lite 2v6 bk0_fl_wdata p1_hrdata p0_hwdata bk0_fl_rdata hdt bk0_fl_addr, 24 dual-port p0_hrdata p0_haddr+hattr interface p1_haddr+hattr p1_hwdata config control array0_biu0_regout[31:0] array0_biu1_regout[31:0] array0_biu2_regout[31:0] array0_biu3_regout[31:0] 128 64 control bk1_fl_wdata bk1_fl_rdata bk1_fl_addr, 24 128 64 control bk2_fl_wdata bk2_fl_rdata bk2_fl_addr, 24 128 64 control b2_p1 4x128 b2_p0 4x128 b1_p1 1x128 b1_p0 1x128 b0_p1 4x128 b0_p0 4x128 triple-bank flash interface
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-91 preliminary?subject to change without notice 17.4.1.3 modes of operation the pflash2p_lca module does not support any special modes of operation. its operation is driven from the amba-ahb memory references it receives from the platform?s bus masters. its configuration is defined by the setting of it s programming model registers, physically located as part of the flash array modules. 17.4.2 external signal descriptions the pflash2p_lca does not dir ectly interface with any extern al signals. as shown in figure 17-42 and figure 17-43 , its primary internal interfac es include two input connections from amba-ahb crossbar (or memory protection unit) slave ports and output connections wi th up to three banks (2 code and 1 data) of flash memory, each containing one or more instantiations of the low-co st flash array. additionally, the operating configuration for the pflash2p_lca is defined by the contents of certain bank0 array0 registers which are inputs to the module. a summary of the major pflash2p_lca internal connections is shown in table 17-61 . 17.4.3 memory map and register definition there are two memory maps associated with the pflash2p_lca: one for the flash memory space and another for the program-visible cont rol and configuration registers. the flash memory space is accessed via the amba-ahb ports while the program-visible registers are acces sed via the slave peripheral bus. details on both memory spaces are provided in section 17.4.3.1, memory map ?. there are no program-visible regist ers that physically reside inside the pflash2p_lca. rather, the pflash2p_lca receives control and configuration in formation from the flash array controller(s) to determine the operating conf iguration. these are part of the flash array?s co nfiguration registers mapped into its slave peripheral (ips) addr ess space but are described here. 17.4.3.1 memory map first, consider the flash memory space accessed vi a transactions from the pflash2p_lca?s ahb ports. to support the three separate flas h memory banks, the pflash2p_lca c ontroller uses address bits 23 and 19 ( haddr[23, 19] ) to steer the access to the appropriate memory bank. the address decode allocates two 4 mbyte spaces for bank0 and bank2 and an 8 mbyte space for bank1. in addition to the actual flash table 17-61. pflash2p_lca module connections pflash2p_lca connection description input p0 processor core input p1 non-core masters output b0 bank0, code flash output b1 bank1, data flash output b2 bank2, code flash
pxd10 microcontroller reference manual, rev. 1 17-92 freescale semiconductor preliminary?subject to change without notice memory regions, there are shadow and test sectors included in the system memory map. the program-visible control and configur ation registers associated with each memory array are included in the slave peripheral address regi on. the system memory map defines up to 4 code flash arrays and 1 data flash array, although the address space for 3 additiona l data flash arrays is reserved. see table 17-62 . table 17-62. pflash2p_lca decodes for flash-related regions in the system memory map start address end address size [kb] region 0x0000_0000 0x0007_ffff 512 bank0 = code flash array 0 0x0008_0000 0x000f_ffff 512 bank2 = code flash array 1 0x0010_0000 0x0017_ffff 512 bank0 = reserved for code flash array 2 0x0018_0000 0x001f_ffff 512 bank2 = reserved for code flash array 3 0x0020_0000 0x0027_ffff 512 bank0 = code flash array 0: shadow sector 0x0028_0000 0x002f_ffff 512 bank2 = c ode flash array 1: shadow sector 0x0030_0000 0x0037_ffff 512 bank0 = reserved for code flash array 2: shadow sector 0x0038_0000 0x003f_ffff 512 bank2 = reserved for code flash array 3: shadow sector 0x0040_0000 0x0047_ffff 512 bank0 = code flash array 0: test sector 0x0048_0000 0x004f_ffff 512 bank2 = c ode flash array 1: test sector 0x0050_0000 0x0057_ffff 512 bank0 = reserved for code flash array 2: test sector 0x0058_0000 0x005f_ffff 512 bank2 = reserved for code flash array 3: test sector 0x0060_0000 0x007f_ffff 2048 reserved 0x0080_0000 0x0087_ffff 512 data flash array 0 0x0088_0000 0x008f_ffff 512 reserved for data flash array 1 0x0090_0000 0x0097_ffff 512 reserved for data flash array 2 0x0098_0000 0x009f_ffff 512 reserved for data flash array 3 0x00a0_0000 0x00a7_ffff 512 data flash array 0: shadow sector 0x00a8_0000 0x00af_ffff 512 reserved for data flash array 1: shadow sector 0x00b0_0000 0x00b7_ffff 512 reserved for data flash array 2: shadow sector 0x00b8_0000 0x00bf_ffff 512 reserved for data flash array 3: shadow sector 0x00c0_0000 0x00c7_ffff 512 data flash array 0: test sector 0x00c8_0000 0x00cf_ffff 512 reserved for data flash array 1: test sector 0x00d0_0000 0x00d7_ffff 512 reserved for data flash array 2: test sector 0x00d8_0000 0x00df_ffff 512 reserved for data flash array 3: test sector 0x00e0_0000 0x00ff_ffff 2048 reserved 0x0100_0000 0x1fff_ffff 507904 emulation mapping 0xffe8_8000 0xffe8_bfff 16 code flash array 0 configuration 1 0xffe8_c000 0xffe8_ffff 16 data flash array 0 configuration 1
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-93 preliminary?subject to change without notice for additional information on the address-based read access timing for emulation of other memory types, see section 17.4.4.12, wait-state emulation ?. next, consider the memory map associated wi th the control and configuration registers. there are multiple registers that control operation of the pflash2p_lca. these registers are generically defined as ?bus interface unit n (biu n ) register? in the flash array documentation, where n = 0,1,2,3 and are to be only referenced with 32-bit accesses. note the first two flash array re gisters (biu0, biu1) are reset to an soc-defined value, while the remaining two array registers (biu2, bi u3) are loaded at reset from specific locations in the array?s shadow region. regardless of the number of populated banks or the number of flash arrays included in a given bank, the configuration of the pflash2p_lca is wholly spec ified by the biu registers associated with bank0 array0 . these register settings defi ne the operating behavior of all flash banks; it is recommended that the biu registers for all physically-present ar rays be set to th e bank0 array0 values. ? note: to perform program and erase operations, the control registers in the actual referenced flash array must be programmed, but the configuration of the pflash2p_lc a module is defined by the biun registers of bank0 array0. the 32-bit memory map for the pflash2p_ lca control registers is shown in table 17-63 . 17.4.3.2 register descriptions this section details the individua l registers of the pflash2p_lca. to be consistent with the flash documentation, this description uses a lsb=0 vector bit numbering convention . 0xffeb_0000 0xffeb_3f ff 16 code flash array 1 configuration 2 0xffeb_4000 0xffeb_7fff 16 reserved fo r code flash array 2 configuration 2 0xffeb_8000 0xffeb_bfff 16 reserved for code flash array 3 configuration 2 1 this region is also aliased to address 0xc3f8_nnnn. 2 this region is also aliased to address 0xc3fb_nnnn. table 17-63. pflash2p_lca 32-bit memory map address register acces s reset value location 0xffe8_8000 + 0x01c platform flash configuration re gister 0 (pfcr0) r/w 0x1085_93ed on page 94 0xffe8_8000 + 0x020 platform flash configuration register 1 (pfcr1) r/w 0x1085_8181 on page 98 0xffe8_8000 + 0x024 platform flash access protection register (pfapr) r/w 0xffff_fff f on page 100 table 17-62. pflash2p_lca decodes for flash-related regions in the system memory map (continued) start address end address size [kb] region
pxd10 microcontroller reference manual, rev. 1 17-94 freescale semiconductor preliminary?subject to change without notice within the pflash2p_lca's programming model, there are a variety of control and configuration fields. some are associated with the operati ng configuration of the memory banks, while others are related to the behavior of the ahb master ports. due to limitations in the availabl e register bits in th e programming model, the pflash controllers (both the single and dual-ported versions) do not provide completely symmetri c capabilities for the various memory banks. in fact, the pflash2p_lca groups togeth er the attributes of the two code flash arrays attached to bank0 and bank2 of the c ontroller while the configuration of the data flash (bank1) is treated separately. first, consider the operating configur ation of the flash banks. in particul ar, there are 4 unique configuration fields that are associated with a bank. these include all the parame ters associated wi th the timing (read and write wait states, address pipeline control) as well as the read-while-write control field. accordingly, the programming model supports two se parate sets of these 4 fields: one for banks 0 and 2 in pfcr0, and another for bank1 in pfcr1: // per memory bank configuration controls b02_apc, b1_apc // address pipeline control b02_wwsc, b1_wwsc // write wait state control b02_rwsc, b1_rwsc // read wait state control b02_rwwc, b1_rwwc // read-while-write control where b02 is used to refer to configuration and cont rol information common to banks 0 and 2 while b1 refers to bank1. second, there are a total of 6 confi guration fields that relate to the operation of the pflash2p_lca?s page buffers. these fields are defined on a ?per port? basis since the control needs to be associated with the ahb master port and not the destination flash bank . in addition, recall that bank1, connected to the data flash, does not support prefetchi ng, etc., so the configuration contro ls for that bank are considerably reduced compared to banks 0 a nd 2. the resulting fields are: // per ahb master port configuration controls b02_p0_bcfg, b02_p1_bcfg // page buffer configuration b02_p0_dpfen, b02_p1_dpfen // data prefetch enable b02_p0_ipfen, b02_p1_ipfen // inst prefetch enable b02_p0_pflim, b02_p1_pflim // page buffer prefetch limit b02_p0_bfen, b02_p1_bfen // page buffer enable for banks 0,2 b1_p0_bfen, b1_p1_bfen // page buffer enable for bank1 all these fields are located in the pf cr0 and pfcr1 registers described below. 17.4.3.2.1 platform flash confi guration register 0 (pfcr0) this register defines the configur ation associated with flash memory banks 0 and 2. collectively, this corresponds to the ?code flash? and the operating conf iguration defined by certain fields applies to both
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-95 preliminary?subject to change without notice memory banks. additionally, it include s fields that provide specific information for the two separate ahb ports (p0 and p1). the register is described below in figure 17-44 and table 17-64 . offset 0x01c access: read/write 0123456789101112131415 r b02_apc b02_wwsc b02_rwsc b02_r wwc w reset0001000010000101 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r b02_r wwc b02_p1_bcfg b02_p 1_dpf e b02_p 1_ipf e b02_p1_pflm b02_p 1_bfe b02_r wwc b0_p0_bcfg b02_p 0_dpf e b02_p 0_ipf e b02_p0_pflm b02_p 0_bfe w reset1001001111101101 figure 17-44. pflash configur ation register 0 (pfcr0) table 17-64. pflash configurati on register 0 field descriptions field description b02_apc bank0+2 address pipelining control. this field is used to control the number of cycles between flash array access requests. this field must be set to a value appropriate to the operating frequency of the pflash. the required settin gs are documented in table 17-70 . higher operating frequencies require non-zero settings for this field for proper flash operation. this field is set to 0b00010 by hardware reset. 00000 accesses may be initiated on consecutive (back-to-back) cycles 00001 access requests require one additional hold cycle 00010 access requests require two additional hold cycles ... 11110 access requests require 30 additional hold cycles 11111 access requests require 31 additional hold cycles b02_wwsc bank0+2 write wait state control. this field is used to control the number of wait-states to be added to the flash array access time for writes. this field must be set to a value appropriate to the operating frequency of the pflash. the requi red settings are documented in table 17-70 . higher operating frequencies require non-zero settings for this field for proper flash operation. this field is set to 0b00010 by hardware reset. 00000 no additional wait-states are added 00001 1 additional wait-state is added 00010 2 additional wait-states are added ... 111111 31 additional wait-states are added
pxd10 microcontroller reference manual, rev. 1 17-96 freescale semiconductor preliminary?subject to change without notice b02_rwsc bank0+2 read wait state control. this field is used to control the number of wait-states to be added to the flash array access time for reads. this field must be set to a value corresponding to the operating frequency of the pflash and the actual read access time of the pflash. the required settings are documented in the so c specification. higher operating frequencies require non-zero settings for this field for proper flash operation. 0 mhz, < 23 mhz apc=rwsc=0 23 mhz, < 45 mhz apc=rwsc=1 45 mhz, < 68 mhz apc=rwsc=2 68 mhz, < 90 mhz apc=rwsc=3 this field is set to 0b00010 by hardware reset. 00000 no additional wait-states are added 00001 1 additional wait-state is added 00010 2 additional wait-states are added ... 111111 31 additional wait-states are added b02_rwwc bank0+2 read-while-write control. this 3-bit field defines the controller response to flash reads while the array is busy with a program (write) or erase operation. 0-- terminate any attempted read whil e write/erase with an error response 111 generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable the abort + abort notification interrupt 110 generate a bus stall for a read while write/eras e, enable the stall notification interrupt, disable the abort + abort notification interrupt 101 generate a bus stall for a read while write/erase, enable the operation abort, disable the abort notification interrupt 100 generate a bus stall for a read while write/erase, enable the operation abort and the abort notification interrupt this field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the abort and notification interrupts. b02_p1_bcfg bank0+2, port 1 page buffer configuration. this field controls the conf iguration of the four page buffers in the pflash controller. the buffers can be organized as a ?pool? of available resources, or with a fixed partition between instruction and data buffers. if enabled, when a buffer miss occurs, it is alloca ted to the least-recently-u sed buffer within the group and the just-fetched entry then marked as most-recently-use d. if the flash access is for the next-sequential line, the buffer is not marked as most-recently-used until th e given address produces a buffer hit. 00 all four buffers are available for any flash access , that is, there is no partitioning of the buffers based on the access type. 01 reserved 10 the buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. 11 the buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. table 17-64. pflash configuration regi ster 0 field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-97 preliminary?subject to change without notice b02_p1_dpfe bank0+2, port 1 data prefetch enable. this field enables or disables prefetching initiated by a data read access. this field is set by hardware reset. 0 no prefetching is triggered by a data read access 1 if page buffers are enabled (b02_p1_bfe = 1), prefetching is triggered by any data read access b02_p1_ipfe bank0+2, port 1 instruction prefetch enable. this fi eld enables or disables prefetching initiated by an instruction fetch read access. this field is cleared by hardware reset. 0 no prefetching is triggered by an instruction fetch read access 1 if page buffers are enabled (b02_p1_bfe = 1), pr efetching is triggered by any instruction fetch read access b02_p1_pflm bank0+2, port 1 prefetch limit. this field cont rols the prefetch algorithm used by the pflash controller. this field defines the prefetch behavior. in all situations when enabled, only a single prefetch is initiated on each buffer miss or hit. this field is set to 2b01 by hardware reset. 00 no prefetching is performed. 01 the referenced line is prefetched on a buffer miss, that is, prefetch on miss . 1- the referenced line is prefetched on a buffer miss, or the next sequential page is prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit . b02_p1_bfe bank0+2, port 1 buffer enable. this bit enables or disables page buffer read hits. it is also used to invalidate the buffers. this bit is set by hardware reset, enabling the page buffers. 0 the page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1 the page buffers are enabled to satisfy read requests on hits. buffer valid bits may be set when the buffers are successfully filled. b02_p0_bcfg bank0+2, port 0 page buffer configuration. this field controls the conf iguration of the four page buffers in the pflash controller. the buffers can be organized as a ?pool? of available resources, or with a fixed partition between instruction and data buffers. if enabled, when a buffer miss occurs, it is alloca ted to the least-recently-u sed buffer within the group and the just-fetched entry then marked as most-recently-use d. if the flash access is for the next-sequential line, the buffer is not marked as most-recently-used until th e given address produces a buffer hit. 00 all four buffers are available for any flash access , that is, there is no partitioning of the buffers based on the access type. 01 reserved 10 the buffers are partitioned into two groups with buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. 11 the buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. this field is set to 2b11 by hardware reset. b02_p0_dpfe bank0+2, port 0 data prefetch enable. this field enables or disables prefetching initiated by a data read access. this field is cleared by hardware reset. 0 no prefetching is triggered by a data read access 1 if page buffers are enabled (b0_p0_bfe = 1), prefetching is triggered by any data read access table 17-64. pflash configuration regi ster 0 field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 17-98 freescale semiconductor preliminary?subject to change without notice 17.4.3.2.2 platform flash confi guration register 1 (pfcr1) this register defines the configurat ion associated with flash memory bank1. this typically corresponds to the optional ?data flash?. if bank1 is not present, the contents of this re gister are ignored. the register is described below in figure 17-45 and table 17-65 . b02_p0_ipfe bank0+2, port 0 instruction prefetch enable. this fi eld enables or disables prefetching initiated by an instruction fetch read access. this field is set by hardware reset. 0 no prefetching is triggered by an instruction fetch read access 1 if page buffers are enabled (b0_p0_bfe = 1), pr efetching is triggered by any instruction fetch read access b02_p0_pflm bank0+2, port 0 prefetch limit. this field cont rols the prefetch algorithm used by the pflash controller. this field defines the prefetch behavior. in all situations when enabled, only a single prefetch is initiated on each buffer miss or hit. this field is set to 2b10 by hardware reset. 00 no prefetching is performed. 01 the referenced line is prefetched on a buffer miss, that is, prefetch on miss . 1- the referenced line is prefetched on a buffer miss, or the next sequential page is prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit . b02_p0_bfe bank0+2, port 0 buffer enable. this bit enables or disables page buffer read hits. it is also used to invalidate the buffers. this bit is set by hardware reset. 0 the page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1 the page buffers are enabled to satisfy read requests on hits. buffer valid bits may be set when the buffers are successfully filled. offset 0x020 access: read/write 0123456789101112131415 r b1_apc b1_wwsc b1_rwsc b1_r wwc w reset0001000010000101 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r b1_r wwc 000000 b1_p1 _bfe b1_r wwc 000000 b1_p0 _bfe w reset1000000110000001 figure 17-45. pflash configur ation register 1 (pfcr1) table 17-64. pflash configuration regi ster 0 field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-99 preliminary?subject to change without notice table 17-65. pflash configurati on register 1 field descriptions field description b1_apc bank1 address pipelining control. this field is us ed to control the number of cycles between flash array access requests. this field must be set to a value appropriate to the operating frequency of the pflash. the required settings are document ed in the soc specification. higher operating frequencies require non-zero settings for this field fo r proper flash operation. this field is set to 0b00010 by hardware reset. 00000 accesses may be initiated on consecutive (back-to-back) cycles 00001 access requests require one additional hold cycle 00010 access requests require two additional hold cycles ... 11110 access requests require 30 additional hold cycles 11111 access requests require 31 additional hold cycles this field is ignored in single bank flash configurations. b1_wwsc bank1 write wait state control. this field is used to control the number of wait-states to be added to the flash array access time for writes. this field must be set to a value appropriate to the operating frequency of the pflash. the required settings are documented in the soc specification. higher operating frequencies require n on-zero settings for this field for proper flash operation. this field is set to an appropriate value by hardware reset. this field is set to 0b00010 by hardware reset. 00000 no additional wait-states are added 00001 1 additional wait-state is added 00010 2 additional wait-states are added ... 111111 31 additional wait-states are added this field is ignored in single bank flash configurations. b1_rwsc bank1 read wait state control. this field is used to control the number of wait-states to be added to the flash array access time for reads. this field must be set to a value corresponding to the operating frequency of the pflash and the actual read access time of the pflash. the required settings are documented in the soc specificatio n. higher operating frequencies require non-zero settings for this field for proper flash operation. shown below are the maximum operating frequencies for legal apc and rwsc settings based on estimated low-cost flash access times at 150c. the integrator is strongly encouraged to verify these settings based on actual silicon results. 0 mhz, < 23 mhz apc=rwsc=0 23 mhz, < 45 mhz apc=rwsc=1 45 mhz, < 68 mhz apc=rwsc=2 68 mhz, < 90 mhz apc=rwsc=3 this field is set to 0b00010 by hardware reset. 00000 no additional wait-states are added 00001 1 additional wait-state is added 00010 2 additional wait-states are added ... 111111 31 additional wait-states are added this field is ignored in single bank flash configurations.
pxd10 microcontroller reference manual, rev. 1 17-100 freescale semiconductor preliminary?subject to change without notice 17.4.3.2.3 platform flash access protection register (pfapr) the pflash access protection register (pfapr) is used to control read and write accesses to the flash based on system master number. pref etching capabilities are defined on a per master basis. this register also defines the arbitration mode between the 2 ahb ports for the pflash2p _lca. the register is described below in figure 17-46 and table 17-66 . the contents of the register are loaded from locat ion 0x203e00 of the shadow region in the code flash (bank0) array at reset. to temporarily change the values of any of the fields in the pfapr, a write to the ips-mapped register is performed. to change the values loaded into the pfapr at reset , the word location at address 0x203e00 of the shadow region in the flash array must be programmed using the normal b1_rwwc bank1 read-while-write control. this 3-bit field defines the controller response to flash reads while the array is busy with a program (write) or erase operation. 0-- terminate any attempted read whil e write/erase with an error response 111 generate a bus stall for a read while write/erase, disable the stall notification interrupt, disable the abort + abort notification interrupt 110 generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable the abort + abort notification interrupt 101 generate a bus stall for a read while write/erase, enable the operation abort, disable the abort notification interrupt 100 generate a bus stall for a read while write/erase, enable the operation abort and the abort notification interrupt this field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the abort and notification interrupts. this field is ignored in single bank flash configurations. b1_p1_bfe bank1, port 1 buffer enable. this bit enables or disables read hits from the 128-bit holding register. it is also used to invalidate the contents of the hol ding register. this bit is set by hardware reset, enabling the use of the holding register. 0 the holding register is disabled from satisfying read requests. 1 the holding register is enabled to satisfy read requests on hits. b1_p0_bfe bank1, port 0 buffer enable. this bit enables or disables read hits from the 128-bit holding register. it is also used to invalidate the contents of the hol ding register. this bit is set by hardware reset, enabling the use of the holding register. 0 the holding register is disabled from satisfying read requests. 1 the holding register is enabled to satisfy read requests on hits. table 17-65. pflash configuration regi ster 1 field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-101 preliminary?subject to change without notice sequence of operations. the reset value shown in figure 17-46 reflects an erased or unprogrammed value from the shadow region. 17.4.4 functional description references to the pflash2p_l ca block diagram shown in figure 17-43 will assist in understanding much of the discussion in this section. the pflash2p_lca interfaces between 2 ahb-lite 2.v6 system bus mast er ports and three banks of low-cost flash memory arrays. the pflash2p_lca generates three sets of interface signals for the fl ash banks, including read and write enables, the flash array address, write size, and write data as inputs to each flash bank. the offset 0x024 access: read/write 0123456789101112131415 r 0 0 0 0 0 0 arbm m7pf d m6pf d m5pf d m4pf d m3pf d m2pf d m1pf d m0pf d w reset****** 1111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m7ap m6ap m5ap m4ap m3ap m2ap m1ap m0ap w reset1111111111111111 figure 17-46. pflash access protection register (pfapr) table 17-66. pflash access protection register field descriptions field description arbm arbitration mode. this 2-bit field controls the arbitration for pflash controllers supporting 2 ahb ports. the port arbitration mode is used only when accesses from the 2 ahb ports attempt to simultaneously reference the same flash bank. simu ltaneous references to different memory banks are processed concurrently. 00 fixed priority arbitration with ahb p0 > p1 01 fixed priority arbitration with ahb p1 > p0 1- round-robin arbitration mxpfd master x prefetch disable (x = 0,1,2,...,7). these bits control whether prefetching may be triggered based on the master number of t he requesting ahb master. this field is further qualified by the pfcrn[b02_px_dpfe, b02_px_ipfe, bx_py_bfe] bits. 0 prefetching may be triggered by this master 1 no prefetching may be triggered by this master mxap master x access protection (x = 0,1,2,...,7). t hese fields control whether read and write accesses to the flash are allowed based on the ma ster number of the initiating module. 00 no accesses may be performed by this master 01 only read accesses may be performed by this master 10 only write accesses may be performed by this master 11 both read and write accesses may be performed by this master
pxd10 microcontroller reference manual, rev. 1 17-102 freescale semiconductor preliminary?subject to change without notice pflash2p_lca captures read data from the flash banks and drives it onto the ahb. each flash bank includes data storage for fetched page s on a per ahb port basis, either in the form of 4-entry page buffers (banks 0 and 2) or a 1-entry tempor ary holding register (bank 1). pages may be prefetched in advance of being requested by the ahb interface, allowing single- cycle (zero ahb wait-state s) read data responses on buffer hits. multiple prefetch control algorithms ar e available for controlli ng page read buffer fill s. prefetch triggering may be restricted to instruction accesses only, da ta accesses only, or may be unrestricted. prefetch triggering may also be contro lled on a per-master basis. buffers may also be selectively enabled or disabl ed for allocation by instruction and data prefetch. access protections may be applied on a per-master basis for both reads a nd writes to support security and privilege mechanisms. recall the logic of the pf lash2p_lca is structured to support si multaneous ahb accesses from the two ports fully in parallel when the references are targ eted to different memory banks. if simultaneous ahb accesses reference the same bank, th en arbitration logic within the pflash2p_lca determines the order the references are granted access to the bank. for more information, see section 17.4.4.10, input port arbitration ?. 17.4.4.1 access protections the pflash2p_lca provides programmable configurab le access protections for both read and write cycles from masters via the pflash ac cess protection register (pfapr). it allows restriction of read and write requests on a per-ma ster basis. this functi onality is described in section 17.4.3.2.3, platform flash access protection re gister (pfapr) ?. detection of a protec tion violation results in an error response from the pflash2p_lca on the ahb transfer. 17.4.4.2 read cycles - buffer miss read cycles from the flash array are init iated by driving a valid access address on bkn_fl_addr[23:0] and asserting bkn_fl_rd_en for the required setup (and hold) time before (and af ter) the rising edge of hclk . the pflash2p_lca then waits for the programmed number of read wait states before sampling the read data on bkn_fl_rdata[127:0] . this data is normally stored in the l east-recently updated page read buffer for banks 0 and 2 in parallel with the requested data being forwarded to the ahb. for bank1, the data is captured in the page-wide temporar y holding register as the requested data is forwarde d to the ahb bus. timing diagrams of basic read accesse s from the flash array are shown in figure 17-47 through figure 17-50 . if the flash access was the direct result of an ahb transaction, the page buffer is marked as most-recently-used as it is being lo aded. if the flash access was the result of a speculative prefetch to the next sequential line, it is first loaded into the leas t-recently-used buffer. the status of this buffer is not changed to most-recently-used until a subsequent buffer hit occurs.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-103 preliminary?subject to change without notice 17.4.4.3 read cycles - buffer hit single cycle read responses to the ahb are possibl e with the pflash2p_lca when the requested read access was previously loaded into one of the page buffers associated w ith banks 0 and 2. in these ?buffer hit? cases, read data is returned to the ah b data phase with a zero wait-state response. likewise, the bank1 logic includes 128- bit temporary holding registers ( one per ahb port) and sequential accesses which ?hit? in these registers are also serviced with a zero wait-state response. 17.4.4.4 write cycles in a write cycle, address, write data, and cont rol signals are launched off the same edge of hclk at the completion of the first ahb data phase cycle. write cycl es to the flash array are initiated by driving a valid access address on bkn_fl_addr[23:0] , driving write data on bkn_fl_wdata[63:0] , and asserting bkn_fl_wr_en . again, the controller drives the address and control informat ion for the required setup time before the rising edge of hclk , and provides the require d amount of hold time. the pflash2p_lca then waits for the appropriate num ber of write wait-states be fore terminating the write operati on. on the cycle following the programmed wait stat e value, the pflash2p_lca asserts hready_out to indicate to the ahb port that the cycle has terminated. 17.4.4.5 error termination the pflash2p_lca follows the standard procedure wh en an ahb bus cycle is terminated with an error response. first, the pflash2p_lca asserts hresp[0] and negates hready_out to signal an error has occurred. on the following clock cycle, the pflash2p_lca asserts hready_out and holds both hresp[0] and hready_out asserted until hready_in is asserted. the first case that can cause an error response to the ahb is when an access is attempted by an ahb master whose corresponding read a ccess control or write access cont rol settings do not allow the access, thus causing a protection vi olation. in this case, the pflash2p_ lca does not initiate a flash array access. the second case that can cause an error response to th e ahb is when an access is performed to the flash array and is terminated with a flash error response. see section 17.4.4.7, flash error response operation ?. this may occur for either a read or a write operation. the third case that can cause an er ror response to the ahb is when a wr ite access is attemp ted to the flash array and is disallowed by the state of the bkn_fl_ary_access control input. this case is similar to case 1. a fourth case involves an attempte d read access while the flash array is busy doing a write (program) or erase operation if the appropriate read -while-write control fi eld is programmed for th is response. the 3-bit read-while-write control allows for immediate error termination of an attempted read, or various combinations involving stalls with optional notifi cation interrupts while prog ram/erase operations are occurring. the pflash2p_lca can also termin ate the current ahb access if hready_in is asserted before the end of the current bus access. while this circumstance should not occur, this does not result in an error condition being reported, as this be havior is initiated by the ahb master. in this circumstance, the
pxd10 microcontroller reference manual, rev. 1 17-104 freescale semiconductor preliminary?subject to change without notice pflash2p_lca control state machine completes any flash array access in pr ogress (without signaling the ahb) before handling a new access request. 17.4.4.6 access pipelining the pflash2p_lca controller does not support access pipelining since this capability is not supported by the low-cost flash array. as a result, the apc (addr ess pipelining control) fiel d is typically set to the same value as the rwsc (read wait state control) field for best performan ce, that is, bn_apc = bn_rwsc. it cannot be less than the rwsc. 17.4.4.7 flash error response operation the flash array may signal an error response by asserting bkn_fl_xfr_err to terminate a requested access with an error. this may occur due to an uncorrect able ecc error, or beca use of improper sequencing during program/erase operations. when an erro r response is received, the pflash2p_lca does not update or validate a bank 0 or 2 page read buffer nor the bank1 temporary hold ing register. an error response may be signaled on read or write operations. for more information on the specifics related to signaling of errors, including flash ecc, refer to th e low-cost flash array doc umentation. for additional information on the system registers which capture the faulting address, a ttributes, data and ecc information, see the ecsm chapter. 17.4.4.8 bank 0 and 2 page read buffers and prefetch operation the logic associated with banks 0 and 2 of the pfl ash2p_lca contains four page read buffers which are used to hold data read from the flash array. each buffer stores 4 pages (4 x 128b storage) operates independently, and is filled using a single array access. the buffers are used for both prefetch and normal demand fetches. the organization of each page buffer is described below in a pseudo-code representation. the hardware structure includes the buffer address and valid bit, along with 128 bits of page read data and several error flags. struct { // bx_py_page_buffer reg addr[23:4]; // page address reg valid; // valid bit reg rdata[127:0]; // page read data reg xfr_error; // transfer error indicator from flash array reg multi_ecc_error; // multi-bit ecc error indicator from flash array reg single_ecc_error; // single-bit correctable ecc indicator from flash array } bx_py_page_buffer[4]; given this definition, the pflash2p_lca includes four instantiati ons of the basic 4 x 128b page buffer. these are named: b0_p0, b0_p1, b2_p0 and b2_p1. for the general case, a page buffer is written at the completion of an er ror-free flash access and the valid bit asserted. subsequent fl ash accesses that ?hit? the buffer, that is, the current access address matches the address stored in the buffer, can be serviced in 0 ahb wait-states as the stored re ad data is routed from the given page buffer back to the requesting bus master.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-105 preliminary?subject to change without notice as noted in section 17.4.4.7, flash erro r response operation ?, a page buffer is not marked as valid if the flash array access terminated with any t ype of transfer error. however, the result is that flash array accesses that are tagged with a single-bit co rrectable ecc event are loaded into the page buffer and validated. for additional comments on this topic, see section 17.4.4.8.4, buffer invalidation ?. prefetch triggering is controllable on a per-master and access-type basi s. bus masters may be enabled or disabled from triggering prefetches , and triggering may be further re stricted based on whether a read access is for instruction or data. a read access to th e pflash2p_lca may trigger a prefetch to the next sequential page of array data on the first idle cycle following the request . the access address is incremented to the next-higher 16-byte boundary, and a flas h array prefetch is initiated if the data is not already resident in a page buffer. prefetched data is always loaded into th e least-recently-used buffer. buffers may be in one of six states , listed here in prioritized order: 9. invalid - the buffer contains no valid data 10. used - the buffer contains valid data which has been provided to satisfy an ahb burst type read 11. valid - the buffer contains valid data which ha s been provided to satisf y an ahb single type read 12. prefetched - the buffer contains valid data which has been prefetch ed to satisfy a potential future ahb access 13. busy ahb - the buffer is currently being used to satisfy an ahb burst read 14. busy fill - the buffer has been allocated to receive data from th e flash array, and the array access is still in progress selection of a buffer to be loaded on a miss is based on the following replacement algorithm: 1. first, the buffers are examined to determine if there are any inva lid buffers. if there are multiple invalid buffers, the one to be used is selected using a simple numeric priori ty, where buffer 0 is selected first, then buffer 1, etc. 2. if there are no invalid buffers, the least-re cently-used buffer is se lected for replacement. once the candidate page buffer has been selected, the fl ash array is accessed and re ad data loaded into the buffer. if the buffer load was in response to a miss , the just-loaded buffer is immediately marked as most-recently-used. if the buffer load was in response to a speculative fetch to the next-sequential line address after a buffer hit, the recently-used status is not changed . rather, it is marked as most-recently-used only afte r a subsequent buffer hit. this policy maximizes performance based on refere nce patterns of flash accesses and allows for prefetched data to remain valid when non-prefe tch enabled bus masters are granted flash access. multiple algorithms are available for prefetch control which trade off pe rformance versus power. they are defined by the bx_py_pflm (prefetch li mit) register field. more aggre ssive prefetching increases power slightly due to the number of wa sted (discarded) prefetches, but may increase performance by lowering average read latency. in order for prefetching to occur, a number of control bits must be enabled. specifically, the global buffer enable (bx_py_bfe) must be set, the prefetch limit (bx_py_ pflm) must be non-zero and either instruction prefetching (bx_py_ipfe) or data pref etching (bx_py_dpfe) enable d. recall the prefetch
pxd10 microcontroller reference manual, rev. 1 17-106 freescale semiconductor preliminary?subject to change without notice and buffer enables are defined on a per ahb port in the pfcr0 and pfcr1 registers. refer to section 17.4.3.2, register descriptions ? for a description of these control fields. 17.4.4.8.1 inst/data prefetch triggering prefetch triggering may be enabled for instruction reads via the bx_py_ipfe c ontrol field, while prefetching for data reads is enabled via the b x_py_dpfe control field. addi tionally, the bx_py_pflim field must also be set to enable prefetching. prefetches are never triggered by write cycles. 17.4.4.8.2 per-master prefetch triggering prefetch triggering may be also controlled for individual bus mast ers. ahb accesses indicate the requesting master via the hmaster[3:0] inputs. refer to pfapr descript ion for details on these controls. 17.4.4.8.3 buffer allocation allocation of the page read buffers is controlled via page buffer c onfiguration (bx_py_bcfg) field. this field defines the operating organization of the four page buffers. the buffe rs can be organized as a ?pool? of available resour ces (with all four buffers in the pool) or with a fixed part ition between buffers allocated to instruction or data accesses. for the fixed partition, two configurati ons are supported. in one configuration, buffers 0 and 1 are allocated for instruct ion fetches and buffers 2 a nd 3 for data accesses. in the second configuration, buffers 0, 1 and 2 are allocated fo r instruction fetches a nd buffer 3 reserved for data accesses. 17.4.4.8.4 buffer invalidation the page read buffers may be invalidate d under hardware or software control. any falling edge tran sition of the array?s bkn_fl_done signal causes the page read buffers to be marked as invalid. this input is negated by the flash array at th e beginning of all program/erase operations as well as in certain other cases. buffer i nvalidation occurs at th e next ahb non-sequentia l access boundary, but does not affect a burst from a page r ead buffer which is in progress. software may invalidate the buffers by clearing the bx_py_bfe bit, which also disables the buffers. software may then re-assert the bx_py_bfe bit to its previous state, and the buffers will have been invalidated. one special case needing software invalidation relates to page buffer ?hits? on fl ash data which was tagged with a single-bit ecc event on the original array access. recall that the page buf fer structure includes an status bit signaling the array access de tected and corrected a single-bit ecc error. on all subsequent buffer hits to this type of page data, a single-bit ec c event is signaled by the pflash2p_lca. depending on the specific hardware configurati on, this reporting of a single-bit ecc event may generate an ecc alert interrupt. in order to prevent repeated ecc alert interrupts, the page buffers need to be invalidated by software after the first notificat ion of the single-bit ecc event . finally, the buffers are invali dated by hardware on any non-sequent ial access with a non-zero value on haddr[28:24] to support wait-state emulation.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-107 preliminary?subject to change without notice 17.4.4.9 bank1 temporary holding registers recall the bank1 logic within the pflash2p_lca includes two 128- bit data registers (one for each ahb port), used for capturing read data . since this bank does not support pr efetching, the read data for the referenced address is bypassed directly back to th e ahb data bus. the page is also loaded into the appropriate temporary data register a nd subsequent accesses to this page can hit from this register, if it is enabled (b1_py_bfe). the organization of the temporary holding register is described below in a pseudo-code representation. the hardware structure includes the buf fer address and valid bit, along with 128 bits of page read data and several error flags and is the same as an individual bank 0 or 2 page buffer. struct { // b1_py_page_buffer reg addr[23:4]; // page address reg valid; // valid bit reg rdata[127:0]; // page read data reg xfr_error; // transfer error indicator from flash array reg multi_ecc_error; // multi-bit ecc error indicator from flash array reg single_ecc_error; // single-bit correctable ecc indicator from flash array } b1_py_page_buffer; given this definition, the pflash2p_lca includes two instantiations of this temporary holding register for bank 1. these are named: b1_p0 and b1_p1. for the general case, a temporary hold ing register is written at the comp letion of an error-free flash access and the valid bit asserted. s ubsequent flash accesses that ?hit? the buffer, that is , the current access address matches the address stored in the temporary holding regi ster, can be serviced in 0 ahb wait-states as the stored read data is routed from the temporar y register back to the requesting bus master. the contents of the holding re gister are invalidated by the falling edge transition of b1_fl_done and on any non-sequential access with a non-zero value on haddr[28:24] (to support wait-state em ulation) in the same manner as the bank0 page buffers. addi tionally, the b1_py_bfe register bi t can be cleared by software to invalidate the contents of the holding register. as noted in section 17.4.4.7, flash error response operation ?, the temporary holding register is not marked as valid if the flash array acc ess terminated with any type of tran sfer error. however, the result is that flash array accesses that are tagged with a si ngle-bit correctable ecc event are loaded into the temporary holding register and validated. accordingl y, one special case needing software invalidation relates to holding register ?hits? on flash data which was tagged wi th a single-bit ecc event. depending on the specific hardware configurati on, the reporting of a single-bit ecc event may generate an ecc alert interrupt. in order to prevent repeated ecc alert interrupt s, the temporary holding registers need to be invalidated by software after the first notification of the single-bit ecc event . each bank1 temporary holding register effect ively operates like a single page buffer. 17.4.4.10 input port arbitration for maximum system performance, the pflash2p_lc a fully supports concurrent flash accesses from the two ahb input ports when the refe rences are targeted to different fl ash banks. this is expected to be
pxd10 microcontroller reference manual, rev. 1 17-108 freescale semiconductor preliminary?subject to change without notice the typical use-case where ahb p0 (the processor core) mainly accesses bank0 while the non-core ahb masters on p1 mainly reference bank2. in the event that both ahb ports refe rence the same flash bank, there is arbitration logic in the module to determine the order the references are granted access to th e targeted bank. the 2-bit pfapr[arbm] field defines the port arbitration mode and this field can de fine a fixed priority scheme with either p0 > p1 or p1 > p0 or a round-robin mode where the port given pr iority simply toggles on every simultaneous bank conflict. 17.4.4.11 read-while -write functionality the pflash2p_lca supports various programmable responses for re ad accesses while the flash is busy performing a write (program) or eras e operation. for all situations, th e pflash2p_lca uses the state of the flash array?s bkn_fl_done output to determine if it is busy performing some type of high-voltage operation, namely, if bkn_fl_done = 0, the array is busy. specifically, there are two 3-bit r ead-while-write (bn_rwwc) control register fiel ds which define the pflash2p_lca?s response to these types of access sequences. there are 5 uni que responses that are defined by the bn_rwwc setting: one immediately reports an error on an attempted read and four settings that support various stall-while- write capabilities. consider th e details of these settings. ? bn_rwwc = 0b0-- ? for this mode, any attempted fl ash read to a busy array is imme diately terminated with an ahb error response and the read is blocked in the controller and not seen by the flash array. ? bn_rwwc = 0b111 ? this defines the basic st all-while-write capabili ty and represents the default reset setting. for this mode, the pflash2p_lca module simply stal ls any read reference until the flash has completed its program/erase opera tion. if a read access arrives while the array is busy or if a falling-edge on bkn_fl_done occurs while a read is still in progress, the ah b data phase is stalled by negating hready_out and saving the address and attr ibutes into holding registers. once the array has completed its program/erase operation, the pflash2p_lca uses the saved address and attribute info rmation to create a pseudo addr ess phase cycle to ?retry? the read reference and sends the regist ered information to the array as bkn_fl_rd_en is asserted. once the retried address phase is complete, the read is processed norma lly and once the data is valid, it is forwarded to the ahb bus and hready_out negated to terminate the system bus transfer. ? bn_rwwc = 0b110 ? this setting is similar to the basic stall- while-write capability pr ovided when bn_rwwc = 0b111 with the added ability to ge nerate a notification interrupt if a read arrives while the array is busy with a program/erase operation. there are two notification interrupts, one for each bank. ? bn_rwwc = 0b101 ? again, this setting provides the ba sic stall-while-write capability with the added ability to abort any program/erase operation if a read access is initiated. for th is setting, the read request is captured and retried as desc ribed for the basic stall-whil e-write, plus th e program/erase operation is aborted by the pflas h2p_lca?s assertion of the bkn_fl_abort signal. the
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-109 preliminary?subject to change without notice bkn_fl_abort signal remains asserted until bkn_fl_done is driven high. for this setting, there are no notification inte rrupts generated. ? bn_rwwc = 0b100 ? this setting provides the basic stall-while-write capability wi th the ability to abort any program/erase operation if a read access is initiated plus the gene ration of an abort notification interrupt. for this setting, the r ead request is captured and retr ied as described for the basic stall-while-write, the program/erase operati on is aborted by the pfl ash2p_lca?s assertion of the bkn_fl_abort signal and an abort notification inte rrupt generated. there are two abort notification interrupts, one for each bank. as detailed above, there are a total of 4 interrupt requests associated with the stall-while-write functionality. these interrupt request s are captured as part of ecsm?s interrupt register and logically summed together to form a single re quest to the interrupt controller. for example timing diagrams of the stall-while-write and ab ort-while-write operations, see figure 17-51 and figure 17-52 respectively. 17.4.4.12 wait-state emulation emulation of other memory array timings are s upported by the pflash2p_lca on read cycles to the flash. this functionality may be useful to maintain the access timing for blocks of memory which were used to overlay flash blocks for the purpose of system calibration or tuning during code development. the pflash2p_lca inserts additional wait -states according to the values of haddr[28:24] . when these inputs are non-zero, additional cycles are added to ahb read cycles. wr ite cycles are not affected. in addition, no page read buffer prefetches are initiated, a nd buffer hits are ignored. table 17-68 and table 17-69 show the relationship of haddr[28:24] to the number of additional primary wait-states. these wait-states are appl ied to the initial access of a burst fetch or to single-beat read accesses on the ahb system bus. table 17-67. pflash2p_lca stall-while-write interrupts mir[n] interrup t description ecsm.mir[7] platform flash bank0 abort notification, mir[fb0ai] ecsm.mir[6] platform flash bank0 stall notification, mir[fb0si] ecsm.mir[5] platform flash bank1 abort notification, mir[fb1ai] ecsm.mir[4] platform flash bank1 stall notification, mir[fb1s1]
pxd10 microcontroller reference manual, rev. 1 17-110 freescale semiconductor preliminary?subject to change without notice note that the wait-state specifica tion consists of two components: haddr[28:26] and haddr[25:24] and effectively extends the flash read by (8 * haddr[25:24] + haddr[28:26] ) cycles. table 17-69 shows the relationship of haddr[25:24] to the number of additional wait-states. these are applied in addition to those specified by haddr[28:26] and thus extend the total wait-state specification capability. 17.4.4.13 timing diagrams since pflash2p_lca controller is typically used in platform configurations with a cacheless core, the operation of the processor accesses to the platform me mories, e.g., flash and sram, plays a major role in the overall system performance. given the core/platform pipeline structure, the platform?s memory controllers (pflash, pram) are desi gned to provide a zero wait-state data phase response to maximize processor performance. th e following diagrams illustrate operation of various cycle ty pes and responses referenced earlier in this chap ter including stal l-while-read ( figure 17-51 ) and abort-while-read ( figure 17-52 ) diagrams. table 17-68. additional wait-state encoding memory address haddr[28:26] additional wait-states 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 table 17-69. extended additional wait-state encoding memory address haddr[25:24] additional wait-states (added to those specified by haddr[28:26]) 00 0 01 8 10 16 11 24
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-111 preliminary?subject to change without notice figure 17-47. 1-cycle access, no buffering, no prefetch nonseq seq seq addr y addr y+4 addr y+12 c(y) c(y+4) okay okay okay okay okay okay okay okay y c(y) c(y+4) read, no buffering, no prefetch, apc=0, rwsc=0, pflm=0 123456 78 addr y seq addr y+8 y+4 y+8 c(y+8) c(y+12) y+12 addr y+4 addr y+8 c(y+8) c(y+12) hclk htrans haddr, hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_rd_en bkn_fl_wr_en bkn_fl_rdata addr+12
pxd10 microcontroller reference manual, rev. 1 17-112 freescale semiconductor preliminary?subject to change without notice figure 17-48. 3-cycle access, no prefetch, buffering disabled nonseq seq seq addr y addr y+4 addr y+12 c(y) c(y+4) okay okay okay okay okay okay okay okay y c(y) burst read, buffer miss, no prefetch, apc=2, rwsc=2, pflm=0 12345678 addr y seq addr y+8 y+4 addr y+4 c(y+4) y+8 addr y+8 hclk htrans haddr, hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_rd_en bkn_fl_wr_en bkn_fl_rdata bkn_fl_xfr_err
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-113 preliminary?subject to change without notice figure 17-49. 3-cycle access, no prefetch, buffering enabled nonseq seq seq addr y addr y+4 addr y+12 c(y) c(y+4) c(y+8) c(y+12) okay okay okay okay okay okay okay okay y c(y) burst read, buffer miss, no prefetch, apc=2, rwsc=2, pflm=0 123456 78 addr y seq addr y+8 hclk htrans haddr, hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_rd_en bkn_fl_wr_en bkn_fl_rdata bkn_fl_xfr_err
pxd10 microcontroller reference manual, rev. 1 17-114 freescale semiconductor preliminary?subject to change without notice figure 17-50. 3-cycle access, prefetch and buffering enabled nonseq seq seq addr y addr y+4 addr y+12 c(y) c(y+4) c(y+8) c(y+12) okay okay okay okay okay okay okay okay y c(y) burst read, buffer miss, pref etch, apc=2, rwsc=2, pflm=2 1234567 8 addr y seq addr y+8 y+16 c(y+16) seq seq addr y+16 addr y+20 c(y+16) y+32 addr y+16 addr y+32 hclk htrans haddr, hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_rd_en bkn_fl_wr_en bkn_fl_rdata bkn_fl_xfr_err
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-115 preliminary?subject to change without notice figure 17-51. 3-cycle access, stall-and-retry with bn_rwwc = 11x as shown in figure 17-51 , the 3-cycle access to address y is in terrupted when an operation causes the bkn_done signal to be negated signaling that the array ba nk is busy with a high-vol tage program or erase event. eventually, this array operation completes (at the e nd of cycle 4) and bkn_done returns to a logical 1. in cycle 6, the pflash2p_lca module retries the read to address y which was interrupted by the negation of bkn_done in cycle 3. note that throughout cycles 2- 9, the ahb bus pipeline is stalled with a read to address y in the ahb data phase and a read to address y+4 in the a ddress phase. depending on the state of the least-significant-bit of the bn_rwwc control field, the ha rdware may also signal a stall notification interrupt (if bn_rwwc = 110). the stall notification interrupt is shown as the optional assertion of ecsm?s mir[fbnsi] (flash bank n stall interrupt). nonseq seq addr y addr y+4 c(y) c(y+4) okay okay okay okay okay okay okay okay y c(y) burst read, stall-and-retry, apc=2, rwsc=2, pflm=2 123456 7 8 addr y seq addr y+8 y+16 y+16 y okay okay addr y+16 addr y ( retry ) hclk htrans haddr, hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_rd_en bkn_fl_wr_en bkn_fl_rdata bkn_fl_xfr_err bkn_done bkn_abort ecsm_mir[fbnsi] ecsm_mir[fbnai] 9 10
pxd10 microcontroller reference manual, rev. 1 17-116 freescale semiconductor preliminary?subject to change without notice figure 17-52. 3-cycle access, abort-and-retry with bn_rwwc = 10x figure 17-52 shows the abort-while-write t iming diagram. in this example, the 3-cycle access to address y is interrupted when an operation causes the bkn_done signal to be negated si gnaling that the array bank is busy with a high-voltage progr am or erase event. based on th e setting of bn_rwwc, once the bkn_done signal is detected as negated, the pflash2p_lca asserts bkn_abort which forces the flash array to cancel the high-voltage progr am or erase event. the array operation completes (at the e nd of cycle 4) and bkn_done returns to a logical 1. it should be not ed that the time spent in cycle 4 for figure 17-52 is considerably less than the time in the same cycle in figure 17-51 (because of the abort operation). in cycle 6, the pflash2p_lca module retries the read to a ddress y which was interrupted by the negation of bkn_done in cycle 3. note that th roughout cycles 2-9, the ahb bus pipeline is stalled with a read to address y in the ahb data phase and a read to address y+ 4 in the address phase. depending on the state of the least-significant-bit of the bn_rww c control field, the hardware may also signal an abort notification interrupt (if bn_rwwc = 100). the st all notification interrupt is show n as the optional assertion of ecsm?s mir[fbnai] (flas h bank n abort interrupt). 17.5 initialization / application information 17.5.1 background flash array access is relatively slow compared to a full speed system clock ba sed on the pll. to prevent wait states on every flash access, li ne buffers are implement ed. while wait states are required between the flash array and line buffer, no wait states are re quired between a line buffe r and the system bus. for example, if the core is accessing sequential instructi ons starting at location 0, the first 32 bits (one line) nonseq seq addr y addr y+4 c(y) c(y+4) okay okay okay okay okay okay okay okay y c(y) burst read, abort-and-retry, apc=2, rwsc=2, pflm=2 123456 78 addr y seq addr y+8 y+16 y+16 y okay okay addr y+16 addr y ( retry ) hclk htrans haddr, hprot hwrite hrdata hwdata hready_out hresp bkn_fl_addr bkn_fl_rd_en bkn_fl_wr_en bkn_fl_rdata bkn_fl_xfr_err bkn_done bkn_abort ecsm_mir[fbnsi] ecsm_mir[fbnai] 9 10
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-117 preliminary?subject to change without notice fetched will require wait states. th e number of wait states is based on system clock frequency. however, subsequent instructions containe d in that 128 bit line buffer can be accessed without wait states. furthermore, with prefetching conf igured, the next sequential instruct ions outside the current line buffer can be prefetched to differ ent line buffer. after fetchi ng all the instructions in cu rrent line buffer, the next instruction is fetched for the next line buffer without delay. prefetching only helps perf ormance when sequential accesses typically occur, such as for instructions. since data typically is not arrange d sequentially (expept for perhaps gr aphic data) prefetching for data generally is not recommended. the flash module on this device has two ports. port 0 is always connected to the core . port 1 is connected to the other non-core ma sters (dcu and edma). configuring the flash bus interface pa rameters is done by writing to the platform flash configuration registers pfcr0:1 and platform flas h access protection register pfapr. 17.5.2 flash memory setting recommendations table 17-70 provides an example of recomm ended settings for a common scenario with this device. this example assumes port 0 (core) instru ction accesses are typically sequentia l, but not data. port 1 (dcu and edma) will not have any in struction accesses. for illustration, this example assumes por t 1 accesses have a significant amount of sequential data (such as for gr aphics) which are larger than a line buffer, so prefetching data would make sense. if graphic data were not in the internal flash, then prefetching data on port 1 would not be exp ected to be a benefit.
pxd10 microcontroller reference manual, rev. 1 17-118 freescale semiconductor preliminary?subject to change without notice table 17-70. general flash memory setting recommendations for 64 mhz system clock 1 access parameter general recommendations code flash (banks 0 & 2) 4 line buffers per port data flash (bank 1) 1 line buffer per port parameter symbol in register pfcr0 comments parameter symbol in register pfcr1 comments port 0 (core only) page buffer enable b0_p0_bfe = 1 enable port?s buffers b1_p0_bfe = 1 enable port?s buffer instruction prefetch enable b0_p0_ipfe = 1 instructions are mostly sequential, so prefeching can improve performance. ?? data prefetch enable b0_p0_dpfe = 0 data accesses are expected to generally be random, not sequential ?? prefetch limit b0_p0_pflim = 3 prefetch on hit or miss ?? page buffer configuration b0_p0_bcfg = 3 allocate 3 line buffers for instructions, 1 for data ?? port 1 (dcu, edma) page buffer enable b0_p1_bfe = 1 enable port?s buffers b1_p1_bfe = 1 enable port?s buffer instruction prefetch enable b0_p1_ipfe = 0 no instruction access on port 1 ?? data prefetch enable b0_p1_dpfe = 1 enable prefetching assuming there is significant sequential data ?? prefetch limit b0_p1_pflim = 1 prefetch on miss only (allows more bandwidth for core) ?? page buffer configuration b0_p1_bcfg = 0 all 4 line buffers available for any access ??
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 17-119 preliminary?subject to change without notice table 17-71 illustrates flash access and pr otection by master. note that pfapr?s initial value is loaded from shadlow flash location 0x20 3e00 after reset. th e ?master? numbers corr espond to the crossbar masters, which for this device are: ? master 0: e200z0 core instructions ? master 1: e200z0 core data ? master 2: edma ? master 4: dcu array access (for 64 mhz) read wait states bk0_rwsc = 2 values are system clock frequency dependent bk1_rwsc = 2 values are system clock frequency dependent write wait states bk0_wwsc = 2 bk1_wwsc = 2 adv. pipeline ctl. bk0_apc = 2 bk1_apc = 2 read while write ctl. bk0_rrwc = 0 terminate rww attempt with error response. assumes software must first check if any program or erase commands are in progress. bk1_rrwc = 0 terminate rww attempt with error response. assumes software must first check if any program or erase commands are in progress. 1 result value for recomendations in pfcr0 = 0x1084_126e, pfcr1 = 0x1084_0101 table 17-71. access and protection setting recommendations 1 1 result value for recomendations in pfapr = 0x03f2 005d parameter parameter symbol in register pfapr comments arbitration mode arbm = 3 start with round-bi n (2 or 3).change to fixed priority if application analysis indicates improved performance. master n prefetch disable mnpfd = 0 for core instructions, edma and dcu; 1 for core data start with allowing prefetching (0 ) for core instructions since it is expected the core will have mostly sequential instruction accesses. also alow prefetching for edma and dcu, assuming there are large blocks of graphic data accessed. master n access protection mnap = 3 for core data, 1 for core instructions, edma & dcu assuming only the core will program flash, allow read and write access (3) for the core data bus, but read access only (1) for core instructions, edma and dcu. table 17-70. general flash memory setting recommendations for 64 mhz system clock 1 (continued) access parameter general recommendations code flash (banks 0 & 2) 4 line buffers per port data flash (bank 1) 1 line buffer per port parameter symbol in register pfcr0 comments parameter symbol in register pfcr1 comments
pxd10 microcontroller reference manual, rev. 1 17-120 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-1 preliminary?subject to change without notice chapter 18 flexcan 18.1 introduction the flexcan module is a communication controller implementing the can protocol according to the can 2.0b protocol specification. a ge neral block diagram is shown in figure 18-1 , which describes the main sub-blocks implemented in the flexcan module, including two embedded memories, one for storing message buffers (mb) and another one for storing rx indivi dual mask registers. support for up to 64 message buffers is pr ovided. the functions of the sub-modules are described in subsequent sections. figure 18-1. flexcan block diagram 18.1.1 overview the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this fi eld: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan module is a full implementation of the can protocol specificati on, version 2.0 b [ref. 1], which support s both standard and extended message 288/544/1056- bus interface unit max mb # (0?63) ip bus interface can message can tx can rx mb1 mb0 mb62 mb63 clocks, address & data buses, interrupt and test signals buffer management protocol interface byte ram message buffer storage 64/128/256- rximr1 rximr0 rximr62 rximr63 byte ram id mask storage
pxd10 microcontroller reference manual, rev. 1 18-2 freescale semiconductor preliminary?subject to change without notice frames. a flexible number of messa ge buffers (16, 32 or 64) is also supported. the message buffers are stored in an embedded ram dedicate d to the flexcan module. please re fer to the device user guide for the actual number of message bu ffers configured in the mcu. the can protocol interface (cpi) sub-module ma nages the serial comm unication on the can bus, requesting ram access for receiving and transmitting message frames, va lidating received messages and performing error handling. the me ssage buffer management (mbm ) sub-module handles message buffer selection for reception and transmission, taking care of arbitrat ion and id matching algorithms. the bus interface unit (biu) sub-module controls the acce ss to and from the internal interface bus, in order to establish connecti on to the cpu and to other bl ocks. clocks, address and data buses, interrupt outputs and test signals are accessed through the bus interface unit. 18.1.2 flexcan module features the flexcan module includes these distinctive features: ? full implementation of the can pr otocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? zero to eight bytes data length ? programmable bit rate up to 1 mb/sec ? content-related addressing ? flexible message buffers (up to 64) of zero to eight bytes data length ? each mb configurable as rx or tx, al l supporting standard and extended messages ? individual rx mask registers per message buffer ? includes either 1056 bytes (64 mbs) of ram used for mb storage ? includes either 256 bytes (64 mbs) of ram used for indi vidual rx mask registers ? full featured rx fifo with storage capacity for 6 frames and internal pointer handling ? powerful rx fifo id filtering, capable of ma tching incoming ids against either 8 extended, 16 standard or 32 partial (8 bits) id s, with individual masking capability ? selectable backwards compatibilit y with previous flexcan version ? programmable clock source to th e can protocol interface, either bus clock or crystal oscillator ? unused mb and rx mask register space ca n be used as general purpose ram space ? listen only mode capability ? programmable loop-back mode supporting self-test operation ? programmable transmission priority scheme: lowest id, lowest buffer number or highest priority ? time stamp based on 16-bit free-running timer ? global network time, synchr onized by a specific message ? maskable interrupts ? independent of the transm ission medium (an external transceiver is assumed) ? short latency time due to an arbitration scheme for high-priority messages
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-3 preliminary?subject to change without notice ? low power modes 18.1.3 modes of operation the flexcan module has four func tional modes: normal mode (use r and supervisor), freeze mode, listen-only mode and loop-back mode. there is also a low-power mode, disable mode. ? normal mode (user or supervisor): in normal mode, the module operates receiving a nd/or transmitting message frames, errors are handled normally and all the can protocol functions are enable d. user and supervisor modes differ in the access to some restricted control registers. ? freeze mode: it is enabled when the frz bit in the mcr register is asserted. if enabled, freeze mode is entered when the halt bit in mcr is set or when th e mcu is stopped by a debugger. in this mode, no transmission or reception of fr ames is done and synchronicity to the can bus is lost. see section 18.4.9.1, freeze mode , for more information. ? listen-only mode: the module enters this mode when the lom bit in the control regist er is asserted. in this mode, transmission is disable d, all error counters are frozen and the module operates in a can error passive mode [ref. 1]. only messa ges acknowledged by another can station will be received. if flexcan detects a message that has not been ac knowledged, it will flag a bit0 error (without changing the rec), as if it was trying to acknowledge the message. ? loop-back mode: the module enters this mode when the lpb bit in the control register is asserted. in this mode, flexcan performs an internal loop back that can be used for self test operation. the bit stream output of the transmitter is internally fed back to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessi ve state (logic ?1?). flexcan behaves as it normally does when transmitting and treats its own transmitted message as a message received from a remote node. in this mode , flexcan ignores the bit sent during the ac k slot in the can frame acknowledge field to ensure proper reception of its own messa ge. both transmit and receive interrupts are generated. ? module disable mode: this low power mode is entered when the mdis bit in the mcr register is asserted. when disabled, the module shuts down the clocks to th e can protocol interface and message buffer management sub-modules. exit from this mode is done by negating the mdis bit in the mcr register. see section 18.4.9.2, module disable mode , for more information. 18.2 external signal description 18.2.1 overview the flexcan module has two i/o si gnals connected to the external mcu pins. these signals are summarized in table 18-1 and described in more detail in the next sub-sections.
pxd10 microcontroller reference manual, rev. 1 18-4 freescale semiconductor preliminary?subject to change without notice 18.2.2 signal descriptions 18.2.2.1 can rx this pin is the receive pin from the can bus transceive r. dominant state is represented by logic level ?0?. recessive state is represented by logic level ?1?. 18.2.2.2 can tx this pin is the transmit pin to th e can bus transceiver. dominant stat e is represented by logic level ?0?. recessive state is represented by logic level ?1?. 18.3 memory map and register description this section describes the registers and data structures in the flexca n module. the base address of the module depends on the particul ar memory map of the mcu. the addres ses presented here are relative to the base address. the address space occupied by flexcan has 96 bytes fo r registers starting at the module base address, followed by mb storage space in embedded ram st arting at address 0x0060, and an extra id mask storage space in a separate em bedded ram starting at address 0x0880. 18.3.1 flexcan memory mapping the complete memory map fo r a flexcan module with 64 mb s capability is shown in table 18-2 . each individual register is identified by its complete name and the corresponding mnemonic. the access type can be supervisor (s) or unrestricted (u). most of the registers ca n be configured to ha ve either supervisor or unrestricted access by programming the supv bit in the mcr regi ster. these registers are identified as s/u in the access column of table 18-2 . the ifrh and imrh registers are c onsidered reserved space when flexcan is configured with 16 or 32 mbs. the rx global mask (rxgmask), rx buffer 14 mask (rx14mask) and the rx buffer 15 mask (rx15mask) registers are provided for backwards compatibility, a nd are not used when the bcc bit in mcr is asserted. the address ranges 0x0060?0x047f a nd 0x0880?0x097f are occupied by two separate embedded memories. these two ranges are completely occ upied by ram (1056 and 256 bytes, respectively) only when flexcan is configured with 64 mbs. when it is c onfigured with 16 mbs, the memory sizes are 288 table 18-1. flexcan signals signal name 1 1 the actual mcu pins may have different names. please consult the device user guide for the actual signal names. direction description can rx input can receive pin can tx output can transmit pin
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-5 preliminary?subject to change without notice and 64 bytes, so the address ranges 0x0180?0x047f and 0x08c0?0x097f are c onsidered reserved space. when it is configured with 32 mbs, the memory sizes are 544 a nd 128 bytes, so the address ranges 0x0280?0x047f and 0x0900?0x097f are considered reserved sp ace. furthermore, if the bcc bit in mcr is negated, then the whole rx individual mask registers address range (0x0880?0x097f) is considered reserved space. table 18-2. module memory map address use access type affected by hard reset affected by soft reset location base + 0x0000 module configuration (mcr) s yes yes on page 11 base + 0x0004 control register (ctrl) s/u yes no on page 15 base + 0x0008 free running timer (timer) s/u yes yes on page 18 base + 0x000c reserved base + 0x0010 rx global mask (rxgmask) s/u yes no on page 19 base + 0x0014 rx buffer 14 mask (rx14mask) s/u yes no on page 20 base + 0x0018 rx buffer 15 mask (rx15mask) s/u yes no on page 20 base + 0x001c error counter register (ecr) s/u yes yes on page 21 base + 0x0020 error and status register (esr) s/u yes yes on page 22 base + 0x0024 interrupt mask register high (imrh) s/u yes yes on page 25 base + 0x0028 interrupt mask register low (imrl) s/u yes yes on page 26 base + 0x002c interrupt flag register high (ifrh) s/u yes yes on page 26 base + 0x0030 interrupt flag register low (ifrl) s/u yes yes on page 27 base + 0x0034?0x005f reserved base + 0x0060?0x007f reserved base + 0x0080?0x017f message buffers mb0 ? mb15 s/u no no ? base + 0x0180?0x027f message buffers mb16 ? mb31 s/u no no ? base + 0x0280?0x047f message buffers mb32 ? mb63 s/u no no ? base + 0x0480-087f reserved base + 0x0880-0x08bf rx individual mask registers rximr0-rximr15 s/u no no on page 28 base + 0x08c0-0x08ff rx individual mask registers rximr16-rximr31 s/u no no on page 28 base + 0x0900-0x097f rx individual mask registers rximr32-rximr63 s/u no no on page 28
pxd10 microcontroller reference manual, rev. 1 18-6 freescale semiconductor preliminary?subject to change without notice the flexcan module stores can messages for tran smission and reception us ing a message buffer structure. each individual mb is formed by 16 bytes mapped on memory as described in table 18-3 . table 18-3 shows a standard/extended message buffer (mb0) memory map, using 16 bytes total (0x80 ? 0x8f space). 18.3.2 message buffer structure the message buffer structure used by the flexcan module is represented in figure 18-2 . both extended and standard frames (29-bit identifier and 11-bit identifier, re spectively) used in the can specification (version 2.0 part b) are represented. table 18-3. message buffer mb0 memory mapping address offset mb field 0x80 control and status (c/s) 0x84 identifier field 0x88 ? 0x8f data field 0 ? data field 7 (1 byte each) 012345678910111213141516171819202122232425262728293031 0x0 code s r r id e rt r length time stamp 0x4 prio id (standard/extended) id (extended) 0x8 data byte 0 data byte 1 data byte 2 data byte 3 0xc data byte 4 data byte 5 data byte 6 data byte 7 = unimplemented or reserved figure 18-2. message buffer structure table 18-4. message buffer structure field descriptions field description code message buffer code this 4-bit field can be accessed (read or write) by the cpu and by the flexcan module itself, as part of the message buffer matching and arbitr ation process. the encoding is shown in ta bl e 1 8 - 5 and ta bl e 1 8 - 6 . see section 18.4, functional description for additional information. srr substitute re mote request fixed recessive bit, used only in extended format. it must be set to ?1? by the user for transmission (tx buffers) and will be stored with the value received on the can bus for rx receiving buffers. it can be received as either recessive or dominant. if flexcan receives this bit as dominant, then it is interpreted as arbitration loss. 1 = recessive value is compulsory for transmission in extended format frames 0 = dominant is not a valid value for transmission in extended format frames
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-7 preliminary?subject to change without notice ide id extended bit this bit identifies whether the frame format is standard or extended. 1 = frame format is extended 0 = frame format is standard rtr remote transmission request this bit is used for requesting transmissions of a data frame. if flexcan transmits this bit as ?1? (recessive) and receives it as ?0? (dominant), it is interpreted as arbitration loss. if this bit is transmitted as ?0? (dominant), then if it is receiv ed as ?1? (recessive), the flexcan module treats it as bit error. if the value received matches the value transmitted, it is considered as a successful bit transmission. 1 = indicates the current mb has a remote frame to be transmitted 0 = indicates the current mb has a data frame to be transmitted length length of data in bytes this 4-bit field is the length (in bytes) of the rx or tx data, which is located in offset 0x8 through 0xf of the mb space (see ta b l e 1 8 - 2 ). in reception, this field is written by the flexcan module, copied from the dlc (data length code) field of the received frame. in transmission, this field is written by the cpu and corresponds to the dlc field value of the frame to be transmitted. when rtr=1, the frame to be transmitted is a remote frame and does not include the data field, regardless of the length field. time stamp free-running counter time stamp this 16-bit field is a copy of the free-running time r, captured for tx and rx frames at the time when the beginning of the identifier field appears on the can bus. prio local priority this 3-bit field is only used when lprio_en bit is set in mcr and it only makes sense for tx buffers. these bits are not transmitted. they are appended to the regular id to define the transmission priority. see section 18.4.3, ar bitration process . id frame identifier in standard frame format, only the 11 most significant bits (3 to 13) are used for frame identification in both receive and transmit cases. the 18 least significant bits are ignored. in extended frame format, all bits are used for frame identification in both receive and transmit cases. data data field up to eight bytes can be used for a data frame. for rx frames, the data is stored as it is received from the can bus. for tx frames, the cpu prepares the data field to be transmitted within the frame. table 18-5. message buffer code for rx buffers rx code before rx new frame description rx code after rx new frame comment 0000 inactive: mb is not active. ? mb does not participate in the matching process. 0100 empty: mb is active and empty. 0010 mb participates in the matching process. when a frame is received successfully, the code is automatically updated to full. table 18-4. message buffer structure field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 18-8 freescale semiconductor preliminary?subject to change without notice 0010 full: mb is full. 0010 the act of reading the c/s word followed by unlocking the mb does not make the code return to empty. it remains full. if a new frame is written to the mb after the c/s word was read and the mb was unlocked, the code still remains full. 0110 if the mb is full and a new frame is overwritten to this mb before the cpu had time to read it, the code is automatically updated to overrun. refer to section 18.4.5, matching process for details about overrun behavior. 0110 overrun: a frame was overwritten into a full buffer. 0010 if the code indicates overrun but the cpu reads the c/s word and then unlocks the mb, when a new frame is written to the mb the code returns to full. 0110 if the code already indicates overrun, and yet another new frame mu st be written, the mb will be overwritten again, and the code will remain overrun. refer to section 18.4.5, matching process for details about overrun behavior. 0xy1 1 busy: flexcan is updating the contents of the mb. the cpu must not access the mb. 0010 an empty buffer was written with a new frame (xy was 01). 0110 a full/overrun buffer was overwritten (xy was 11). 1 note that for tx mbs (see ta bl e 1 8 - 6 ), the busy bit should be ignored upon read, except when aen bit is set in the mcr register. table 18-6. message buffer code for tx buffers rtr initial tx code code after successful transmission description x 1000 ? inactive: mb does not partic ipate in the arbitration process. x 1001 ? abort: mb was configured as tx and cpu aborted the transmission. this code is only valid when aen bit in mcr is asserted. mb does not participate in the arbitration process. 0 1100 1000 transmit data frame unconditi onally once. after transmission, the mb automatically returns to the inactive state. 1 1100 0100 transmit remote frame unconditionally once. after transmission, the mb automatically becomes an rx mb with the same id. table 18-5. message buffer code for rx buffers (continued) rx code before rx new frame description rx code after rx new frame comment
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-9 preliminary?subject to change without notice 18.3.3 rx fifo structure when the fen bit is set in the m cr, the memory area from 0x80 to 0x ff (which is normally occupied by mbs 0 to 7) is used by the reception fifo engine. figure 18-3 shows the rx fifo data structure. the region 0x0-0xc contains an mb stru cture which is the port through wh ich the cpu reads data from the fifo (the oldest frame r eceived and not read yet). the region 0x10- 0xdf is reserved for internal use of the fifo engine. the region 0xe0-0xff contains an 8-entry id table that specifies filtering criteria for accepting frames into the fifo. figure 18-4 shows the three different format s that the elements of the id table can assume, depending on the idam field of the mcr. note that all elements of the table must have the same format. see section 18.4.7, rx fifo for more information. 0 1010 1010 transmit a data frame whenever a remote request frame with the same id is received. this mb participates simultaneously in both the matching and arbitration processes. the matching process compares the id of the incoming remote request frame with the id of the mb. if a match occurs this mb is allowed to participate in the current arbitration process and the code field is automatically updated to ?1110? to allow the mb to participate in future arbitration runs. when the frame is eventually transmitted successfully, the code automatically returns to ?1010? to restart the process again. 0 1110 1010 this is an intermediate code th at is automatically written to the mb by the mbm as a result of match to a remote request frame. the data frame will be transmitted unconditionally once and then the code will automatically return to ?1010?. the cpu can also write this code with the same effect. table 18-6. message buffer code for tx buffers (continued) rtr initial tx code code after successful transmission description
pxd10 microcontroller reference manual, rev. 1 18-10 freescale semiconductor preliminary?subject to change without notice 012345678910111213141516171819202122232425262728293031 0x0 s r r id e rt r length time stamp 0x4 id (standard/extended) id (extended) 0x8 data byte 0 data byte 1 data byte 2 data byte 3 0xc data byte 4 data byte 5 data byte 6 data byte 7 0x10 reserved to 0xdf 0xe0 id table 0 0xe4 id table 1 0xe8 id table 2 0xec id table 3 0xf0 id table 4 0xf4 id table 5 0xf8 id table 6 0xfc id table 7 = unimplemented or reserved figure 18-3. rx fifo structure 012345678910111213141516171819202122232425262728293031 a r e m e x t rxida (standard = 2-12, extended = 2-31) b r e m e x t rxidb_0 (standard =2-12, extended = 2-15) r e m e x t rxidb_1 (standard = 18-28, extended = 18-31) crxidc_0 (std/ext = 0-7) rxidc_1 (std/ext = 8-15) rxidc_2 (std/ext = 16-23) rxidc_3 (std/ext = 24-31) = unimplemented or reserved figure 18-4. id table 0 - 7
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-11 preliminary?subject to change without notice 18.3.4 register descriptions the flexcan registers are described in this section in as cending address order. 18.3.4.1 module configur ation register (mcr) this register defines global system configurations, such as the m odule operation mode (e.g., low power) and maximum message buffer configuratio n. most of the fields in this re gister can be acce ssed at any time, except the maxmb field, which should only be ch anged while the module is in freeze mode. table 18-7. rx fifo structure field descriptions field description rem remote frame this bit specifies if remote frames are accept ed into the fifo if they match the target id. 1 = remote frames can be acc epted and data frames are rejected 0 = remote frames are rejected and data frames can be accepted ext extended frame specifies whether extended or standard frames are a ccepted into the fifo if they match the target id. 1 = extended frames can be accepted and standard frames are rejected 0 = extended frames are rejected an d standard frames can be accepted rxida rx frame identifier (format a) specifies an id to be used as acceptance criteria for the fifo. in the standard frame format, only the 11 most significant bits (3 to 13)are used for frame identification. in the extended frame format, all bits are used. rxidb_0, rxidb_1 rx frame identifier (format b) specifies an id to be used as acceptance criteria for the fifo. in the standard frame format, the 11 most significant bits (a full standard id) (3 to 13)are used for frame identification. in the extended frame format, all 14 bits of the field are compared to the 14 most significant bits of the received id. rxidc_0, rxidc_1, rxidc_2, rxidc_3 rx frame identifier (format c) specifies an id to be used as acceptance criter ia for the fifo. in both standard and extended frame formats, all 8 bits of the field are compared to the 8 most significant bits of the received id.
pxd10 microcontroller reference manual, rev. 1 18-12 freescale semiconductor preliminary?subject to change without notice base + 0x0000 0123456789101112131415 r mdis frz fen halt not_ rdy 0soft _rst frz_ ack supv 0 wrn_ en lpm_ ack 0dozesrx _dis bcc w reset: note 1 1 reset value of this bit is different on various platform s. consult the specific mcu documentation to determine its value. 101100note 2 2 different on various platforms, but it is always the opposite of the mdis reset value. 100note 3 3 different on various platforms, but it is always the same as the mdis reset value. 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00lprio _en aen 0 0 idam 0 0 maxmb w reset: 0000000000001111 = unimplemented or reserved figure 18-5. module configuration register (mcr) table 18-8. module configuration register (mcr) field descriptions field description mdis module disable this bit controls whether flexcan is enabled or not. when disabled, flexcan shuts down the clocks to the can protocol interface and message buffer management sub-modules. this is the only bit in mcr not affected by soft reset. see section 18.4.9.2, module disable mode for more information. 1 = disable the flexcan module 0 = enable the flexcan module frz freeze enable the frz bit specifies the flexcan behavior when the halt bit in the mcr register is set or when the mcu is stopped by a debugger. when frz is asserted, flexcan is enabled to enter freeze mode. negation of this bit field causes flexcan to exit from freeze mode. 1 = enabled to enter freeze mode 0 = not enabled to enter freeze mode fen fifo enable this bit controls whether the fifo feature is enabled or not. when fen is set, mbs 0 to 7 cannot be used for normal reception and transmission because the corresponding memory region (0x80-0xff) is used by the fifo engine. see section 18.3.3, rx fifo structure and section 18.4.7, rx fifo for more information. 1 = fifo enabled 0 = fifo not enabled
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-13 preliminary?subject to change without notice halt halt flexcan assertion of this bit puts the flexcan module into freeze mode. the cpu should clear it after initializing the message buffers and control register . no reception or transmission is performed by flexcan before this bit is cleared. while in freeze mode, the cpu has write access to the error counter register, that is otherwise read-only. freeze mode can not be entered while flexcan is in any of the low power modes. see section 18.4.9.1, freeze mode for more information. 1 = enters freeze mode if the frz bit is asserted. 0 = no freeze mode request. not_rdy flexcan not ready this read-only bit indicates that flexcan is either in disable mode or freeze mode. it is negated once flexcan has exited these modes. 1 = flexcan module is either in disable mode freeze mode 0 = flexcan module is either in normal mode, listen-only mode or loop-back mode soft_rst soft reset when this bit is asserted, flexcan resets its internal state machines and some of the memory mapped registers. the following registers are reset: mcr (except the mdis bit), timer, ecr, esr, imrl, imrh, ifrl, ifrh. configuration registers t hat control the interface to the can bus are not affected by soft reset. the fo llowing registers are unaffected: ?ctrl ? rximr0?rximr63 ? rxgmask, rx14mask, rx15mask ? all message buffers the soft_rst bit can be asserted di rectly by the cpu when it writes to the mcr register, but it is also asserted when global soft reset is requested at mcu level. since soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate its effect. the soft_rst bit remains asserted while reset is pending, and is automatically negated when reset completes. therefor e, software can poll this bit to know when the soft reset has completed. soft reset cannot be applied while clocks are shut down in any of the low power modes. the module should be first removed from low power mode, and then soft reset can be applied. 1 = resets the registers marked as ?affected by soft reset? in table 18-2 0 = no reset request frz_ack freeze mode acknowledge this read-only bit indicates that flexcan is in freeze mode and its prescaler is stopped. the freeze mode request cannot be granted until current transmi ssion or reception processes have finished. therefore the software can poll the frz_ack bit to know when flexcan has actually entered freeze mode. if freeze mode request is negate d, then this bit is negated once the flexcan prescaler is running again. if freeze mode is requested while flexcan is in any of the low power modes, then the frz_ack bit will only be set when the low power mode is exited. see section 18.4.9.1, freeze mode for more information. 1 = flexcan in freeze mode, prescaler stopped 0 = flexcan not in freeze mode, prescaler running supv supervisor mode this bit configures some of the flexcan registers to be either in supervisor or unrestricted memory space. the registers affected by this bit ar e marked as s/u in the access type column of ta b l e 1 8 - 2 . reset value of this bit is ?1?, so the affected registers start with supervisor access restrictions. 1 = affected registers are in supervisor memory space. any access withou t supervisor permission behaves as though the access was done to an unimplemented register location 0 = affected registers are in unrestricted memory space table 18-8. module configuration regist er (mcr) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 18-14 freescale semiconductor preliminary?subject to change without notice wrn_en warning interrupt enable when asserted, this bit enables the generation of the twrn_int and rwrn_int flags in the error and status register. if wrn_en is negated, the twrn_int and rwrn_int flags will always be zero, independent of the values of the error counters, and no warning interrupt will ever be generated. 1 = twrn_int and rwrn_int bits are set when t he respective error counter transition from <96 to ? 96. 0 = twrn_int and rwrn_int bits are zero, independent of the values in the error counters. lpm_ack low power mode acknowledge this read-only bit indicates that flexcan is in di sable mode. this mode cannot be entered until all current transmission or reception processes have finished, so the cpu can poll the lpm_ack bit to know when flexcan has actually entered low power mode. see section 18.4.9.2, module disable mode ? for more information. 1 = flexcan is either in disable mode 0 = flexcan not in any of the low power modes doze doze mode enable this bit defines whether flexcan is allowed to enter low power mode when doze mode is requested at mcu level. this bit is automatica lly reset when flexcan wakes up from doze mode upon detecting activity on the can bus (self wake-up enabled). 1 = flexcan is enabled to enter low power mode when doze mode is requested 0 = flexcan is not enabled to enter low power mode when doze mode is requested srx_dis self reception disable this bit defines whether flexcan is allowed to rece ive frames transmitted by itself. if this bit is asserted, frames transmitted by the module will not be stored in any mb, regardless if the mb is programmed with an id that matches the transmitted frame, and no interrupt flag or interrupt signal will be generated due to the frame reception. 1 = self reception disabled 0 = self reception enabled bcc backwards compatibility configuration this bit is provided to support backwards compatib ility with previous flexcan versions. when this bit is negated, the following configuration is applied: ? for mcus supporting individual rx id masking, th is feature is disabled. instead of individual id masking per mb, flexcan uses its previous masking scheme with rxgmask, rx14mask and rx15mask. ? the reception queue feature is disabled. upon receiving a message, if the first mb with a matching id that is found is still occupied by a previous unread message, flexcan will not look for another matching mb. it will override this mb with the new message and set the code field to ?0110? (overrun). upon reset this bit is negated, allowing legacy software to work without modification. 1 = individual rx masking and queue feature are enabled. 0 = individual rx masking and queue feature are disabled. lprio_en local priority enable this bit is provided for backwards compatibility reasons. it controls whether the local priority feature is enabled or not. it is used to extend the id us ed during the arbitration process. with this extended id concept, the arbitration process is done based on the full 32-bit word, but the actual transmitted id still has 11-bit for standard frames and 29-bit for extended frames. 1 = local priority enabled 0 = local priority disabled table 18-8. module configuration regist er (mcr) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-15 preliminary?subject to change without notice 18.3.4.2 control register (ctrl) this register is defined for specifi c flexcan control features related to the can bus, such as bit-rate, programmable sampling point within an rx bit, loop back mode, listen only mode, bus off recovery behavior and interrupt enabling (bus-off, error, warni ng). it also determines th e division factor for the clock prescaler. most of the fields in this register shoul d only be changed while the module is in disable mode or in freeze mode. exceptions are the boff_msk, err_msk, twrn_msk, rwrn_msk and boff_rec bits, that can be accessed at any time. aen abort enable this bit is supplied for backwards compatibility reasons. when asserted, it enables the tx abort feature. this feature guarantees a safe proced ure for aborting a pending transmission, so that no frame is sent in the ca n bus without notification. 1 = abort enabled 0 = abort disabled idam id acceptance mode this 2-bit field identifies the format of the elemen ts of the rx fifo filter table, as shown in ta bl e 1 8 - 9 . note that all elements of the table are configur ed at the same time by this field (they are all the same format). see section 18.3.3, rx fifo structure . maxmb maximum number of message buffers this 6-bit field defines the maximum number of me ssage buffers that will take part in the matching and arbitration processes. the reset value (0x0f) is equivalent to 16 mb configuration. this field should be changed only while the module is in freeze mode. maximum mbs in use = maxmb + 1 note: maxmb has to be programmed with a value smal ler or equal to the number of available message buffers, otherwise flexcan will not transmit or receive frames. note: when the rx fifo is enabled, it uses 8 mbs. these should be included in the maxmb total. thus, for example, if t he rx fifo and 4 other mb s are enabled, maxmb = 11. table 18-9. idam coding idam format explanation 00 a one full id (standard or ex tended) per filter element. 01 b two full standard ids or two partia l 14-bit extended ids per filter element. 10 c four partial 8-bit ids (standard or extended) per filter element. 11 d all frames rejected. table 18-8. module configuration regist er (mcr) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 18-16 freescale semiconductor preliminary?subject to change without notice base + 0x0004 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r presdiv rjw pseg1 pseg2 w reset: 0000 0 0 0000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r boff _msk err_ msk clk_ src lpb twrn _msk rwrn _msk 00smpboff _rec tsyn lbuf lom propseg w reset: 0000 0 0 0000000000 = unimplemented or reserved figure 18-6. control register (ctrl) table 18-10. control register (ctrl) field descriptions field description 0-7 presdiv prescaler division factor this 8-bit field defines the ratio between the cpi clock frequency and the serial clock (sclock) frequency. the sclock period defines the time quant um of the can protocol. for the reset value, the sclock frequency is equal to the cpi clock frequency. the maximum value of this register is 0xff, that gives a minimum sclock frequency equal to the cpi clock frequency divided by 256. for more information refer to section 18.4.8.4, protocol timing . sclock frequency = cpi clock frequency / (presdiv + 1) 8-9 rjw resync jump width this 2-bit field defines the maximum number of time quanta 1 that a bit time can be changed by one resynchronization. the valid programmable values are 0 ? 3. resync jump width = rjw + 1. 10-12 pseg1 pseg1 ? phase segment 1 this 3-bit field defines the length of phase buffer segment 1 in the bit time. the valid programmable values are 0 ? 7. phase buffer segment 1 = (pseg1 + 1) x time-quanta. 13-15 pseg2 pseg2 ? phase segment 2 this 3-bit field defines the length of phase buffer segment 2 in the bit time. the valid programmable values are 1 ? 7. phase buffer segment 2 = (pseg2 + 1) x time-quanta. 16 boff_msk bus off mask this bit provides a mask for the bus off interrupt. 1= bus off interrupt enabled 0 = bus off interrupt disabled
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-17 preliminary?subject to change without notice 17 err_msk error mask this bit provides a mask for the error interrupt. 1 = error interrupt enabled 0 = error interrupt disabled 18 clk_src can engine clock source this bit selects the clock source to the can protocol interface (cpi) to be either the peripheral clock (driven by the pll) or the crystal oscillator clock. the selected clock is the one fed to the prescaler to generate the serial clock (sclock). in order to guarantee reliable operation, this bit should only be changed while the module is in disable mode. see section 18.4.8.4, protocol timing for more information. 1 = the can engine clock source is the bus clock 0 = the can engine clock source is the oscillator clock note: this clock selection feature may not be available in all mcus. a particular mcu may not have a pll, in which case it would have only the o scillator clock, or it may use only the pll clock feeding the flexcan module. in these cases, this bit has no effect on the module operation. 19 twrn_msk tx warning interrupt mask this bit provides a mask for the tx warning interrupt associated with the twrn_int flag in the error and status register. this bit has no effect if the wrn_en bit in mcr is negated and it is read as zero when wrn_en is negated. 1 = tx warning interrupt enabled 0 = tx warning interrupt disabled 20 rwrn_msk rx warning interrupt mask this bit provides a mask for the rx warning interrupt associated with the rwrn_int flag in the error and status register. this bit has no effect if the wrn_en bit in mcr is negated and it is read as zero when wrn_en is negated. 1 = rx warning interrupt enabled 0 = rx warning interrupt disabled 21 lpb loop back this bit configures flexcan to operate in loop-back mode. in this mode, flexcan performs an internal loop back that can be used for self test operation. the bit stream output of the transmitter is fed back internally to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic ?1?). flexcan b ehaves as it normally does when transmitting, and treats its own transmitted message as a message received from a remote node. in this mode, flexcan ignores the bit sent during the ack slot in the can frame acknowledge field, generating an internal acknowledge bit to ensure proper reception of its own message. both transmit and receive interrupts are generated. 1 = loop back enabled 0 = loop back disabled 24 smp sampling mode this bit defines the sampling mode of can bits at the rx input. 1 = three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples, a majority rule is used 0 = just one sample is used to determine the bit value table 18-10. control register (ctr l) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 18-18 freescale semiconductor preliminary?subject to change without notice 18.3.4.3 free running timer (timer) this register represents a 16-bit free running counter that can be read and written by the cpu. the timer starts from 0x0000 after reset, counts linearly to 0xffff, and wraps around. the timer is clocked by the flex can bit-clock (which de fines the baud rate on the can bus). during a message transmission/recepti on, it increments by one for each bit that is received or transmitted. when 25 boff_rec bus off recovery mode this bit defines how flexcan recovers from bus off state. if this bit is negated, automatic recovering from bus off state occu rs according to the can specification 2.0b. if the bit is asserted, automatic recovering from bus off is disabled and the module remains in bus off state until the bit is negated by the user. if the negation occurs before 128 sequences of 11 recessive bits are detected on the can bus, then bus off recovery happens as if the boff_rec bit had never been asserted. if the negation occurs after 128 sequen ces of 11 recessive bits occurred, then flexcan will resynchronize to the bus by waiting for 11 recessive bits before joining the bus. after negation, the boff_rec bit can be re-asserted again during bus off, but it will only be effective the next time the module enters bus off. if boff_rec was negated when the module entered bus off, asserting it during bus off will not be effective for the current bus off recovery. 1 = automatic recovering from bus off state disabled 0 = automatic recovering from bus off state enabled, according to can spec 2.0 part b 26 tsyn timer sync mode this bit enables a mechanism that resets the fr ee-running timer each time a message is received in message buffer 0. this feature provides mean s to synchronize multiple flexcan stations with a special ?sync? message (i.e., global network time ). if the fen bit in mcr is set (fifo enabled), mb8 is used for timer synchronization instead of mb0. 1 = timer sync feature enabled 0 = timer sync feature disabled 27 lbuf lowest buffer tr ansmitted first this bit defines the ordering mechanism for message buffer transmission. when asserted, the lprio_en bit does not affect the priority arbitration. 1 = lowest number buffer is transmitted first 0 = buffer with highest priority is transmitted first 28 lom listen-only mode this bit configures flexcan to operate in listen on ly mode. in this mode, transmission is disabled, all error counters are frozen and the module operates in a can error passive mode [ref. 1]. only messages acknowledged by another can station w ill be received. if flexcan detects a message that has not been acknowledged, it will flag a bit0 error (without changing the rec), as if it was trying to acknowledge the message. 1 = flexcan module operates in listen only mode 0 = listen only mode is deactivated 29-31 propseg propagation segment this 3-bit field defines the length of the pr opagation segment in the bit time. the valid programmable values are 0?7. propagation segment time = (propseg + 1) * time-quanta. time-quantum = one sclock period. 1 one time quantum is equal to the sclock period. table 18-10. control register (ctr l) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-19 preliminary?subject to change without notice there is no message on the bus, it counts using the previously program med baud rate. du ring freeze mode, the timer is not incremented. the timer value is captured at the beginning of the identifier field of any frame on the can bus. this captured value is written into the time stamp entry in a message buffer after a successful reception or transmission of a message. writing to the timer is an indirect operation. the data is first written to an auxili ary register and then an internal request/acknowledge procedur e across clock domains is executed. all this is transparent to the user, except for the fact that the da ta will take some time to be actuall y written to the register. if desired, software can poll the register to discove r when the data was actually written. 18.3.4.4 rx global mask (rxgmask) this register is provided for legacy support and for lo w cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individua l masks per mb, setti ng the bcc bit in mcr causes the rxgmask regi ster to have no effect on the m odule operation. for mcus not supporting individual masks per mb, this re gister is always effective. rxgmask is used as acceptance mask for all rx mbs, excluding mbs 14 ? 15, which have individual mask registers. when the fen bit in mcr is set (fifo enabled), the rxgmask also applies to all elements of the id filter table, except elements 6-7, which have individual masks. the contents of this register must be programmed while the module is in freeze mode, and must not be modified when the module is tr ansmitting or r eceiving frames. base + 0x0008 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r timer w reset: 0000000000000000 = unimplemented or reserved figure 18-7. free running timer (timer)
pxd10 microcontroller reference manual, rev. 1 18-20 freescale semiconductor preliminary?subject to change without notice 18.3.4.5 rx 14 mask (rx14mask) this register is provided for legacy support and for lo w cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individua l masks per mb, setti ng the bcc bit in mcr causes the rx14mask register to ha ve no effect on the module operation. rx14mask is used as acceptance mask for the identi fier in message buffer 14. when the fen bit in mcr is set (fifo enabled), the rxg14mask also applies to element 6 of the id filt er table. this register has the same structure as the rx global mask regi ster. it must be programmed while the module is in freeze mode, and must not be m odified when the module is tr ansmitting or receiving frames. ? address offset: 0x14 ? reset value: 0xffff_ffff 18.3.4.6 rx 15 mask (rx15mask) this register is provided for legacy support and for lo w cost mcus that do not have the individual masking per message buffer feature. for mcus supporting individua l masks per mb, setti ng the bcc bit in mcr causes the rx15mask register to ha ve no effect on the module operation. base + 0x0010 0123456789101112131415 r mi31 mi30 mi29 mi28 mi27 mi 26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 w reset: 1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mi15 mi14 mi13 mi12 mi11 mi10 mi9 m i8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 w reset: 1111111111111111 = unimplemented or reserved figure 18-8. rx global mask register (rxgmask) table 18-11. rx global mask regist er (rxgmask) field descriptions field description 0-31 mi31 - mi0 mask bits for normal rx mbs, the mask bits affect the id filter programmed on the mb. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 1 = the corresponding bit in the filter is checked against the one received 0 = the corresponding bit in the filter is ?don?t care?
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-21 preliminary?subject to change without notice when the bcc bit is negated, rx15mask is used as ac ceptance mask for the identifier in message buffer 15. when the fen bit in mcr is set (fifo enabled), the rxg14mask also applies to element 7 of the id filter table. this register has the same structure as the rx global ma sk register. it must be programmed while the module is in freeze mode, and must not be modified when the module is transmitting or receiving frames. ? address offset: 0x18 ? reset value: 0xffff_ffff 18.3.4.7 error counte r register (ecr) this register has 2 8-bit fields re flecting the value of two flexcan error counters: transmit error counter (tx_err_counter field) and receive error counter (rx_err_counter field) . the rules for increasing and decreasing these counters are descri bed in the can protocol and are completely implemented in the flexcan module. both counters are read only except in fr eeze mode, where they can be written by the cpu. writing to the error counter register while in free ze mode is an indirect ope ration. the data is first written to an auxiliary register an d then an internal request/acknowle dge procedure acro ss clock domains is executed. all this is transparent to the user, except for the fact that the data wi ll take some time to be actually written to the register. if desired, software can poll the regist er to discover when the data was actually written. flexcan responds to any bus state as described in th e protocol, e.g. transmit ?e rror active? or ?error passive? flag, delay its transmission start time (?error passive?) and avoid any influence on the bus when in ?bus off? state. the following are the basic rules for flexcan bus state transitions. ? if the value of tx_err_counter or rx_err_counter increases to be greater than or equal to 128, the flt_conf field in the error and status register is updated to reflect ?error passive? state. ? if the flexcan state is ?error passive?, and either tx_err_counter or rx_err_counter decrements to a value less than or equal to 127 while the other already sati sfies this condition, the flt_conf field in the error and status register is updated to reflect ?error active? state. ? if the value of tx_err_c ounter increases to be greater than 255, the flt_conf field in the error and status register is updated to reflect ?bus off? state, and an interrupt may be issued. the value of tx_err_counter is then reset to zero. ? if flexcan is in ?bus off? state, then tx_err_co unter is cascaded together with another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. hence, tx_err_counter is reset to zero a nd counts in a manner where the in ternal counter counts 11 such bits and then wraps around wh ile incrementing the tx_err_counter. when tx_err_counter reaches the value of 128, the flt_conf field in th e error and status register is updated to be ?error active? and both error counters are reset to zero. at any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal coun ter resets itself to zero without affecting the tx_err_counter value. ? if during system start-up, only one node is operati ng, then its tx_err_counter increases in each message it is trying to transmit, as a result of acknowledge erro rs (indicated by the ack_err bit in the error and status register). after the transi tion to ?error passive? state, the tx_err_counter
pxd10 microcontroller reference manual, rev. 1 18-22 freescale semiconductor preliminary?subject to change without notice does not increment anymore by acknow ledge errors. therefore the device never goes to the ?bus off? state. ? if the rx_err_counter increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver. at the next successful message reception, the counter is set to a value between 119 and 127 to resume to ?error active? state. 18.3.4.8 error and status register (esr) this register reflects various error conditions, some genera l status of the de vice and it is th e source of four interrupts to the cpu. the reported er ror conditions (bits 16-21) are those th at occurred since the last time the cpu read this register. the cpu read acti on clears bits 16-21. bits 22-28 are status bits. most bits in this register ar e read only, except twrn_int, rwrn _int, boff_int and err_int, that are interrupt flags that can be cleared by writi ng ?1? to them (writing ?0? has no effect). see section 18.4.10, interrupts for more details. base + 0x001c 0123456789101112131415 r 0000000000000000 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rx_err_counter tx_err_counter w reset: 0000000000000000 = unimplemented or reserved figure 18-9. error counter register (ecr)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-23 preliminary?subject to change without notice base + 0x0020 0123456789101112131415 r 00000000000000twrn _int rwrn _int w w1c w1c reset: 00000000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bit1_ err bit0_ err ack_ err crc_ err frm_ err stf_ err tx_w rn rx_w rn idle txrx flt_conf 0 boff _int err_ int 0 w w1c w1c reset: 00000000000000 0 0 = unimplemented or reserved figure 18-10. error and status register (esr) table 18-12. error and status register (esr) field descriptions field description twrn_int tx warning interrupt flag if the wrn_en bit in mcr is asserted, the twrn_ int bit is set when the tx_wrn flag transition from ?0? to ?1?, meaning that the tx error coun ter reached 96. if the corresponding mask bit in the control register (twrn_msk) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1 = the tx error counter transition from < 96 to ? 96 0 = no such occurrence rwrn_int rx warning interrupt flag if the wrn_en bit in mcr is asserted, the rwrn_int bit is set when the rx_wrn flag transition from ?0? to ?1?, meaning that th e rx error counters reached 96. if the corresponding mask bit in the control register (rwrn_msk) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1 = the rx error counter transition from < 96 to ? 96 0 = no such occurrence bit1_err bit1 error this bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 1 = at least one bit sent as recessive is received as dominant 0 = no such occurrence note: this bit is not set by a transmitter in case of ar bitration field or ack slot, or in case of a node sending a passive error flag that detects dominant bits.
pxd10 microcontroller reference manual, rev. 1 18-24 freescale semiconductor preliminary?subject to change without notice bit0_err bit0 error this bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 1 = at least one bit sent as dominant is received as recessive 0 = no such occurrence ack_err acknowledge error this bit indicates that an acknowledge error has been detected by the transmitter node, i.e., a dominant bit has not been detected during the ack slot. 1 = an ack error occurred since last read of this register 0 = no such occurrence crc_err cyclic redundancy check error this bit indicates that a crc error has been detect ed by the receiver node, i.e., the calculated crc is different from the received. 1 = a crc error occurred since last read of this register. 0 = no such occurrence frm_err form error this bit indicates that a form error has been detected by the receiver node, i.e., a fixed-form bit field contains at least one illegal bit. 1 = a form error occurred since last read of this register 0 = no such occurrence stf_err stuffing error this bit indicates that a stuffing error has been detected. 1 = a stuffing error occurred since last read of this register. 0 = no such occurrence. tx_wrn tx error counter this bit indicates when repetitive errors are occurring during message transmission. 1 = tx_err_counter ? 96 0 = no such occurrence rx_wrn rx error counter this bit indicates when repetitive errors are occurring during message reception. 1 = rx_err_counter ?? 96 0 = no such occurrence idle can bus idle state this bit indicates when can bus is in idle state. 1 = can bus is now idle 0 = no such occurrence txrx current flexcan status (transmitting/receiving) this bit indicates if flexcan is transmitting or receiving a message when the can bus is not in idle state. this bit has no meaning when idle is asserted. 1 = flexcan is transmitting a message (idle=0) 0 = flexcan is receiving a message (idle=0) flt_conf fault confinement state this 2-bit field indicates the confinement state of the flexcan module, as shown in table 18-13 . if the lom bit in the control register is asserted, the flt_conf field will indicate ?error passive?. since the control register is not affected by soft reset, the flt_conf field will not be affected by soft reset if the lo m bit is asserted. table 18-12. error and status register (esr) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-25 preliminary?subject to change without notice 18.3.4.9 interrupt mask register high (imrh) this register allows any num ber of a range of 32 message buffer in terrupts to be enabled or disabled. it contains one interrupt mask bit per buffer, enabling the cpu to de termine which buffer generates an interrupt after a successful transmission or recep tion (i.e. when the corresponding ifrh bit is set). boff_int bus off? interrupt this bit is set when flexcan enters ?bus off? st ate. if the corresponding mask bit in the control register (boff_msk) is set, an interrupt is genera ted to the cpu. this bit is cleared by writing it to ?1?. writing ?0? has no effect. 1 = flexcan module entered ?bus off? state 0 = no such occurrence err_int error interrupt this bit indicates that at least one of the error bits (bits 16-21) is set. if the corresponding mask bit in the control register (err_msk) is set, an interr upt is generated to the cpu. this bit is cleared by writing it to ?1?.writing ?0? has no effect. 1 = indicates setting of any error bit in the error and status register 0 = no such occurrence table 18-13. fault confinement state value meaning 00 error active 01 error passive 1x bus off base + 0x0024 0123456789101112131415 r buf 63m buf 62m buf 61m buf 60m buf 59m buf 58m buf 57m buf 56m buf 55m buf 54m buf 53m buf 52m buf 51m buf 50m buf 49m buf 48m w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 47m buf 46m buf 45m buf 44m buf 43m buf 42m buf 41m buf 40m buf 39m buf 38m buf 37m buf 36m buf 35m buf 34m buf 33m buf 32m w reset: 0000000000000000 figure 18-11. interrupt mask register high (imrh) table 18-12. error and status register (esr) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 18-26 freescale semiconductor preliminary?subject to change without notice 18.3.4.10 interrupt mask register low (imrl) this register allows to enable or disable any number of a ra nge of 32 message buffer interrupts. it contains one interrupt mask bit per buffer, en abling the cpu to determine which bu ffer generates an interrupt after a successful transmission or reception (i.e ., when the corresponding ifrl bit is set). 18.3.4.11 interrupt flag register high (ifrh) this register defines the flags for 32 message buffer interrupts. it contains one interrupt flag bit per buffer. each successful transmission or re ception sets the corresponding ifrh bi t. if the corresponding imrh bit table 18-14. imrh field descriptions field description buf63m ? buf32m buffer mb i mask each bit enables or disables the respective flexcan message buffer (mb32 to mb63) interrupt. 1 = the corresponding buffer interrupt is enabled 0 = the corresponding buffer interrupt is disabled note: setting or clearing a bit in the imrh register can assert or negate an interrupt request, if the corresponding ifrh bit is set. base + 0x0028 0123456789101112131415 r buf 31m buf 30m buf 29m buf 28m buf 27m buf 26m buf 25m buf 24m buf 23m buf 22m buf 21m buf 20m buf 19m buf 18m buf 17m buf 16m w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15m buf 14m buf 13m buf 12m buf 11m buf 10m buf 9m buf 8m buf 7m buf 6m buf 5m buf 4m buf 3m buf 2m buf 1m buf 0m w reset: 0000000000000000 figure 18-12. interrupt mask register low (imrl) table 18-15. imrl field descriptions field description buf31m ? buf0m buf31m?buf0m ? buffer mb i mask each bit enables or disables the respective flexcan message buffer (mb0 to mb31) interrupt. 1 = the corresponding buffer interrupt is enabled 0 = the corresponding buffer interrupt is disabled note: setting or clearing a bit in the imrl register can assert or negate an interrupt request, if the corresponding ifrl bit is set.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-27 preliminary?subject to change without notice is set, an interrupt will be generated. the interrupt fl ag must be cleared by writi ng it to ?1?. writing ?0? has no effect. when the aen bit in the mcr is set (abort enabled), while the ifrh bit is set for a mb configured as tx, the writing access done by cpu into the corresponding mb will be blocked. 18.3.4.12 interrupt flag register low (ifrl) this register defines the flags fo r 32 message buffer interrupts and fi fo interrupts. it contains one interrupt flag bit per buffer. each successful transmis sion or reception sets the corresponding ifrl bit. if the corresponding imrl bit is set, an interrupt will be generated. the interrupt flag must be cleared by writing it to ?1?. writing ?0? has no effect. when the aen bit in the mcr is set (abort enabled), while the ifrl bit is set for a mb configured as tx, the writing access done by cpu into th e corresponding mb will be blocked. when the fen bit in the mcr is se t (fifo enabled), the function of th e 8 least significant interrupt flags (buf7i - buf0i) is changed to support the fifo operati on. buf7i, buf6i and bu f5i indicate operating conditions of the fifo, while buf4i to buf0i are not used. base + 0x002c 0123456789101112131415 r buf 63i buf 62i buf 61i buf 60i buf 59i buf 58i buf 57i buf 56i buf 55i buf 54i buf 53i buf 52i buf 51i buf 50i buf 49i buf 48i w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 47i buf 46i buf 45i buf 44i buf 43i buf 42i buf 41i buf 40i buf 39i buf 38i buf 37i buf 36i buf 35i buf 34i buf 33i buf 32i w reset: 0000000000000000 figure 18-13. interrupt flag register high (ifrh) table 18-16. ifrh field descriptions field description buf32i ? buf63i buffer mb i interrupt each bit flags the respective flexcan message buffer (mb32 to mb63) interrupt. 1 = the corresponding buffer has successfu lly completed transmission or reception 0 = no such occurrence
pxd10 microcontroller reference manual, rev. 1 18-28 freescale semiconductor preliminary?subject to change without notice 18.3.4.13 rx individual mask registers (rximr0 ? rximr63) these registers are used as acceptan ce masks for id filtering in rx mbs and the fifo. if the fifo is not enabled, one mask register is provi ded for each available message buff er, providing id masking capability base + 0x0030 0123456789101112131415 r buf 31i buf 30i buf 29i buf 28i buf 27i buf 26i buf 25i buf 24i buf 23i buf 22i buf 21i buf 20i buf 19i buf 18i buf 17i buf 16i w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15i buf 14i buf 13i buf 12i buf 11i buf 10i buf 9i buf 8i buf 7i buf 6i buf 5i buf 4i buf 3i buf 2i buf 1i buf 0i w reset: 0000000000000000 figure 18-14. interrupt flag register low (ifrl) table 18-17. ifrl field descriptions field description buf31i ? buf8i buffer mb i interrupt each bit flags the respective flexcan message buffer (mb8 to mb31) interrupt. 1 = the corresponding mb has successfully completed transmission or reception 0 = no such occurrence buf7i buffer mb7 interrupt or ?fifo overflow? if the fifo is not enabled, this bit flags the inte rrupt for mb7. if the fifo is enabled, this flag indicates an overflow condition in the fi fo (frame lost because fifo is full). 1 = mb7 completed transmission/reception or fifo overflow 0 = no such occurrence buf6i buffer mb6 interrup t or ?fifo warning? if the fifo is not enabled, this bit flags the inte rrupt for mb6. if the fifo is enabled, this flag indicates that 4 out of 6 buffers of the fi fo are already occupied (fifo almost full). 1 = mb6 completed transmission/reception or fifo almost full 0 = no such occurrence buf5i buffer mb5 interrupt or ?frames available in fifo? if the fifo is not enabled, this bit flags the inte rrupt for mb5. if the fifo is enabled, this flag indicates that at least one frame is available to be read from the fifo. 1 = mb5 completed transmission/reception or frames available in the fifo 0 = no such occurrence buf4i ? buf0i buffer mb i interrupt or ?reserved? if the fifo is not enabled, these bits flag the inte rrupts for mb0 to mb4. if the fifo is enabled, these flags are not used and must be considered as reserved locations. 1 = corresponding mb completed transmission/reception 0 = no such occurrence
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-29 preliminary?subject to change without notice on a per message buffer basis. when the fifo is en abled (fen bit in mcr is set), the first 8 mask registers apply to the 8 elements of the fifo filter table (on a one-t o-one correspondence), while the rest of the registers apply to the regular mbs, starting from mb8. the individual rx mask regi sters are implemented in ram, so they are not affected by reset and must be explicitly initialized prior to any reception. furtherm ore, they can only be accessed by the cpu while the module is in freeze mode. out of freeze mode, write accesse s are blocked and read accesses will return ?all zeros?. furthermore, if the bcc bit in the mcr register is nega ted, any read or write operation to these registers results in access error. 18.4 functional description 18.4.1 overview the flexcan module is a can protocol engine with a very flexible mailbox system for transmitting and receiving can frames. the mailbox syst em is composed by a set of up to 64 message buffers (mb) that store configuration and control data, ti me stamp, message id and data (see section 18.3.2, message buffer structure ). the memory corresponding to the first 8 mbs can be configured to support a fifo reception scheme with a powerful id filteri ng mechanism, capable of checking in coming frames against a table of ids (up to 8 extended ids or 16 standard ids or 32 8-bi t id slices), each one wi th its own i ndividual mask register. simultaneous reception through fifo and mailbox is supported. for mailbox reception, a matching algorithm makes it possible to store received frames only in to mbs that have the same id base + 0x0004 0123456789101112131415 r mi31 mi30 mi29 mi28 mi27 mi 26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mi15 mi14 mi13 mi12 mi11 mi10 mi9 m i8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 w reset: 0000000000000000 figure 18-15. rx individual mask registers (rximr0 - rximr63) table 18-18. rx individual mask registers (rximr0 - rximr63) field descriptions field description 0-31 mi31?mi0 mask bits for normal rx mbs, the mask bits affect the id filter programmed on the mb. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 1 = the corresponding bit in the filter is checked against the one received 0 = the corresponding bit in the filter is ?don?t care?
pxd10 microcontroller reference manual, rev. 1 18-30 freescale semiconductor preliminary?subject to change without notice programmed on its id field. a masking scheme makes it possibl e to match the id programmed on the mb with a range of ids on received can frames. for tr ansmission, an arbitratio n algorithm decides the prioritization of mbs to be transm itted based on the message id (optionally augmented by 3 local priority bits) or the mb ordering. before proceeding with the functional description, an important concept must be explained. a message buffer is said to be ?active? at a given time if it can participate in the matchi ng and arbitrat ion algorithms that are happening at that time. an rx mb with a ?0000? code is inactive (refer to table 18-5 ). similarly, a tx mb with a ?1000? or ?1001? c ode is also inac tive (refer to table 18-6 ). an mb not programmed with ?0000?, ?1000? or ?1001? will be temporarily deactivated (will not participate in the current arbitration or matching run) when the cpu writes to the c/s field of that mb (see section 18.4.6.2, message buffer deactivation ). 18.4.2 transmit process in order to transmit a can frame, the cpu must prepare a message buffer for transmission by executing the following procedure: ? if the mb is active (transmissi on pending), write an abort code (?1001?) to the code field of the control and status word to request an abortion of the transmission, then r ead back the code field and the ifrl/ifrh registers to check if the transmission was aborted (see section 18.4.6.1, transmission abort mechanism ). if backwards compatibility is desired (aen in mcr negated), just write ?1000? to the code field to inactiv ate the mb but then the pending frame may be transmitted without notification (see section 18.4.6.2, message bu ffer deactivation ). ? write the id word. ? write the data bytes. ? write the length, control and c ode fields of the control and status word to activate the mb. once the mb is activated in the fourth step, it will participate into the arbitrat ion process and eventually be transmitted according to its priority. at the end of the successful transmission, the value of the free running timer is written into the time stamp field, the code field in the control and status word is updated, a status flag is set in the interrupt flag regi ster and an interrupt is generated if allowed by the corresponding interrupt mask register bit. the new code fi eld after transmission de pends on the code that was used to activate the mb in step four (see table 18-5 and table 18-6 in section 18.3.2, message buffer structure ). when the abort feature is enable d (aen in mcr is asserted), afte r the interrupt flag is asserted for a mb configured as tran smit buffer, the mb is blocked, therefore the cpu is not able to update it until the interrupt flag be negated by cpu. it means that the cpu must clear the corresponding interrupt flag bit before starting to prepare this mb for a new transmission or reception. 18.4.3 arbitration process the arbitration process is an algorithm executed by the mbm that scans th e whole mb memory looking for the highest priority message to be transmitted. all mbs program med as transmit buffers will be
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-31 preliminary?subject to change without notice scanned to find the lowest id 1 or the lowest mb number or the hi ghest priority, depending on the lbuf and lprio_en bits on the control register. the arbitr ation process is triggered in the following events: ? during the crc field of the can frame ? during the error delimiter field of the can frame ? during intermission, if the winner mb defined in a previous arbitration was deactivated, or if there was no mb to transmit, but the cpu wrote to the c/s word of a ny mb after the previous arbitration finished ? when mbm is in idle or bus off state and the cpu writes to the c/s word of any mb ? upon leaving freeze mode when lbuf is asserted, the lprio_en bit has no effect and the lowest number buffer is transmitted first. when lbuf and lprio_en ar e both negated, the mb with the lowest id is transmitted fi rst but. if lbuf is negated and lprio_en is asserte d, the prio bits augment the id us ed during the arb itration process. with this extended id concept, arbi tration is done based on the full 32- bit id and the prio bits define which mb should be transmitted first, therefore mbs wi th prio = 000 have higher pr iority. if two or more mbs have the same priority, the regul ar id will determine th e priority of transmission. if two or more mbs have the same priority (3 extra bits) and the same regular id, the lowest mb will be transmitted first. once the highest priority mb is sel ected, it is transferred to a tem porary storage space called serial message buffer (smb), which has the same structure as a normal mb but is not user accessible. this operation is called ?move-out? and after it is done, wr ite access to the corresponding mb is blocked (if the aen bit in mcr is asserted). the write access is released in the following events: ? after the mb is transmitted ? flexcan enters in halt or bus off ? flexcan loses the bus arbitration or th ere is an error during the transmission at the first opportunity window on the can bus, the me ssage on the smb is tran smitted according to the can protocol rules. flexc an transmits up to eight data bytes, even if the dlc (data length code) value is bigger. 18.4.4 receive process to be able to receive can frames into the mail box mbs, the cpu must prep are one or more message buffers for reception by executing the following steps: ? if the mb has a pending transmission, write an abort code (?1001?) to the code field of the control and status word to request an abortion of the transmission, then r ead back the code field and the ifrl/ifrh registers to check if the transmission was aborted (see section 18.4.6.1, transmission abort mechanism ). if backwards compatibility is desired (aen in mcr negated), just write ?1000? to the code field to inactiv ate the mb, but then the pending frame may be transmitted without notification (see section 18.4.6.2, message bu ffer deactivation ). if the mb already programmed as a receiver, just write ?0000? to the code field of the control and status word to keep the mb inactive. 1. actually, if lbuf is negated, the arbitration considers not only the id, but also the rtr and ide bits placed inside the id a t the same positions they are tr ansmitted in the can frame.
pxd10 microcontroller reference manual, rev. 1 18-32 freescale semiconductor preliminary?subject to change without notice ? write the id word ? write ?0100? to the code field of the c ontrol and status word to activate the mb once the mb is activated in the third step, it will be able to receive frames that match the programmed id. at the end of a successful reception, the mb is updated by the mbm as follows: ? the value of the free running timer is written into the time stamp field ? the received id, data (8 bytes at most) and length fields are stored ? the code field in the control and status word is updated (see table 18-5 and table 18-6 in section 18.3.2, message buffer structure ) ? a status flag is set in the interrupt flag regist er and an interrupt is generated if allowed by the corresponding interrupt mask register bit upon receiving the mb interrupt, the cpu should se rvice the received frame using the following procedure: ? read the control and status word (mandatory ? activates an internal lock for this buffer) ? read the id field (optional ? needed only if a mask was used) ? read the data field ? read the free running timer (optional ? releases the internal lock) upon reading the control and status word, if the busy bit is set in the code field, then the cpu should defer the access to the mb until th is bit is negated. reading the free running timer is not mandatory. if not executed the mb remains locke d, unless the cpu reads th e c/s word of another mb. note that only a single mb is locked at a time. th e only mandatory cpu read operation is the one on the control and status word to assure data coherency (see section 18.4.6, data coherence ). the cpu should synchronize to frame reception by the status flag bit for the specific mb in one of the interrupt flag registers (ifrl, ifrh ) and not by the code fiel d of that mb. polling the code field does not work because once a frame was received and the cpu se rvices the mb (by readi ng the c/s word followed by unlocking the mb), the code field will not return to empty. it wi ll remain full, as explained in table 18-5 . if the cpu tries to workaround this behavior by writing to the c/s word to force an empty code after reading the mb, the mb is actually deactivated from any currently ongoing ma tching process. as a result, a newly received frame matching th e id of that mb may be lost. in summary: never do polling by reading directly the c/s word of the mbs. instead, read the in terrupt flag registers (ifrl, ifrh). note that the received id field is al ways stored in the matching mb, thus the contents of the id field in an mb may change if the match was due to masking. note also that flexcan does r eceive frames transmitted by itself if there exists an rx matching mb, provi ded the srx_dis bit in the mcr is not asserted. if srx_dis is asserted, flexcan will not store frames transmitted by itself in any mb, even if it contains a matching mb, and no interrupt flag or interrupt si gnal will be generated due to the frame reception. to be able to receive can frames through the fifo, the cpu must enab le and configure the fifo during freeze mode (see section 18.4.7, rx fifo ). upon receiving the frames avai lable interrupt from fifo, the cpu should service the received fram e using the following procedure: ? read the control and status word (optional ? ne eded only if a mask wa s used for ide and rtr bits)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-33 preliminary?subject to change without notice ? read the id field (optional ? needed only if a mask was used) ? read the data field ? clear the frames available interr upt (mandatory ? release the buffe r and allow the cpu to read the next fifo entry) 18.4.5 matching process the matching process is an algorithm executed by th e mbm that scans the mb memory looking for rx mbs programmed with the same id as the one receiv ed from the can bus. if the fifo is enabled, the 8-entry id table from fifo is sca nned first and then, if a match is not found within the fifo table, the other mbs are scanned. in the event that the fifo is full, the matching algorithm will always look for a matching mb outside the fifo region. when the frame is received, it is te mporarily stored in a hi dden auxiliary mb called serial message buffer (smb). the matching process takes pl ace during the crc field of the receiv ed frame. if a matching id is found in the fifo table or in one of the regular mbs, the contents of the smb will be transferred to the fifo or to the matched mb during the 6th bit of the end-of-frame field of the can protocol. this operation is called ?move-in?. if a ny protocol error (crc, ack, etc.) is detected, than the move-in operation does not happen. for the regular mailbox mbs, an mb is said to be ?free to receive? a new frame if the following conditions are satisfied: ? the mb is not locked (see section 18.4.6.3, message buffer lock mechanism ) ? the code field is either empty or else it is full or overrun but the cpu has already serviced the mb (read the c/s word and then unlocked the mb) if the first mb with a matching id is not ?free to receive? the new frame, then the matching algorithm keeps looking for another free mb until it finds one. if it can not find one that is fr ee, then it will overwrite the last matching mb (unless it is locked) and set the code field to overrun (refer to table 18-5 and table 18-6 ). if the last matching mb is locked, then th e new message remains in the smb, waiting for the mb to be unlocked (see section 18.4.6.3, message buff er lock mechanism ). suppose, for example, that the fifo is disabled a nd there are two mbs with the same id, and flexcan starts receiving messages with that id. let us say that these mbs are the second and the fifth in the array. when the first message arrives, the matching algorithm will find the first match in mb number 2. the code of this mb is empty, so the message is stored there. when the second message arrives, the matching algorithm will find mb number 2 again, but it is not ?free to receive?, so it will keep looking and find mb number 5 and store the message there. if yet anothe r message with the same id arrives, the matching algorithm finds out that there are no matching mbs that are ?free to receiv e?, so it decides to overwrite the last matched mb, which is number 5. in doing so, it se ts the code field of th e mb to indicate overrun. the ability to match the same id in more than one mb can be exploited to implement a reception queue (in addition to the full featured fi fo) to allow more time for the cpu to service the mbs. by programming more than one mb with the same id, received me ssages will be queued into the mbs. the cpu can examine the time stamp field of the mbs to dete rmine the order in which the messages arrived.
pxd10 microcontroller reference manual, rev. 1 18-34 freescale semiconductor preliminary?subject to change without notice the matching algorithm described above can be changed to be the same one used in previous versions of the flexcan module. when the bcc bit in mcr is negated, the matchi ng algorithm stops at the first mb with a matching id that it founds, whether this mb is free or not. as a result, the message queueing feature does not work if the bcc bit is negated. matching to a range of ids is possible by using id acceptance masks. flexcan supports individual masking per mb. please refer to section 18.3.4.13, rx individual mask registers (rximr0?rximr63) . during the matching algorithm, if a ma sk bit is asserted, th en the corresponding id bi t is compared. if the mask bit is negated, the corresponding id bit is ?d on?t care?. please note th at the individual mask registers are implemented in ram, so they are not initialized out of reset. also, they can only be programmed if the bcc bit is asserted and while the module is in freeze mode. flexcan also supports an alternate masking sche me with only three mask registers (rgxmask, rx14mask and rx15mask) for backwards compatibilit y. this alternate masking scheme is enabled when the bcc bit in the mcr register is negated. 18.4.6 data coherence in order to maintain data cohere ncy and flexcan proper ope ration, the cpu must obe y the rules described in transmit process and section 18.4.4, receive process . any form of cpu accessing an mb structure within flexcan other than those specified may ca use flexcan to behave in an unpredictable way. 18.4.6.1 transmission abort mechanism the abort mechanism provides a safe way to request the abortion of a pending transmission. a feedback mechanism is provided to inform th e cpu if the transmission was aborte d or if the frame could not be aborted and was transmitted instead. in order to maintain backwards compatibility, the abort mechanism must be explicitly enabled by as serting the aen bit in the mcr. in order to abort a transmission, the cpu must write a specific abort code (1001) to the code field of the control and status word. when the abort mechanism is enabled, the acti ve mbs configured as trasmission must be aborted first and then they may be updated. if the abort code is wr itten to an mb th at is currently being transmitted, or to an mb th at was already loaded into the sm b for transmission, the write operation is blocked and the mb is not deactivated, but the a bort request is captured a nd kept pending until one of the following conditions are satisfied: ? the module loses the bus arbitration ? there is an error during the transmission ? the module is put into freeze mode if none of conditions above are reache d, the mb is transmitted correctly, the interrupt flag is set in the interrupt flag registers (ifrl, if rh) and an interrupt to the cpu is generated (if enabled). the abort request is automatically cleared when the interrupt fl ag is set. in the other hand, if one of the above conditions is reached, the frame is not transmitted, ther efore the abort code is wr itten into the code field, the interrupt flag is set in the interrupt flag regi sters (ifrl, ifrh) and an interrupt is (optionally) generated to the cpu.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-35 preliminary?subject to change without notice if the cpu writes the abort code before the transmissi on begins internally, then the write operation is not blocked, therefore the mb is updated and no interrupt flag is set. in th is way the cpu just needs to read the abort code to make sure the active mb was deactivated. although th e aen bit is asserted and the cpu wrote the abort code, in this case the mb is deactiv ated and not aborted, because the transmission did not start yet. one mb is only aborted when the abort request is captured and kept pending until one of the previous conditions are satisfied. the abort procedure can be summarized as follows: ? cpu writes 1001 into the code field of the c/s word ? cpu reads the code field and compares it to the value that was written ? if the code field that was read is different from the value that was written, the cpu must read the corresponding interrupt flag to check if the fr ame was transmitted or it is being currently transmitted. if the corresponding in terrupt flag bit is set, the frame was transmitted. if the corresponding interrupt flag bit is reset, the cpu must wait for it to be set, and then the cpu must read the code field to check if the mb wa s aborted (code=1001) or it was transmitted (code=1000). 18.4.6.2 message buffer deactivation deactivation is mechanism pr ovided to maintain data coherence when the cpu writes to the control and status word of active mbs out of freeze mode. any cpu write access to the control and status word of an mb causes that mb to be excluded from the tran smit or receive processes during the current matching or arbitration round. the de activation is temporary, affecting only for the current match/arbitration round. the purpose of deactivation is data coherency. the match/arbitration process scans the mbs to decide which mb to transmit or receive. if the cpu updates the mb in the middle of a match or arbitration process, the data of that mb ma y no longer be coherent, therefore de activation of that mb is done. even with the coherence mechanism described above, writing to the control and status word of active mbs when not in freeze mode may produ ce undesirable results. examples are: ? matching and arbitration are one-p ass processes. if mbs are deactivated after they are scanned, no re-evaluation is done to determine a new match/ winner. if an rx mb with a matching id is deactivated during the matching proce ss after it was scanned, then this mb is marked as invalid to receive the frame, and flexcan wi ll keep looking for another matc hing mb within the ones it has not scanned yet. if it can not find one, then the message will be lost . suppose, for example, that two mbs have a matching id to a recei ved frame, and the user deactivat ed the first matching mb after flexcan has scanned the second. the received frame will be lost ev en if the second matching mb was ?free to receive?. ? if a tx mb containing th e lowest id is deactivated after fl excan has scanned it, then flexcan will look for another winner within the mbs that it has not scanned yet. ther efore, it may transmit an mb with id that may not be the lowest at the time because a lo wer id might be present in one of the mbs that it had already scanned before the deactivation. ? there is a point in time until which the deactivati on of a tx mb causes it not to be transmitted (end of move-out). after this point, it is transmitted but no interrupt is issued and the code field is not
pxd10 microcontroller reference manual, rev. 1 18-36 freescale semiconductor preliminary?subject to change without notice updated. in order to avoid this situati on, the abort procedures described in section 18.4.6.1, transmission abort mechanism should be used. 18.4.6.3 message buffer lock mechanism besides mb deactivation, flexcan ha s another data coherence mechanis m for the receive process. when the cpu reads the control and status word of an ?active not empty? rx mb, flexcan assumes that the cpu wants to read the whole mb in an atomic operation, and thus it sets an internal lock flag for that mb. the lock is released when the cpu reads the free running timer (global unlock operation), or when it reads the control and status word of another mb. th e mb locking is done to prevent a new frame to be written into the mb while the cpu is reading it. note the locking mechanism only applies to rx mbs which have a code different than inactive (?0000?) or empty 1 (?0100?). also, tx mbs can not be locked. suppose, for example, that the fifo is disabled and the second and the fifth mbs of the array are programmed with the same id, and flexcan has already received and stored messages into these two mbs. suppose now that the cpu decide s to read mb number 5 and at th e same time another message with the same id is arriving. when the cpu reads the cont rol and status word of mb number 5, this mb is locked. the new message arrives and the matching algorithm finds out that there are no ?free to receive? mbs, so it decides to override mb number 5. however, this mb is lock ed, so the new me ssage can not be written there. it will remain in the smb waiting fo r the mb to be unlocked, a nd only then will be written to the mb. if the mb is not unlocke d in time and yet anothe r new message with the same id arrives, then the new message overwrites th e one on the smb and there wi ll be no indication of lo st messages either in the code field of the mb or in the error and status register. while the message is being moved-in from the smb to the mb, the busy bit on the code field is asserted. if the cpu reads the control and status word and finds out that the busy bit is set, it should defer accessing the mb until the busy bit is negated. note if the busy bit is asserted or if the mb is empty, then reading the control and status word does not lock the mb. deactivation takes precedence over lock ing. if the cpu deactivates a locked rx mb, then its lock status is negated and the mb is marked as invalid fo r the current matching round. any pending message on the smb will not be transferred anymore to the mb. 18.4.7 rx fifo the receive-only fifo is enabled by a sserting the fen bit in the mcr. the reset value of this bit is zero to maintain software backwards comp atibility with previous versions of the module that did not have the fifo feature. when the fifo is enabled, the me mory region normally occ upied by the first 8 mbs 1. in previous flexcan versions, reading the c/s word locked the mb even if it was empty. this behavior will be honoured when the bcc bit is negated.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-37 preliminary?subject to change without notice (0x80-0xff) is now reserved for use of the fifo engine (see section 18.3.3, rx fifo structure ). management of read and write pointers is done inte rnally by the fifo engine. the cpu can read the received frames sequentially, in the order they we re received, by repeatedly accessing a message buffer structure at the beginning of the memory. the fifo can store up to six frames pending service by the cpu. an interrupt is sent to the cpu when new frames are available in the fifo. upon receiv ing the interrupt, the cpu must read the frame (accessing an mb in the 0x80 address) a nd then clear the interrupt. the act of clearing the interrupt triggers the fifo engine to replace the mb in 0x80 with the next frame in the queue, and then issue another interrupt to the cpu. if the fifo is full and more frames continue to be received, an overflow interrupt is issued to the cpu and subsequent frames are not accepted until the cpu creates space in the fifo by reading one or more fram es. a warning interrupt is also generated when four frames are accumulated in the fifo. a powerful filtering scheme is provided to accept onl y frames intended for the target application, thus reducing the interrupt servicing work load. the filtering criteria is sp ecified by programmin g a table of 8 32-bit registers that can be configured to one of the following formats (see also section 18.3.3, rx fifo structure ): ? format a: 8 extended or standard ids (including ide and rtr) ? format b: 16 standard ids or 16 extended 14-bit id slices (i ncluding ide and rtr) ? format c: 32 standard or extended 8-bit id slices note a chosen format is applied to all eight re gisters of the filter table. it is not possible to mix formats within the table. the eight elements of the filter ta ble are individually affected by the first eight individual mask registers (rximr0 - rximr7), allowing very powerful filtering criteria to be defined. the rest of the rximr, starting from rxim8, continue to affe ct the regular mbs, starting from mb8. if the bcc bit is negated (or if the rximr are not available for the particular mcu), then the fifo filt er table is affected by the legacy mask registers as follows: elem ent 6 is affected by rx14mask, el ement 7 is affected by rx15mask and the other elements (0 to 5) are affected by rxgmask. 18.4.8 can protocol related features 18.4.8.1 remote frames remote frame is a special kind of frame. the user can program a mb to be a request remote frame by writing the mb as transmit with th e rtr bit set to ?1?. after the remote request frame is transmitted successfully, the mb becomes a receive message buffer, with the same id as before. when a remote request frame is received by flexcan, its id is compared to the ids of the transmit message buffers with the code fi eld ?1010?. if there is a matching id, then this mb frame will be transmitted. note that if the matching mb has the rt r bit set, then flexcan will transmit a remote frame as a response.
pxd10 microcontroller reference manual, rev. 1 18-38 freescale semiconductor preliminary?subject to change without notice a received remote request frame is no t stored in a receive buffer. it is only used to trigger a transmission of a frame in response. the mask re gisters are not used in remote fram e matching, and all id bits (except rtr) of the incoming received frame should match. in the case that a remote request frame was r eceived and matched an mb, this message buffer immediately enters the internal arbi tration process, but is considered as normal tx mb, with no higher priority. the data length of this fr ame is independent of the dlc field in the remote frame that initiated its transmission. if the rx fifo is enabled (bit fen set in mcr), flexcan will not generate an automatic response for remote request frames that match the fifo filteri ng criteria. if the remote frame matches one of the target ids, it will be stor ed in the fifo and presented to the cpu. note that for filtering formats a and b, it is possible to select wh ether remote frames are ac cepted or not. for format c, remote frames are always accepted (if they match the id). 18.4.8.2 overload frames flexcan does transmit overload frames due to detection of following conditions on can bus: ? detection of a dominant bit in th e first/second bit of intermission ? detection of a dominant bit at the 7th bit (last) of end of frame field (rx frames) ? detection of a dominant bit at th e 8th bit (last) of error fram e delimiter or overload frame delimiter 18.4.8.3 time stamp the value of the free running timer is sampled at the beginning of th e identifier field on the can bus, and is stored at the end of ?move -in? in the time stamp field, provi ding network behavior with respect to time. note that the free running timer can be reset upon a specific frame recepti on, enabling network time synchronization. refer to tsyn description in section 18.3.4.2, control register (ctrl) . 18.4.8.4 protocol timing figure 18-16 shows the structure of the clock generation ci rcuitry that feeds the can protocol interface (cpi) sub-module. the clock source bit (clk_src) in the ctrl register defines whether the internal clock is connected to the output of a crystal oscill ator (oscillator clock) or to the peripheral clock (generally from a pll). in order to guarantee reliable opera tion, the clock source s hould be selected while the module is in disable mode (bit mdis set in the module c onfiguration register).
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-39 preliminary?subject to change without notice figure 18-16. can engine clocking scheme the crystal oscillator cloc k should be selected whenever a tight to lerance (up to 0.1%) is required in the can bus timing. the crystal oscillator clock has better jitter pe rformance than pll generated clocks. note this clock selection featur e may not be available in all mcus. a particular mcu may not have a pll, in which case it would have only the oscillator clock, or it may use only the pll cl ock feeding the flexcan module. in these cases, the clk_src bit in the ctrl register has no effect on the module operation. the flexcan module supports a variet y of means to setup bi t timing parameters th at are required by the can protocol. the control register has various fields used to control bit timing parameters: presdiv, propseg, pseg1, pseg2 and rjw. see section 18.3.4.2, control register (ctrl) . the presdiv field controls a prescal er that generates the serial cloc k (sclock), whose period defines the ?time quantum? used to compose th e can waveform. a time quantum is the atomic unit of time handled by the can engine. a bit time is subdivided into three segments 1 (reference figure 18-17 and table 18-19 ): ? sync_seg: this segment has a fixed length of one time quantum. signal e dges are expected to happen within this section ? time segment 1: this segment includes the propa gation segment and the phase segment 1 of the can standard. it can be program med by setting the propseg and th e pseg1 fields of the ctrl register so that their sum (plus 2) is in the range of 4 to 16 time quanta ? time segment 2: this segment represents the ph ase segment 2 of the can standard. it can be programmed by setting the pse g2 field of the ctrl register (plu s 1) to be 2 to 8 time quanta long 1. for further explanation of the underlying concepts please refer to iso/dis 11519 ? 1, section 10.3. reference also the bosch can 2.0a/b protocol specification dated september 1991 for bit timing. peripheral clock (pll) oscillator clock (xtal) clk_src prescaler (1 .. 256) sclock cpi clock f tq f canclk prescaler v alue t ?? ---------------------- ----------------- ---------------- - = bit rate f tq number of time quanta tt t ?? ------------------- ------------------ ----------------- ------------------ ---------------- - = t
pxd10 microcontroller reference manual, rev. 1 18-40 freescale semiconductor preliminary?subject to change without notice figure 18-17. segments within the bit time table 18-20 gives an overview of the can compliant segmen t settings and the related parameter values. table 18-19. time segment syntax syntax description sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node samples the bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. table 18-20. can standard compliant bit time segment settings time segment 1 time segment 2 resynchronization jump width 5 .. 10 2 1 .. 2 4 .. 11 3 1 .. 3 5 .. 12 4 1 .. 4 6 .. 13 5 1 .. 4 7 .. 14 6 1 .. 4 8 .. 15 7 1 .. 4 9 .. 16 8 1 .. 4 sync_seg time segment 1 time segment 2 1 4 ... 16 2 ... 8 8 ... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + pseg1 + 2) (pseg2 + 1) transmit point
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-41 preliminary?subject to change without notice note it is the user?s responsibility to ensure the bit time settings are in compliance with the can standard. for bit time calculations, use an ipt (information processing time) of 2, which is the value implemented in the flexcan module. 18.4.8.5 arbitration a nd matching timing during normal transmission or rece ption of frames, the arbitrati on, matching, move-in and move-out processes are executed during certain time windows inside the can frame, as shown in figure 18-18 . figure 18-18. arbitration, match and move time windows when doing matching and arbitration, flexcan needs to scan the whole message bu ffer memory during the available time slot. in order to have sufficient time to do that, the following requirements must be observed: ? a valid can bit timing must be programmed, as indicated in table 18-20 ? the peripheral clock frequency can not be smaller than the oscillator clock frequency, i.e. the pll can not be programmed to divi de down the oscillator clock ? there must be a minimum ratio between the peri pheral clock frequency and the can bit rate, as specified in table 18-21 a direct consequence of the first re quirement is that the minimum numbe r of time quanta per can bit must be 8, so the oscillator cl ock frequency should be at least 8 times the can bit ra te. the minimum frequency ratio specified in table 18-21 can be achieved by choosing a high e nough peripheral clock frequency when compared to the oscillator clock frequency, or by adjusting one or more of the bit timing parameters (presdiv, propseg, pseg1, pseg2). as an example, taking the case of 64 mbs, if the oscillator and peripheral clock frequencies are e qual and the can bit timing is progr ammed to have 8 time quanta per bit, then the prescaler factor (pre sdiv + 1) should be at least 2. for prescaler factor equal to one and table 18-21. minimum ratio between peri pheral clock frequency and can bit rate number of message buffers minimum ratio 16 8 32 8 64 16 crc (15) eof (7) interm start move matching/arbitration window (24 bits) move (bit 6) window
pxd10 microcontroller reference manual, rev. 1 18-42 freescale semiconductor preliminary?subject to change without notice can bit timing with 8 time quanta per bit, the ratio between peripheral and os cillator clock frequencies should be at least 2. 18.4.9 modes of operation: details 18.4.9.1 freeze mode this mode is entered by asserting the halt bit in the mcr register or when the mcu is stopped by a debugger. in both cases it is also necessary that the fr z bit is asserted in the mcr register and the module is not in any of the low power modes (disable, doze, stop). when freeze m ode is requested during transmission or reception, flexcan does the following: ? waits to be in either intermission, passive error, bus off or idle state ? waits for all internal activi ties like arbitration, matching, move-in and move-out to finish ? ignores the rx input pin and dr ives the tx pin as recessive ? stops the prescaler, thus halt ing all can prot ocol activities ? grants write access to the erro r counters register, which is read-only in other modes ? sets the not_rdy and frz_ack bits in mcr after requesting freeze mode, the us er must wait for the frz_ack bit to be asserted in mcr before executing any other action, otherwise flexcan may operate in an unpredic table way. in freeze mode, all memory mapped registers are accessible. exiting freeze mode is done in one of the following ways: ? cpu negates the frz bit in the mcr register ? the mcu is started by the debugger and/or the halt bit is negated once out of freeze mode, fl excan tries to resynchronize to the can bus by waiting fo r 11 consecutive recessive bits. 18.4.9.2 module disable mode this low power mode is entered when the mdis bit in the mcr register is asserted. if the module is disabled during freeze mode, it shuts down the clocks to the cpi and mbm sub-modules, sets the lpm_ack bit and negates the frz_ack bit. if the m odule is disabled during tr ansmission or reception, flexcan does the following: ? waits to be in either idle or bus off state, or else waits for th e third bit of intermission and then checks it to be recessive ? waits for all internal activi ties like arbitration, matching, move-in and move-out to finish ? ignores its rx input pin and dr ives its tx pin as recessive ? shuts down the clocks to the cpi and mbm sub-modules ? sets the not_rdy and lpm_ack bits in mcr the bus interface unit continues to operate, enabling the cpu to access memory mapped registers, except the free running timer, the error counter register and the message buffers, which cannot be accessed
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-43 preliminary?subject to change without notice when the module is in disable mode . exiting from this mode is done by negating the mdis bit, which will resume the clocks and negate the lpm_ack bit. 18.4.10 interrupts the module can generate up to 70 inte rrupt sources (64 interrupts due to message buffers and 6 interrupts due to ored interrupts from mbs, bus off, error, tx warning, rx warning and wake up). the number of actual sources depends on the conf igured number of message buffers. on this device, the individual mb interrupts are grouped as follows: ? groups of four interrupts (up to mb 16) ? mb16_31 ? mb32_63 these are then used as the interrupt source. each one of the message buffers can be an interrupt s ource, if its corresponding ma sk bit is set. there is no distinction between tx and rx in terrupts for a particular buffer, unde r the assumption that the buffer is initialized for either transmission or reception. each of the buffers has assigned a flag bit in the ifrl or ifrh registers. the bit is set when the corresponding buffer completes a successf ul transmission/reception and is cleared when the cpu writes it to ?1? (unles s another interrupt is gene rated at the same time). note it must be guaranteed that the cpu only clears the bit causing the current interrupt. for this reason, bit manipulati on instructions (bset) must not be used to clear interrupt flags. thes e instructions may cause accidental clearing of interrupt flags which are se t after entering the current interrupt service routine. if the rx fifo is enabled (bit fen on mcr set) , the interrupts corresponding to mbs 0 to 7 have a different behavior. bit 7 of the if rl becomes the ?fifo overflow? flag ; bit 6 becomes the fifo warning flag, bit 5 becomes the ?frames available in fifo flag? and bits 4-0 are unused. see section 18.3.4.12, interrupt flag register low (ifrl) for more information. a combined interrupt for all mbs is also generated by an or of all the interrupt sources from mbs. this interrupt gets generated when any of the mbs generate s an interrupt. in this case the cpu must read the ifrl and ifrh registers to determ ine which mb caused the interrupt. the other 5 interrupt source s (bus off, error, tx warning, rx wa rning and wake up) generate interrupts like the mb ones, and can be read from the error and status register. the bus off, error, tx warning and rx warning interrupt mask bits are located in the c ontrol register, and the wake -up interrupt mask bit is located in the mcr. 18.4.11 bus interface the cpu access to flexcan registers ar e subject to the following rules: ? read and write access to supe rvisor registers in user mo de results in access error.
pxd10 microcontroller reference manual, rev. 1 18-44 freescale semiconductor preliminary?subject to change without notice ? read and write access to unimplement ed or reserved address space al so results in access error. any access to unimplemented mb or rx individual mask regist er locations results in access error. any access to the rx individual mask register space when the bcc bit in mcr is negated results in access error. ? if maxmb is programmed with a value smaller than the available number of mbs, then the unused memory space can be used as general pu rpose ram space. note that the rx individual mask registers can only be accessed in freeze mode , and this is still true for unused space within this memory. note also that re served words within ram cannot be used. as an example, suppose flexcan is configured with 64 mbs and maxmb is program med with zero. the maximum number of mbs in this case b ecomes one. the mb memory star ts at 0x0060, but the space from 0x0060 to 0x007f is reserved (for smb usage), and the space fr om 0x0080 to 0x008f is used by the one mb. this leaves us wi th the available space from 0x0090 to 0x047f. the available memory in the mask registers space would be from 0x0884 to 0x097f. note unused mb space must not be us ed as general purpose ram while flexcan is transmitting an d receiving can frames. 18.5 initialization/application information this section provide instructions for initializing the flexcan module. 18.5.1 flexcan initialization sequence the flexcan module may be reset in three ways: ? mcu level hard reset, which resets all memory mapped re gisters asynchronously ? mcu level soft reset, which rese ts some of the memory mapped re gisters synchronous ly (refer to table 18-2 to see what registers are affected by soft reset) ? soft_rst bit in mcr, which has the same effect as the mcu level soft reset soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. therefore, it may take some time to full y propagate its effects. the soft_rst bit remains asserted while soft reset is pending, so software can poll this bit to know when the reset has completed. also, soft reset can not be applied while clocks ar e shut down in any of the low power modes. the low power mode should be exited and the cloc ks resumed before applying soft reset. the clock source (clk_src bit) should be selected while the module is in disa ble mode. after the clock source is selected and the module is enabled (mdis bit negated), fl excan automatically goes to freeze mode. in freeze mode, flexcan is un-synchronized to the can bus, the halt and frz bits in mcr register are set, the internal state machines ar e disabled and the frz_ack and not_rdy bits in the mcr register are set. the tx pin is in recessive state a nd flexcan does not initi ate any transmission or reception of can frames. note that the message buffers and the rx in dividual mask registers are not affected by reset, so they ar e not automatically initialized.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 18-45 preliminary?subject to change without notice for any configuration change/initialization it is re quired that flexcan is put into freeze mode (see section 18.4.9.1, freeze mode ). the following is a generic initia lization sequence applicable to the flexcan module: ? initialize the module configuration register ? enable the individual filtering per mb and r eception queue features by setting the bcc bit ? enable the warning interrupts by setting the wrn_en bit ? if required, disable frame self re ception by setting the srx_dis bit ? enable the fifo by setting the fen bit ? enable the abort mechanism by setting the aen bit ? enable the local priority feature by setting the lprio_en bit ? initialize the control register ? determine the bit timing parame ters: propseg, pseg1, pseg2, rjw ? determine the bit rate by programming the presdiv field ? determine the internal ar bitration mode (lbuf bit) ? initialize the message buffers ? the control and status word of all message buffers must be initialized ? if fifo was enabled, the 8-entr y id table must be initialized ? other entries in each message buffer should be initialized as required ? initialize the rx individual mask registers ? set required interrupt mask bits in the mask registers (for all mb in terrupts), in ctrl register (for bus off and error interrupts) and in mcr register for wake-up interrupt ? negate the halt bit in mcr starting with the last event, flexcan attempts to synchronize to the can bus. 18.5.2 flexcan addressing an d ram size configurations there are 3 ram configurations that can be impl emented within the flexcan module. the possible configurations are: ? for 16 mbs: 288 bytes for mb memory an d 64 bytes for individual mask registers ? for 32 mbs: 544 bytes for mb memory an d 128 bytes for individual mask registers ? for 64 mbs: 1056 bytes for mb memory a nd 256 bytes for individual mask registers in each configuration the user ca n program the maximum number of mbs that will take part in the matching and arbitration proce sses using the maxmb field in the mcr register. for 16 mb configuration, maxmb can be any number between 0?15. for 32 mb configuration, maxmb can be any number between 0?31. for 64 mb configura tion, maxmb can be a ny number between 0 ? 63.
pxd10 microcontroller reference manual, rev. 1 18-46 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 19-1 preliminary?subject to change without notice chapter 19 ieee 1149.1 test access port controller (jtagc) 19.1 introduction the jtag port of the device consists of three inputs and one output. these pins include test data input (tdi), test data output (tdo), test mode select (tms), and test cloc k input (tck). tdi, tdo, tms, and tck are compliant with the ieee 1149.1-2001 standard and are shared with the ndi through the test access port (tap) interface. ieee 1149.7 (cjtag) is not supported on this device. 19.2 block diagram figure 19-1 is a block diagram of the jtag controller (jtagc). figure 19-1. jtag controller block diagram 19.3 overview the jtagc provides the means to test chip functionality and connectivit y while remaining transparent to system logic when not in test mode. testing is performed via a boundary scan t echnique, as defined in the ieee 1149.1-2001 standard. in additi on, instructions can be executed th at allow the test access port (tap) to be shared with other modules on the mcu. all data input to and output from the jtagc is communicated in serial format. tck tms tdi test access port (tap) tdo 32-bit device identification register boundary scan register . . controller 1-bit bypass register . 5-bit tap instruction decoder 5-bit tap instruction register . . . power-on reset
pxd10 microcontroller reference manual, rev. 1 19-2 freescale semiconductor preliminary?subject to change without notice 19.4 features the jtagc is compliant with the ieee 1149.1-2001 st andard, and supports th e following features: ? ieee 1149.1-2001 test access port (tap) interface ? 4 pins (see section 19.6, external signal description ) ?tdi ?tms ?tck ?tdo ? a 5-bit instruction register th at supports several ieee 1149.1-2001 defined instru ctions, as well as several public and private mcu specific instructions ? three test data registers, a bypass register, and a de vice identification register ? a tap controller state machine that controls the operation of the data registers, instruction register and associated circuitry 19.5 modes of operation the jtagc uses a power-on reset indication as it s primary reset signals. several ieee 1149.1-2001 defined test modes are supporte d, as well as a bypass mode. 19.5.1 reset the jtagc is placed in reset when the tap controller state machine is in the test-logic-reset state. the test-logic-reset state is ente red upon the assertion of the power -on reset signal, or through tap controller state machine transitions controlled by tms. as serting power-on reset results in asynchronous entry into the reset state. while in reset, the following actions occur: ? the tap controller is forced into the test-logic- reset state, thereby disa bling the test logic and allowing normal operation of the on-chip system logic to continue unhindered. ? the instruction register is load ed with the idcode instruction. in addition, execution of certain instructions can result in assertion of the internal system reset. these instructions include extest. 19.5.2 ieee 1149.1-2001 defined test modes the jtagc supports several ieee 1149.1- 2001 defined test modes. the test mode is selected by loading the appropriate instruction into the instruction re gister while the jtagc is enabled. supported test instructions include extest, sample and sample/ preload. each instruction defines the set of data registers that can operate and in teract with the on-chip system logi c while the instruction is current. only one test data register path is enabled to shift data betwee n tdi and tdo for each instruction. the boundary scan register is external to jtagc but can be accessed by jtagc tap through extest,sample,sample/preload instructions. the f unctionality of each test mode is explained in more detail in section 19.8.4, jtagc instructions .?
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 19-3 preliminary?subject to change without notice 19.5.2.1 bypass mode when no test operation is required, the bypass instruction can be load ed to place the jtagc into bypass mode. while in bypass mode, the single-bit bypass shif t register is used to provide a minimum-length serial path to shift da ta between tdi and tdo. 19.5.2.2 tap sharing mode there are three selectable auxiliar y tap controllers that share the tap with the jtagc. selectable tap controllers include the nexus port controller (npc) and platfrom. the instructions required to grant ownership of the tap to the auxiliary tap controllers are access_aux_tap_npc, access_aux_tap_once, access_aux_tap_tcu. in struction opcodes for each instruction are shown in table 19-3 . when the access instruction fo r an auxiliary tap is loaded, control of the jtag pins is transferred to the selected tap controller. a ny data input via tdi and tm s is passed to the selected tap controller, and any tdo output from the selected tap c ontroller is sent back to the jtagc to be output on the pins. the jtagc regains control of the jt ag port during the update-dr st ate if the pause-dr state was entered. auxiliary tap controllers are held in run-test/idle while they are inactive. for more information on the tap controllers refer to chapter 26, nexus development interface (ndi) .
pxd10 microcontroller reference manual, rev. 1 19-4 freescale semiconductor preliminary?subject to change without notice 19.6 external signal description the jtagc consists of four signals that connect to off-chip development tools and allow access to test support functions. the jtagc signals are outlined in table 19-1 . all 4 jtag pins (tck/tms/tdi/tdo) are shared with gpio pins, so that the software may configure these pins as input/output by progr amming the appropriate registers. to ensure the proper working of jtag, these registers have a reset value such th at these pins behave as jtag pins when the por is lifted: ? tdi : input/pull-up ? tck : input/pull-up ? tms : input/pull-up ? tdo : high-z/pull-disabled on entry to standby mode the tdo pin goes to the high-z/pull-disabled state. some external debugger connections may expect th e tdo to be in a known state during sta ndby so an external pull up or down may be required for correct operation when debugging standby. 19.7 memory map and register description this section provides a detailed de scription of the jtagc registers accessible thr ough the tap interface, including data registers and the instru ction register. individual bit-level descriptions and reset states of each register are included. these registers are not memory-mapped a nd can only be accessed through the tap. 19.7.1 instruction register the jtagc uses a 5-bit instruction register as shown in figure 19-2 . the instruction register allows instructions to be loaded into the module to select the test to be performed or the test data register to be accessed or both. instructions are shifted in through tdi while the tap controller is in the shift-ir state, and latched on the falling edge of tck in the update -ir state. the latched inst ruction value can only be changed in the update-ir and te st-logic-reset tap controller st ates. synchronous entry into the test-logic-reset state results in the idcode inst ruction being loaded on the falling edge of tck. asynchronous entry into the test-logic-reset state results in asynchronous loading of the idcode instruction. during the capture-ir tap co ntroller state, the instruction sh ift register is loaded with the value 0b10101, making this value the register?s read value when the ta p controller is sequenced into the shift-ir state. table 19-1. jtag signal properties name i/o function reset state tck i test clock pull up tdi i test data in pull up tdo o test data out high z tms i test mode select pull up
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 19-5 preliminary?subject to change without notice 19.7.2 bypass register the bypass register is a single-bit shif t register path selected for serial data transfer be tween tdi and tdo when the bypass, or reserve instructions are active. after entry into the captur e-dr state, the single-bit shift register is set to a logic 0. therefore, the first bit shifted out after selecting the bypass register is always a logic 0. 19.7.3 device identification register the device identification register, shown in figure 19-3 , allows the part revisi on number, design center, part identification number, and manuf acturer identity code to be dete rmined through the tap. the device identification register is selected for serial data transfer betw een tdi and tdo when the idcode instruction is active. entry into the capture-dr stat e while the device identificat ion register is selected loads the idcode into the shift regi ster to be shifted out on tdo in the shift-dr st ate. no action occurs in the update-dr state. 43210 r1 0 1 01 w instruction code reset00001 figure 19-2. 5-bit instruction register ir[4:0]: 0_0001 (idcode) access: r/o 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r prn dc pin mic id w reset 00001010111001100000000000011101 figure 19-3. device identification register table 19-2. device identification register field descriptions field description 0?3 prn part revision number. contains the revision number of the device. this field changes with each revision of the device or module. 4?9 dc design center. 10?19 pin part identification number. contains the part number of the device. 20?30 mic manufacturer identity code. contains the reduced joint electron device engineering council (jedec) id for freescale, 0xe 31 id idcode register id. identifies th is register as the device identification register and not the bypass register. always set to 1.
pxd10 microcontroller reference manual, rev. 1 19-6 freescale semiconductor preliminary?subject to change without notice 19.7.4 boundary scan register the boundary scan register is connected betw een tdi and tdo when the extest, sample or sample/preload instructions are active. it is used to capture input pin da ta, force fixed values on output pins, and select a logic value and direction fo r bidirectional pins. each bit of the boundary scan register represents a sepa rate boundary scan register cell, as described in the ieee 1149.1-2001 standard and discussed in section 19.8.5, boundary scan .? the size of the boundary scan register is 464 bits. 19.8 functional description 19.8.1 jtagc reset configuration while in reset, the tap controller is forced into the test-logic-reset state, thus disabling the test logic and allowing normal operation of the on-chip system logic. in addition, the inst ruction register is loaded with the idcode instruction. 19.8.2 ieee 1149.1-2001 (j tag) test access port the jtagc uses the ieee 1149.1-2001 tap for accessing re gisters. this port can be shared with other tap controllers on the mcu. for more detail on tap sharing via jtagc in structions refer to section 19.8.4.2, access_aux_tap_x instructions .? data is shifted between tdi and tdo though the selected register starting wi th the least significant bit, as illustrated in figure 19-4 . this applies for the instruction regist er, test data registers, and the bypass register. figure 19-4. shifting data through a register 19.8.3 tap controller state machine the tap controller is a synchronous state machine that interprets the sequence of logical values on the tms pin. figure 19-5 shows the machine?s states. the value show n next to each state is the value of the tms signal sampled on the rising edge of the tck signal. as figure 19-5 shows, holding tms at logic 1 while cloc king tck through a suffic ient number of rising edges also causes the state machine to enter the test-logic-reset state. selected register msb lsb tdi tdo
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 19-7 preliminary?subject to change without notice figure 19-5. ieee 1149.1-2001 tap c ontroller finite state machine test logic reset run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 1 1 00 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 note: the value shown adjacent to each state transition in this figure represents the value of tms at the time of a rising edge of tck.
pxd10 microcontroller reference manual, rev. 1 19-8 freescale semiconductor preliminary?subject to change without notice 19.8.3.1 selecting an ie ee 1149.1-2001 register access to the jtagc data registers is done by loading the instruction register with any of the jtagc instructions while the jtagc is enab led. instructions are shifted in via the select-ir-scan path and loaded in the update-ir state. at this poi nt, all data register access is perf ormed via the select-dr-scan path. the select-dr-scan path is used to read or write the register data by shifting in the data (lsb first) during the shift-dr state. when reading a register, the register value is loaded into the ieee 1149.1-2001 shifter during the capture-dr state. when writing a register, the value is loaded from the ieee 1149.1-2001 shifter to the register during the update-dr state. wh en reading a register, there is no requirement to shift out the entire register c ontents. shifting can be terminated afte r fetching the required number of bits. 19.8.4 jtagc instructions this section gives an overview of each instructi on, refer to the ieee 1149.1-2001 standard for more details. the jtagc implements the ieee 1149.1-2001 defined instructions listed in table 19-3 . table 19-4 shows the implementation for sili con cut1. by mistake, the access to nexus port controller is not using the standard powerpc instruction. for silicon cut2, the instruction coding will be ch anged to be 100% compatible with existing powerpc. table 19-3. jtag instructions instruction code[4:0] instruction summary idcode 00001 selects device iden tification register for shift sample/preload 00010 selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation sample 00011 selects boundary scan register for shifting and sampling without disturbing functional operation extest 00100 selects boundary scan register while applying preloaded values to output pins and asserting functional reset access_aux_tap_tcu 11011 grants the tcu ownership of the tap access_aux_tap_once 10001 grants the platfrom ownership of the tap access_aux_tap_npc 10000 grants the nexus port controller (npc) ownership of the tap bypass 11111 selects bypass register for data operations factory debug reserved 1 1 intended for factory debug, and not customer use 00101 00110 01010 intended for factory debug only reserved 2 2 freescale reserves the right to change the decoding of reserved instruction codes all other codes decoded to select bypass register
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 19-9 preliminary?subject to change without notice 19.8.4.1 bypass instruction bypass selects the bypass register, creating a single-bit shift regist er path between tdi and tdo. bypass enhances test efficiency by reducing the overall shift path when no test operation of the mcu is required. this allows more rapid move ment of test data to and from other components on a board that are required to perform test functions. while the bypass instruction is active the system logic operates normally. 19.8.4.2 access_aux_tap_ x instructions the access_aux_tap_ x instructions allow the ne xus modules on the mcu to ta ke control of the tap. when this instruction is loaded, control of the tap pins is transferred to the selected auxiliary tap controller. any data input via tdi and tms is passed to the selected tap contro ller, and any tdo output from the selected tap controller is sent back to the jtagc to be output on the pins. the jtagc regains control of the jtag port during the update-dr state if the pause-dr state was entered. auxiliary tap controllers are held in run-test/idle while they are inactive. 19.8.4.3 extest ? extern al test instruction extest selects the boundary scan regi ster as the shift path between td i and tdo. it allows testing of off-chip circuitry and board-level interconnections by driving preloa ded data contained in the boundary scan register onto the syst em output pins. typically, th e preloaded data is loaded into the boundary scan register using the sample/preload instruction before the selecti on of extest. extest asserts the table 19-4. jtag instructions for silicon cut1 instruction code[4:0] instruction summary idcode 00001 selects device identi fication register for shift sample/preload 00010 selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation sample 00011 selects boundary scan register fo r shifting and sampling without disturbing functional operation extest 00100 selects boundary scan register wh ile applying preloaded values to output pins and asserting functional reset access_aux_tap_tcu 10000 grants the tcu ownership of the tap access_aux_tap_once 10001 grants the platform ownership of the tap access_aux_tap_npc 10010 grants the nexus por t controller (npc) ownership of the tap bypass 11111 selects bypass register for data operations factory debug reserved 1 1 intended for factory debug, and not customer use 00101 00110 01010 intended for factory debug only reserved 2 2 freescale reserves the right to change the decoding of reserved instruction codes all other codes decoded to select bypass register
pxd10 microcontroller reference manual, rev. 1 19-10 freescale semiconductor preliminary?subject to change without notice internal system reset for the mcu to force a predictable internal st ate while performing external boundary scan operations. 19.8.4.4 idcode instruction idcode selects the 32-bit device identification regist er as the shift path between tdi and tdo. this instruction allows interrogation of the mcu to determ ine its version number and other part identification data. idcode is the instruction placed into th e instruction register when the jtagc is reset. 19.8.4.5 sample instruction the sample instruction obtains a samp le of the system data and contro l signals present at the mcu input pins and just before the boundary scan register cells at the output pins . this sampling occurs on the rising edge of tck in the capture-dr state when the sample instruction is active. the sampled data is viewed by shifting it through th e boundary scan register to the tdo output during the shift-dr state. there is no defined action in the update -dr state. both the data capture and the shift operation are transparent to system operation. 19.8.4.6 sample/preload instruction the sample/preload instru ction has two functions: ? the sample part of the instruction samples the system data and control signals on the mcu input pins and just before the boundary scan register ce lls at the output pins. this sampling occurs on the rising-edge of tck in the capture-dr state wh en the sample/preload in struction is active. the sampled data is viewed by shifting it thr ough the boundary scan register to the tdo output during the shift-dr state. both th e data capture and the shift operation are transparent to system operation. ? the preload part of the instruction initializes the boundary scan register cells before selecting the extest instructions to perform boundary scan tests. this is achieved by shifting in initialization data to the boundary sc an register during the shift-dr st ate. the initialization data is transferred to the parallel outputs of the boundary s can register cells on the falling edge of tck in the update-dr state. the data is applied to the external output pins by the extest instruction. system operation is not affected. 19.8.5 boundary scan the boundary scan technique allows signals at component boundaries to be controlled and observed through the shift-register stage asso ciated with each pad. each stage is part of a larger boundary scan register cell, and cells for each pad are interconnected serially to form a shift-register chain around the border of the design. the boundary scan register consists of this shift -register chain, and is connected between tdi and tdo when the extest, sample, or sample/preload instructions are loaded. the shift-register chain contains a serial input and serial output, as well as clock and control signals.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 19-11 preliminary?subject to change without notice 19.9 e200z0 once controller the e200z0 core once controller s upports a complete set of nexus 1 de bug features, as we ll as providing access to the nexus2+ configuration registers. a complete discussion of the e200z0 once debug features is available in the e200z0 reference manual . 19.9.1 e200z0 once controller block diagram figure 19-6 is a block diagram of the e200z0 once block. figure 19-6. e200z0 once block diagram 19.9.2 e200z0 once controlle r functional description the functional description for the e200z0 once controller is the same as for the jtagc, with the differences described below. 19.9.2.1 enabling the tap controller to access the e200z0 once controller, the proper jt agc instruction needs to be loaded in the jtagc instruction register, as discussed in section 19.5.2.2, tap sharing mode . tck e200z0_tms tdi test access port (tap) e200z0_tdo bypass register external data register . . controller tap instruction register . once mapped debug registers auxiliary data register . . . e200z0_trst (once ocmd) tdo mux control { from jtagc (to jtagc)
pxd10 microcontroller reference manual, rev. 1 19-12 freescale semiconductor preliminary?subject to change without notice 19.9.3 e200z0 once controller register description most e200z0 once debug register s are fully documented in the e200z0 reference manual . 19.9.3.1 once command register (ocmd) the once command register (ocmd) is a 10-bit shift re gister that receives its serial data from the tdi pin and serves as the instruction re gister (ir). it holds th e 10-bit commands to be used as input for the e200z0 once decoder. th e ocmd is shown in table 19-5 . the ocmd is updated when the tap controller enters the update -ir state. it contains fields for cont rolling access to a resource, as well as controlling single-step operati on and exit from once mode. although the ocmd is updated during the update-ir tap controller stat e, the correspondi ng resource is accessed in the dr scan sequence of the tap cont roller, and as such, the update-dr state must be transitioned through in order for an access to occu r. in addition, the update-dr state must also be transitioned through in order for the single-step and/or exit functionali ty to be performed, even though the command appears to have no data resour ce requirement associated with it. 012 3 456789 r r/w go ex rs[0:6] w reset:000 0 011011 table 19-5. once command register (ocmd) table 19-6. e200z0 once register addressing rs[0:6] register selected 000 0000 ? 000 0001 reserved 000 0010 jtag id (read-only) 000 0011 ? 000 1111 reserved 001 0000 cpu scan register (cpuscr) 001 0001 no register selected (bypass) 001 0010 once control register (ocr) 001 0011 ? 001 1111 reserved 010 0000 instruction address compare 1 (iac1) 010 0001 instruction address compare 2 (iac2) 010 0010 instruction address compare 3 (iac3) 010 0011 instruction address compare 4 (iac4) 010 0100 data address compare 1 (dac1) 010 0101 data address compare 2 (dac2) 010 0110 data value compare 1 (dvc1)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 19-13 preliminary?subject to change without notice 19.10 initialization/application information the test logic is a static logic de sign, and tck can be stopped in either a high or low state without loss of data. however, the system clock is not synchroni zed to tck internally. a ny mixed operation using both the test logic and the system functional logic requires extern al synchronization. to initialize the jtagc module and enable access to registers, the follow ing sequence is required: 1. place the jtagc in reset through tap controller state machine transitions controlled by tms 2. load the appropriate instruction for the test or action to be performed. 010 0111 data value compare 2 (dvc2) 010 1000 ? 010 1111 reserved 011 0000 debug status register (dbsr) 011 0001 debug control register 0 (dbcr0) 011 0010 debug control register 1 (dbcr1) 011 0011 debug control register 2 (dbcr2) 011 0100 ? 101 1111 reserved (do not access) 110 1111 reserved (do not access) 111 0000 ? 111 1001 general purpose register selects [0:9] 111 1010 ? 111 1011 reserved 111 1100 nexus2+ access 111 1101 lsrl select (factory test use only) 111 1110 enable_once 111 1111 bypass table 19-6. e200z0 once register addressing (continued) rs[0:6] register selected
pxd10 microcontroller reference manual, rev. 1 19-14 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 20-1 preliminary?subject to change without notice chapter 20 inter-integrated circuit bus controller module (i 2 c) 20.1 introduction 20.1.1 overview the inter-integrated circuit (i 2 c or iic) bus is a two wire bidirecti onal serial bus that provides a simple and efficient method of data excha nge between devices. it minimizes the number of external connections to devices and does not require an external address decoder. this bus is suitable for applicat ions requiring occasional communications over a short distance between a number of devices. it also provides flexibility, allowing additional device s to be connected to the bus for further expansion and system development. the interface is designed to operate up to 100 kbps with maximum bus lo ading and timing. the device is capable of operating at higher baud rates, up to a ma ximum of module clock/20, with reduced bus loading. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pf. 20.1.2 features the i 2 c module has the following key features: ? compatible with i 2 c bus standard ? multi-master operation ? software programmable for one of 256 different serial clock frequencies ? software selectable acknowledge bit ? interrupt driven byte-by-byte data transfer ? arbitration lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus busy detection features currently not supported: ? no support for general call address ? not compliant to ten-bit addressing 20.1.3 block diagram the block diagram of the i 2 c module is shown in figure 20-1 .
pxd10 microcontroller reference manual, rev. 1 20-2 freescale semiconductor preliminary?subject to change without notice figure 20-1. i 2 c block diagram 20.2 modes of operation the i 2 c module has the following modes of operation: ? run mode: this is the basic mode of operation. ? stop mode: this is the lowest power saving mode and allows the system to turn of all the clocks to the i 2 c module. this state can only be entered wh en there are no active transfers on the bus. 20.3 external signal description 20.3.1 overview the inter-integrated circuit (i 2 c) module has 2 external pins. 20.3.2 detailed signal descriptions 20.3.2.1 scl this is the bidirectional seri al clock line (scl) of the m odule, compatible with the i 2 c-bus specification. 20.3.2.2 sda this is the bidirectional seri al data line (sda) of the m odule, compatible with the i 2 c-bus specification. in/out data shift register address compare sda interrupt clock control start stop arbitration control scl bus_clock i 2 c registers
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 20-3 preliminary?subject to change without notice 20.4 memory map and register description 20.4.1 overview this section provides a detailed descripti on of all memory-mapped registers in the i 2 c module. 20.4.2 module memory map the memory map for the i 2 c module is given below in table 20-1 . the total address for each register is the sum of the base address for the i 2 c module and the address offset for each register. all registers are accessible via 8-bit, 16-bit or 32-bit accesses. ho wever, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be ali gned to 32-bit boundaries. as an example, the ibdf register for the frequency devide r is accessible by a 16-bit read/w rite to address base + 0x000, but performing a 16-bit access to base + 0x001 is illegal. 20.4.3 register description this section consists of re gister descriptions in addr ess order. each description includes a standard register diagram with an associated figure number. details of register bit and field function follow the register diagrams, in bit order. table 20-1. module memory map address register size (bits) access mode 1 1 u = user mode, s = supervisor mode, a = all (no restrictions) location base + 0x00 i 2 c bus address register (ibad) 8 r/w a on page 4 base + 0x01 i 2 c bus frequency divider register (ibfd) 8 r/w a on page 4 base + 0x02 i 2 c bus control register (ibcr) 8 r/w a on page 10 base + 0x03 i 2 c bus status register (ibsr) 8 r/w a on page 11 base + 0x04 i 2 c bus data i/o register (ibdr) 8 r/w a on page 12 base + 0x05 i 2 c bus interrupt configuration register (ibic) 8 r/w a on page 13 base + 0x06 unused 8 r a ? base + 0x07 unused 8 r a ? base + 0x08 ? base + 0x3fff reserved see note 2 2 if enabled at the soc level, reads or writes to these regi sters will cause bus aborts. refer to the system services module documentation for more details. ? always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 20-2. key to register fields
pxd10 microcontroller reference manual, rev. 1 20-4 freescale semiconductor preliminary?subject to change without notice 20.4.3.1 i 2 c bus address register this register contai ns the address the i 2 c bus will respond to when addressed as a slave; note that it is not the address sent on the bus during the address transfer. 20.4.3.2 i 2 c bus frequency divider register offset 0x00000 access: read/write any time 01234567 r adr 0 w reset00000000 figure 20-3. i 2 c bus address register (ibad) table 20-2. ibad field descriptions field description adr slave address. specific slave address to be used by the i 2 c bus module. note: the default mode of i 2 c bus is slave mode for an address match on the bus. offset 0x0001 access: read/write any time 01234567 r ibc w reset00000000 figure 20-4. i 2 c bus frequency divider register (ibfd) table 20-3. ibfd field descriptions field description ibc i-bus clock rate. this field is used to prescale the clock for bit rate selection. the bit clock generator is implemented as a prescale divider. the ibc bits ar e decoded to give the tap and prescale values as follows: 0?1 select the prescaled shift register (see ta bl e 2 0 - 4 ) 2?4 select the prescaler divider (see ta bl e 2 0 - 5 ) 5?7 select the shift r egister tap point (see table 20-6 ) table 20-4. i-bus multiplier factor ibc[0:1] mul 00 01 01 02 10 04 11 reserved
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 20-5 preliminary?subject to change without notice the number of clocks from the falling edge of scl to the first tap (tap[1 ]) is defined by the values shown in the scl2tap column of table 20-5 . all subsequent tap points are separated by 2 ibc[2:4] as shown in the tap2tap column in table 20-5 . the scl tap is used to generate th e scl period and the sda tap is used to determine the delay from the falling edge of scl to the change of state of sda i.e. the sda hold time. table 20-5. i-bus prescaler divider values ibc[2:4] scl2start (clocks) scl2stop (clocks) scl2tap (clocks) tap2tap (clocks) 0002741 0012742 0102964 0116968 100 14171416 101 30333032 110 62656264 111 126 129 126 128 table 20-6. i-bus tap and prescale values ibc[5:7] scl tap (clocks) sda tap (clocks) 000 5 1 001 6 1 010 7 2 011 8 2 100 9 3 101 10 3 110 12 4 111 15 4
pxd10 microcontroller reference manual, rev. 1 20-6 freescale semiconductor preliminary?subject to change without notice figure 20-5. sda hold time figure 20-6. scl divider and sda hold the equation used to generate the divi der values from the ibfd bits is: scl divider = mul x {2 x (scl2tap + [(scl_tap -1) x tap2tap] + 2)} eqn. 20-1 the sda hold delay is equal to the cpu clock pe riod multiplied by the sda hold value shown in table 20-7 . the equation used to generate the sd a hold value from the ibfd bits is: sda hold = mul x {scl2tap + [(sda_tap - 1) x tap2tap] + 3} eqn. 20-2 the equation for scl hold values to generate the start and stop conditions fr om the ibfd bits is: scl hold(start) = mul x [scl2start + (scl_tap - 1) x tap2tap] eqn. 20-3 scl hold(stop) = mul x [scl2stop + (scl_tap - 1) x tap2tap] eqn. 20-4 scl divider sda hold scl sda sda scl start condition stop condition scl hold(start) scl hold(stop)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 20-7 preliminary?subject to change without notice table 20-7. i 2 c divider and hold values ibc (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) mul = 1 00 20 7 6 11 01 22 7 7 12 02 24 8 8 13 03 26 8 9 14 04 28 9 10 15 05 30 9 11 16 06 34 10 13 18 07 40 10 16 21 08 28 7 10 15 09 32 7 12 17 0a 36 9 14 19 0b 40 9 16 21 0c 44 11 18 23 0d 48 11 20 25 0e 56 13 24 29 0f 68 13 30 35 10 48 9 18 25 11 56 9 22 29 12 64 13 26 33 13 72 13 30 37 14 80 17 34 41 15 88 17 38 45 16 104 21 46 53 17 128 21 58 65 18 80 9 38 41 19 96 9 46 49 1a 112 175457 1b 128 176265 1c 144 25 70 73 1d 160 25 78 81 1e 192 339497 1f 240 33 118 121 20 160 17 78 81 21 192 17 94 97 22 224 33 110 113 23 256 33 126 129 24 288 49 142 145 25 320 49 158 161 26 384 65 190 193 27 480 65 238 241 28 320 33 158 161 29 384 33 190 193 2a 448 65 222 225 2b 512 65 254 257 2c 576 97 286 289 2d 640 97 318 321 2e 768 129 382 385 2f 960 129 478 481 30 640 65 318 321 31 768 65 382 385 32 896 129 446 449 33 1024 129 510 513 34 1152 193 574 577 35 1280 193 638 641 36 1536 257 766 769 37 1920 257 958 961 38 1280 129 638 641 39 1536 129 766 769 3a 1792 257 894 897 3b 2048 257 1022 1025 3c 2304 385 1150 1153 3d 2560 385 1278 1281 3e 3072 513 1534 1537 3f 3840 513 1918 1921
pxd10 microcontroller reference manual, rev. 1 20-8 freescale semiconductor preliminary?subject to change without notice mul = 2 40 40 14 12 22 41 44 14 14 24 42 48 16 16 26 43 52 16 18 28 44 56 18 20 30 45 60 18 22 32 46 68 20 26 36 47 80 20 32 42 48 56 14 20 30 49 64 14 24 34 4a 72 18 28 38 4b 80 18 32 42 4c 88 22 36 46 4d 96 22 40 50 4e 112 264858 4f 136 26 60 70 50 96 18 36 50 51 112 18 44 58 52 128 26 52 66 53 144 26 60 74 54 160 34 68 82 55 176 34 76 90 56 208 42 92 106 57 256 42 116 130 58 160 18 76 82 59 192 18 92 98 5a 224 34 108 114 5b 256 34 124 130 5c 288 50 140 146 5d 320 50 156 162 5e 384 66 188 194 5f 480 66 236 242 60 320 28 156 162 61 384 28 188 194 62 448 32 220 226 63 512 32 252 258 64 576 36 284 290 65 640 36 316 322 66 768 40 380 386 67 960 40 476 482 68 640 28 316 322 69 768 28 380 386 6a 896 36 444 450 6b 1024 36 508 514 6c 1152 44 572 578 6d 1280 44 636 642 6e 1536 52 764 770 6f 1920 52 956 962 70 1280 36 636 642 71 1536 36 764 770 72 1792 52 892 898 73 2048 52 1020 1026 74 2304 68 1148 1154 75 2560 68 1276 1282 76 3072 84 1532 1538 77 3840 84 1916 1922 78 2560 36 1276 1282 79 3072 36 1532 1538 7a 3584 68 1788 1794 7b 4096 68 2044 2050 7c 4608 100 2300 2306 7d 5120 100 2556 2562 7e 6144 132 3068 3074 7f 7680 132 3836 3842 table 20-7. i 2 c divider and hold values (continued) ibc (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 20-9 preliminary?subject to change without notice mul = 4 80 80 28 24 44 81 88 28 28 48 82 96 32 32 52 83 104 32 36 56 84 112 36 40 60 85 120 36 44 64 86 136 40 52 72 87 160 40 64 84 88 112 28 40 60 89 128 28 48 68 8a 144 365676 8b 160 366484 8c 176 44 72 92 8d 192 44 80 100 8e 224 52 96 116 8f 272 52 120 140 90 192 36 72 100 91 224 36 88 116 92 256 52 104 132 93 288 52 120 148 94 320 68 136 164 95 352 68 152 180 96 416 84 184 212 97 512 84 232 260 98 320 36 152 164 99 384 36 184 196 9a 448 68 216 228 9b 512 68 248 260 9c 576 100 280 292 9d 640 100 312 324 9e 768 132 376 388 9f 960 132 472 484 a0 640 68 312 324 a1 768 68 376 388 a2 896 132 440 452 a3 1024 132 504 516 a4 1152 196 568 580 a5 1280 196 632 644 a6 1536 260 760 772 a7 1920 260 952 964 a8 1280 132 632 644 a9 1536 132 760 772 aa 1792 260 888 900 ab 2048 260 1016 1028 ac 2304 388 1144 1156 ad 2560 388 1272 1284 ae 3072 516 1528 1540 af 3840 516 1912 1924 30 2560 260 1272 1284 b1 3072 260 1528 1540 b2 3584 516 1784 1796 b3 4096 516 2040 2052 b4 4608 772 2296 2308 b5 5120 772 2552 2564 b6 6144 1028 3064 3076 b7 7680 1028 3832 3844 b8 5120 516 2552 2564 b9 6144 516 3064 3076 ba 7168 1028 3576 3588 bb 8192 1028 4088 4100 bc 9216 1540 4600 4612 bd 10240 1540 5112 5124 be 12288 2052 6136 6148 bf 15360 2052 7672 7684 table 20-7. i 2 c divider and hold values (continued) ibc (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
pxd10 microcontroller reference manual, rev. 1 20-10 freescale semiconductor preliminary?subject to change without notice 20.4.3.3 i 2 c bus control register offset 0x0002 access: read/write any time 01234567 r mdis ibie ms/sl tx/rx noack 0 dmaen ibdoze wrsta reset10000000 figure 20-7. i 2 c bus control re gister (ibcr) table 20-8. ibcr field descriptions field description mdis module disable. this bit controls the software reset of the entire i 2 c bus module. 1 the module is reset and disabled. this is the power-o n reset situation. when high, the interface is held in reset, but registers can still be accessed 0the i 2 c bus module is enabled. this bit must be cleared before any other ibcr bits have any effect note: if the i 2 c bus mdule is enabled in the middle of a byte transfer, the interface behaves as follows: slave mode ignores the current transfer on the bus and starts operating whenever a subsequent start condition is detected. master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the current bus cycle may become corr upt. this would ultimately result in either the current bus master or the i 2 c bus module losing arbitration, afte r which, bus operation would return to normal. ibie i-bus interrupt enable. 1 interrupts from the i 2 c bus module are enabled. an i 2 c bus interrupt occurs pr ovided the ibif bit in the status register is also set. 0 interrupts from the i 2 c bus module are disabled. note that this does not clear any currently pending interrupt condition ms/sl master/slave mode select. upon reset, this bit is clea red. when this bit is changed from 0 to 1, a start signal is generated on the bus and the master mode is selected. when this bit is changed from 1 to 0, a stop signal is generated and the operation mode changes from master to slave. a stop signal should be generated only if the ibif flag is set. ms/sl is cleared without generating a stop signal when the master loses arbitration. 1 master mode 0slave mode tx/rx transmit/receive mode sele ct. this bit selects the direction of master and slave transfers. when addressed as a slave this bit should be set by software according to the srw bit in the status register. in master mode this bit should be set according to t he type of transfer required. therefore, for address cycles, this bit will always be high. 1 transmit 0 receive noack data acknowledge disable. this bit specifies the value driven onto sda during data acknowledge cycles for both master and slave receivers. the i 2 c module will always acknowledge address matches, provided it is enabled, regardless of the val ue of noack. note that values written to this bit are only used when the i 2 c bus is a receiver, not a transmitter. 1 no acknowledge signal response is sent (i.e., acknowledge bit = 1) 0 an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 20-11 preliminary?subject to change without notice 20.4.3.4 i 2 c bus status register rsta repeat start. writing a 1 to this bit will generate a repeated start condition on the bus, provided it is the current bus master. this bit will always be read as a lo w. attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 generate repeat start cycle 0 no effect dmaen dma enable. when this bit is set, the dma tx and rx lines will be asserted when the i 2 c module requires data to be read or written to the data register. no tr ansfer done interrupts will be generated when this bit is set, however an interrupt will be generated if t he loss of arbitration or addressed as slave conditions occur. the dma mode is only valid when the i 2 c module is configured as a master and the dma transfer still requires cpu intervention at the start and the end of each frame of data. see the dma application information section for more details. 1 enable the dma tx/rx request signals 0 disable the dma tx/rx request signals ibsdoz e i-bus interface stop in doze mode. 1halt i 2 c bus module clock generation (if doze mode signal asserted) 0i 2 c bus module clock operates normally note: if the ibsdoze mode is set, the i 2 c module will enter doze mode when the doze signal is asserted, if there are no current transactions on the bus. the i 2 c module would then signal to the system that the clock can be shut down. note: if it were the case that the ibdoze bit was cl eared when the doze signal was asserted, the i 2 c bus module clock would remain alive, and any current transactions would continue as normal. offset 0x0003 access: read-only any time 1 1 with the exception of ibif and i bal, which are software clearable. 01234567 r tcf iaas ibb ibal 0 srw ibif rxak w w1c w1c reset10000000 figure 20-8. i 2 c bus status register (ibsr) table 20-9. ibsr field descriptions field description tcf transfer complete. while one byte of data is being transf erred, this bit is cleared. it is set by the falling edge of the 9th clock of a byte transfer. note that this bit is only valid during or immediately following a transfer to the i 2 c module or from the i 2 c module. 1 transfer complete 0 transfer in progress iaas addressed as a slave. when its own specific addre ss (i-bus address register) is matched with the calling address, this bit is set. the cpu is interrupted prov ided the ibie is set. then the cpu needs to check the srw bit and set its tx/rx mode accordingly. writing to the i-bus control register clears this bit. 1 addressed as a slave 0 not addressed table 20-8. ibcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 20-12 freescale semiconductor preliminary?subject to change without notice 20.4.3.5 i 2 c bus data i/o register in master transmit mode, when data is written to ibdr , a data transfer is initia ted. the most significant bit is sent first. in master receive mode, reading this re gister initiates next byte data receiving. in slave mode, the same functions are availabl e after an address match has occurred. note that the tx/rx bit in the ibcr must correctly reflect the desired direction of transf er in master and slave m odes for the transmission to ibb bus busy. this bit indicates the status of the bus. when a start signal is detect ed, the ibb is set. if a stop signal is detected, ibb is cl eared and the bus enters idle state. 1bus is busy 0 bus is idle ibal arbitration lost. the arbitration lo st bit (ibal) is set by hardware when the arbitration procedure is lost. arbitration is lost in the following circumstances: ? sda is sampled low when the master drives a high during an address or data transmit cycle. ? sda is sampled low when the master drives a high during the acknowledge bit of a data receive cycle. ? a start cycle is attempted when the bus is busy. ? a repeated start cycle is requested in slave mode. ? a stop condition is detected when the master did not request it. this bit must be cleared by software, by writi ng a one to it. a write of zero has no effect. srw slave read/write. when iaas is se t, this bit indicates th e value of the r/w comm and bit of the calling address sent from the master. this bit is only valid when the i-bus is in slave mode, a complete address transfer has occurred with an address match and no othe r transfers have been initiated. by programming this bit, the cpu can select slave transmit/receive mode according to the command of the master. 1 slave transmit, master reading from slave 0 slave receive, master writing to slave ibif i-bus interrupt flag. the ibif bit is set when one of the following conditions occurs: ? arbitration lost (ibal bit set) ? byte transfer complete (tcf bit set) ? addressed as slave (iaas bit set) ? noack from slave (ms & tx bits set) ?i 2 c bus going idle (ibb high-low transition and enabled by biie) a processor interrupt request will be caused if the ibie bit is set. this bit must be cleared by software, by writing a one to it. a write of zero has no effect on this bit.. rxak received acknowledge. this is the value of sda during the acknowledge bit of a bus cycle. if the received acknowledge bit (rxak) is low, it indicates an ackn owledge signal has been received afte r the completion of 8 bits data transmission on the bus. if rxak is high, it means no acknowledge signal is detected at the 9th clock. 1 no acknowledge received 0 acknowledge received offset 0x0004 access: read/write any time 01234567 r data w reset00000000 figure 20-9. i 2 c bus data i/o register (ibdr) table 20-9. ibsr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 20-13 preliminary?subject to change without notice begin. for instance, if the i 2 c is configured for master transmit but a master receive is desired, then reading the ibdr will not initiate the receive. reading the ibdr will return th e last byte received while the i 2 c is configured in eith er master receive or slave receive modes. the ibdr does not refl ect every byte that is transmitted on the i 2 c bus, nor can software verify that a byte has been writte n to the ibdr correctly by reading it back. in master transmit mode, the first byte of data written to the ibdr following assertion of ms/sl is used for the address transfer and should comprise the ca lling address (in position d 7?d1) concatenated with the required r/w bit (in position d0). 20.4.3.6 i 2 c bus interrupt configuration register 20.5 functional description 20.5.1 general this section provides a complete functional de scription of the inter-integrated circuit (i 2 c). 20.5.2 i-bus protocol the i 2 c bus system uses a serial data line (sda) and a serial clock li ne (scl) for data transfer. all devices connected to it must have open drain or open collector outputs. a logical and function is exercised on both lines with external pull-up resistors. the value of th ese resistors is system dependent. normally, a standard communication is composed of four parts: start signal, slave addr ess transmission, data transfer and stop signal. they are described briefly in the following sect ions and illustrated in figure 20-11 . offset 0x0005 access: read/write any time 01234567 rbiie0000000 w reset00000000 figure 20-10. i 2 c bus interrupt configuration register (ibic) table 20-10. ibic field descriptions field description biie bus idle interrupt enable bit. this config bit can be used to enable the generation of an interrupt once the i 2 c bus becomes idle. once this bit is set, an ibb high -low transition will set the ibif bit. this feature can be used to signal to the cpu the completion of a stop on the i 2 c bus. 1 bus idle interrupts enabled 0 bus idle interrupts disabled
pxd10 microcontroller reference manual, rev. 1 20-14 freescale semiconductor preliminary?subject to change without notice figure 20-11. i 2 c bus transmission signals 20.5.2.1 start signal when the bus is free, i.e. no master device is enga ging the bus (both scl and sda lines are at logical high), a master may initiate communicati on by sending a start signal. as shown in figure 20-11 , a start signal is defined as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transf er (each data transfer may contain several bytes of da ta) and brings all slaves out of their idle states. figure 20-12. start and stop conditions scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 1 2 5 678 msb lsb repeated 34 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write stop signal no ack bit read/ write sda scl start condition stop condition
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 20-15 preliminary?subject to change without notice 20.5.2.2 slave address transmission the first byte of data transfer im mediately after the start signal is the slave address transmitted by the master. this is a seven-bit calling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. 1 = read transfer - the slave transmits data to the master 0 = write transfer - the master transmits data to the slave only the slave with a calling address that matche s the one transmitted by the master will respond by sending back an acknowledge bit. this is done by pul ling the sda low at the 9th clock (see figure 20-11 ). no two slaves in the system may have the same address. if the i 2 c bus is master, it must not transmit an address that is equal to it s own slave address. the i 2 c bus cannot be master and slave at the same time. however, if arbitration is lost during an address cycle the i 2 c bus will revert to slave mode and operate correctly, even if it is being addressed by another master. 20.5.2.3 data transfer once successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the r/w bit sent by the calling master. all transfers that come after an addres s cycle are referred to as data transf ers, even if they carry sub-address information for the slave device. each data byte is 8 bits long. data may be changed only while scl is lo w and must be held stable while scl is high as shown in figure 20-11 . there is one clock pulse on scl fo r each data bit, the msb being transferred first. each data byte must be follow ed by an acknowledge bit, wh ich is signalled from the receiving device by pulling the sda lo w at the ninth clock. therefore, one complete data byte transfer needs nine clock pulses. if the slave receiver does not acknowledge the master, the sda line must be left high by the slave. the master can then generate a stop signal to abort the da ta transfer or a start signal (repeated start) to commence a new calling. if the master receiver doe s not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the sda li ne for the master to genera te a stop or start signal. 20.5.2.4 stop signal the master can terminate the comm unication by generating a stop signa l to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal first. this is called repeated start. a stop signal is defined as a low-to-hi gh transition of sda while scl is at logical ?1? (see figure 20-11 ). the master can generate a stop even if the slave has generated an acknowledge, at which point the slave must release the bus.
pxd10 microcontroller reference manual, rev. 1 20-16 freescale semiconductor preliminary?subject to change without notice 20.5.2.5 repeated start signal as shown in figure 20-11 , a repeated start signal is a start signal generate d without first generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 20.5.2.6 arbitration procedure the inter-ic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a clock sync hronization procedur e determines the bus clock, for which the low period is equal to the longest clock low pe riod and the high is equal to the shortest one among the masters. the relative priority of the contending masters is determined by a data arbitration procedure. a bus master lo ses arbitration if it tr ansmits logic ?1? while a nother master transmits logic ?0?. the losing masters immediately switch ov er to slave receive mode and stop driving the sda output. in this case, the transitio n from master to slave mode doe s not generate a stop condition. meanwhile, a status bit is set by hard ware to indicate loss of arbitration. 20.5.2.7 clock synchronization since wire-and logic is performed on the scl line, a high-to-low tran sition on the scl line affects all the devices connected on the bus. the devices start counting their low pe riod and once a device's clock has gone low, it holds the scl line lo w until the clock high state is reache d. however, the change of low to high in this device clock may not cha nge the state of the scl line if anot her device clock is still within its low period. therefore, synchronized clock scl is he ld low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 20-13 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the de vice clocks and the state of the scl line and all the devices start counting their high peri ods. the first device to complete its high period pulls the scl line low again. figure 20-13. i 2 c bus clock synchronization scl1 scl2 scl internal counter reset wait start counting high period
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 20-17 preliminary?subject to change without notice 20.5.2.8 handshaking the clock synchronization mechanism can be used as a handshake in data transf er. slave devices may hold the scl low after completion of one byt e transfer (9 bits). in such cases , it halts the bus clock and forces the master clock into wait state un til the slave releases the scl line. 20.5.2.9 clock stretching the clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low, the slave can drive scl low for the required period and then release it. if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 20.5.3 interrupts 20.5.3.1 general the i 2 c module uses only one interrupt vector. 20.5.3.2 interrupt description there are five types of internal interrupts in the i 2 c. the interrupt service routine can determine the interrupt type by reading the status register. i 2 c interrupt can be generated on ? arbitration lost condition (ibal bit set) ? byte transfer condition (tcf bit set) ? address detect condition (iaas bit set) ? no acknowledge from slave received when expected ? bus going idle (ibb bit not set) the i 2 c interrupt is enabled by the ibie bit in the i 2 c control register. it must be cleared by writing ?1? to the ibif bit in the interrupt service routine. the bu s going idle interrupt needs to be additionaly enabled by the biie bit in the ibic register. table 20-11. interrupt summary interrupt offset vector priority source description i 2 c interrupt ???ibal, tcf, iaas, ibb bits in ibsr register when any of ibal, tcf or iaas bi ts is set an interrupt may be caused based on arbitration lost, transfer complete or address detect conditions. if enabled by biie, the deassertion of ibb can also cause an interrupt, indicating that the bus is idle.
pxd10 microcontroller reference manual, rev. 1 20-18 freescale semiconductor preliminary?subject to change without notice 20.6 initialization/application information 20.6.1 i 2 c programming examples 20.6.1.1 initialization sequence reset will put the i 2 c bus control register to its default state. before the in terface can be used to transfer serial data, an initializ ation procedure must be carried out, as follows: 1. update the frequency divider re gister (ibfd) and sel ect the required divisi on ratio to obtain scl frequency from system clock. 2. update the i 2 c bus address register (ibad) to define its slave address. 3. clear the ibdis bit of the i 2 c bus control register (ibcr) to enable the i 2 c interface system. 4. modify the bits of the i 2 c bus control register (ibcr) to select master/slave mode, transmit/receive mode and interr upt enable or not. op tionally also modify the bits of the i 2 c bus interrupt config register (ibic) to further refine the interrupt behavior. 20.6.1.2 generation of start after completion of the initialization procedure, seri al data can be transmitte d by selecting the 'master transmitter' mode. if the device is connected to a multi-master bus system, the state of the i 2 c bus busy bit (ibb) must be tested to check whether the serial bus is free. if the bus is free (ibb=0), the start condition and the fi rst byte (the slave address) can be sent. the data written to the data register comprises the slave calli ng address and the lsb, which is set to indicate the direction of transfer required from the slave. the bus free time (i.e., the time between a stop condition and the fo llowing start condition) is built into the hardware that generates the start cycle. depending on the relative fr equencies of the system clock and the scl period, it may be necessary to wait until the i 2 c is busy after writi ng the calling address to the ibdr before proceeding with the following instru ctions. this is illustrated in the following example. an example of the sequence of events which genera tes the start signal and transmits the first byte of data (slave address) is shown below: while (bit 5, ibsr ==1)// wait in loop for ibb flag to clear bit4 and bit 5, ibcr = 1// set transmit and master mode, i.e. generate start condition ibdr = calling_address// send the calling address to the data register while (bit 5, ibsr ==0)// wait in loop for ibb flag to be set 20.6.1.3 post-transfer software response transmission or reception of a byte will set the data transferring bit (tcf) to 1, which indicates one byte communication is finished. the i 2 c bus interrupt bit (ibif) is set also; an interrupt will be generated if the interrupt function is enabled during in itialization by setting the ibie bit. the ibif (i nterrupt flag) can be cleared by writing 1 (in the interrupt service routine, if interrupts are used). the tcf bit will be cleared to indi cate data transfer in progress by reading the ibdr data register in receive mode or writing the ibdr in transmit mode. the tcf bit should not be used as a data transfer
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 20-19 preliminary?subject to change without notice complete flag as the flag timing is depe ndent on a number of factors including the i 2 c bus frequency. this bit may not conclusively provide an indication of a transfer complete situation. it is recommended that transfer complete situations ar e detected using the ibif flag. software may service the i 2 c i/o in the main program by monitoring the ibif bit if the interrupt function is disabled. note that polling should monitor the ibif bit rather than the tcf bit since their operation is different when arbitration is lost. note that when an interrupt occurs at the end of the address cycle, the master will always be in transmit mode, i.e. the address is transmitte d. if master receive mode is requ ired, indicated by r/w bit in ibdr, then the tx/rx bit should be toggled at this stage. during slave mode address cycles (iaa s=1) the srw bit in the status register is read to determine the direction of the subsequent transfer and the tx/rx bit is programmed accordingl y. for slave mode data cycles (iaas=0) the srw bit is not valid. the tx/rx bit in the contro l register should be read to determine the direction of the current transfer. the following is an example soft ware sequence for 'master transmit ter' in the interrupt routine. clear bit 1, ibsr// clear the ibif flag if (bit 5, ibcr ==0) slave_mode()// run slave mode routine if (bit 4, ibcr ==0)) receive_mode()// run receive_mode routine if (bit 0, ibsr == 1)// if no ack end();// end transmission else ibdr = data_to_transmit// transmit next byte of data 20.6.1.4 generation of stop a data transfer ends with a stop signal generated by the 'master' devi ce. a master transmitter can simply generate a stop signal afte r all the data has been transmitted. th e following is an example showing how a stop condition is generated by a master transmitter. if (tx_count == 0) or// check to see if all data bytes have been transmitted (bit 0, ibsr == 1) {// or if no ack generated clear bit 5, ibcr// generate stop condition } else { ibdr = data_to_transmit// write byte of data to data register tx_count --// decrement counter }// return from interrupt if a master receiver wants to te rminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data which can be done by setting th e transmit acknowledge bit (txak) before reading the 2nd last byte of data. before readi ng the last byte of data, a stop signal must first be generated. the following is an example showing ho w a stop signal is generated by a master receiver. rx_count --// decrease the rx counter if (rx_count ==1)// 2nd last byte to be read ? bit 3, ibcr = 1// disable ack if (rx_count == 0)// last byte to be read ? bit 1, ibcr = 0// generate stop signal else
pxd10 microcontroller reference manual, rev. 1 20-20 freescale semiconductor preliminary?subject to change without notice data_received = ibdr// read rx data and store 20.6.1.5 generation of repeated start at the end of data transfer, if the master still wa nts to communicate on the bus , it can generate another start signal followed by another slave address wi thout first generating a stop signal. a program example is as shown. bit 2, ibcr = 1// generate another start ( restart) ibdr == calling_address// transmit the calling address 20.6.1.6 slave mode in the slave interrupt service routin e, the module addressed as slave bit (iaas) shoul d be tested to check if a calling of its own address has just been re ceived. if iaas is set, software should set the transmit/receive mode sel ect bit (tx/rx bit of ib cr) according to the r/w co mmand bit (srw). writing to the ibcr clears iaas automatically. note that the only time i aas is read as set is from the interrupt at the end of the address cycle wher e an address match occurred. interr upts resulting from subsequent data transfers will have iaas cleared. a data transfer may now be initiate d by writing information to ibdr for slave transmits or dummy reading from ibdr in slave receive mode. the slave will drive scl low in-between byte transfers scl is released when the ibdr is accessed in the required mode. in slave transmitter routine, the r eceived acknowledge bit (rxak) must be tested before transmitting the next byte of data. setting rxak means an 'end of data' signal from th e master receiver, after which it must be switched from transmitter mode to receiver mode by software. a dummy read then releases the scl line so that the master can generate a stop signal. 20.6.1.7 arbitration lost if several masters try to engage the bus simultan eously, only one master wins and the others lose arbitration. the devices that lost arbitration are immediately switch ed to slave receive mode by the hardware. their data output to the sda line is stopped, but scl is still generated until the end of the byte during which arbitration was lo st. an interrupt occurs at the falling e dge of the ninth cloc k of this transfer with ibal=1 and ms/sl=0. if one master attempts to start transmission, while the bus is being engaged by another master, the hardware will inhibit the transmission, switch th e ms/sl bit from 1 to 0 without generating a stop condition, generate an interrupt to cpu and set the ibal to indicate that the attempt to engage the bus is failed. when considering these cases, the slave service routine should test the ibal first and the software should clear the ibal bit if it is set.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 20-21 preliminary?subject to change without notice figure 20-14. flow-chart of typical i 2 c interrupt routine clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to ibdr switch to rx mode dummy read from ibdr generate stop signal read data from ibdr and store set txak =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear ibal iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to ibdr set rx mode dummy read from ibdr ack from receiver ? tx next byte read data from ibdr and store switch to rx mode dummy read from ibdr rti yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n ibif address transfer data transfer
pxd10 microcontroller reference manual, rev. 1 20-22 freescale semiconductor preliminary?subject to change without notice 20.6.2 dma application information the dma interface on the i 2 c is not completely autonomous and re quires intervention from the cpu to start and to terminate the frame transfer. dma mode is only valid for master tran smit and master receive modes. software must ensure that the ibcr[dmaen] bit is not set when the i 2 c module is configured in master mode. the dma controller must only transfer one byte of da ta per tx/rx request. this is because there is no fifo on the i 2 c block. the cpu should also keep the i 2 c interrupt enabled during a dma transf er to detect the arbitration lost condition and take action to recover from this situation. the ibcr[dmaen ] bit works as a disable for the transfer complete interrupt. this m eans that during normal tran sfers (no errors) there wi ll always be either an interrupt or a re quest to the dma controller, depending on the setting of the dm aen bit. all error conditions will trigger an interr upt and require cpu intervention. th e address match condition will not occur in dma mode as the i 2 c should never be configured for slave operation.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-1 preliminary?subject to change without notice chapter 21 interrupt controller (intc) 21.1 introduction the intc provides priority-based preemptive schedul ing of interrupt service requests (isrs). this scheduling scheme is suitable for statically scheduled hard real-t ime systems. the intc supports 122 interrupt requests. it is targeted to work with power arch itecture technology and au tomotive applications where the isrs nest to multiple levels, but it also can be used with other pr ocessors and applications. for high-priority interrupt requests in these target applications, the time from the assertion of the peripheral?s interrupt request to wh en the processor is performing usef ul work to service the interrupt request needs to be minimized. the intc supports this goal by pr oviding a unique vector for each interrupt request source. it also pr ovides 16 priorities so that lower prio rity isrs do not de lay the execution of higher priority isrs. because each individual application will have different priori ties for each source of interrupt request, the priority of each interrupt request is configurable. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providi ng a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. multiple processors can assert interrupt requests to each other through software configurable interrupt requests. these software configurable interrupt requests can also be used to separate the work involved in servicing an interrupt request into a high-priority portion and a low-priority portion. the high-priority portion is initiated by a peripheral interrupt request, but then the isr can assert a software configurable interrupt request to finish the servicing in a lower priority isr. therefore th ese software configurable interrupt requests can be used instead of the peripheral isr scheduling a task through the rtos. 21.2 features ? supports 114 peripheral and 8 software-c onfigurable interrupt request sources ? unique 9-bit vector per interrupt source ? each interrupt source can be pr ogrammed to one of 16 priorities ? preemption ? preemptive prioritized inte rrupt requests to processor ? isr at a higher priority preempts isrs or tasks at lower priorities ? automatic pushing or popping of pree mpted priority to or from a lifo ? ability to modify the isr or task priority; modi fying the priority can be used to implement the priority ceiling protocol fo r accessing shared resources. ? low latency - three clocks from re ceipt of interrupt reque st from peripheral to interrupt request to processor
pxd10 microcontroller reference manual, rev. 1 21-2 freescale semiconductor preliminary?subject to change without notice table 21-1. interrupt sources available interrupt sources number available software 8 ecsm 3 edma 17 swt 1 stm 4 real time counter (rtc/api) 2 system integration unit lite (siul) 2 wakeup unit (wkup) 3 mc_me 4 mc_rgm 1 fxosc 1 pit 4 analog to digital converter 0 (adc0) 3 flexcan 0 (can0) 9 flexcan 1 (can1) 9 dspi 0 5 dspi 1 5 linflex 0 3 linflex 1 3 inter-ic bus interface controller 0 (i2c0) 1 inter-ic bus interface controller 1 (i2c1) 1 inter-ic bus interface controller 2 (i2c2) 1 inter-ic bus interface controller 3 (i2c3) 1 enhanced modular i/o subsystem 0 (emios0) 8 enhanced modular i/o subsystem 1 (emios1) 4 sound generation logic (sgl) 1 display control unit (dcu) 4 stepper motor driver (smd0) 1 stepper stall detect 0 (ssd0) 1 stepper stall detect 1 (ssd1) 1 stepper stall detect 2 (ssd2) 1 stepper stall detect3 (ssd3) 1 stepper stall detect 4 (ssd4) 1
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-3 preliminary?subject to change without notice 21.3 block diagram figure 21-1 is a block diagram of the interrupt controller (intc). 1 the total number of interrupt sources is 122, which includes 16 reserved sources and 8 software sources. figure 21-1. intc block diagram 21.4 modes of operation 21.4.1 normal mode in normal mode, the intc has two handshaking modes with the processor: software vector mode and hardware vector mode. stepper stall detect 5 (ssd5) 1 liquid crystal display 0 (lcd0) 1 quadspi 6 table 21-1. interrupt sources available (continued) interrupt sources number available hardware vector enable software set/clear interrupt registers flag bits priority select registers peripheral interrupt requests module configuration register highest priority 4 priority comparator slave interface for reads & writes 1 push/update/acknowledge 1 1 1 update interrupt vector 1 interrupt request to processor memory mapped registers non-memory mapped logic end of interrupt register request selector priority arbitrator highest priority interrupt requests n 1 n 1 vector encoder interrupt vector 9 processor 0 interrupt acknowledge register interrupt vector 9 n 1 8 n 1 x 4-bits new priority 4 current priority 4 processor 0 current priority register processor 0 priority lifo pop 1 lowest vector interrupt request 1 vector table entry size pushed priority 4 popped priority 4 interrupt acknowledge peripheral bus
pxd10 microcontroller reference manual, rev. 1 21-4 freescale semiconductor preliminary?subject to change without notice 21.4.1.1 software vector mode in software vector mode, the interrupt exception handl er software must read a register in the intc to obtain the vector associated with the interrupt request to the processor. the intc will use software vector mode for a given processor when it s associated hven bit in intc_mcr is negated. the hardware vector enable signal to processor 0 or processor 1 is driven as negated when its associ ated hven bit is negated. the vector is read from inc_iackr. reading the intc_iackr negates the in terrupt request to the associated processor. even if a higher priority inte rrupt request arrived while waiting for this interrupt acknowledge, the interrupt reque st to the processor will negate for at least one clock. the reading also pushes the pri value in intc_cpr onto the associ ated lifo and updates pri in the associated intc_cpr with the new priority. furthermore, the interrupt vector to the processor is driven as all 0s. the interrupt acknowledge signal from the associated processor is ignored. 21.4.1.2 hardware vector mode in hardware vector mode, the hardware signals the in terrupt vector from the in tc in conjunction with a processor that can use that vector. this hardware causes the first instruction to be executed in handling the interrupt request to the processor to be specific to that vector. therefore, the interrupt exception handler is specific to a peripheral or software configurable interrupt request rather than being common to all of them. the intc uses hardware vector mode for a given processor when the associated hven bit in the intc_mcr is asserted. the hardware vector enable signal to the asso ciated processor is driven as asserted. when the interrupt request to the associated processor asserts, the in terrupt vector signal is updated. the value of that interrupt ve ctor is the unique vector associ ated with the preempting peripheral or software configurable interrupt request. the vector value matches the value of the intvec field in the intc_iackr field in the intc_i ackr, depending on which processo r was assigned to handle a given interrupt source. the processor negates the interrupt request to the pr ocessor driven by the intc by asserting the interrupt acknowledge signal for one cl ock. even if a higher priority interrupt request arrived while waiting for the interrupt acknowledge, the interrupt request to the processor will negate for at least one clock. the assertion of the interrupt acknowledge signal for a given processor pushes the associated pri value in the associated intc_cpr register onto the associ ated lifo and updates the associated pri in the associated intc_cpr register with the new priority . this pushing of the pri value onto the associated lifo and updating pri in the asso ciated intc_cpr does not occur when the associated interrupt acknowledge signal asserts and intc_sscir0_3?intc_sscir4_7 is writt en at a time such that the pri value in the associated intc_cpr register would need to be pushed and the previously last pushed pri value would need to be popped simu ltaneously. in this ca se, pri in the associated intc_cpr is updated with the new priority, and the associ ated lifo is neither pushed or popped. 21.4.1.3 debug mode the intc operation in debug mode is iden tical to its operation in normal mode.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-5 preliminary?subject to change without notice 21.4.1.4 stop mode the intc supports stop mode. the intc can have its cl ock input disabled at any time by the clock driver on the device. while its clocks are disabl ed, the intc registers are not accessible. the intc requires clocking in order for a peripheral inte rrupt request to generate an interrupt request to the processor. since the intc is not clocked in stop mode, peripheral interrupt re quests can not be used as a wakeup source, unless the clock, reset, and power m odule (crp) supports that interrupt request as a wakeup source. 21.5 memory map and register description 21.5.1 module memory map table 21-2 shows the intc memory map. 21.5.2 register description with exception of the intc_ssci n and intc_psr n , all registers are 32 bits in width. any combination of accessing the four bytes of a register with a si ngle access is supported, provi ded that the access does not table 21-2. intc memory map offset from intc_base_ addr 1 1 intc_base_addr = 0xfff4_8000 register access reset value location 0x0000 intc_mcr?intc module conf iguration register r/w 0x0000_0000 on page 6 0x0004 reserved ? ? ? 0x0008 intc_cpr?intc current priority register r/w 0x0000_000f on page 6 0x00c reserved 0x0010 intc_iackr?intc interrupt acknowledge register r 2 /w 2 when the hven bit in the intc module configuration regi ster (intc_mcr) is asserted, a read of the intc_iackr has no side effects. 0x0000_0000 on page 8 0x0014 reserved 0x0018 intc_eoir?intc end of interrupt register w 0x0000_0000 on page 9 0x001c reserved 0x0020? 0x0027 intc_sscir[0:7]?intc software set/clear interrupt register [0:7] r/w 0x0000_0000 on page 9 0x0028? 0x003c reserved ? ? ? 0x0040? 0x010c intc_psrn -intc priority select register [0:206] 3 3 the pri fields are ?reserved? for peripheral interrupt requests whose vectors are labeled as reserved in figure 21-3 r/w 0x0000_0000 on page 11
pxd10 microcontroller reference manual, rev. 1 21-6 freescale semiconductor preliminary?subject to change without notice cross a register boundary. these suppor ted accesses include type s and sizes of eight bits, aligned 16 bits, misaligned 16 bits to the middle two bytes, and aligned 32 bits. although intc_ssci n and intc_psr n are 8 bits wide, they can be accessed with a single 16-bit or 32-bit access, provided th at the access does not cross a 32-bit boundary. in software vector mode, the side ef fects of a read of intc _iackr arethe same rega rdless of the size of the read. in either software or hardware vector mode, the size of a write to either intc_sscir0_3?intc_sscir4_7 or intc_eoir doe s not affect the ope ration of the write. 21.5.2.1 intc module configur ation register (intc_mcr) the module configuration register is us ed to configure options of the intc. 21.5.2.2 intc current priority re gister for processor (intc_cpr) offset: 0x0000 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11121314 15 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset 00 00000 0 00 0 0000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0000 0 0 0 vtes 0 0 0 0 hven w reset 00 00000 0 00 0 0000 0 figure 21-2. intc module configuration register (intc_mcr) table 21-3. intc_mcr field descriptions field description 26 vtes vector table entry size. controls the number of ?0?s to the right of intvec in section 21.5.2.3, intc interrupt acknowledge register (intc_iackr)? ). if the contents of intc_iackr are used as an address of an entry in a vectortable as in softwar e vector mode, then the nu mber of rightmost ?0?s will determine the size of each vector table entry. vtes impacts software vector mode operation but also affects intc_iackr[intvec] position in both hardware vector mode and software vector mode. 0 4 bytes. 1 8 bytes. 31 hven hardware vector enable. controls whether the intc is in hardware vector mode or software vector mode. refer to section 21.4, modes of operation, for the details of the handshaking with the processor in each mode. 0 software vector mode. 1 hardware vector mode.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-7 preliminary?subject to change without notice the intc_cpr masks any peripheral or software settable interrupt re quest set at the same or lower priority as the current value of the intc_cpr[pri] field from genera ting an interrupt request to the processor. when the intc interrupt acknowledge regi ster (intc_iackr) is r ead in software vector mode or the interrupt acknowledge signal from the pr ocessor is asserted in ha rdware vector mode, the value of pri is pushed onto the li fo, and pri is updated with the pr iority of the preempting interrupt request. when the intc end-of-inter rupt register (intc_eoir) is wr itten, the lifo is popped into the intc_cpr?s pri field. the masking priority can be raised or lowered by wr iting to the pri field, supporting the pcp. refer to section 21.7.5, priority ceiling protocol.? note a store to modify the pri fi eld that closely precedes or follows an access to a shared resource can result in a non- coherent access to the resource. refer to section 21.7.5.2, ensuring coherency ? for example code to ensure coherency. offset: 0x0008 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000000000 00000000 00 pri w reset 00000000000000000000000000001111 figure 21-3. intc current priority register (intc_cpr) table 21-4. intc_cpr field descriptions field description 28?31 pri[0:3] priority. pri is the priority of the currently exec uting isr according to the field values defined in ta bl e 2 1 - 5 . table 21-5. pri values pri meaning 1111 priority 15?highest priority 1110 priority 14 1101 priority 13 1100 priority 12 1011 priority 11 1010 priority 10 1001 priority 9 1000 priority 8 0111 priority 7
pxd10 microcontroller reference manual, rev. 1 21-8 freescale semiconductor preliminary?subject to change without notice 21.5.2.3 intc interrupt acknowledge register (intc_iackr) 0110 priority 6 0101 priority 5 0100 priority 4 0011 priority 3 0010 priority 2 0001 priority 1 0000 priority 0?lowest priority offset: 0x0010 access: user read/write 0123456789101112131415 r vtba (most significant 16 bits) w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vtba (least significant five bits) intvec 1 0 0 w reset 0000000000000000 1 when the vtes bit in intc_mcr is asserted, intvec is sh ifted to the left one bit. bit 29 is read as a 0. vtba is narrowed to 20 bits in width. figure 21-4. intc interrupt acknowledge register (intc_iackr) table 21-6. intc_iackr field descriptions field description 0?20 or 0?19 vtba vector table base address. can be the base addre ss of a vector table of addresses of isrs. the vtba only uses the leftmost 20 bits when the vtes bit in intc_mcr is asserted. 21?29 or 20?28 intvec interrupt vector.it is the vector of the peripheral or software configurable interrupt request that caused the interrupt request to the processor. wh en the interrupt request to the processor asserts, the intvec is updated, whether the intc is in software or hardware vector mode. note: if intc_mcr[vtes] = 1, then the intvec field is shifted left one position to bits 20?28. vtba is then shortened by one bit to bits 0?19. table 21-5. pri values (continued) pri meaning
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-9 preliminary?subject to change without notice the interrupt acknowledge register provides a va lue that can be used to load the address of an isr from a vector table. the vector table ca n be composed of addresses of th e isrs specific to their respective interrupt vectors. in software vector mode, the intc _iackr has side effects from re ads. therefore, it must not be speculatively read while in this m ode. the side effects are the same regardless of the size of the read. reading the intc_iackr does not have si de effects in hardware vector mode. 21.5.2.4 intc end-of-interrupt register (intc_eoir) writing to the end-of-interrupt regi ster signals the end of the servici ng of the interrupt request. when the intc_eoir is written, the priority last pushed on th e lifo is popped into intc _cpr. an exception to this behavior is described in section 21.4.1.2, hardware vector mode .? the values and size of data written to the intc_eoir are ignored. the values and sizes written to this regi ster neither update the intc_eoir contents or affect whet her the lifo pops. for possible future compatib ility, write four bytes of all 0s to the intc_eoir. reading the intc_eoir has no effect on the lifo. 21.5.2.5 intc software set/clear interrupt registers (intc_sscir0_3?i ntc_sscir4_7) offset 0x0018 access: write only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000000000 00000000 000000 w reset 00000000000000000000000000000000 figure 21-5. intc end-of-interrupt register (intc_eoir) offset: 0x0020 access: user read/write 0123456789101112131415 r 0 0 0 0 0 0 0 clr0 0 0 0 0 0 0 0 clr1 w set0 set1 reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 clr2 0 0 0 0 0 0 0 clr3 w set2 set3 reset 0000000000000000 figure 21-6. intc software set/clear interrupt register 0?3 (intc_sscir[0:3])
pxd10 microcontroller reference manual, rev. 1 21-10 freescale semiconductor preliminary?subject to change without notice the software set/clear interrupt regi sters support the setting or clearing of software configurable interrupt request. these registers cont ain eight independent sets of bits to set and clea r a corresponding flag bit by software. excepting being set by software, this flag bit behaves the same as a flag bit set within a peripheral. this flag bit ge nerates an interrupt request within the intc like a periphera l interrupt request. writing a 1 to set x will leave set x unchanged at 0 but sets clr x . writing a 0 to set x has no effect. clr x is the flag bit. writing a 1 to clr x clears it. writing a 0 to clr x has no effect. if a 1 is written simultaneously to a pair of set x and clr x bits, clr x will be asserted, rega rdless of whether clr x was asserted before the write. offset: 0x0024 access: user read/write 0123456789101112131415 r 0 0 0 0 0 0 0 clr4 0 0 0 0 0 0 0 clr5 w set4 set5 reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 clr6 0 0 0 0 0 0 0 clr7 w set6 set7 reset 0000000000000000 figure 21-7. intc software set/clear interrupt register 4?7 (intc_sscir[4:7]) table 21-7. intc_sscir[0:7] field descriptions field description 6, 14, 22, 30 set[0:7] set flag bits. writing a 1 sets the corresponding clr x bit. writing a 0 has no effect. each set x always will be read as a 0. 7, 15, 23, 31 clr[0:7] clear flag bits. clr x is the flag bit. writing a 1 to clr x clears it provided that a 1 is not written simultaneously to its corresponding set x bit. writing a 0 to clr x has no effect. 0 interrupt request not pending within intc. 1 interrupt request pending within intc.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-11 preliminary?subject to change without notice 21.5.2.6 intc priority select regi sters (intc_psr0 _3?intc_psr204_207) offset: 0x0040 access: user read/write 0123456789101112131415 r 0000 pri0 0000 pri1 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 pri2 0000 pri3 w reset 0000000000000000 figure 21-8. intc priority select register 0?3 (intc_psr[0:3]) offset: 0x00d0 access: user read/write 0123456789101112131415 r 0000 pri204 0000 pri205 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 pri206 00000000 w reset 0000000000000000 figure 21-9. intc priority select register 204-206 (intc_psr[204:206]) table 21-8. intc_psr0_3?intc_psr204-206 field descriptions field description 4?7, 12?15, 20?23, 28?31 pri[0:3]? pri204:206 priority select. pri x selects the priority for interrupt requests. refer to section 21.6, functional description .? table 21-9. intc priority select register address offsets intc_psr x _ x offset address intc_psr x _ x offset address intc_psr0_3 0x0040 intc_psr104_107 0x00a8 intc_psr4_7 0x0044 intc_psr108_111 0x00ac intc_psr8_11 0x0048 intc_psr112_115 0x00b0
pxd10 microcontroller reference manual, rev. 1 21-12 freescale semiconductor preliminary?subject to change without notice 21.6 functional description the functional description involves the areas of interrupt request s ources, priority management, and handshaking with the processor. intc_psr12_15 0x004c intc_psr116_119 0x00b4 intc_psr16_19 0x0050 intc_psr120_123 0x00b8 intc_psr20_23 0x0054 intc_psr124_127 0x00bc intc_psr24_27 0x0058 intc_psr128_131 0x00c0 intc_psr28_31 0x005c intc_psr132_135 0x00c4 intc_psr32_35 0x0060 intc_psr136_139 0x00c8 intc_psr36_39 0x0064 intc_psr140_143 0x00cc intc_psr40_43 0x0068 intc_psr144_147 0x00d0 intc_psr44_47 0x006c intc_psr148_151 0x00d4 intc_psr48_51 0x0070 intc_psr152_155 0x00d8 intc_psr52_55 0x0074 intc_psr156_159 0x00dc intc_psr56_59 0x0078 intc_psr160_163 0x00e0 intc_psr60_63 0x007c intc_psr164_167 0x00e4 intc_psr64_67 0x0080 intc_psr168_171 0x00e8 intc_psr68_71 0x0084 intc_psr172_175 0x00ec intc_psr72_75 0x0088 intc_psr176_179 0x00f0 intc_psr76_79 0x008c intc_psr180_183 0x00f4 intc_psr80_83 0x0090 intc_psr184_187 0x00f8 intc_psr84_87 0x0094 intc_psr188_191 0x00fc intc_psr88_91 0x0098 intc_psr192_195 0x0100 intc_psr92_95 0x009c intc_psr196_199 0x0104 intc_psr96_99 0x00a0 intc_psr200_203 0x0108 intc_psr100_103 0x00a4 intc_psr204_207 0x010c table 21-9. intc priority select register address offsets (continued) intc_psr x _ x offset address intc_psr x _ x offset address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-13 preliminary?subject to change without notice note the intc has no spurious vector s upport. therefore, if an asserted peripheral or software settabl e interrupt request, whose pri n value in intc_psr0_3?intc_psr204_206 is higher than the pri value in intc_cpr, negates before the interrupt request to the processor for that peripheral or software settable inte rrupt request is acknowledged, the interrupt request to the proc essor still can assert or will remain asserted for that peripheral or softwa re settable interrupt request. in this case, the interrupt vector will correspond to th at peripheral or software settable interrupt request. also, the pri valu e in the intc_cpr will be updated with the corresponding pri n value in intc_psr n . furthermore, clearing the peripheral interrupt request?s enable bit in the peripheral or, alternatively, setting its mask bit has the same consequences as clearing its flag bit. setting its enable bit or clea ring its mask bit while its flag bit is asserted has the same effect on the in tc as an interrupt event setting the flag bit. table 21-10. interrupt vector table irq # offset size [byte] this device resource module section a (core section) - 0x0000 16 x critical input (intc software vector mode) core - 0x0010 16 x machine check / nmi core - 0x0020 16 x data storage core - 0x0030 16 x instruction storage core - 0x0040 16 x external input (intc software vector mode) core - 0x0050 16 x alignment core - 0x0060 16 x program core - 0x0070 16 x reserved core - 0x0080 16 x system call core - 0x0090 96 x unused core -0x00f016xdebug core - 0x0100 1792 x unused core section b (on-platform peripherals)
pxd10 microcontroller reference manual, rev. 1 21-14 freescale semiconductor preliminary?subject to change without notice 0 0x0800 4 x software setable flag 0 software 1 0x0804 4 x software setable flag 1 software 2 0x0808 4 x software setable flag 2 software 3 0x080c 4 x software setable flag 3 software 4 0x0810 4 x software setable flag 4 software 5 0x0814 4 x software setable flag 5 software 6 0x0818 4 x software setable flag 6 software 7 0x081c 4 x software setable flag 7 software 8 0x0820 4 reserved 9 0x0824 4 x platform flash bank 0 abort | platform flash bank 0 stall | platform flash bank 1 abort | platform flash bank 1 stall | platform flash bank 2 abort | platform flash bank 2 stall | platform flash bank 3 abort | platform flash bank 3 stall ecsm 10 0x0828 4 x combined error dma2x 11 0x082c 4 x channel 0 dma2x 12 0x0830 4 x channel 1 dma2x 13 0x0834 4 x channel 2 dma2x 14 0x0838 4 x channel 3 dma2x 15 0x083c 4 x channel 4 dma2x 16 0x0840 4 x channel 5 dma2x 17 0x0844 4 x channel 6 dma2x 18 0x0848 4 x channel 7 dma2x 19 0x084c 4 x channel 8 dma2x 20 0x0850 4 x channel 9 dma2x 21 0x0854 4 x channel 10 dma2x table 21-10. interrupt vector table (continued) irq # offset size [byte] this device resource module
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-15 preliminary?subject to change without notice 22 0x0858 4 x channel 11 dma2x 23 0x085c 4 x channel 12 dma2x 24 0x0860 4 x channel 13 dma2x 25 0x0864 4 x channel 14 dma2x 26 0x0868 4 x channel 15 dma2x 27 0x086c 4 reserved 28 0x0870 4 x timeout software watchdog (swt) 29 0x0874 4 reserved 30 0x0878 4 x match on channel 0 stm 31 0x087c 4 x match on channel 1 stm 32 0x0880 4 x match on channel 2 stm 33 0x0884 4 x match on channel 3 stm 34 0x0888 4 reserved 35 0x088c 4 x ecc_dbd_platformflash | ecc_dbd_platformram ecsm 36 0x0890 4 x ecc_sbc_platformflash | ecc_sbc_platformram ecsm 37 0x0894 4 reserved section c 38 0x0898 4 x rtc real time counter (rtc/api) 39 0x089c 4 x api real time counter (rtc/api) 40 0x08a0 4 reserved 41 0x08a4 4 x siu external irq_0 system integration unit lite (siul) 42 0x08a8 4 x siu external irq_1 system integration unit lite (siul) 43 0x08ac 4 reserved 44 0x08b0 4 reserved 45 0x08b4 4 reserved table 21-10. interrupt vector table (continued) irq # offset size [byte] this device resource module
pxd10 microcontroller reference manual, rev. 1 21-16 freescale semiconductor preliminary?subject to change without notice 46 0x08b8 4 x wakeup_irq_0 wakeup unit (wkup) 47 0x08bc 4 x wakeup_irq_1 wakeup unit (wkup) 48 0x08c0 4 x wakeup_irq_2 wakeup unit (wkup) 50 0x08c4 4 reserved 50 0x08c8 4 reserved 51 0x08cc 4 x safe mode interrupt mc_me 52 0x08d0 4 x mode transition interrupt mc_me 53 0x08d4 4 x invalid mode interrupt mc_me 54 0x08d8 4 x invalid mode config mc_me 55 0x08dc 4 o reserved 56 0x08e0 4 x functional and destructive reset alternate event interrupt (ipi_int) mc_rgm 57 0x08e4 4 x fxosc counter expired (ipi_int_osc) fxosc 58 0x08e8 4 o reserved 59 0x08ec 4 x pitimer channel 0 per iodic interrupt timer (pit) 60 0x08f0 4 x pitimer channel 1 periodic interrupt timer (pit) 61 0x08f4 4 x pitimer channel 2 periodic interrupt timer (pit) 62 0x08f8 4 x adc_eoc analog to digital converter 0 (adc0) 63 0x08fc 4 x adc_er analog to digital converter 0 (adc0) 64 0x0900 4 x adc_wd analog to digital converter 0 (adc0) 65 0x0904 4 x flexcan_esr[err_int] flexcan 0 (can0) 66 0x0908 4 x flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan 0 (can0) 67 0x090c 4 o reserved table 21-10. interrupt vector table (continued) irq # offset size [byte] this device resource module
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-17 preliminary?subject to change without notice 68 0x0910 4 x flexcan_buf_00_03 flexcan 0 (can0) 69 0x0914 4 x flexcan_buf_04_07 flexcan 0 (can0) 70 0x0918 4 x flexcan_buf_08_11 flexcan 0 (can0) 71 0x091c 4 x flexcan_buf_12_15 flexcan 0 (can0) 72 0x0920 4 x flexcan_buf_16_31 flexcan 0 (can0) 73 0x0924 4 x flexcan_buf_32_63 flexcan 0 (can0) 74 0x0928 4 x dspi_sr[tfuf] dspi_sr[rfof] dspi 0 75 0x092c 4 x dspi_sr[eoqf] dspi 0 76 0x0930 4 x dspi_sr[tfff] dspi 0 77 0x0934 4 x dspi_sr[tcf] dspi 0 78 0x0938 4 x dspi_sr[rfdf] dspi 0 79 0x093c 4 x linflex_rxi linflex 0 80 0x0940 4 x linflex_txi linflex 0 81 0x0944 4 x linflex_err linflex 0 82 0x0948 4 o reserved 83 0x094c 4 o reserved 84 0x0950 4 o reserved 85 0x0954 4 x flexcan_esr[err_int] flexcan 1 (can1) 86 0x0958 4 x flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan 1 (can1) 87 0x095c 4 o reserved 88 0x0960 4 x flexcan_buf_00_03 flexcan 1 (can1) 89 0x0964 4 x flexcan_buf_04_07 flexcan 1 (can1) 90 0x0968 4 x flexcan_buf_08_11 flexcan 1 (can1) 91 0x096c 4 x flexcan_buf_12_15 flexcan 1 (can1) table 21-10. interrupt vector table (continued) irq # offset size [byte] this device resource module
pxd10 microcontroller reference manual, rev. 1 21-18 freescale semiconductor preliminary?subject to change without notice 92 0x0970 4 x flexcan_buf_16_31 flexcan 1 (can1) 93 0x0974 4 x flexcan_buf_32_63 flexcan 1 (can1) 94 0x0978 4 x dspi_sr[tfuf] dspi_sr[rfof] dspi 1 95 0x097c 4 x dspi_sr[eoqf] dspi 1 96 0x0980 4 x dspi_sr[tfff] dspi 1 97 0x0984 4 x dspi_sr[tcf] dspi 1 98 0x0988 4 x dspi_sr[rfdf] dspi 1 99 0x098c 4 x linflex_rxi linflex 1 100 0x0990 4 x linflex_txi linflex 1 101 0x0994 4 x linflex_err linflex 1 102 0x0998 4 o reserved 103 0x099c 4 o reserved 104 0x09a0 4 o reserved 105 0x09a4 4 o reserved 106 0x09a8 4 o reserved 107 0x09ac 4 o reserved 108 0x09b0 4 o reserved 109 0x09b4 4 o reserved 110 0x09b8 4 o reserved 111 0x09bc 4 o reserved 112 0x09c0 4 o reserved 113 0x09c4 4 o reserved 114 0x09c8 4 o reserved 115 0x09cc 4 o reserved 116 0x09d0 4 o reserved 117 0x09d4 4 o reserved table 21-10. interrupt vector table (continued) irq # offset size [byte] this device resource module
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-19 preliminary?subject to change without notice 118 0x09d8 4 o reserved 119 0x09dc 4 o reserved 120 0x09e0 4 o reserved 121 0x09e4 4 o reserved 122 0x09e8 4 o reserved 123 0x09ec 4 o reserved 124 0x09f0 4 o reserved 125 0x09f4 4 x ibif inter-ic bu s interface controller 0 (i2c0) 126 0x09f8 4 x ibif inter-ic bu s interface controller 1 (i2c1) 127 0x09fc 4 x pitimer channel 3 periodic interrupt timer (pit) 128 0x0a00 4 o reserved 129 0x0a04 4 o reserved 130 0x0a08 4 o reserved 131 0x0a0c 4 o reserved 132 0x0a10 4 o reserved 133 0x0a14 4 o reserved 134 0x0a18 4 o reserved 135 0x0a1c 4 o reserved 136 0x0a20 4 o reserved 137 0x0a24 4 o reserved 138 0x0a28 4 o reserved 139 0x0a2c 4 o reserved 140 0x0a30 4 o reserved 141 0x0a34 4 x emios_gfr[f8,f9] enh anced modular i/o subsystem 0 (emios0) table 21-10. interrupt vector table (continued) irq # offset size [byte] this device resource module
pxd10 microcontroller reference manual, rev. 1 21-20 freescale semiconductor preliminary?subject to change without notice 142 0x0a38 4 x emios_gfr[f10,f11] enh anced modular i/o subsystem 0 (emios0) 143 0x0a3c 4 x emios_gfr[f12,f13] enh anced modular i/o subsystem 0 (emios0) 144 0x0a40 4 x emios_gfr[f14,f15] enh anced modular i/o subsystem 0 (emios0) 145 0x0a44 4 x emios_gfr[f16,f7] enh anced modular i/o subsystem 0 (emios0) 146 0x0a48 4 x emios_gfr[f18,f19] enh anced modular i/o subsystem 0 (emios0) 147 0x0a4c 4 x emios_gfr[f20,f21] enh anced modular i/o subsystem 0 (emios0) 148 0x0a50 4 x emios_gfr[f22,f23] enh anced modular i/o subsystem 0 (emios0) 149 0x0a54 4 o reserved 150 0x0a58 4 o reserved 151 0x0a5c 4 o reserved 152 0x0a60 4 o reserved 153 0x0a64 4 o reserved 154 0x0a68 4 o reserved 155 0x0a6c 4 o reserved 156 0x0a70 4 o reserved section d (device-specific section) 157 0x0a74 4 x emios_gfr[f16,f17] enh anced modular i/o subsystem 1 (emios1) 158 0x0a78 4 x emios_gfr[f18,f19] enh anced modular i/o subsystem 1 (emios1) 159 0x0a7c 4 x emios_gfr[f20,f21] enh anced modular i/o subsystem 1 (emios1) 160 0x0a80 4 x emios_gfr[f22,f23] enh anced modular i/o subsystem 1 (emios1) table 21-10. interrupt vector table (continued) irq # offset size [byte] this device resource module
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-21 preliminary?subject to change without notice 161 0x0a84 4 o reserved 162 0x0a88 4 o reserved 163 0x0a8c 4 o reserved 164 0x0a90 4 o reserved 165 0x0a94 4 o reserved 166 0x0a98 4 o reserved 167 0x0a9c 4 o reserved 168 0x0aao 4 o reserved 169 0x0aa4 4 o reserved 170 0x0aa8 4 o reserved 171 0x0aac 4 o reserved 172 0x0ab0 4 o reserved 173 0x0ab4 4 x ibif inter-ic bus interface controller 2 (i2c2) 174 0x0ab8 4 x ibif inter-ic bus interface controller 3 (i2c3) 175 0x0abc 4 o reserved 176 0x0ac0 4 o reserved 177 0x0ac4 4 o reserved 178 0x0ac8 4 o reserved 179 0x0acc 4 o reserved 180 0x0ad0 4 o reserved 181 0x0ad4 4 o reserved 182 0x0ad8 4 o reserved 183 0x0adc 4 x sdci sound generation logic (sgl) 184 0x0ae0 4 x vs_blank, ls_bf_vs, vsync display control unit (dcu0) 185 0x0ae4 4 x undrun display control unit (dcu0) table 21-10. interrupt vector table (continued) irq # offset size [byte] this device resource module
pxd10 microcontroller reference manual, rev. 1 21-22 freescale semiconductor preliminary?subject to change without notice 21.6.1 interrupt request sources the intc has two types of interr upt requests, peripheral and softwa re configurable. these interrupt requests can assert on any clock cycle. 186 0x0ae8 4 x parerr display control unit (dcu0) 187 0x0aec 4 x pdi display control unit (dcu0) 188 0x0af0 4 o reserved 189 0x0af4 4 o reserved 190 0x0af8 4 o reserved 191 0x0afc 4 o reserved 192 0x0b00 4 x mctoi, scdetect[0:23] stepper motor driver (smd0) 193 0x0b04 4 x blnif, itgif, and acovif stepper stall detect 0 (ssd0) 194 0x0b08 4 x blnif, itgif, and acovif stepper stall detect 1 (ssd1) 195 0x0b0c 4 x blnif, itgif, and acovif stepper stall detect 2 (ssd2) 196 0x0b10 4 x blnif, itgif, and acovif stepper stall detect 3 (ssd3) 197 0x0b14 4 x blnif, itgif, and acovif stepper stall detect 4 (ssd4) 198 0x0b18 4 x blnif, itgif, and acovif stepper stall detect 5 (ssd5) 199 0x0b1c 4 x eof liquid crystal display 0 (lcd0) 200 0x0b20 4 o reserved 201 0x0b24 4 x tfuf, rfof, tbuf, rbof, abof quadspi 0 202 0x0b28 4 x eoqf quadspi 0 203 0x0b2c 4 x tfff, tbff quadspi 0 204 0x0b30 4 x tcf, tff quadspi 0 205 0x0b34 4 x rfdf, rbdf quadspi 0 206 0x0b38 4 x ipaef, ipief, icef quadspi 0 table 21-10. interrupt vector table (continued) irq # offset size [byte] this device resource module
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-23 preliminary?subject to change without notice 21.6.1.1 peripheral interrupt requests an interrupt event in a peripheral?s hardware sets a flag bit that resi des in the peripheral. the interrupt request from the peripheral is driven by that flag bit. the time from when the peripheral starts to drive its peripheral interrupt request to the intc to the time that the intc starts to drive the interrupt request to the processor is three clocks. external interrupts are handled by the siu (see section 37.6.4, external interrupts ?). 21.6.1.2 software configurable interrupt requests an interrupt request is triggered by software by writing a 1 to a set x bit in intc_sscir0_3?intc_sscir4_7. th is write sets the corr esponding flag bit, clr x , resulting in the interrupt request. the interrupt request is cleared by writing a 1 to the clr x bit. the time from the write to the set x bit to the time that th e intc starts to drive th e interrupt request to the processor is four clocks. 21.6.1.3 unique vector for each interrupt request source each peripheral and software confi gurable interrupt request is assigne d a hardwired unique 9-bit vector. software configurable interrupts 0?7 are assigned vectors 0?7 respectively. the peripheral interrupt requests are assigned vectors 8 to as high as needed to in clude all the peripheral interrupt requests. the peripheral interrupt request input por ts at the boundary of the intc bl ock are assigned specific hardwired vectors within the intc (see table 21-1 ). 21.6.2 priority management the asserted interrupt requests are comp ared to each other based on their pri x values set in intc_psr0_3?intc_psr204_206. the result is compared to pri in the associ ated intc_cpr. the results of those comparisons manage the priority of the isr executed by the associated processor. the associated lifo also assist s in managing that priority. 21.6.2.1 current prio rity and preemption the priority arbitrator, selector, encode r, and comparator subblocks shown in figure 21-1 compare the priority of the asserted inte rrupt requests to the current priority. if the priority of any asserted peripheral or software configurable interrupt reque st is higher than the current priority for a given processor, then the interrupt request to the processor is asserted. al so, a unique vector for the preempting peripheral or software settable interrupt request is generated for intc interrupt acknowledge register (intc_iackr), and if in hardware vector mode, for the interrupt vector provided to the processor. 21.6.2.1.1 priority ar bitrator subblock the priority arbitrator subblock for e ach processor compares all the prioriti es of all of the asserted interrupt requests assigned to that processor, both peripheral a nd software configurable. th e output of the priority arbitrator subblock is the highest of those priorities assigned to a gi ven processor. also, any interrupt
pxd10 microcontroller reference manual, rev. 1 21-24 freescale semiconductor preliminary?subject to change without notice requests which have this highest priority are output as asserted interrupt requests to the associated request selector subblock. 21.6.2.1.2 request selector subblock if only one interrupt request from the associated priority arbitrator subbloc k is asserted, then it is passed as asserted to the associ ated vector encoder subbloc k. if multiple interrupt re quests from the associated priority arbitrator subblock are asserted, only the one with the lowest vector passes as asserted to the associated vector encode r subblock. the lower vector is chosen regardless of the time order of the assertions of the peripheral or soft ware configurable interrupt requests. 21.6.2.1.3 vector encoder subblock the vector encoder subblock generate s the unique 9-bit vector for the as serted interrupt request from the request selector subblock fo r the associated processor. 21.6.2.1.4 priority co mparator subblock the priority comparator submodule compares the highe st priority output from the priority arbitrator submodule with pri in intc_c pr. if the priority comparator submodul e detects that this highest priority is higher than the current priority, then it asserts the interrupt request to the processor. this interrupt request to the processor asserts whether this highest priority is raised above the value of pri in intc_cpr or the pri value in intc_cpr is lowered be low this highest priority. this high est priority then becomes the new priority which will be written to pri in intc_cpr when the interr upt request to the processor is acknowledged. interrupt requests whose pri n in intc_psr n are zero will not cause a preemption because their pri n will not be higher than pri in intc_cpr. 21.6.2.2 last-in first-out (lifo) the lifo stores the preempted pri values from the intc_cpr. therefore, becau se these priorities are stacked within the intc, if interrupt s need to be enabled during the isr, at the beginning of the interrupt exception handler the pri value in the intc_cpr does not need to be loaded from the intc_cpr and stored onto the context stack. likewise at the end of the interrupt exce ption handler, the priority does not need to be loaded from the context stack and stored in to the intc_cpr. the pri value in the intc_cpr is pushed onto the lifo when the intc_iackr is read in softwarevector mode or the interrupt acknowledge signal from th e processor is asserted in hardware vector mode. the priority is popped into pri in the intc_cpr whenever the intc_eoir is written. although the intc supports 16 priorities, an isr execut ing with pri in the intc_cpr equal to 15 will not be preempted. therefore, the lifo supports the st acking of 15 priorities. ho wever, the lifo is only 14 entries deep. an entry for a priority of 0 is not needed because of how pushing onto a full lifo and popping an empty lifo are treat ed. if the lifo is pushed 15 or more times than it is popped, the priorities first pushed are overwritten. a priority of 0 woul d be an overwritten priority . however, the lifo will pop ?0?s if it is popped more times than it is pushed. th erefore, although a priority of 0 was overwritten, it is regenerated with the popping of an empty lifo. the lifo is not memory mapped.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-25 preliminary?subject to change without notice 21.6.3 handshaking with processor 21.6.3.1 software vect or mode handshaking this section describes handshaki ng in software vector mode. 21.6.3.1.1 acknowledging inte rrupt request to processor a timing diagram of the interrupt request and acknowledge handshaking in software vector mode and the handshake near the end of the inte rrupt exception handler, is shown in figure 21-10 . the intc examines the peripheral and software configur able interrupt requests. when it finds an asserted peripheral or software configurable interrupt request with a hi gher priority than pri in the associated intc_cpr , it asserts the interrupt request to the processor. the intvec field in th e associated intc _iackr is updated with the preempting interrupt request?s vector when the interrupt request to the processor is asserted. the intvec field retains that value until the next time the interrupt request to the processor is asserted. the rest of handshaking process is described in section 21.4.1.1, software vector mode? . ? 21.6.3.1.2 end of inte rrupt exception handler before the interrupt exception handli ng completes, intc end-of-interrupt register (intc_eoir) must be written.when written, the associated lifo is popped so th e preempted priority is restored into pri of the intc_cpr. before it is written, the peripheral or software configurable flag bit must be cleared so that the peripheral or software configur able interrupt request is negated. note to ensure proper operation acro ss all esys mcus, execute an mbar or msync instruction between the access to clear the flag bit and the write to the intc_eoir. when returning from the preemption, the intc does not search for the periphe ral or software settable interrupt request whose isr was pr eempted. depending on how much the isr progressed, that interrupt request may no longer even be asserted. when pri in intc_cpr is lowered to the priority of the preempted isr, the interrupt reques t for the preempted isr or any othe r asserted peripheral or software settable interrupt request at or below that priority wi ll not cause a preemption. in stead, after the restoration of the preempted context, the processor will return to the instruction address that it was to next execute before it was preempted. this next instruction is part of the preempt ed isr or the interrupt exception handler?s prolog or epilog.
pxd10 microcontroller reference manual, rev. 1 21-26 freescale semiconductor preliminary?subject to change without notice figure 21-10. software vector mode handshaking timing diagram 21.6.3.2 hardware vector mode handshaking a timing diagram of the in terrupt request and acknow ledge handshaking in hard ware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in figure 21-11 . as in software vector mode, the intc ex amines the peripheral and software settable interrupt requests, and when it finds an asserted one with a higher priority than pri in intc_cpr, it as serts the interrupt request to the processor. the intvec field in the intc_i ackr is updated with the preempting peripheral or software settable interrupt request?s vector when th e interrupt request to the processor is asserted. the intvec field retains that value until the next time the interrupt request to the processor is asserted. in addition, the value of the interrupt v ector to the processor matches the value of the intvec field in the intc_iackr. the rest of the handshaking is described in section 21.4.1.2, hardware vector mode.? the handshaking near the end of the interrupt excepti on handler, that is the wri ting to the intc_eoir, is the same as in software vector mode. refer to section 21.6.3.1.2, end of interrupt exception handler.? 0 1 0 clock interrupt request to processor hardware vector enable interrupt vector interrupt acknowledge read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 108 0
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-27 preliminary?subject to change without notice figure 21-11. hardware vector mode handshaking timing diagram 21.7 initialization/application information 21.7.1 initialization flow after exiting reset, all of the pri n fields in intc prior ity select registers (intc_psr0_3?intc_psr_204_206) will be zero, and pri in intc current priority register (intc_cpr) will be 15. thes e reset values will prevent the intc from assert ing the interrupt request to the processor. the enable or mask bi ts in the peripherals are reset such that the peripheral interrupt requests are negated. an initialization sequenc e for allowing the peripheral and so ftware settable in terrupt requests to cause an interrupt request to the proc essor is:interrupt_re quest_initialization: interrupt_request_initialization: configure vtes and hven in intc_mcr configure vtba in intc_iackr raise the pri n fields in intc_psr n set the enable bits or clear the mask bits for the peripheral interrupt requests lower pri in intc_cpr to zero enable processor recognition of interrupts 21.7.2 interrupt exception handler these example interrupt exception handlers use power architecture assembly code. 0 108 0 1 0 clock interrupt request to processor hardware vector enable interrupt vector interrupt acknowledge read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 108
pxd10 microcontroller reference manual, rev. 1 21-28 freescale semiconductor preliminary?subject to change without notice 21.7.2.1 software vector mode interrupt_exception_handler: code to create stack frame, save working register, and save srr0 and srr1 lis r3,intc_iackr@ha # form adjusted upper half of intc_iackr address lwz r3,intc_iackr@l(r3) # load intc_iackr, which clears request to processor lwz r3,0x0(r3) # load address of isr from vector table wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 eabi mtlr r3 # move intc_iackr contents into link register blrl # branch to isr; link register updated with epilog # address epilog: code to restore most of context required by e500 eabi # popping the lifo after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,intc_eoir@ha # form adjusted upper half of intc_eoir address li r4,0x0 # form 0 to write to intc_eoir wrteei 0 # disable processor recognition of interrupts stw r4,intc_eoir@l(r3) # store to intc_eoir, informing intc to lower priority code to restore srr0 and srr1, restore working registers, and delete stack frame rfi vector_table_base_address: address of isr for interrupt with vector 0 address of isr for interrupt with vector 1 . . . address of isr for interrupt with vector 510 address of isr for interrupt with vector 511 isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # return to epilog 21.7.2.2 hardware vector mode this interrupt exception handler is useful with processor and system bus implementations which support a hardware vector. this example assu mes that each inte rrupt_exception_handler x only has space for four instructions, and therefore a branch to interrupt_exception_handler_continued x is needed. interrupt_exception_handler x : b interrupt_exception_handler_continued x # 4 instructions available, branch to continue
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-29 preliminary?subject to change without notice interrupt_exception_handler_continued x : code to create stack frame, save working register, and save srr0 and srr1 wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 eabi bl isr x # branch to isr for interrupt with vector x epilog: code to restore most of context required by e500 eabi # popping the lifo after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,intc_eoir@ha # form adjusted upper half of intc_eoir address li r4,0x0 # form 0 to write to intc_eoir wrteei 0 # disable processor recognition of interrupts stw r4,intc_eoir@l(r3) # store to intc_eoir, informing intc to lower priority code to restore srr0 and srr1, restore working registers, and delete stack frame rfi isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # branch to epilog 21.7.3 isr, rtos, and task hierarchy the rtos and all of the tasks under it s control typically execute with pri in intc current priority register (intc_cpr) having a value of 0. the rtos will execute the tasks accord ing to whatever priority scheme that it may have, but that priority scheme is independent and has a lo wer priority of execution than the priority scheme of the intc. in other words, the isrs execute above intc_cpr priority 0 and outside the control of the rtos, the rtos executes at in tc_cpr priority 0, and while the tasks execute at different priorities under the control of the rtos , they also execute at intc_cpr priority 0. if a task shares a resource with an isr and the pcp is being used to mana ge that shared resource, then the task?s priority can be elevated in the intc _cpr while the shared resource is being accessed. an isr whose pri n in intc priority select registers (intc_psr0_3?intc_psr204_206) has a value of 0 will not caus e an interrupt request to the pr ocessor, even if its peripheral or software settable interrupt request is asserted. for a peripheral interrupt request, not setting its enable bit or disabling the mask bit will cause it to remain negated, which consequently also will not cause an interrupt request to the processor. since the isrs are outside the control of th e rtos, this isr will not r un unless called by another isr or the interrupt exception handler , perhaps after executing another isr.
pxd10 microcontroller reference manual, rev. 1 21-30 freescale semiconductor preliminary?subject to change without notice 21.7.4 order of execution an isr with a higher priority can pr eempt an isr with a lower priority , regardless of the unique vectors associated with each of their periphe ral or software configur able interrupt requests. however, if multiple peripheral or software configurable interrupt requests are asserted, more than one has the highest priority, and that priority is high enough to cause preemption, the intc selects the one with the lowest unique vector regardless of the order in time that they assert ed. however, the ability to meet deadlines with this scheduling scheme is no less than if the isrs execute in the time order that their peripheral or software configurable interrupt requests asserted. the example in table 21-11 shows the order of execution of both is rs with different priorities and the same priority table 21-11. order of isr execution example step step description code executing at end of step pri in intc_cpr at end of step rtos isr108 1 isr208 isr308 isr408 interrupt exception handler 1 rtos at priority 0 is executing. x 0 2 peripheral interrupt request 100 at priority 1 asserts. interrupt taken. x1 3 peripheral interrupt request 400 at priority 4 is asserts. interrupt taken. x4 4 peripheral interrupt request 300 at priority 3 is asserts. x4 5 peripheral interrupt request 200 at priority 3 is asserts. x4 6 isr408 completes. interrupt exception handler writes to intc_eoir. x1 7 interrupt taken. isr208 starts to execute, even though peripheral interrupt request 300 asserted first. x3 8 isr208 completes. interrupt exception handler writes to intc_eoir. x1 9 interrupt taken. isr308 starts to execute. x3 10 isr308 completes. interrupt exception handler writes to intc_eoir. x1 11 isr108 completes. interrupt exception handler writes to intc_eoir. x0 12 rtos continues execution. x 0
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-31 preliminary?subject to change without notice 21.7.5 priority ceiling protocol 21.7.5.1 elevating priority the pri field in intc_cpr is elevated in the osek pcp to the ceiling of all of the priorities of the isrs that share a resource. this protocol allows coherent accesses of the isrs to that shared resource. for example, isr1 has a priority of 1, isr2 has a priority of 2, and is r3 has a priority of 3. they share the same resource. before isr1 or isr2 can access that resource, they must raise the pri value in intc_cpr to 3, the ceiling of all of the isr priorities. after they rel ease the resource, the pri value in intc_cpr can be lowered. if they do not raise thei r priority, isr2 can preempt isr1, and isr3 can preempt isr1 or isr2, possibly co rrupting the shared resource. anot her possible failure mechanism is deadlock if the higher priority isr needs the lower pr iority isr to release the resource before it can continue, but the lower priority isr cannot release the resource until th e higher priority isr completes and execution returns to the lower priority isr. using the pcp instead of disabli ng processor recognition of all inte rrupts eliminates the time when accessing a shared resource that all higher priority interrupts are blocked. for ex ample, while isr3 cannot preempt isr1 while it is accessing the shared resource, all of the isrs with a priority higher than 3 can preempt isr1. 21.7.5.2 ensuring coherency a scenario can cause non-coherent accesses to the shared resource. fo r example, isr1 and isr2 are both running on the same core and both shar e a resource. isr1 has a lower prio rity than isr2. isr1 is executing and writes to the intc_cpr. the instru ction following this store is a stor e to a value in a shared coherent data block. either immediately before or at the same time as the first st ore, the intc asse rts the interrupt request to the processor be cause the peripheral interrupt request for isr2 has asse rted. as the processor is responding to the interrupt request from the intc, a nd as it is aborting tran sactions and flushing its pipeline, it is possible that both stor es will be executed. isr2 thereby th inks that it can access the data block coherently, but the data block has been corrupted. osek uses the getresource and rele aseresource system services to mana ge access to a shared resource. to prevent corruption of a coherent data block, modifications to pri in intc_cpr can be made by those system services with the code sequence: disable processor recognition of interrupts pri modification enable processor recognition of interrupts 21.7.6 selecting priorities accordin g to request rates and deadlines the selection of the priorities for the isrs can be made using rate monotonic scheduling (rms) or a superset of it, deadline monotonic scheduling (dms). in rms, the is rs which have higher request rates have higher priorities. in dms, if th e deadline is before the next time th e isr is requested, then the isr is 1 isr108 executes for peripheral interrupt request 100 beca use the first eight isrs are for software configurable interrupt requests.
pxd10 microcontroller reference manual, rev. 1 21-32 freescale semiconductor preliminary?subject to change without notice assigned a priority according to the time from the request for the isr to the deadline, not from the time of the request for the isr to the next request for it. for example, isr1 executes every 100 ? s, isr2 executes every 200 ? s, and isr3 executes every 300 ? s. isr1 has a higher priority than isr2 which has a higher priority than isr3 ; however, if isr3 has a deadline of 150 ? s, then it has a higher priority than isr2. the intc has 16 priorities, which may be less than the number of isrs. in this case, the isrs should be grouped with other isrs that have si milar deadlines. for example, a prio rity could be allocated for every time the request rate doubles. isrs wi th request rates around 1 ms would sh are a priority, is rs with request rates around 500 ? s would share a priority, isrs with request rates around 250 ? s would share a priority, etc. with this approach, a ra nge of isr reque st rates of 2 16 could be included, rega rdless of the number of isrs. reducing the number of priorities reduc es the processor?s ability to meet its deadlines. however, reducing the number of priorities can reduce the size and latency through the in terrupt controller. it also allows easier management of isrs with si milar deadlines that share a resource. they do not need to use the pcp to access the shared resource. 21.7.7 software configur able interrupt requests the software configurable interrupt requests can be used in two ways. they can be used to schedule a lower priority portion of an isr and they may also be used by processors to interrupt othe r processors in a multiple processor system. 21.7.7.1 scheduling a lower pr iority portion of an isr a portion of an isr needs to be executed at the pri x value in intc_psr0_3 -intc_psr204_206, which becomes the pri value in intc_cpr with the inte rrupt acknowledge. the isr, however, can have a portion that does not need to be executed at this higher priority. th erefore, executing the later portion that does not need to be executed at th is higher priority can prevent the ex ecution of isrs wh ich do not have a higher priority than the earlier porti on of the isr but do have a higher pr iority than what the later portion of the isr needs. this preemptive scheduling ineffi ciency reduces the processor?s ability to meet its deadlines. one option is for the isr to complete the earlier higher priority portion, but then schedule through the rtos a task to execute the later lower priority por tion. however, some rtoss can require a large amount of time for an isr to schedule a task. therefore, a second option is fo r the isr, after co mpleting the higher priority portion, to set a set x bit in intc_sscir0_3?intc_sscir4_7. writing a 1 to set x causes a software configurable interrupt reque st. this software configurable in terrupt request will usually have a lower pri x value in the intc_psr x _ x and will not cause preemptive scheduling inefficiencies. after generating a software settable interru pt request, the higher priority isr completes. the lower priority isr is scheduled according to its priority. execution of the higher priority isr is not resumed after the completion of the lower priority isr.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 21-33 preliminary?subject to change without notice 21.7.7.2 scheduling an is r on another processor because the set x bits in the intc_sscir x _ x are memory mapped, processors in multiple-processor systems can schedule isrs on the other processors. one applicatio n is that one processor wants to command another processor to perform a piece of work and the initia ting processor does not need to use the results of that work. if the in itiating processor is concerned that the processor execut ing the software configurable isr has not completed the work before asking it to again execute the isr, it can check if the corresponding clr x bit in intc_sscir x _ x is asserted before again writing a 1 to the set x bit. another application is the sharing of a block of data. for example, a first processor has completed accessing a block of data and wants a second processo r to then access it. furt hermore, after the second processor has completed accessing th e block of data, the first proce ssor again wants to access it. the accesses to the block of data must be done coherently. to do this, the first processo r writes a 1 to a set x bit on the second processor. after accessing the bl ock of data, the second processor clears the corresponding clr x bit and then writes 1 to a set x bit on the first processor, in forming it that it can now access the block of data. 21.7.8 lowering priority within an isr a common method for avoiding preemptive scheduling inefficiencies with an isr whose work spans multiple priorities (see section 21.7.7.1, scheduling a lower pr iority portion of an isr?) is to lower the current priority. however, the intc has a lifo whose depth is determ ined by the number of priorities. note lowering the pri value in intc_cpr within an isr to below the isr?s corresponding pri value in in tc_psr0_3?intc_psr292_293 allows more preemptions than the lifo depth can support. therefore, the intc does not support lowering the current pr iority within an isr as a way to avoid preemptive scheduling inefficiencies. 21.7.9 negating an interrupt request outside of its isr 21.7.9.1 negating an interrupt request as a side effect of an isr some peripherals have flag bits that can be cleared as a side effect of servicing a peripheral interrupt request. for example, reading a spec ific register can clear the flag bits and their corresponding interrupt requests. this clearing as a side effect of servicing a peripheral in terrupt request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request whose isr presently is executing. this negating of a periphe ral interrupt request outside of its isr can be a desired effect. 21.7.9.2 negating multiple in terrupt requests in one isr an isr can clear other flag bits besi des its own. one reason that an isr cl ears multiple flag bits is because it serviced those flag bits, and therefore the isrs for these flag bits do not need to be executed.
pxd10 microcontroller reference manual, rev. 1 21-34 freescale semiconductor preliminary?subject to change without notice 21.7.9.3 proper setting of interrupt request priority whether an interrupt request negates outside its own isr due to the side effect of an isr execution or the intentional clearing a flag bit, the pr iorities of the peripheral or software configurable interrupt requests for these other flag bits must be selected properly. their pri x values in intc_psr0_3?intc_psr204_206 must be selected to be at or lower than the priority of the isr that cleared their flag bits. otherwise, those flag bits can cause the interrupt reque st to the processor to assert. furthe rmore, the clearing of these other flag bits also has the same ti ming relationship to the writing to intc_sscir0_3?intc_sscir4_7 as the clearing of the flag bit that caused the present isr to be executed (see section 21.6.3.1.2, end of interrupt exception handler ?) . a flag bit whose enable bit or mask bit negates its peripheral interrupt request can be clea red at any time, regardless of the periphera l interrupt request?s pri x value in intc_psr x _ x . 21.7.10 examining lifo contents in normal mode, the user does not need to know the contents of the lifo. he may not even know how deeply the lifo is nested. however, if he wants to read the contents, such as in debug mode, they are not memory mapped. the contents can be read by popping the lifo and reading the pri field in either intc_cpr. the code sequence is: pop_lifo: store to intc_eoir load intc_cpr, examine pri, and store onto stack if pri is not zero or value when interrupts were enabled, branch to pop_lifo when the examination is complete, the lifo can be restored using this code sequence: push_lifo: load stacked pri value and store to intc_cpr load intc_iackr if stacked pri values are not depleted, branch to push_lifo
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-1 preliminary?subject to change without notice chapter 22 lcd driver (lcd64f6b) 22.1 information specific to this device this section presents device-speci fic parameterization and customizat ion information not specifically referenced in the remainder of this chapter. 22.1.1 number of front and back planes 22.1.2 lcd clock selection table 22-2 shows the clocks selected by the lcdcr[lcdocs] bit. 22.1.3 settings du ring standby mode to keep the lcd driver shut down in standby mode, the following settings are needed: ? lcdcr[lcdrst] = 0 ? lcdcr[lcdrcs] = 0 to keep the lcd driver on (functioning) in st andby mode, the following settings are needed: ? lcdcr[lcdrst] = 1 ? lcdcr[lcdrcs] = 1 ? lcdcr[lcdocs] = 0 or 1 ? if this field is 0, the lcd dr iver will operate from sirc. ? if this field is 1, the lcd dr iver will operate from sxosc. table 22-1. number of front and back planes parameter value number of front planes 38 or 40 1 1 software-configurable number of back planes 4 or 6 1 table 22-2. lcd clock selection based on lcdcr[lcdocs] value of lcdcr[lcdocs] clock selected 1 32 khz osc 0 128 khz osc
pxd10 microcontroller reference manual, rev. 1 22-2 freescale semiconductor preliminary?subject to change without notice 22.2 introduction 22.2.1 overview the lcd driver module has up to 64 frontplane drivers ( n ) and up to 6 backplane drivers ( m ) so that a maximum of 384 lcd segments are cont rollable. the actua l implementation ( n , m ) depends on the device specification. each segment is controlled by a corres ponding bit in the lcd ram. m multiplex modes (1/1, 1/2,...1/ m duty), and three bias (1/1, 1/2, 1/3) methods are available. the v 0 voltage is the lowest level of the output waveform and v 3 becomes the highest level. all fr ontplane and backplane pins can be multiplexed with other port functions. the lcd driver system consists of five major sub-modules: ? timing and control ? consists of registers a nd control logic for frame clock generation, bias voltage level select, frame duty select, contrast adjustment, ba ckplane select and frontplane select/enable, remapping of bac kplane drivers to produce the requi red frame frequency and voltage waveforms. ? lcd ram ? contains the data to be displayed on the lcd. data can be read from or written to the display ram at any time. ? frontplane drivers ? consists of n frontplane drivers. ? backplane drivers ? consists of m backplane drivers. ? voltage generator ? based on reference voltage, i. e. applied to vlcd, it generates the voltage levels for the timing and control logic to produce the frontplane and backplane waveforms.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-3 preliminary?subject to change without notice figure 22-1. block diagram 22.2.2 features the lcd64f6b includes these distinctive features: ? up to 64 frontplane drivers ? each frontplane has an individual enable bit ? up to 6 backplane drivers ? remapping of backplane drivers ? programmable frame clock generator ? programmable bias vol tage level selector ? programmable output current ? selectable output current boost during transitions. ? selectable lcd frame fr equency interrupt event ? on-chip generation of four different output voltage levels ? two contrast adjustment options: ? using vlcd voltage if available at pin ? using contrast adjustment phases ? selectable continuous drive of lcd while in power down mode lcd ram timing and control logic frontplane drivers voltage generator backplane drivers internal address/data/clocks v 3 v 2 v 1 v 0 v 3 v 2 v 1 v 0 fp[ n -1:0] bp[ m -1:0] prescaler clk lcd clock osc vddx vlcd
pxd10 microcontroller reference manual, rev. 1 22-4 freescale semiconductor preliminary?subject to change without notice 22.2.3 modes of operation the lcd64f6b module supports up to seven operation modes with differ ent numbers of backplanes and different biasing levels.during po wer saving mode the lcd operation can be suspended under software control. depending on the state of internal bits, the lcd can operate normally wi th source clock applied, or the lcd clock generation can be turned off a nd the lcd64f6b module ente rs a power conservation state. this is a high level description on ly, detailed descriptions of opera ting modes are contained in later sections. 22.3 external signal description 22.3.1 detailed signal descriptions table 22-3. signal properties name port function reset pull up m backplane waveforms bp[ m -1:0] backplane waveform signals that connect directly to the pads high impedance n frontplane waveforms fp[ n -1:0] frontplane waveform signals that connect directly to the pads high impedance lcd voltage vlcd lcd reference supply voltage vddx voltage vddx lcd supply voltage vssx voltage vssx lcd ground voltage table 22-4. interface a?detailed signal descriptions signal description bp[ m -1:0] this output signal vector represents the anal og backplane waveforms of the lcd64f6b module and is connected directly to the corresponding pads. fp[ n -1:0] this output signal vector represents the analo g frontplane waveforms of the lcd64f6b module and is connected directly to the corresponding pads. vlcd positive reference supply voltage for the lcd waveform generation. vddx positive supply voltage for the lcd waveform generation. vssx ground supply voltage for th e lcd waveform generation.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-5 preliminary?subject to change without notice 22.4 memory map and register definition 22.4.1 memory map table 22-5. block memory map offset or address register access reset value location general registers 0x00 lcd control register (lcdcr) r/w 0x0000_0000 on page 6 0x04 lcd prescaler control register (lcdpcr) r/w 0x0000_0000 on page 9 0x08 lcd contrast control register (lcdccr) r/w 0x0000_0000 on page 10 0x0c unimplemented 0x10 lcd frontplane enable register 0 (fpenr0) r/w 0x0000_0000 on page 11 0x14 lcd frontplane enable register 1 (fpenr1) r/w 0x0000_0000 on page 12 0x18 unimplemented 0x1c unimplemented 0x20 lcdram (location 0) r/w 0x0000_0000 on page 13 0x24 lcdram (location 1) r/w 0x0000_0000 on page 14 0x28 lcdram (location 2) r/w 0x0000_0000 on page 15 0x2c lcdram (location 3) r/w 0x0000_0000 on page 16 0x30 lcdram (location 4) r/w 0x0000_0000 on page 17 0x34 lcdram (location 5) r/w 0x0000_0000 on page 18 0x38 lcdram (location 6) r/w 0x0000_0000 on page 19 0x3c lcdram (location 7) r/w 0x0000_0000 on page 20 0x40 lcdram (location 8) 1 1 end of implemented ram for 36 fps r/w 0x0000_0000 on page 21 0x44 lcdram (location 9) 2 2 end of implemented ram for 40 fps r/w 0x0000_0000 on page 22 0x48 lcdram (location 10) 3 3 end of implemented ram for 44 fps r/w 0x0000_0000 on page 23 0x4c lcdram (location 11) 4 4 end of implemented ram for 48 fps r/w 0x0000_0000 on page 24 0x50 lcdram (location 12) 5 5 end of implemented ram for 52 fps r/w 0x0000_0000 on page 25 0x54 lcdram (location 13) 6 r/w 0x0000_0000 on page 26 0x58 lcdram (location 14) 7 r/w 0x0000_0000 on page 27 0x5c lcdram (location 15) 8 r/w 0x0000_0000 on page 28
pxd10 microcontroller reference manual, rev. 1 22-6 freescale semiconductor preliminary?subject to change without notice 22.4.2 register descriptions this section consists of re gister descriptions in addr ess order. each description includes a standard register diagram with an associ ated figure number. 22.4.2.1 lcd contro l register (lcdcr) 6 end of implemented ram for 56 fps 7 end of implemented ram for 60 fps 8 end of implemented ram for 64 fps 0x00 access: user read/write 01234567 r lcden lcdrst lcdrcs duty bias vlcds w reset00000000 8 9 10 11 12 13 14 15 r pwr bsten bstsel bstao lcdocs lcdint eof w reset00000000 16 17 18 19 20 21 22 23 rnof w reset00000000 24 25 26 27 28 29 30 31 r lcdbpa lcdbps w reset00000000 = unimplemented figure 22-2. lcd control register (lcdcr)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-7 preliminary?subject to change without notice table 22-6. lcdcr field descriptions field description 0 lcden. lcd driver system enable. 0 all frontplane and backplane pins are disabled. in addition, the lcd driver is disabled and all lcd waveform generation clocks are stopped. 1 lcd driver system is enabled. all fp[ n -1:0] pins with fp[ n -1]en set, will output an lcd driver waveform. the bp[ m -1:0] pins will output an lcd driver wa veform based on the settings of duty. 1 lcdrst. continue to drive lcd display while stop/standby requested. can be written only when lcden is cleared. see section 22.5.8, operation in power saving modes , for details. 0 stop lcd64f6b display driver syst em while stop/standby requested. 1 lcd display driver system operates nor mally while stop/standby requested. 2 lcdrcs. lcd reference clock select. can be written only when lcden is cleared. 0 source clock for lcd driver system (prescaler input) is system clock. 1 source clock for lcd driver system (prescaler input) is osc clock. see device level documentation for detail on osc clk. 3:5 duty. lcd duty select the duty bits select the duty (multiplex mode) of the lcd driver system, as shown in table 22-29 . the multiplex mode should be changed only when lcd driver is disabled, lcden is not set. 6 bias. bias voltage select this bit selects the bias voltage levels during various lcd operating modes, as shown in ta b l e 2 2 - 2 9 7 vlcds. lcd voltage reference select. the vclds bit selects which supply is be used as lcd waveform reference supply. can be written only when lcden is cleared. 0: vddx is used as reference supply. 1: vlcd is used as reference supply. 8:9 pwr. lcd power mode the pwr bits select the output current and have a direct impact on the power consumption and drive capability of the lcd64f6b module. table 22-30 lists the possible selections. 10 bsten. lcd output current boost enable since the lcd appears like a capacitance to the driver it is sometimes useful to boost the output current during transitions to increase the slew rate of the driver. 0: no output current boost available. 1: output current boost during transitions according to the bstsel bit.
pxd10 microcontroller reference manual, rev. 1 22-8 freescale semiconductor preliminary?subject to change without notice 11 bstsel. lcd output current boost select the bst bit sets the multiplier for th e output current boost. if the bsten bit is set, the output current is boosted during transitions in the following way: 0 8 times boosting. 1 16 times boosting. 12 bstao. lcd boost always on if set, the selected by bst and enabled by bsten boost current is always on and not only during the time frame generated by the state machine. 0 the boost always on feature is disabled. 1 the boost always on feature is enabled. 13 lcdocs. lcd osc clock select. can be written only when lcden is cleared. see device level information which osc clock is defined as first and second osc clock. 0 first osc clock is selected as clock for lcd driver system (prescaler input) if lcdrcs is set. 1 second osc clock is selected as clock for lcd driver system (prescaler input) if lcdrcs is set. 14 lcdint. lcd interrupt enable. 0: interrupt request is disabled. 1: interrupt will be requested whenever eof is set. 15 eof. end of frame interrupt flag. end of frame interrupt flag bit is set every time when nof frames have been executed while lcden is set. this flag can only be cleared by writing a 1. writin g a 0 has no effect. if enabled (lcdint = 1), eof causes an interrupt request. 0: defined via nof bits frames have not been executed yet. 1: defined via nof bits frames have been executed. 16:23 nof: number of frames. the number of frames bits determine how many fr ames are counted until an interrupt will be requested. the possible number of frames are: 0x00: an interrupt is request ed at the end of every frame. 0x01: an interrupt is requested at the end of every second frame. . . 0xff: an interrupt is requested at the end of every 256th frame. table 22-6. lcdcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-9 preliminary?subject to change without notice 22.4.2.2 lcd prescaler c ontrol register (lcdpcr) 26 lcdbpa: backplane adding if set, the backplanes, which are not available in stan dard configuration, will be mapped on frontplanes as shown in ta b l e 2 2 - 2 8 . hence, up to six backplanes can be used to drive lcd displays. 0: no additional backplanes will be mapped on frontplanes. 1: additional backplanes will be mapped on frontplanes. 29:31 lcdbps: backplane shifting using these bits, backplanes will be swapped with frontplanes as shown in table 22-28 . 0x04 access: user read/write 01234567 r000 0lclk w reset00000000 8 9 10 11 12 13 14 15 r000 0 0 000 w reset00000000 16 17 18 19 20 21 22 23 r 0 c000000 w reset00000000 24 25 26 27 28 29 30 31 r00000000 w reset00000000 = unimplemented figure 22-3. lcd prescaler control register (lcdpcr) table 22-6. lcdcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 22-10 freescale semiconductor preliminary?subject to change without notice 22.4.2.3 lcd contrast c ontrol register (lcdccr) table 22-7. lcdpcr field descriptions field description 4:7 lclk. lcd clock prescaler. the lcd clock prescaler bits determine the clock divider value to produce the lcd clock frequency. for detailed description of the correlation between lcd clock prescaler bits and the divider value please refer to table 22-27 . lcd clock prescaler bits should be changed only when lcd driver is disabled, lcden is not set. 0x08 access: user read/write 01234567 rccen 0 000 lcc w reset00000000 8 9 10 11 12 13 14 15 rlcc w reset00000000 16 17 18 19 20 21 22 23 r 0 000 0 000 w reset00000000 24 25 26 27 28 29 30 31 r 0 000 0 000 w reset00000000 = unimplemented figure 22-4. lcd contrast control register (lcdccr)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-11 preliminary?subject to change without notice 22.4.2.4 lcd frontplane enable register 0 (fpenr0) table 22-8. lcdccr field descriptions field description 0 ccen. lcd contrast control enable. 0 the contrast control is disabled. 1 the contrast control is enabled. the length of the contrast phase depends on the bits lcc. 5:15 lcc. lcd contrast control. the contrast control bits determi ne the width of the contrast phase. 0x7ff = contrast phase lasts the whole duty cycle. 0x000 = contrast phase has no duration what results in highest contrast. 0x10 access: user read/write 01234567 r fp31en fp30en fp29en fp28en fp27en fp26en fp25en fp24en w reset00000000 8 9 10 11 12 13 14 15 r fp23en fp22en fp121en fp20en fp19en fp18en fp17en fp16en w reset00000000 16 17 18 19 20 21 22 23 r fp15en fp14en fp13en fp12en fp11en fp10en fp9en fp8en w reset00000000 24 25 26 27 28 29 30 31 r fp7en fp6en fp5en fp4en fp3en fp2en fp1en fp0en w reset00000000 = unimplemented figure 22-5. lcd frontplane enable register 0 (fpenr0)
pxd10 microcontroller reference manual, rev. 1 22-12 freescale semiconductor preliminary?subject to change without notice 22.4.2.5 lcd frontplane enable register 1 (fpenr1) table 22-9. fpenr0 field descriptions field description 0:31 fp[31:0]en. frontpl ane output enable. the fp[31:0]en bits enable the frontplane driver output s. if lcden = 0, these bits have no effect on the state of the i/o pins. it is recommended to set fp[31:0]en bits before lcden is set. 1 = frontplane driver output enabled on fp[31:0]. 0 = frontplane driver output disabled on fp[31:0]. 0x14 access: user read/write 01234567 r fp63en fp62en fp61en fp60en fp59en fp58en fp57en fp56en w reset00000000 8 9 10 11 12 13 14 15 r fp55en fp54en fp53en fp52en fp51en fp50en fp49en fp48en w reset00000000 16 17 18 19 20 21 22 23 r fp47en fp46en fp45en fp44en fp43en fp42en fp41en fp40en w reset00000000 24 25 26 27 28 29 30 31 r fp39en fp38en fp37en fp36en fp35en fp34en fp33en fp32en w reset00000000 = unimplemented figure 22-6. lcd frontplane enable register 1 (fpenr1)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-13 preliminary?subject to change without notice 22.4.2.6 lcdram (location 0) table 22-10. fpenr1 field descriptions field description 0:31 fp[63:32]en. frontplane output enable. the fp[63:32]en bits enable the frontplane driver outp uts. if lcden = 0, these bi ts have no effect on the state of the i/o pins. it is recommended to set fp[63:32]en bits before lcden is set. 1 = frontplane driver output enabled on fp[63:32]. 0 = frontplane driver output disabled on fp[63:32]. note: the implemented fp[ n -1]en bits depend on the number of implemented frontplanes. 0x20 access: user read/write 01234567 r 0 0 fp0bp5 fp0bp4 fp0bp3 fp0bp2 fp0bp1 fp0bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp1bp5 fp1bp4 fp1bp3 fp1bp2 fp1bp1 fp1bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp2bp5 fp2bp4 fp2bp3 fp2bp2 fp2bp1 fp2bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp3bp5 fp3bp4 fp3bp3 fp3bp2 fp3bp1 fp3bp0 w reset00000000 = unimplemented figure 22-7. lcdram (location 0)
pxd10 microcontroller reference manual, rev. 1 22-14 freescale semiconductor preliminary?subject to change without notice 22.4.2.7 lcdram (location 1) table 22-11. lcdram (location 0) field descriptions field description 0:31 fp[0:3]bp[5:0]. lcd segment on. the fp[0:3]bp[5:0] bit displays (turns on) the lcd segment connected between fp[0:3] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x24 access: user read/write 01234567 r 0 0 fp4bp5 fp4bp4 fp4bp3 fp4bp2 fp4bp1 fp4bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp5bp5 fp5bp4 fp5bp3 fp5bp2 fp5bp1 fp5bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp6bp5 fp6bp4 fp6bp3 fp6bp2 fp6bp1 fp6bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp7bp5 fp7bp4 fp7bp3 fp7bp2 fp7bp1 fp7bp0 w reset00000000 = unimplemented figure 22-8. lcdram (location 1)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-15 preliminary?subject to change without notice 22.4.2.8 lcdram (location 2) table 22-12. lcdram (location 1) field descriptions field description 0:31 fp[4:7]bp[5:0]. lcd segment on. the fp[4:7]bp[5:0] bit displays (turns on) the lcd segment connected between fp[4:7] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x28 access: user read/write 01234567 r 0 0 fp8bp5 fp8bp4 fp8bp3 fp8bp2 fp8bp1 fp8bp0- w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp9bp5 fp9bp4 fp9bp3 fp9bp2 fp9bp1 fp9bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp10bp5 fp10bp4 fp10bp3 fp10bp2 fp10bp1 fp10bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp11bp5 fp11bp4 fp11bp3 fp11bp2 fp11bp1 fp11bp0 w reset00000000 = unimplemented figure 22-9. lcdram (location 2)
pxd10 microcontroller reference manual, rev. 1 22-16 freescale semiconductor preliminary?subject to change without notice 22.4.2.9 lcdram (location 3) table 22-13. lcdram (location 2) field descriptions field description 0:31 fp[8:11]bp[5:0]. lcd segment on. the fp[8:11]bp[5:0] bit displays (t urns on) the lcd segment connec ted between fp[8:11] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x2c access: user read/write 01234567 r 0 0 fp12bp5 fp12bp4 fp12bp3 fp12bp2 fp12bp1 fp12bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp13bp5 fp13bp4 fp13bp3 fp13bp2 fp13bp1 fp13bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp14bp5 fp14bp4 fp14bp3 fp14bp2 fp14bp1 fp14bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp15bp5 fp15bp4 fp15bp3 fp15bp2 fp15bp1 fp15bp0 w reset00000000 = unimplemented figure 22-10. lcdram (location 3)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-17 preliminary?subject to change without notice 22.4.2.10 lcdram (location 4) table 22-14. lcdram (location 3) field descriptions field description 0:31 fp[12:15]bp[5:0]. lcd segment on. the fp[12:15]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[12:15] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x30 access: user read/write 01234567 r 0 0 fp16bp5 fp16bp4 fp16bp3 fp16bp2 fp16bp1 fp16bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp17bp5 fp17bp4 fp17bp3 fp17bp2 fp17bp1 fp17bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp18bp5 fp18bp4 fp18bp3 fp18bp2 fp18bp1 fp18bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp19bp5 fp19bp4 fp19bp3 fp19bp2 fp19bp1 fp19bp0 w reset00000000 = unimplemented figure 22-11. lcdram (location 4)
pxd10 microcontroller reference manual, rev. 1 22-18 freescale semiconductor preliminary?subject to change without notice 22.4.2.11 lcdram (location 5) table 22-15. lcdram (location 4) field descriptions field description 0:31 fp[16:19]bp[5:0]. lcd segment on. the fp[16:19]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[16:19] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x34 access: user read/write 01234567 r 0 0 fp20bp5 fp20bp4 fp20bp3 fp20bp2 fp20bp1 fp20bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp21bp5 fp21bp4 fp21bp3 fp21bp2 fp21bp1 fp21bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp22bp5 fp22bp4 fp22bp3 fp22bp2 fp22bp1 fp22bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp23bp5 fp23bp4 fp23bp3 fp23bp2 fp23bp1 fp23bp0 w reset00000000 = unimplemented figure 22-12. lcdram (location 5)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-19 preliminary?subject to change without notice 22.4.2.12 lcdram (location 6) table 22-16. lcdram (location 5) field descriptions field description 0:31 fp[20:23]bp[5:0]. lcd segment on. the fp[20:23]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[20:23] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x38 access: user read/write 01234567 r 0 0 fp24bp5 fp24bp4 fp24bp3 fp24bp2 fp24bp1 fp24bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp25bp5 fp25bp4 fp25bp3 fp25bp2 fp25bp1 fp25bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp26bp5 fp26bp4 fp26bp3 fp26bp2 fp26bp1 fp26bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp27bp5 fp27bp4 fp27bp3 fp27bp2 fp27bp1 fp27bp0 w reset00000000 = unimplemented figure 22-13. lcdram (location 6)
pxd10 microcontroller reference manual, rev. 1 22-20 freescale semiconductor preliminary?subject to change without notice 22.4.2.13 lcdram (location 7) table 22-17. lcdram (location 6) field descriptions field description 0:31 fp[24:27]bp[5:0]. lcd segment on. the fp[24:27]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[24:27] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x3c access: user read/write 01234567 r 0 0 fp28bp5 fp28bp4 fp28bp3 fp28bp2 fp28bp1 fp28bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp29bp5 fp29bp4 fp29bp3 fp29bp2 fp29bp1 fp29bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp30bp5 fp30bp4 fp30bp3 fp30bp2 fp30bp1 fp30bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp31bp5 fp31bp4 fp31bp3 fp31bp2 fp31bp1 fp31bp0 w reset00000000 = unimplemented figure 22-14. lcdram (location 7)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-21 preliminary?subject to change without notice 22.4.2.14 lcdram (location 8) table 22-18. lcdram (location 7) field descriptions field description 0:31 fp[28:31]bp[5:0]. lcd segment on. the fp[28:31]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[28:31] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x40 access: user read/write 01234567 r 0 0 fp32bp5 fp32bp4 fp32bp3 fp32bp2 fp32bp1 fp32bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp33bp5 fp33bp4 fp33bp3 fp33bp2 fp33bp1 fp33bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp34bp5 fp34bp4 fp34bp3 fp34bp2 fp34bp1 fp34bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp35bp5 fp35bp4 fp35bp3 fp35bp2 fp35bp1 fp35bp0 w reset00000000 = unimplemented figure 22-15. lcdram (location 8)
pxd10 microcontroller reference manual, rev. 1 22-22 freescale semiconductor preliminary?subject to change without notice 22.4.2.15 lcdram (location 9) table 22-19. lcdram (location 8) field descriptions field description 0:31 fp[32:35]bp[5:0]. lcd segment on. the fp[32:35]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[32:35] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x44 access: user read/write 01234567 r 0 0 fp36bp5 fp36bp4 fp36bp3 fp36bp2 fp36bp1 fp36bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp37bp5 fp37bp4 fp37bp3 fp37bp2 fp37bp1 fp37bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp38bp5 fp38bp4 fp38bp3 fp38bp2 fp38bp1 fp38bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp39bp5 fp39bp4 fp39bp3 fp39bp2 fp39bp1 fp39bp0 w reset00000000 = unimplemented figure 22-16. lcdram (location 9)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-23 preliminary?subject to change without notice 22.4.2.16 lcdram (location 10) table 22-20. lcdram (location 9) field descriptions field description 0:31 fp[36:39]bp[5:0]. lcd segment on. the fp[36:39]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[36:39] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x48 access: user read/write 01234567 r 0 0 fp40bp5 fp40bp4 fp40bp3 fp40bp2 fp40bp1 fp40bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp41bp5 fp41bp4 fp41bp3 fp41bp2 fp41bp1 fp41bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp42bp5 fp42bp4 fp42bp3 fp42bp2 fp42bp1 fp42bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp43bp5 fp43bp4 fp43bp3 fp43bp2 fp43bp1 fp43bp0 w reset00000000 = unimplemented figure 22-17. lcdram (location 10)
pxd10 microcontroller reference manual, rev. 1 22-24 freescale semiconductor preliminary?subject to change without notice 22.4.2.17 lcdram (location 11) table 22-21. lcdram (location 10) field descriptions field description 0:31 fp[40:43]bp[5:0]. lcd segment on. the fp[40:43]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[40:43] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x4c access: user read/write 01234567 r 0 0 fp44bp5 fp44bp4 fp44bp3 fp44bp2 fp44bp1 fp44bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp45bp5 fp45bp4 fp45bp3 fp45bp2 fp45bp1 fp45bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp46bp5 fp46bp4 fp46bp3 fp46bp2 fp46bp1 fp46bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp47bp5 fp47bp4 fp47bp3 fp47bp2 fp47bp1 fp47bp0 w reset00000000 = unimplemented figure 22-18. lcdram (location 11)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-25 preliminary?subject to change without notice 22.4.2.18 lcdram (location 12) table 22-22. lcdram (location 11) field descriptions field description 0:31 fp[44:47]bp[5:0]. lcd segment on. the fp[44:47]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[44:47] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x50 access: user read/write 01234567 r 0 0 fp48bp5 fp48bp4 fp48bp3 fp48bp2 fp48bp1 fp48bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp49bp5 fp49bp4 fp49bp3 fp49bp2 fp49bp1 fp49bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp50bp5 fp50bp4 fp50bp3 fp50bp2 fp50bp1 fp50bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp51bp5 fp51bp4 fp51bp3 fp51bp2 fp51bp1 fp51bp0 w reset00000000 = unimplemented figure 22-19. lcdram (location 12)
pxd10 microcontroller reference manual, rev. 1 22-26 freescale semiconductor preliminary?subject to change without notice 22.4.2.19 lcdram (location 13) table 22-23. lcdram (location 12) field descriptions field description 0:31 fp[48:51]bp[5:0]. lcd segment on. the fp[48:51]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[48:51] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x54 access: user read/write 01234567 r 0 0 fp52bp5 fp52bp4 fp52bp3 fp52bp2 fp52bp1 fp52bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp53bp5 fp53bp4 fp53bp3 fp53bp2 fp53bp1 fp53bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp54bp5 fp54bp4 fp54bp3 fp54bp2 fp54bp1 fp54bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp55bp5 fp55bp4 fp55bp3 fp55bp2 fp55bp1 fp55bp0 w reset00000000 = unimplemented figure 22-20. lcdram (location 13)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-27 preliminary?subject to change without notice 22.4.2.20 lcdram (location 14) table 22-24. lcdram (location 13) field descriptions field description 0:31 fp[52:55]bp[5:0]. lcd segment on. the fp[52:55]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[52:55] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x58 access: user read/write 01234567 r 0 0 fp56bp5 fp56bp4 fp56bp3 fp56bp2 fp56bp1 fp56bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp57bp5 fp57bp4 fp57bp3 fp57bp2 fp57bp1 fp57bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp58bp5 fp58bp4 fp58bp3 fp58bp2 fp58bp1 fp58bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp59bp5 fp59bp4 fp59bp3 fp59bp2 fp59bp1 fp59bp0 w reset00000000 = unimplemented figure 22-21. lcdram (location 14)
pxd10 microcontroller reference manual, rev. 1 22-28 freescale semiconductor preliminary?subject to change without notice 22.4.2.21 lcdram (location 15) table 22-25. lcdram (location 14) field descriptions field description 0:31 fp[56:59]bp[5:0]. lcd segment on. the fp[56:59]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[56:59] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. 0x5c access: user read/write 01234567 r 0 0 fp60bp5 fp60bp4 fp60bp3 fp60bp2 fp60bp1 fp60bp0 w reset00000000 8 9 10 11 12 13 14 15 r 0 0 fp61bp5 fp61bp4 fp61bp3 fp61bp2 fp61bp1 fp61bp0 w reset00000000 16 17 18 19 20 21 22 23 r 0 0 fp62bp5 fp62bp4 fp62bp3 fp62bp2 fp62bp1 fp62bp0 w reset00000000 24 25 26 27 28 29 30 31 r 0 0 fp63bp5 fp63bp4 fp63bp3 fp63bp2 fp63bp1 fp63bp0 w reset00000000 = unimplemented figure 22-22. lcdram (location 15)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-29 preliminary?subject to change without notice 22.5 functional description 22.5.1 frontplane, backplane, and lcd system during reset during a reset the following conditions exist: ? all frontplane enable bits, fp[ n -1:0]en are cleared and the on/off control for the display, the lcden bit is cleared, thereby fo rcing all frontplane and backpl ane driver outputs to the high impedance state. the pin state during re set is defined by the port control module. ? the lcd64f6b system is configured in the de fault mode, 1/1 duty and 1/ 1 bias, that means only bp0 is used, system clock as reference, vlcd pin not used as voltage reference. 22.5.2 lcd clock and frame frequency the frequency of the clock and the clock divider determine the lcd cloc k frequency. the input clock for the prescaler can be selected by lcdrcs bit. the di vider is set by the lcd cloc k prescaler bits, in the lcd prescaler control register according to table 22-27 . table 22-26. lcdram (location 15) field descriptions field description 0:31 fp[60:63]bp[5:0]. lcd segment on. the fp[60:63]bp[5:0] bit displays (turns on) the lcd segment connec ted between fp[60:63] and bp[5:0]. 1 = lcd segment on 0 = lcd segment off. table 22-27. clock divider lclk divider 0000 480 0001 2 * 480 0010 2 2 * 480 0011 2 3 * 480 0100 2 4 * 480 0101 2 5 * 480 0110 2 6 * 480 0111 2 7 * 480 1000 2 8 * 480 1001 2 9 * 480 1010 2 10 * 480 1011 2 11 * 480 1100 2 12 * 480
pxd10 microcontroller reference manual, rev. 1 22-30 freescale semiconductor preliminary?subject to change without notice the following formula may be used to calculate the lcd frame frequency: eqn. 22-1 example: clock = 16 mhz, prescaler = 1010; eqn. 22-2 note a ?frame? is the full refresh cycle of the display. see section 22.6, lcd waveform examples ,? for waveform illustrations. 22.5.3 contrast adjustment the lcd driver module offers two di fferent ways to adjust contrast: 22.5.3.1 adjusting the supply voltage (vlcd) the vlcd voltage can directly be used as reference and source to drive the lcd segments. the contrast could be easily adjusted by altering the voltage at the vlcd pin. 22.5.3.2 adding contrast adjustment phases another way to adjust the contrast is to add another phase to the refr esh cycle which keeps the voltage the same on all frontplane a nd backplane electrodes (v ss in this case). this will contribute towards lowering the v onrms and v offrms voltages over the segment. for this reas on, the whole frame is divided into steps. the value from the c ontrast control register (lcc) determines how many of these steps are taken by the contrast phase. whenev er the length of the contra st adjustment phase is ch anged, the length of the other phases is automatically changed to ensure the frame length remains the same. example: a value of 256 in the contrast control (lcc ) register will force th e contrast phase to take approximately a 256/2047 of the length of the whole frame. 1101 2 13 * 480 1110 2 14 * 480 1111 2 15 * 480 table 22-27. clock divider (continued) lclk divider lcd frame frequency (hz) oscclk hz ?? divider ------------------------------------- - = 16 10 6 ? 2 10 480 ? ---------------------- 33 hz ?
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-31 preliminary?subject to change without notice figure 22-23 shows an example of waveform with 1/1 duty and 1/1 bias ratios with the additional contrast adjustment phases figure 22-23. contrast adjustment phases note rms stands for root mean square a nd is a statistical measure of the magnitude of a varying quantity. it is calculated with the formula: eqn. 22-3 22.5.4 lcd ram for a segment on the lcd to be displayed, data must be written to the lcd ram which is shown in section 22.4, memory map and register definition .? the bits in the lcd ram correspond to the segments that are driven by the fr ontplane and backplane drivers. writi ng a ?1? to a given location will result in the corresponding display segment being dr iven with a differential rms voltage, based on selected reference, necessary to turn the segment on when the lc den bit is set and the corresponding fp[ n -1:0]en bit is set. writing a ?0? to a given loca tion will result in the corresponding display segment being driven with a differential rms voltage necessary to turn the segment off. the lcd ram is a dual port ram that interfaces with the inte rnal address and data buses of the mcu. it is possible to read from lcd ram locations for scrolling pur poses. writing or reading of the lcden bit does not change the contents of the lcd ram. after a reset, the lcd ram contents will be cleared. 22.5.5 lcd driver system enable and frontplane enable sequencing if lcden = 0 (lcd driver system disabl ed) and the frontplane enable bit, fp[ n -1:0]en, is set, the frontplane driver waveform will not appear on the out put until lcden is set. if lcden = 1 (lcd driver system enabled), the frontplane dr iver waveform will appear on th e output as soon as the corresponding frontplane enable bit, fp[ n -1:0]en, in the registers fpenr0 and fpenr1 is set. bp0 fpx (xxx0) fpy (xxx1) 1 frame = contrast adjustment phase bp0 fpx (xxx0) fpy (xxx1) 1 frame v rms v 2 t d 0 t ? t -------------- - =
pxd10 microcontroller reference manual, rev. 1 22-32 freescale semiconductor preliminary?subject to change without notice 22.5.6 lcd driver backplane remapping the backplane and frontplane pins can be re mapped/swapped using lcdbps and lcdbpa. while lcdbpa adds the non available backplane waveforms onto fp pi ns, lcdbps does a swapping of backplanes waveforms with frontpl anes waveforms on selected pins. the swapping of lcdbps depends on the availability of frontplane pi ns fp[n-1:0]. if the number of frontplanes n implemented is not sufficient no remapping will occur. see table 22-28 for details. examples: 1. 40 (n=40) frontplanes and 4 (m=4) backplanes are implemented. lcdbps is set to 000 and lcdbpa is set to 1 frontplanes fp[39:2] and bp[3:0] will stay the same, but fp[1:0] pins will controlled by bp[5:4] functionality. 2. 40 (n=40) frontplanes and 4 (m=4) backplanes are implemented. lcdbps is set to 010 and lcdbpa is set to 0 frontplanes fp[39:16] and fp[11:0] will stay th e same, but fp[15:12] pi ns are swapped with bp[3:0]. 3. 40 (n=40) frontplanes and 4 (m=4) backplanes are implemented. lcdbps is set to 010 and lcdbpa is set to 1 frontplanes fp[39:18] and fp[11:0] will stay the same. fp[15:12] pins are swapped with bp[3:0]. fp[17:16] is replaced by bp[5:4] functionality. 4. 40 (n=40) frontplanes and 4 (m=4) backplanes are implemented. lcdbps is set to 101 and lcdbpa is set to 1 table 22-28. backplane remapping lcdbps condition: fp[n-1:0] remapping lcdbpa=0 bp[m-1:0] remapping lcdbpa=1 bp[m-1:0] 000 no remapping fp[5-m:0] <- bp[5:m] if m=6 no remapping 001 bp[m-1:0] <- fp[m-1+4:4] fp[m-1+4:4] <- bp[m-1:0] bp[m-1:0] <- fp[m-1+4:4] fp[5+4:4] <- bp[5:0] 010 bp[m-1:0] <- fp[m-1+12:12] fp[m-1+12:12] <- bp[m-1:0] bp[m-1:0] <- fp[m-1+12:12] fp[5+12:12] <- bp[5:0] 011 bp[m-1:0] <- fp[m-1+20:20] fp[m-1+20:20] <- bp[m-1:0] bp[m-1:0] <- fp[m-1+20:20] fp[5+20:20] <- bp[5:0] 100 n=36 or n>36 bp[m-1:0] <- fp[m-1+28:28] fp[m-1+28:28] <- bp[m-1:0] bp[m-1:0] <- fp[m-1+28:28] fp[5+28:28] <- bp[5:0] 101 n=44 or n>44 bp[m-1:0] <- fp[m-1+36:36] fp[m-1+36:36] <- bp[m-1:0] bp[m-1:0] <- fp[m-1+36:36] fp[5+36:36] <- bp[5:0] 110 n=52 or n>52 bp[m-1:0] <- fp[m-1+44:44] fp[m-1+44:44] <- bp[m-1:0] bp[m-1:0] <- fp[m-1+44:44] fp[5+44:44] <- bp[5:0] 111 n=60 or n>60 bp[m-1:0] <- fp[m-1+52:52] fp[m-1+52:52] <- bp[m-1:0] bp[m-1:0] <- fp[m-1+52:52] fp[5+52:52] <- bp[5:0]
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-33 preliminary?subject to change without notice no remapping: frontplan es fp[39:0] and bp[3:0] will stay the same, be cause condition n>=44 is not fulfilled. 22.5.7 lcd bias and modes of operation the lcd64f6b driver has seven modes of operation: ? 1/1 duty (1 backplane), 1/1 bias (2 voltage levels) ? 1/2 duty (2 backplanes), 1/2 bias (3 voltage levels) ? 1/2 duty (2 backplanes), 1/3 bias (4 voltage levels) ? 1/3 duty (3 backplanes), 1/3 bias (4 voltage levels) ? 1/4 duty (4 backplanes), 1/3 bias (4 voltage levels) ? 1/5 duty (5 backplanes), 1/3 bias (4 voltage levels) ? 1/6 duty (6 backplanes), 1/3 bias (4 voltage levels) the voltage levels required for the different operating modes are genera ted internally based on selected reference voltage. if vlcd as reference selected, changing vlcd alters the differential rms voltage across the segments in the on and off st ates, thereby setting the display contrast. the backplane waveforms are continuous and repetitive every frame. they are fixed within each operating mode and are not affected by the data in the lcd ram. the frontplane waveforms generated are dependent on the state (on or off) of the lcd segments as defined in the lcd ram. the lcd driver hardware uses the data in the lcd ram to construct the frontplane waveform to create a differential rms voltage necessary to turn the segment on or off. the lcd duty is decided by the duty bits in the lcd control register (lcdcr). the number of bias voltage levels is determined by the bias bit in the lcdcr. table 22-29 summarizes the multiplex modes (duties) and the bias voltage levels that can be selected for each multiplex mode (duty). the backplane pins have their corresponding back plane waveform output bp[ m -1:0] in high impedance state when in the off state as indicated in table 22-29 . in the off state th e corresponding pins bp[ m -1:0]can be used for other functionality. table 22-29. lcd duty and bias duty lcdcr register backplanes bias level duty bp5 bp4 bp3 bp2 bp1 bp0 bias=0 bias=1 1/1 000 off on 1/1 1/2 001 off on 1/2 1/3 1/3 010 off on 1/3 1/4 011 off on 1/3 1/5 100 off on 1/3 1/6 101 on 1/3 1/6 110 on 1/3 1/6 111 on 1/3
pxd10 microcontroller reference manual, rev. 1 22-34 freescale semiconductor preliminary?subject to change without notice 22.5.8 operation in power saving modes 22.5.8.1 operation in stop mode the lcd64f6b system opera tion during stop mode is controlled by the lcdrst bit in the lcd control register (lcdcr). if the lcd64f6b is requested to enter stop mode and lcdrst is cleared wh ile lcden is set the lcd waveform generation clocks are st opped and the lcd64f6b drivers pull down to ground those frontplane and backplane pins that we re enabled before entering stop mode.t he contents of the lcd ram and the lcd registers retain the values th ey had prior to entering stop mode. if lcdrst is set while lcden is set and the lcd 64f6b is requested to enter stop mode the lcd waveform generation is continued. 22.5.8.2 operation in standby mode see device guide for information if the lcd64f6b is powered down or stays powered in standby mode. the lcd64f6b system operat ion during standby mode is controlled by th e lcdrst bit in the lcd control register (lcdcr). if the lcd64f6b is powered down by the system , those frontplane and backplane pins goes high impedance, that were enabled before entering standby mode. if the lcd64f6b is not powered down by the system , and is requested to enter standby mode and lcdrst is cleared while lcden is set the lcd waveform generation cloc ks are stopped and the lcd64f6b drivers pull down to ground those frontplane and backplane pi ns that were enabled before entering standby mode.the contents of the lcd ra m and the lcd registers retain the values they had prior to entering standby mode. if the lcd64f6b is not powered down by the system , and is requested to enter standby mode and lcdrst is set while lcden is set the lcd waveform genera tion is continued. note the user needs to take care that the system keeps the clock applied to the running lcd64f6b module during all modes where it is enabled. if no clock is applied while the lcd64f6b module is running the lcd could be damaged. 22.5.9 other power saving the lcd64f6b has features to ad just the frontplane & backplane drive strength and to boost the drive strength while the planes are switching.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-35 preliminary?subject to change without notice 22.5.9.1 lcd reference clock select using lcdrcs the lcd reference clock can be select ed. if lcdrcs is cleared, the system clock is applied as reference clock to the prescaler input. if lcdrcs is set, the source clock for lcd driver system (prescaler input) is osc clock. see device level document ation for detail on osc clk. selecting the lower power consuming clock of both as refere nce clock for the prescaler input can save power consumption. 22.5.9.2 boost at switching since the lcd appears like a capacitance to the driver it is sometimes useful to boost the output current during transitions to increase the sl ew rate of the driver. if boosting is enabled, the drive strength capability is increased a little ahead in time when the planes are switching, and reduced again to normal drive after a certain time. to enable the boosting bsten need to be set. if bsten is not set, standard drive strength is used. using the bst bit if bsten is set, lcd output curr ent magnification (boost) can be selected. available is 8 times boosting, when bst is deasserted and 16 times boosting when bst is asserted. the selected boost via bst bit can be switched to be always on by setting bstao, if bsten is set. 22.5.9.3 standard drive selection the output current has a direct imp act on the power consumption and dr ive capability of the lcd64f6b module. the pwr bits select the output current height and can be used to in fluence power consumption and drive strength. table 22-30 lists the possible selections of pwr. 22.5.9.4 usage recommendation it is recommended to start with maximum output current and maximu m enabled boosting. as long as the lcd is fully functional in all environments a re duction of output current and boosting can be done. when reducing the output current (pwr), the power consumption of the lc d module and the maximum switching current of the planes is reduced. when reducing or disabling the boosti ng (bst,bsten), the output current, while planes are switching, is reduced. the user can select any combination of pwr, bst, bsten, bstao to what fit his needs best. figure 22-24 gives an overview what is the impact when taking advance of boost at switching and standard drive selection. table 22-30. output current selection (pwr) pwr current 00 standard current 01 2 * standard current 10 3 * standard current 11 4 * standard current
pxd10 microcontroller reference manual, rev. 1 22-36 freescale semiconductor preliminary?subject to change without notice figure 22-24. pwr, bst, bsten example diagram 22.5.10 interrupts this section describes all inte rrupts originated by lcd64f6b. 22.5.10.1 eof interrupt lcden must be set to enable the interrupt at end of frame feature. every ti me a frame generation was completed a counter is decremented by 1. if the count er reaches zero end of frame interrupt flag (eof) bit is set and the counter is reset to nof. the counter is reset to request interrupt at the end of every frame, as if nof would be 0x00, if lcden is asserted while the lcd is off. current at plane time plane switching 16 x boost 8 x boost boost disabled standard current with current consumed time plane switching 4 x standard 2 x standard standard current output current variation by system with and without boost boost variation 2x standard current with boost variation
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-37 preliminary?subject to change without notice the eof flag can only be cleared by writing a 1. writing a 0 has no effect. if enab led (lcdint = 1), eof causes an interrupt request . the number of frames (nof ) bits determine how many frames are count until eof flag is set. the possible number of frames are: nof= 0x00: an interrupt is request ed at the end of every frame. nof= 0x01: an interrupt is requested at the end of every second frame. nof= 0x02: an interrupt is requested at the end of every third frame. ... nof= 0xff: an interrupt is requested at the end of every 256th frame. 22.6 lcd waveform examples the following figures show the timing examples of th e lcd output waveforms fo r the available modes of operation. the contrast control is disabled in all examples (ccen = 0 in lc dccr). selected reference voltage is vlcd, but could also be vddx. 22.6.1 1/1 duty multiplexed with 1/1 bias mode duty = 1/1:duty = 000 bias = 1/1:bias = 0 or bias = 1 v 0 = v 1 = vssx v 2 = v 3 = vlcd - only bp0 is used, a maximum of 64 segments are displayed.
pxd10 microcontroller reference manual, rev. 1 22-38 freescale semiconductor preliminary?subject to change without notice figure 22-25. 1/1 duty and 1/1 bias 22.6.2 1/2 duty multiplexed with 1/2 bias mode duty = 1/2:duty = 001 bias = 1/2:bias = 0 v 0 = vssx, v 1 = vlcd * 1/3, v 2 = vlcd * 2/3, v 3 = vlcd - only bp0 and bp1 are used, a maxi mum of 128 segments are displayed. 0 0 vlcd vssx bp0 + vlcd - vlcd bp0-fpx (off) + vlcd -vlcd bp0-fpy (on) vlcd vssx fpx (xxx0) vlcd vssx fpy (xxx1) 1 frame
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-39 preliminary?subject to change without notice figure 22-26. 1/2 duty and 1/2 bias 22.6.3 1/2 duty multiplexed with 1/3 bias mode duty = 1/2:duty = 001 bias = 1/3:bias = 1 v 0 = vssx, v 1 = vlcd * 1/3, v 2 = vlcd * 2/3, v 3 = vlcd - only bp0 and bp1 are used, a maxi mum of 128 segments are displayed. 0 vlcd vssx bp0 + vlcd - vlcd bp0-fpx (off) 1 frame vlcd ?? 1/2 vlcd vssx bp1 vlcd vssx fpx (xx10) vlcd vssx fpy (xx00) vlcd vssx fpz (xx11) + vlcd ?? 1/2 - vlcd ?? 1/2 0 + vlcd - vlcd bp1-fpx (on) + vlcd ?? 1/2 - vlcd ?? 1/2 0 + vlcd - vlcd bp0-fpy (off) + vlcd ?? 1/2 - vlcd ?? 1/2 0 + vlcd - vlcd bp0-fpz (on) + vlcd ?? 1/2 - vlcd ?? 1/2 vlcd ?? 1/2 vlcd ?? 1/2 vlcd ?? 1/2 vlcd ?? 1/2
pxd10 microcontroller reference manual, rev. 1 22-40 freescale semiconductor preliminary?subject to change without notice figure 22-27. 1/2 duty and 1/3 bias 22.6.4 1/3 duty multiple xed with 1/3 bias mode duty = 1/3:duty = 010 bias = 1/3:bias = 0 or bias = 1 0 vlcd vssx bp0 + vlcd - vlcd bp0-fpx (off) 1 frame vlcd ?? 2/3 + vlcd ?? 2/3 - vlcd ?? 2/3 vlcd vssx bp1 vlcd ?? 2/3 vlcd vssx fpx (xx10) vlcd ?? 2/3 vlcd vssx fpy (xx00) vlcd ?? 2/3 vlcd vssx fpz (xx11) vlcd ?? 2/3 + vlcd ??? 1/3 - vlcd ??? 1/3 0 + vlcd - vlcd bp1-fpx (on) + vlcd ?? 2/3 - vlcd ?? 2/3 + vlcd ??? 1/3 - vlcd ??? 1/3 0 + vlcd - vlcd bp0-fpy (off) + vlcd ?? 2/3 - vlcd ?? 2/3 + vlcd ??? 1/3 - vlcd ??? 1/3 0 + vlcd - vlcd bp0-fpz (on) + vlcd ?? 2/3 - vlcd ?? 2/3 + vlcd ??? 1/3 - vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-41 preliminary?subject to change without notice v 0 = vssx, v 1 = vlcd * 1/3, v 2 = vlcd * 2/3, v 3 = vlcd - only bp0, bp1 and bp2 are used, a maximum of 192 segments are displayed. figure 22-28. 1/3 duty and 1/3 bias 22.6.5 1/4 duty multiple xed with 1/3 bias mode duty = 1/4:duty = 011 bias = 1/3:bias = 0 or bias = 1 v 0 = vssx, v 1 = vlcd * 1/3, v 2 = vlcd * 2/3, v 3 = vlcd - bp4 and bp5 are not used, a maximu m of 256 segments are displayed. 0 vlcd vssx bp0 + vlcd - vlcd bp0-fpx (off) 1 frame vlcd ?? 2/3 + vlcd ?? 2/3 - vlcd ?? 2/3 vlcd vssx bp1 vlcd ?? 2/3 vlcd vssx bp2 vlcd ?? 2/3 + vlcd ??? 1/3 - vlcd ??? 1/3 0 + vlcd - vlcd bp1-fpx (on) + vlcd ?? 2/3 - vlcd ?? 2/3 + vlcd ??? 1/3 - vlcd ??? 1/3 vlcd vssx fpx (x010) vlcd ?? 2/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3
pxd10 microcontroller reference manual, rev. 1 22-42 freescale semiconductor preliminary?subject to change without notice figure 22-29. 1/4 duty and 1/3 bias 22.6.6 1/5 duty multip lexed with 1/3 bias duty = 1/5:duty = 100 bias = 1/3:bias = 0 or bias = 1 v 0 = vssx, v 1 = vlcd * 1/3, v 2 = vlcd * 2/3, v 3 = vlcd - bp5 is not used, a maximum of 320 segments are displayed. 0 vlcd vssx bp0 + vlcd - vlcd bp0-fpx (on) 1 frame vlcd ?? 2/3 + vlcd ?? 2/3 - vlcd ?? 2/3 vlcd vssx bp1 vlcd ?? 2/3 vlcd vssx bp2 vlcd ?? 2/3 + vlcd ??? 1/3 - vlcd ??? 1/3 0 + vlcd - vlcd bp1-fpx (off) + vlcd ?? 2/3 - vlcd ?? 2/3 + vlcd ??? 1/3 - vlcd ??? 1/3 vlcd vssx fpx (1001) vlcd ?? 2/3 vlcd vssx bp3 vlcd ?? 2/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-43 preliminary?subject to change without notice figure 22-30. 1/5 duty and 1/3 bias 22.6.7 1/6 duty multiple xed with 1/3 bias mode duty = 1/5:duty = 101 bias = 1/3:bias = 0 or bias = 1 v 0 = vssx, v 1 = vlcd * 1/3, v 2 = vlcd * 2/3, v 3 = vlcd - all backplanes are used, a maxi mum of 384 segments are displayed. bp0 bp0-fpx (on) 1 frame bp1 bp2 bp1-fpx (off) fpx (10010) bp3 bp4 0 vlcd vssx + vlcd - vlcd vlcd ?? 2/3 + vlcd ?? 2/3 - vlcd ?? 2/3 vlcd vssx vlcd ?? 2/3 vlcd vssx vlcd ?? 2/3 + vlcd ??? 1/3 - vlcd ??? 1/3 0 + vlcd - vlcd + vlcd ?? 2/3 - vlcd ?? 2/3 + vlcd ??? 1/3 - vlcd ??? 1/3 vlcd vssx vlcd ?? 2/3 vlcd vssx vlcd ?? 2/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd vssx vlcd ?? 2/3 vlcd ??? 1/3
pxd10 microcontroller reference manual, rev. 1 22-44 freescale semiconductor preliminary?subject to change without notice figure 22-31. 1/6 duty and 1/3 bias 22.7 initialization information this is a step-wise example instruct ion for initializing. the initial valu es of all regist ers are the reset values. bp0 bp5-fpx (on) 1 frame bp1 bp2 bp1-fpx (off) fpx (000101) bp3 bp4 0 vlcd vssx + vlcd - vlcd vlcd ?? 2/3 + vlcd ?? 2/3 - vlcd ?? 2/3 vlcd vssx vlcd ?? 2/3 vlcd vssx vlcd ?? 2/3 + vlcd ??? 1/3 - vlcd ??? 1/3 0 + vlcd - vlcd + vlcd ?? 2/3 - vlcd ?? 2/3 + vlcd ??? 1/3 - vlcd ??? 1/3 vlcd vssx vlcd ?? 2/3 vlcd vssx vlcd ?? 2/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd ??? 1/3 vlcd vssx vlcd ?? 2/3 vlcd ??? 1/3 bp5 vlcd vssx vlcd ?? 2/3 vlcd ??? 1/3
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 22-45 preliminary?subject to change without notice figure 22-32. example initialization diagram i.e. pulls init set lcdpcr set fpenr0/1 disable all other functions on the ports which will be used for vlcd lcden = 1 access ram and lcdccr set lcdcr init lcdram and plane pins,
pxd10 microcontroller reference manual, rev. 1 22-46 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-1 preliminary?subject to change without notice chapter 23 serial controller (uart) 23.1 introduction the linflex (local interconnect network flexible) controller interfaces the lin network and supports the lin protocol versions 1.3; 2.0 and 2.1; and j2602 in both master a nd slave modes. linflex includes a lin mode that provides additiona l features (compared to standard uart) to ease lin implementation, improve system robustness, minimize cpu load and allow slave node resynchronization. this device contains two linflex modules, linfle x_0 and linflex_1. of these, only linflex_0 can be configured in slave mode. 23.2 main features 23.2.1 lin mode features ? supports lin protocol versions 1.3, 2.0, 2.1 and j2602 ? master mode with aut onomous message handling ? classic and enhanced checksum calculation and check ? single 8-byte buffer for transmission/reception ? extended frame mode for in-app lication programming (iap) purposes ? wake-up event on dominant bit detection ? true lin field state machine ? advanced lin error detection ? header, response and frame timeout ? slave mode ? autonomous header handling ? autonomous transmit/receive data handling ? lin automatic resynchronization, allowing operation with 16 mhz fast internal rc oscillator as clock source ? 16 identifier filters for autonom ous message handling in slave mode 23.2.2 uart mode features ? full duplex communication ? 8- or 9-bit with parity ? 4-byte buffer for reception, 4-byte buffer for transmission ? 8-bit counter for timeout management
pxd10 microcontroller reference manual, rev. 1 23-2 freescale semiconductor preliminary?subject to change without notice 23.2.3 features common to lin and uart ? fractional baud rate generator ? 3 operating modes for power saving and configuration registers lock: ? initialization ? normal ?sleep ? 2 test modes: ? loop back ?self test ? maskable interrupts 23.3 general description the increasing number of communicat ion peripherals embedded on microc ontrollers, for example can, lin and spi, requires more and more cpu resour ces for communication management. even a 32-bit microcontroller is overloaded if it s peripherals do not provide high-le vel features to autonomously handle the communication. even though the lin protocol with a maximum baud rate of 20 kbps is rela tively slow, it still generates a non-negligible load on the cpu if the lin is impl emented on a standard uart, as usually the case. to minimize the cpu load in master mode, li nflex handles the lin messages autonomously. in master mode, once the software has triggered the header transm ission, linflex does not request any software intervention until the next header trans mission request in transmis sion mode or until the checksum reception in reception mode. to minimize the cpu load in slave mode, li nflex requires software intervention only to: ? trigger transmission or reception or data discard depending on the identifier ? write data into the buffer (tra nsmission mode) or read data fr om the buffer (reception mode) after checksum reception if filter mode is activated for sl ave mode, linflex requires software in tervention only to write data into the buffer (transmission mode) or read data from the buffer (reception mode) the software uses the control, stat us and configuration registers to: ? configure lin parameters (for example, baud rate or mode) ? request transmissions ? handle receptions ? manage interrupts ? configure lin error and timeout detection ? process diagnostic information the message buffer stores transm itted or received lin frames.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-3 preliminary?subject to change without notice figure 23-1. lin topology network figure 23-2. linflex block diagram 23.4 fractional baud rate generation the baud rates for the receiver and transmitter are both set to the sa me value as programmed in the mantissa (linibrr) and fr action (linfbrr) registers . lin master node lin slave node 1 lin slave node n lin lin lin rx tx lin transceiver linflex controller mcu lin bus application lin protocol handler register model / application interface lin status baud rate filter configuration message slave lin control configuration message handler master message handler identifier filters (1) control status buffer interface 1. filter activation optional
pxd10 microcontroller reference manual, rev. 1 23-4 freescale semiconductor preliminary?subject to change without notice eqn. 23-1 lfdiv is an unsigned fixed point num ber. the 12-bit mantissa is code d in the linibrr and the fraction is coded in the linfbrr. the following examples show how to derive lf div from linibrr and li nfbrr register values: example 23-1. deriving lfdiv from linibrr and linfbrr register values if linibrr = 27d and linfbrr = 12d, then mantissa (lfdiv) = 27d fraction (lfdiv) = 12/16 = 0.75d therefore lfdiv = 27.75d example 23-2. programming lfdiv from linibrr and linfbrr register values to program lfdiv = 25.62d, linfbrr = 16 0.62 = 9.92, nearest real number 10d = 0xa linibrr = mantissa (25.620d) = 25d = 0x19 note the baud counters are updated with the ne w value of the baud registers after a write to linibrr. hence the baud re gister value must not be changed during a transaction. the linfbrr (cont aining the fraction bits) must be programmed before the linibrr. note lfdiv must be greater than or equal to 1.5d, i.e. linibrr = 1 and linfbrr = 8. therefore, the ma ximum possible baudrate is fperiph_set_1_clk / 24. table 23-1. error calculation for programmed baud rates baud rate f periph_set_1_clk = mhz f periph_set_1_clk = 16 mhz actual value programmed in the baud rate register % error = (calculated ? desired) baud rate / desired baud rate actual value programmed in the baud rate register % error = (calculated ? desired) baud rate / desired baud rate linibrr linfbrr linibrr linfbrr 10417 10416.7 384 0 ?0.003 10416.7 96 0 ?0.003 tx/ rx baud = f periph_set_1_clk (16 lfdiv)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-5 preliminary?subject to change without notice 23.5 operating modes linflex has three main operating mo des: initialization, no rmal and sleep. after a hardware reset, linflex is in sleep mode to reduce power consum ption. the software instructs linflex to enter initialization mode or sleep mode by setting the init bit or sleep bit in the lincr1. figure 23-3. linflex operating modes 23.5.1 initialization mode the software can be initialized while the hardware is in initialization mode. to enter this mode the software sets the init bit in the lincr1. to exit initialization mode, the software clears the init bit. while in initialization mode, all message transfers to and from the lin bus are stopped and the status of the lin bus output lintx is recessive (high). entering initialization mode does not cha nge any of the configuration registers. to initialize the linflex controller, the software sel ects the mode (lin master, lin slave or uart), sets up the baud rate register a nd, if lin slave mode with fi lter activation is selected, initializes the identifier list. 23.5.2 normal mode once initilization is complete, software clears the init bit in the lincr1 to put the hardware into normal mode. sleep initialization normal s l e e p s l e e p * i n i t reset s l e e p l i n r x d o m i n a n t s l e e p * i n i t sl eep * i n i t
pxd10 microcontroller reference manual, rev. 1 23-6 freescale semiconductor preliminary?subject to change without notice 23.5.3 low power mode (sleep) to reduce power consumption, linfle x has a low power mode called sl eep mode. to enter sleep mode, software sets the sleep bit in the lincr1. in this mode, the linflex clock is stopped. consequently, the linflex will not update the stat us bits but software can still access the linflex registers. linflex can be awakened (exit slee p mode) either by software clearing the sleep bit or on detection of lin bus activity if automatic wake-up mode is enabled (awum bit is set). on lin bus activity detection, hardware automatical ly performs the wake-up sequence by clearing the sleep bit if the awum bit in the lincr1 is set. to exit from sleep mode if the awum bit is cleared, software clears the sleep bit when a wake-up event occurs. 23.6 test modes two test modes are available to the user: loop back mode and self test mode. they can be selected by the lbkm and sftm bits in the lincr 1. these bits must be configured while linflex is in initialization mode. once one of the two test m odes has been selected, linflex mu st be started in normal mode. 23.6.1 loop back mode linflex can be put in loop back mo de by setting the lbkm bit in th e lincr. in loop back mode, the linflex treats its own transmitted messages as received messages. figure 23-4. linflex in loop back mode this mode is provided for self test functions. to be independent of external events, the lin core ignores the linrx signal. in this mode, the linflex performs an internal feedback from its tx output to its rx input. the actual value of the linrx input pin is disregarded by the linflex. the transmitted messages can be monitored on the lintx pin. 23.6.2 self test mode linflex can be put in self test mode by setting the lbkm and sft m bits in the lincr. this mode can be used for a ?hot self test?, meaning the linfle x can be tested as in loop back mode but without affecting a running lin syst em connected to the lintx and linrx pins. in this mode, the linrx pin is disconnected from the linflex and the lintx pin is held recessive. lintx linrx linflex tx rx
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-7 preliminary?subject to change without notice figure 23-5. linflex in self test mode 23.7 memory map and registers description 23.7.1 memory map the base addresses for the li nflex modules are as follows: ? 0xffe4_0000 (linflex_0) ? 0xffe4_4000 (linflex_1) table 23-2 shows the linflex memory map. table 23-2. linflex memory map offset from linflex_base register access reset value location 0x0000 lin control register 1 (lincr1) r/w see note 1 on page 9 0x0004 lin interrupt enable register (linier) r/w 0x0000_0000 on page 12 0x0008 lin status register (linsr) r/w 0x0000_0080 on page 14 0x000c lin error status register (linesr) r/w 0x0000_0000 on page 17 0x0010 uart mode control register (uartcr) r/w 0x0000_0000 on page 18 0x0014 uart mode status register (uartsr) r/w 0x0000_0000 on page 20 0x0018 lin timeout control status register (lintcsr) r/w 0x0000_0040 on page 22 0x001c lin output compare register (linocr) r/w 0x0000_ffff on page 23 0x0020 lin timeout control register (lintocr) r/w see note 2 on page 23 0x0024 lin fractional baud rate register (linfbrr) r/w 0x0000_0000 on page 24 0x0028 lin integer baud rate register (linibrr) r/w 0x0000_0000 on page 25 0x002c lin checksum field register (lincfr) r/w 0x0000_0000 on page 26 0x0030 lin control register 2 (lincr2) r/w see note 3 on page 26 0x0034 buffer identifier register (bidr) r/w 0x0000_0000 on page 28 0x0038 buffer data register lsb (bdrl) 4 r/w 0x0000_0000 on page 29 linflex lintx linrx tx rx =1
pxd10 microcontroller reference manual, rev. 1 23-8 freescale semiconductor preliminary?subject to change without notice 23.7.2 register description this section describes in address order all the linf lex registers. each descri ption includes a standard register diagram. details of regist er bit and field function follow th e register diagrams, in bit order. 0x003c buffer data register msb (bdrm) 5 r/w 0x0000_0000 on page 29 0x0040 identifier filter enable register (ifer) 6 r/w 0x0000_0000 on page 30 0x0044 identifier filter match index (ifmi) 6 r 0x0000_0000 on page 31 0x0048 identifier filter mode register (ifmr) 6 r/w 0x0000_0000 on page 32 0x004c identifier filter control register 0 (ifcr0) 6 r/w 0x0000_0000 on page 33 0x0050 identifier filter control register 1 (ifcr1) 6 r/w 0x0000_0000 on page 34 0x0054 identifier filter control register 2 (ifcr2) 6 r/w 0x0000_0000 on page 34 0x0058 identifier filter control register 3 (ifcr3) 6 r/w 0x0000_0000 on page 34 0x005c identifier filter control register 4 (ifcr4) 6 r/w 0x0000_0000 on page 34 0x0060 identifier filter control register 5 (ifcr5) 6 r/w 0x0000_0000 on page 34 0x0064 identifier filter control register 6 (ifcr6) 6 r/w 0x0000_0000 on page 34 0x0068 identifier filter control register 7 (ifcr7) 6 r/w 0x0000_0000 on page 34 0x006c identifier filter control register 8 (ifcr8) 6 r/w 0x0000_0000 on page 34 0x0070 identifier filter control register 9 (ifcr9) 6 r/w 0x0000_0000 on page 34 0x0074 identifier filter control register 10 (ifcr10) 6 r/w 0x0000_0000 on page 34 0x0078 identifier filter control register 11 (ifcr11) 6 r/w 0x0000_0000 on page 34 0x007c identifier filter c ontrol register 12 (ifcr12) 6 r/w 0x0000_0000 on page 34 0x0080 identifier filter control register 13 (ifcr13) 6 r/w 0x0000_0000 on page 34 0x0084 identifier filter control register 14 (ifcr14) 6 r/w 0x0000_0000 on page 34 0x0088 identifier filter control register 15 (ifcr15) 6 r/w 0x0000_0000 on page 34 0x008c?0x000f reserved 1 0000_0082h for linflex_0, 0000_0092h for linflex_1 2 0000_0e2ch for linflex_0, 0000_0e1ch for linflex_1 3 0006_0000h for linflex_0, 0004_0000h for linflex_1 4 lsb: least significant byte 5 msb: most significant byte 6 this register is not implemented on linflex_1. table 23-2. linflex memory map (continued) offset from linflex_base register access reset value location
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-9 preliminary?subject to change without notice figure 23-6. key to register fields note 32-bit read/write access is preferred for all linflex registers.16-bit and 8-bit access is possible for all regist ers except for bdrl and bdrm. for these registers, 16- or 8- bit access is not permitted; they must be accessed in 32-bit mode only. 23.7.2.1 lin control register 1 (lincr1) always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self- clear bit 0 n/a bit w1c bit address: base + 0x0000 ac cess: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ccd cfd lase awum mbl[0:3] bf sftm lbkm mme sbdt rblm sleep init w reset00000000100*0010 *: this field resets to 0 for linflex_0 and 1 for linflex_1. figure 23-7. lin control register 1 (lincr1) table 23-3. lincr1 field descriptions field description 0:15 reserved ccd 16 checksum calculation disable this bit disables the checksum calculation (see table 23-4 ). 0 checksum calculation is done by hardware. when this bit is 0, the lincfr is read-only. 1 checksum calculation is disabled. when this bi t is set the lincfr is read/write. user can program this register to send a software-calculated crc (provided cfd is 0). note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. cfd 17 checksum field disable this bit disables the checksum field transmission (see ta bl e 2 3 - 4 ). 0 checksum field is sent after the required number of data bytes is sent. 1 no checksum field is sent. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode.
pxd10 microcontroller reference manual, rev. 1 23-10 freescale semiconductor preliminary?subject to change without notice lase 18 lin slave automatic resynchronization enable 0 automatic resynchronization disable. 1 automatic resynchronization enable. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. awum 19 automatic wake-up mode this bit controls the behavior of the linflex hardware during sleep mode. 0 the sleep mode is exited on software request by clearing the sleep bit of the lincr. 1 the sleep mode is exited automatically by hardware on linrx dominant state detection. the sleep bit of the lincr is cleared by hardware whenever wuf bit in the linsr is set. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. mbl[0:3] 20:23 lin master break length these bits indicate the break length in master mode (see table 23-5 ). note: these bits can be written in initialization mode only. they are read-only in normal or sleep mode. bf 24 bypass filter 0 no interrupt if identifier does not match any filter. 1 an rx interrupt is generated on identifier not matching any filter. note: ? if no filter is activated, this bit is reserved. ? this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sftm 25 self test mode this bit controls the self te st mode. for more details, see section 23.6.2, self test mode. 0 self test mode disable. 1 self test mode enable. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. lbkm 26 loop back mode this bit controls the loop back mode. for more details see section 23.6.1, loop back mode. 0 loop back mode disable. 1 loop back mode enable. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode mme 27 master mode enable 0 slave mode enable. 1 master mode enable. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. sbdt 28 slave mode break detection threshold 0 11-bit break. 1 10-bit break. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. rblm 29 receive buffer locked mode 0 receive buffer not locked on overrun. once the slave receive buffer is full the next incoming message overwrites the previous one. 1 receive buffer locked against overrun. once the receive buffer is full the next incoming message is discarded. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. table 23-3. lincr1 field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-11 preliminary?subject to change without notice sleep 30 sleep mode request this bit is set by software to request linflex to enter sleep mode. this bit is cleared by software to exit sleep mode or by hardware if the awum bit in lincr1 and the wuf bit in linsr are set (see ta b l e 2 3 - 6 ). init 31 initialization request the software sets this bit to switch hardware into initializati on mode. if the sleep bit is reset, linflex enters normal mode when clearing the init bit (see table 23-6 ). table 23-4. checksum bits configuration cfd ccd lincfr checksum sent 1 1 read/write none 1 0 read-only none 0 1 read/write programmed in lincfr by bits cf[0:7] 0 0 read-only hardware calculated table 23-5. lin master break length selection mbl[0:3] length 0000 10-bit 0001 11-bit 0010 12-bit 0011 13-bit 0100 14-bit 0101 15-bit 0110 16-bit 0111 17-bit 1000 18-bit 1001 19-bit 1010 20-bit 1011 21-bit 1100 22-bit 1101 23-bit 1110 36-bit 1111 50-bit table 23-3. lincr1 field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 23-12 freescale semiconductor preliminary?subject to change without notice 23.7.2.2 lin interrupt enable register (linier) table 23-6. operating mode selection sleep init operating mode 1 0 sleep (reset value) x 1 initialization 00normal address: base + 0x0004 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szie ocie beie ceie heie 00 feie boie lsie wuie dbfie dbeie drie dtie hrie w reset0000000000000000 figure 23-8. lin interrupt enable register (linier) table 23-7. linier field descriptions field description 0:15 reserved szie 16 stuck at zero interrupt enable 0 no interrupt when szf bit in linesr or uartsr is set. 1 interrupt generated when szf bit in linesr or uartsr is set. ocie 17 output compare interrupt enable 0 no interrupt when ocf bit in linesr or uartsr is set. 1 interrupt generated when ocf bit in linesr or uartsr is set. beie 18 bit error interrupt enable 0 no interrupt when bef bit in linesr is set. 1 interrupt generated when bef bit in linesr is set. ceie 19 checksum error interrupt enable 0 no interrupt on checksum error. 1 interrupt generated when checksum error flag (cef) in linesr is set. heie 20 header error interrupt enable 0 no interrupt on break delimiter error, synch field error, identifier field error. 1 interrupt generated on break delimiter error, synch field error, identifier field error. 21:22 reserved
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-13 preliminary?subject to change without notice feie 23 framing error interrupt enable 0 no interrupt on framing error. 1 interrupt generated on framing error. boie 24 buffer overrun interrupt enable 0 no interrupt on buffer overrun. 1 interrupt generated on buffer overrun. lsie 25 lin state interrupt enable 0 no interrupt on lin state change. 1 interrupt generated on lin state change. this interrupt can be used for debugging purposes. it has no status flag but is reset when writing ?1111? into lins[0:3] in the linsr. wuie 26 wake-up interrupt enable 0 no interrupt when wuf bit in linsr or uartsr is set. 1 interrupt generated when wuf bit in linsr or uartsr is set. dbfie 27 data buffer full interrupt enable 0 no interrupt when buffer data register is full. 1 interrupt generated when dat a buffer register is full. dbeie 28 data buffer empty interrupt enable 0 no interrupt when buffer data register is empty. 1 interrupt generated when data buffer register is empty. drie 29 data reception complete interrupt enable 0 no interrupt when data reception is completed. 1 interrupt generated when data received fl ag (drf) in linsr or uartsr is set. dtie 30 data transmitted interrupt enable 0 no interrupt when data transmission is completed. 1 interrupt generated when dat a transmitted flag (dtf) is set in linsr or uartsr. hrie 31 header received interrupt enable 0 no interrupt when a valid lin header has been received. 1 interrupt generated when a valid lin header has be en received, that is, hrf bit in linsr is set. table 23-7. linier field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 23-14 freescale semiconductor preliminary?subject to change without notice 23.7.2.3 lin status register (linsr) t address: base + 0x0008 a ccess: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r lins[0:3] 00rmb0 rbsy rps wuf dbff dbef drf dtf hrf w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000001000000 figure 23-9. lin status register (linsr) table 23-8. linsr field descriptions field description 0:15 reserved
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-15 preliminary?subject to change without notice lins[0:3] 16:19 lin modes / normal mode states 0000: sleep mode linflex is in sleep mode to save power consumption. 0001: initialization mode linflex is in initialization mode. normal mode states 0010: idle this state is entered on several events: ? sleep bit and init bit in lincr1 have been cleared by software, ? a falling edge has been received on rx pin and awum bit is set, ? the previous frame reception or transmission has been completed or aborted. 0011: break in slave mode, a falling edge followed by a dominant state has been detected. receiving break. note: in slave mode, in case of error new lin state can be either idle or break depending on last bit state. if last bit is dominant ne w lin state is break, otherwise idle. in master mode, break transmission ongoing. 0100: break delimiter in slave mode, a valid break has been detected. refer to section 23.7.2.1, li n control register 1 (lincr1) for break length configuration (10-bit or 11-bit). waiting for a rising edge. in master mode, break transmission has been completed. break delimiter transmission is ongoing. 0101: synch field in slave mode, a valid break delimiter has been detected (recessive state for at least one bit time). receiving synch field. in master mode, synch field transmission is ongoing. 0110: identifier field in slave mode, a valid synch field has been received. receiving identifier field. in master mode, identifier transmission is ongoing. 0111: header reception/transmission completed in slave mode, a valid header has been received and identifier field is available in the bidr. in master mode, header transmission is completed. 1000: data reception/transmission response reception/transmission is ongoing. 1001: checksum data reception/transmission completed. checksum reception/transmission ongoing. in uart mode, only the following stat es are flagged by the lin state bits: ?init ? sleep ?idle ? data transmission/reception 20:21 reserved rmb 22 release message buffer 0 buffer is free. 1 buffer ready to be read by software. this bit must be cleared by software after reading data received in the buffer. this bit is cleared by hardware in initialization mode. 23 reserved table 23-8. linsr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 23-16 freescale semiconductor preliminary?subject to change without notice rbsy 24 receiver busy flag 0 receiver is idle 1 reception ongoing note: in slave mode, after header reception, if dir bi t in bidr is reset and reception starts then this bit is set. in this case, us er cannot set dtrq bit in lincr2. rps 25 lin receive pin state this bit reflects the current status of linrx pin for diagnostic purposes. wuf 26 wake-up flag this bit is set by hardware and indicates to the software that linflex has detected a falling edge on the linrx pin when: ? slave is in sleep mode ? master is in sleep mode or idle state this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt is generated if wuie bit in linier is set. dbff 27 data buffer full flag this bit is set by hardware and indicates the buffer is full. it is set only when receiving extended frames (dfl > 7). this bit must be cleared by software. it is reset by hardware in initialization mode. dbef 28 data buffer empty flag this bit is set by hardware and indicates the buffer is empty. it is set only when transmitting extended frames (dfl > 7). this bit must be cleared by software, once buffer has been filled again, in order to start transmission. this bit is reset by hardwa re in initialization mode. drf 29 data reception completed flag this bit is set by hardware and indi cates the data reception is completed. this bit must be cleared by software. it is reset by hardware in initialization mode. note: this flag is not set in case of bit error or framing error. dtf 30 data transmission completed flag this bit is set by hardware and indicates the data transmission is completed. this bit must be cleared by software. it is reset by hardware in initialization mode. note: this flag is not set in case of bit error if iobe bit is reset. hrf 31 header reception flag this bit is set by hardware and indicates a valid header reception is completed. this bit must be cleared by software. this bit is reset by hardware in initialization mode and at end of completed or aborted frame. note: if filters are enabled, this bit is set only when identifier software filter ing is required, that is to say: ? all filters are inactive and bf bit in lincr1 is set ? no match in any filter and bf bit in lincr1 is set ? tx filter match table 23-8. linsr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-17 preliminary?subject to change without notice 23.7.2.4 lin error status register (linesr) address: base + 0x000c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szf ocf bef cef sfef bdef idpef fef bof 0 0 0 000nf w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 23-10. lin error status register (linesr) table 23-9. linesr field descriptions field description 0:15 reserved szf 16 stuck at zero flag this bit is set by hardware when the bus is domina nt for more than a 100-bit time. if the dominant state continues, szf flag is set again afte r 87-bit time. it is cleared by software. ocf 17 output compare flag 0 no output compare event occurred 1 the content of the counter has matched the content of oc1[0:7] or oc2[0:7] in linocr. if this bit is set and iot bit in lintcsr is set, linflex moves to idle state. if ltom bit in lintcsr is set, then ocf is cleare d by hardware in initialization mode. if ltom bit is cleared, then ocf maintains its status whatever the mode is. bef 18 bit error flag this bit is set by hardware and indicates to the so ftware that linflex has detected a bit error. this error can occur during response field transmission (slave and master modes) or during header transmission (in master mode). this bit is cleared by software. cef 19 checksum error flag this bit is set by hardware and indicates that the received checksum does not match the hardware calculated checksum. this bit is cleared by software. note: this bit is never set if ccd or cfd bit in lincr1 is set. sfef 20 synch field error flag this bit is set by hardware and indicates that a sy nch field error occurred (inconsistent synch field). bdef 21 break delimiter error flag this bit is set by hardware and indicates that the received break delimiter is too short (less than one bit time).
pxd10 microcontroller reference manual, rev. 1 23-18 freescale semiconductor preliminary?subject to change without notice 23.7.2.5 uart mode control register (uartcr) idpef 22 identifier parity error flag this bit is set by hardware and indicate s that a identifier parity error occurred. note: header interrupt is triggered when sfef or bdef or idpef bit is set and heie bit in linier is set. fef 23 framing error flag this bit is set by hardware and indicates to the software that linflex has detected a framing error (invalid stop bit). this error can occur during reception of any data in the response field (master or slave mode) or during reception of synch field or identifier field in slave mode. bof 24 buffer overrun flag this bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. if rblm in lincr1 is set then the new byte received is discarded. if rblm is reset then the new byte overwrites the buffer. it can be cleared by software. 25:30 reserved nf 31 noise flag this bit is set by hardware when noise is detected on a received character. this bit is cleared by software. address: base + 0x0010 a ccess: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 tdfl[0:1] 0 rdfl[0:1] 00 00 rxen txen op pce wl uart w reset0000000000000000 figure 23-11. uart mode control register (uartcr) table 23-10. uartcr field descriptions field description 0:16 reserved tdfl[0:1] 17:18 transmitter data field length these bits set the number of bytes to be transmitted in uart mode. these bits can be programmed only when the uart bit is set. tdfl[0:1] = transmit buffer size ? 1. 00 transmit buffer size = 1. 01 transmit buffer size = 2. 10 transmit buffer size = 3. 11 transmit buffer size = 4. table 23-9. linesr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-19 preliminary?subject to change without notice 19 reserved rdfl[0:1] 20:21 receiver data field length these bits set the number of bytes to be received in uart mode. these bits can be programmed only when the uart bit is set. rdfl[0:1] = receive buffer size ? 1. 00 receive buffer size = 1. 01 receive buffer size = 2. 10 receive buffer size = 3. 11 receive buffer size = 4. 22:25 reserved rxen 26 receiver enable 0 receiver disable. 1 receiver enable. this bit can be programmed only when the uart bit is set. txen 27 transmitter enable 0 transmitter disable. 1 transmitter enable. this bit can be programmed only when the uart bit is set. note: transmission starts when this bit is set and when writing data0 in the bdrl register. op 28 odd parity 0 sent parity is even. 1 sent parity is odd. this bit can be programmed in initialization mode only when the uart bit is set. pce 29 parity control enable 0 parity transmit/check disable. 1 parity transmit/check enable. this bit can be programmed in initialization mode only when the uart bit is set. wl 30 word length in uart mode 0 7-bit data + parity bit. 1 8-bit data (or 9-bit if pce is set). this bit can be programmed in initialization mode only when the uart bit is set. uart 31 uart mode enable 0lin mode. 1uart mode. this bit can be programmed in initialization mode only. table 23-10. uartcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 23-20 freescale semiconductor preliminary?subject to change without notice 23.7.2.6 uart mode status register (uartsr) address: base + 0x0014 a ccess: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szf ocf pe3 pe2 pe1 pe0 rmb fef bof rps wuf 0 0drfdtfnf w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 23-12. uart mode status register (uartsr) table 23-11. uartsr field descriptions field description 0:15 reserved szf 16 stuck at zero flag this bit is set by hardware when the bus is dominant for more than a 100-bit time. it is cleared by software. ocf 17 ocf output compare flag 0 no output compare event occurred. 1 the content of the counter has matched the content of oc1[0:7] or oc2[0:7] in linocr. an interrupt is generated if the ocie bit in linier register is set. pe3 18 parity error flag rx3 this bit indicates if there is a parity error in the corresponding received byte (rx3). see section 23.8.1.1, buffer in uart mode. no interrupt is generated if this error occurs. 0 no parity error. 1 parity error. pe2 19 parity error flag rx2 this bit indicates if there is a parity error in the corresponding received byte (rx2). see section 23.8.1.1, buffer in uart mode. no interrupt is generated if this error occurs. 0 no parity error. 1 parity error. pe1 20 parity error flag rx1 this bit indicates if there is a parity error in the corresponding received byte (rx1). see section 23.8.1.1, buffer in uart mode. no interrupt is generated if this error occurs. 0 no parity error. 1 parity error. pe0 21 parity error flag rx0 this bit indicates if there is a parity error in the corresponding received byte (rx0). see section 23.8.1.1, buffer in uart mode. no interrupt is generated if this error occurs. 0 no parity error. 1 parity error.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-21 preliminary?subject to change without notice rmb 22 release message buffer 0 buffer is free. 1 buffer ready to be read by software. this bit must be cleared by software after reading data received in the buffer. this bit is cleared by hardware in initialization mode. fef 23 framing error flag this bit is set by hardware and indicates to the software that linflex has detected a framing error (invalid stop bit). bof 24 buffer overrun flag this bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. if rblm in lincr1 is set then the new byte receiv ed is discarded. if rblm is reset then the new byte overwrites buffer. it can be cleared by software. rps 25 lin receive pin state this bit reflects the current status of linrx pin for diagnostic purposes. wuf 26 wake-up flag this bit is set by hardware and indicates to t he software that linflex has detected a falling edge on the linrx pin in sleep mode. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt i generated if wuie bit in linier is set. 27:28 reserved drf 29 data reception completed flag this bit is set by hardware and indicates the data reception is co mpleted, that is , the number of bytes programmed in rdfl[0:1] in uartcr have been received. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt is generated if drie bit in linier is set. note: in uart mode, this flag is set in case of framing error, parity error or overrun. dtf 30 data transmission completed flag this bit is set by hardware and indicates the data transmission is completed, that is, the number of bytes programmed in tdfl[0:1] have been transmitted. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt is generated if dtie bit in linier is set. nf 31 noise flag this bit is set by hardware when noise is detected on a received character. this bit is cleared by software. table 23-11. uartsr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 23-22 freescale semiconductor preliminary?subject to change without notice 23.7.2.7 lin timeout control status register (lintcsr) address: base + 0x0018 a ccess: user read/write 01234 5 6 7 89101112131415 r 0000 000 0 0000 0000 w reset000000 0 0 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0 lto m iot toce cnt[0:7] w reset000000 0 00 00000 figure 23-13. lin timeout control status register (lintcsr) table 23-12. lintcsr field descriptions field description 0:20 reserved lto m 21 lin timeout mode 0 lin timeout mode (header, response and frame timeout detection). 1 output compare mode. this bit can be set/cleared in initialization mode only. iot 22 idle on timeout 0 lin state machine not reset to idle on timeout event. 1 lin state machine reset to idle on timeout event. this bit can be set/cleared in initialization mode only. toce 23 timeout counter enable 0 timeout counter disable. ocf bit in linesr or uartsr is not set on an output compare event. 1 timeout counter enable. ocf bit is set if an output compare event occurs. toce bit is configurable by software in initialization mode. if lin state is not init and if timer is in lin timeout mode, then hardware takes control of toce bit. cnt[0:7] 24:31 counter value these bits indicate the li n timeout counter value.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-23 preliminary?subject to change without notice 23.7.2.8 lin output compare register (linocr) 23.7.2.9 lin timeout cont rol register (lintocr) address: base + 0x001c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r oc2[0:7] 1 oc1[0:7] 1 w reset11111111 11111111 1 if ltom in the lintcsr register is set, these bits are read-only. figure 23-14. lin output compare register (linocr) table 23-13. linocr field descriptions field description 0:15 reserved oc2[0:7] 16:23 output compare 2 value these bits contain the value to be compared to the value of bits cnt[0:7] in lintcsr. oc1[0:7] 24:31 output compare 1 value these bits contain the value to be compared to the value of bits cnt[0:7] in lintcsr. address: base + 0x0020 ac cess: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 rto[0:3] 0 hto[0:6] w reset0000111000 * *1100 *: these bits reset to 10 for linflex_0 and 01 for linflex_1. figure 23-15. lin timeout control register (lintocr)
pxd10 microcontroller reference manual, rev. 1 23-24 freescale semiconductor preliminary?subject to change without notice 23.7.2.10 lin fracti onal baud rate re gister (linfbrr) table 23-14. lintocr field descriptions field description 0:19 reserved rto[0:3] 20:23 response timeout value this register contains the response timeout duration (in bit time) for 1 byte. the reset value is 0xe = 14, corresponding to t response_maximum =1.4t response_nominal 24 reserved hto[0:6] 25:31 header timeout value this register contains the header timeout duration (in bit time). this value does not include the break and the break delimiter. the reset value is the 0x2c = 44, corresponding to t header_maximum. setting mme bit in linsr changes hto[0:6] value to 0x1c = 28. hto[0:6] can be written only in slave mode. address: base + 0x0024 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 0000 div_f[0:3] w reset0000000000000000 figure 23-16. lin fractional ba ud rate register (linfbrr) table 23-15. linfbrr field descriptions field description 0:27 reserved div_f[0:3] 28:31 fraction bits of lfdiv the 4 fraction bits define the value of th e fraction of the linflex divider (lfdiv). fraction (lfdiv) = decimal value of div_f [0:3] / 16. this register can be written in initialization mode only.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-25 preliminary?subject to change without notice 23.7.2.11 lin integer baud rate register (linibrr) address: base + 0x0028 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000 div_m[0:12] w reset0000000000000000 figure 23-17. lin integer ba ud rate register (linibrr) table 23-16. linibrr field descriptions field description 0:18 reserved div_m[0:12] 19:31 lfdiv mantissa these 12 bits define the linflex di vider (lfdiv) mantissa value (see table 23-17 ). this register can be written in initialization mode only. table 23-17. integer baud rate selection div_m[0:12] mantissa 0x0000 lin clock disabled 0x0001 1 ... ... 0x1ffe 8190 ox1fff 8191
pxd10 microcontroller reference manual, rev. 1 23-26 freescale semiconductor preliminary?subject to change without notice 23.7.2.12 lin checksum fi eld register (lincfr) 23.7.2.13 lin control register 2 (lincr2) address: base + 0x002c ac cess: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 cf[0:7] w reset0000000000000000 figure 23-18. lin checksum field register (lincfr) table 23-18. lincfr field descriptions field description 0:23 reserved cf[0:7] 24:31 checksum bits when ccd bit in lincr1 is cleared these bits are read-only. when ccd bit is set, these bits are read/write. see table 23-4 . address: base + 0x0030 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 iobe iope 0 0 0 0 0 0 0 0 w wurq ddrq dtrq abrq htrq reset01*0000000000000 * this bit resets to 1 for li nflex_0 and 0 for linflex_1. figure 23-19. lin control register 2 (lincr2)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-27 preliminary?subject to change without notice table 23-19. lincr2 field descriptions field description 0:16 reserved iobe 17 idle on bit error 0 bit error does not reset lin state machine. 1 bit error reset lin state machine. this bit can be set/cleared in initialization mode only. iope 18 idle on identifier parity error 0 identifier parity error does not reset lin state machine. 1 identifier parity error reset lin state machine. this bit can be set/cleared in initialization mode only. wurq 19 wake-up generation request setting this bit generates a wake-up pulse. it is reset by hardware when the wake-up character has been transmitted. the character sent is copied from data0 in bdrl buffer. note that this bit cannot be set in sleep mode. software has to exit sleep mode before requesting a wake-up. bit error is not checked when transmitting the wake-up request. ddrq 20 data discard request set by software to stop data reception if the fram e does not concern the node. this bit is reset by hardware once linflex has moved to idle state. in slave mode, this bit can be set only when hrf bit in linsr is set and identifier did not match any filter. dtrq 21 data transmission request set by software in slave mode to request the transmi ssion of the lin data field stored in the buffer data register. this bit can be set only when hrf bit in linsr is set. cleared by hardware when the request has been completed or aborted or on an error condition. in master mode, this bit is set by hardware when dir bit in bidr is set and header transmission is completed. abrq 22 abort request set by software to abort the current transmission. cleared by hardware when the transmission has been aborted. linflex aborts the transmission at the end of the current bit. this bit can also abort a wake-up request. it can also be used in uart mode. htrq 23 header transmission request set by software to request the transmission of the lin header. cleared by hardware when the request has been completed or aborted. this bit has no effect in uart mode. 24:31 reserved
pxd10 microcontroller reference manual, rev. 1 23-28 freescale semiconductor preliminary?subject to change without notice 23.7.2.14 buffer identifier register (bidr) address: base + 0x0034 a ccess: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dfl[0:5] dir ccs 00 id[0:5] w reset0000000000000000 figure 23-20. buffer identifier register (bidr) table 23-20. bidr field descriptions field description 0:15 reserved dfl[0:5] 16:21 data field length these bits define the number of data by tes in the response part of the frame. dfl[0:5] = number of data bytes ? 1. normally, lin uses only dfl[0:2] to manage fram es with a maximum of 8 bytes of data. identifier filters are compatible with df l[0:2] only. dfl[3:5] are prov ided to manage extended frames. dir 22 direction this bit controls the direction of the data field. 0 linflex receives the data and copies them in the bdr registers. 1 linflex transmits the data from the bdr registers. ccs 23 classic checksum this bit controls the type of checksum applied on the current message. 0 enhanced checksum covering identifier and da ta fields. this is compatible with lin specification 2.0 and higher. 1 classic checksum covering data fields only. th is is compatible with lin specification 1.3 and earlier. in lin slave mode (mme bit cleared in lincr1), this bit must be configured before the header reception. if the slave has to manage frames with 2 types of checksum, filters must be configured. 24:25 reserved id[0:5] 26:31 identifier identifier part of the identifier field without the identifier parity.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-29 preliminary?subject to change without notice 23.7.2.15 buffer data register lsb (bdrl) 23.7.2.16 buffer data register msb (bdrm) address: base + 0x0038 a ccess: user read/write 0123456789101112131415 r data3[0:7] data2[0:7] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data1[0:7] data0[0:7] w reset0000000000000000 figure 23-21. buffer data register lsb (bdrl) table 23-21. bdrl field descriptions field description data3[0:7] 0:7 data byte 3 data byte 3 of the data field. data2[0:7] 8:15 data byte 2 data byte 2 of the data field. data1[0:7] 16:23 data byte 1 data byte 1 of the data field. data0[0:7] 24:31 data byte 0 data byte 0 of the data field. address: base + 0x003c a ccess: user read/write 0123456789101112131415 r data7[0:7] data6[0:7] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data5[0:7] data4[0:7] w reset0000000000000000 figure 23-22. buffer data register msb (bdrm)
pxd10 microcontroller reference manual, rev. 1 23-30 freescale semiconductor preliminary?subject to change without notice 23.7.2.17 identifier filter enable register (ifer) this register is not implemented on linflex_1. table 23-22. bdrm field descriptions field description data7[0:7] 0:7 data byte 7 data byte 7 of the data field. data6[0:7] 8:15 data byte 6 data byte 6 of the data field. data5[0:7] 16:23 data byte 5 data byte 5 of the data field. data4[0:7] 24:31 data byte 4 data byte 4 of the data field. address: base + 0x0040 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 fact[0:7] w reset0000000000000000 figure 23-23. identifier filter enable register (ifer) table 23-23. ifer field descriptions field description 0:23 reserved fact[0:7] 24:31 filter activation 0 filters 2 n and 2 n + 1 are activated. 1 filters 2 n and 2 n + 1 are deactivated. (refer to table 23-24 .) these bits can be set/cleared in initialization mode only. table 23-24. ifer[fact] configuration bit value result fact[0] 0 filters 0 and 1 are deactivated. 1 filters 0 and 1 are activated.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-31 preliminary?subject to change without notice 23.7.2.18 identifier filter match index (ifmi) this register is not implemented on linflex_1. fact[1] 0 filters 2 and 3 are deactivated. 1 filters 2 and 3 are activated. fact[2] 0 filters 4 and 5 are deactivated. 1 filters 4 and 5 are activated. fact[3] 0 filters 6 and 7 are deactivated. 1 filters 6 and 7 are activated. fact[4] 0 filters 8 and 9 are deactivated. 1 filters 8 and 9 are activated. fact[5] 0 filters 10 and 11 are deactivated. 1 filters 10 and 11 are activated. fact[6] 0 filters 12 and 13 are deactivated. 1 filters 12 and 13 are activated. fact[7] 0 filters 14 and 15 are deactivated. 1 filters 14 and 15 are activated. address: base + 0x0044 access: user read-only 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0000 0000 ifmi[0:4] w reset0000000000000000 figure 23-24. identifier filter match index (ifmi) table 23-25. ifmi field descriptions field description 0:26 reserved table 23-24. ifer[fact] configuration (continued) bit value result
pxd10 microcontroller reference manual, rev. 1 23-32 freescale semiconductor preliminary?subject to change without notice 23.7.2.19 identifier filter mode register (ifmr) this register is not implemented on linflex_1. ifmi[0:4] 27:31 filter match index this register contains the index corresponding to t he received identifier. it can be used to directly write or read the data in sram (see section 23.8.2.2, slave mode for more details). when no filter matches, if mi[0:4] = 0. when filter n is matching, ifmi[0:4] = n +1. address: base + 0x0048 a ccess: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000 0000 0000 0ifm w reset0000000000000000 figure 23-25. identifier filter mode register (ifmr) table 23-26. ifmr field descriptions field description ifm filter mode 0 filters 2 n and 2 n + 1 are in identifier list mode. 1 filters 2 n and 2 n + 1 are in mask mode (filter 2 n + 1 is the mask for the filter 2 n ). (refer to table 23-27 .) table 23-27. ifmr[ifm] configuration bit value result ifm[0] 0 filters 0 and 1 are in identifier list mode. 1 filters 0 and 1 are in mask mode (filt er 1 is the mask for the filter 0). ifm[1] 0 filters 2 and 3 are in identifier list mode. 1 filters 2 and 3 are in mask mode (filt er 3 is the mask for the filter 2). ifm[2] 0 filters 4 and 5 are in identifier list mode. 1 filters 4 and 5 are in mask mode (filt er 5 is the mask for the filter 4). ifm[3] 0 filters 6 and 7 are in identifier list mode. 1 filters 6 and 7 are in mask mode (filt er 7 is the mask for the filter 6). table 23-25. ifmi field descriptions field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-33 preliminary?subject to change without notice 23.7.2.20 identifier filter control register (ifcr2 n ) this register is not implemented on linflex_1. note this register can be writte n in initialization mode only. n = 0: address: base + 0x004c n = 1: address: base + 0x0054 n = 2: address: base + 0x005c n = 3: address: base + 0x0064 n = 4: address: base + 0x006c n = 5: address: base + 0x0074 n = 6: address: base + 0x007c n = 7: address: base + 0x0084 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000 dfl[0:2] dir ccs 0 0 id[0:5] w w1c reset0000000000000000 figure 23-26. identifier filter control register (ifcr2 n ) table 23-28. ifcr2 n field descriptions field description 0:18 reserved dfl[0:2] 19:21 data field length these bits define the number of data by tes in the response part of the frame. dir 22 direction this bit controls the direction of the data field. 0 linflex receives the data and copies them in the bdrl and bdrm registers. 1 linflex transmits the data from the bdrl and bdrm registers. ccs 23 classic checksum this bit controls the type of checksum applied on the current message. 0 enhanced checksum covering identifier and data fiel ds. this is compatible with lin specification 2.0 and higher. 1 classic checksum covering data fields only. this is compatible with li n specification 1.3 and earlier. 24:25 reserved id[0:5] 26:31 identifier identifier part of the id entifier field without the identifier parity.
pxd10 microcontroller reference manual, rev. 1 23-34 freescale semiconductor preliminary?subject to change without notice 23.7.2.21 identifier filter control register (ifcr2 n +1) this register is not implemented on linflex_1. note this register can be writte n in initialization mode only. n = 0: address: base + 0x0050 n = 1: address: base + 0x0058 n = 2: address: base + 0x0060 n = 3: address: base + 0x0068 n = 4: address: base + 0x0070 n = 5: address: base + 0x0078 n = 6: address: base + 0x0080 n = 7: address: base + 0x0088 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000 dfl[0:2] dir ccs 0 0 id[0:5] w w1c reset0000000000000000 figure 23-27. identifier filter control register (ifcr2 n +1) table 23-29. ifcr2 n + 1 field descriptions field description 0:18 reserved dfl[0:2] 19:21 data field length these bits define the number of data bytes in the response part of the frame. dfl[0:2] = number of data bytes ? 1. dir 22 direction this bit controls the direction of the data field. 0 linflex receives the data and copies them in the bdrl and bdrm registers. 1 linflex transmits the data from the bdrl and bdrm registers. ccs 23 classic checksum this bit controls the type of ch ecksum applied on the current message. 0 enhanced checksum covering identifier and data fields. this is compatible with lin specification 2.0 and higher. 1 classic checksum covering data field only. this is compatible with lin specification 1.3 and earlier. 24:25 reserved id[0:5] 26:31 identifier identifier part of the identifier field without the identifier parity
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 23-35 23.7.3 register map and reset values table 23-30. register map and reset values address offset register name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 lincr1 reset value 0000000000000000 ccd 0 cfd 0 lase 0 awum 0 mbl0 0 mbl1 0 mbl2 0 mbl3 0 bf 1 slfm 0 lbkm 0 mme 0 sbdt 0 rblm 0 sleep 1 init 0 4 linier reset value 0000000000000000 szie 0 ocie 0 beie 0 ceie 0 heie 000 feie 0 boie 0 lsie 0 wuie 0 dbfie 0 dbeie 0 drie 0 dtie 0 hrie 0 8linsr reset value 0000000000000000 lins0 0 lins1 0 lins2 0 lins3 000 rmb 00 rbsy 0 rps 1 wuf 0 dbff 0 dbef 0 drf 0 dtf 0 hrf 0 clinesr reset value 0000000000000000 szf 0 ocf 0 bef 0 cef 0 sfef 0 bdef 0 idpef 0 fef 0 bof 0000000 nf 0 10 uartcr reset value 0000000000000000 0 tdfl0 0 tdfl1 00 rdfl0 0 rdfl1 00000 rxen 0 txen 0 op 0 pce 0 wl 0 uart 0 14 uartsr reset value 0000000000000000 szf 0 ocf 0 pe0 0 pe1 0 pe2 0 pe3 0 rmb 0 fef 0 bof 0 rps 0 wuf 000 drf 0 dtf 0 nf 0
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 23-36 18 lintcsr reset value 0000000000000000 00000 lto m 0 iot 1 toce 0 cnt0 0 cnt1 0 cnt2 0 cnt3 0 cnt4 0 cnt5 0 cnt6 0 cnt7 0 1c linocr reset value 0000000000000000 oc20 1 oc21 1 oc22 1 oc23 1 oc24 1 oc25 1 oc26 1 oc27 1 oc10 1 oc11 1 oc12 1 oc13 1 oc14 1 oc15 1 oc16 1 oc17 1 20 lintocr reset value 0000000000000000 0000 rto0 1 rto1 1 rto2 1 rto3 00 hto0 0 hto1 1 hto2 0 hto3 1 hto4 1 hto5 0 hto6 0 24 linfbrr reset value 0000000000000000 000000000000 div_f0 0 div_f1 0 div_f2 0 div_f3 0 28 linibrr reset value 0000000000000000 000 div_m0 0 div_m1 0 div_m2 0 div_m3 0 div_m4 0 div_m5 0 div_m6 0 div_m7 0 div_m8 0 div_m9 0 div_m10 0 div_m11 0 div_m12 0 2c lincfr reset value 0000000000000000 00000000 cf0 0 cf1 0 cf2 0 cf3 0 cf4 0 cf5 0 cf6 0 cf7 0 30 lincr2 reset value 0000000000000000 0 iobe 1 iope 1 wurq 0 ddrq 0 dtrq 0 abrq 0 htrq 000000000 table 23-30. register map and reset values (continued) address offset register name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 23-37 34 bidr reset value 0000000000000000 dfl0 0 dfl1 0 dfl2 0 dfl3 0 dfl4 0 dfl5 0 dir 0 ccs 000 id0 0 id1 0 id2 0 id3 0 id4 0 id5 0 38 bdrl reset value data30 0 data31 0 data32 0 data33 0 data34 0 data35 0 data36 0 data37 0 data20 0 data21 0 data22 0 data23 0 data24 0 data25 0 data26 0 data27 0 data10 0 data11 0 data12 0 data13 0 data14 0 data15 0 data16 0 data17 0 data00 0 data01 0 data02 0 data03 0 data04 0 data05 0 data06 0 data07 0 3c bdrm reset value data70 0 data71 0 data72 0 data73 0 data74 0 data75 0 data76 0 data77 0 data60 0 data61 0 data62 0 data63 0 data64 0 data65 0 data66 0 data67 0 data50 0 data51 0 data52 0 data53 0 data54 0 data55 0 data56 0 data57 0 data40 0 data41 0 data42 0 data43 0 data44 0 data45 0 data46 0 data47 0 40 ifer reset value 0000000000000000 00000000 fact0 0 fact1 0 fact2 0 fact3 0 fact4 0 fact5 0 fact6 0 fact7 0 44 ifmi reset value 0000000000000000 00000000000 ifmi0 0 ifmi1 0 ifmi2 0 ifmi3 0 ifmi4 0 48 ifmr reset value 0000000000000000 000000000000 ifm0 0 ifm1 0 ifm2 0 ifm3 0 table 23-30. register map and reset values (continued) address offset register name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 preliminary?subject to change without notice freescale semiconductor 23-38 4c 54 5c 64 6c 74 7c 84 ifcr2 n reset value 0000000000000000 000 dfl0 0 dfl1 0 dfl2 0 dir 0 ccs 000 id0 0 id1 0 id2 0 id3 0 id4 0 id5 0 50 58 60 68 70 78 80 88 ifcr2 n +1 reset value 0000000000000000 000 dfl0 0 dfl1 0 dfl2 0 dir 0 ccs 000 id0 0 id1 0 id2 0 id3 0 id4 0 id5 0 table 23-30. register map and reset values (continued) address offset register name 0123456789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-39 preliminary?subject to change without notice 23.8 functional description 23.8.1 uart mode the main features in the uart mode are ? full duplex communication ? 8- or 9-bit data with parity ? 4-byte buffer for reception, 4-byte buffer for transmission ? 8-bit counter for timeout management 8-bit data frames : the 8th bit can be a data or a parity bit. even/odd parity can be selected by the odd parity bit in the uartcr. an even pa rity is set if th e modulo-2 sum of the 7 data bits is 1. an odd parity is cleared in this case. figure 23-28. uart mode 8-bit data frame 9-bit frames : the 9th bit is a parity bit. even/odd parity can be selected by the odd parity bit in the uartcr. an even parity is set if th e modulo-2 sum of the 7 data bits is 1. an odd par ity is cleared in this case. figure 23-29. uart mode 9-bit data frame 23.8.1.1 buffer in uart mode the 8-byte buffer is divided into two parts: one for receiver and one for transmitter as shown in table 23-31 . start bit d0 d7 stop bit byte field ? data bit ? parity bit d1 d2 d3 d4 d5 d6 start bit d0 d7 stop bit byte field ? parity bit d1 d2 d3 d4 d5 d6 d8
pxd10 microcontroller reference manual, rev. 1 23-40 freescale semiconductor preliminary?subject to change without notice 23.8.1.2 uart transmitter in order to start transmission in ua rt mode, the uart bit and the tran smitter enable (txen) bit in the uartcr must be set. transmission st arts when data0 (least significan t data byte) is programmed. the number of bytes transmitted is equal to the value configured by th e tdfl[0:1] bits in the uartcr (see table 23-10 ). the transmit buffer is 4 bytes, hence a 4-byte maximum transmission can be triggered. once the programmed number of bytes has been transmitted, the dtf bit is set in uartsr. if the txen bit of uart is reset during a transmission then the cu rrent transmission is completed and no further transmission can be invoked. 23.8.1.3 uart receiver the uart receiver is active as soon as the user exit s initialization mode and sets the rxen bit in the uartcr. there is a dedica ted 4-byte data buffer for received data bytes. once the programmed number (rdfl bits) of bytes has been received, the drf bi t is set in uartsr. if the rxen bit is reset during a reception then the current reception is completed and no further reception can be invoked until rxen is set. if a parity error occurs during recepti on of any byte, then the corresponding pe x bit in the uartsr is set. no interrupt is generated in this cas e. if a framing error occu rs in any byte (fe bit in uartsr is set) then an interrupt is generated if the feie bit in the linier is set. if the last received frame ha s not been read from the buffer (that is , rmb bit is not rese t by the user) then upon reception of the next byte an overr un error occurs (bof bit in uart sr is set) and one message will be lost. which message is lost depends on th e configuration of the rblm bit of lincr1. ? if the buffer lock function is di sabled (rblm bit in lincr1 clear ed) the last message stored in the buffer is overwritten by the new incoming messa ge. in this case the latest message is always available to the application. ? if the buffer lock function is enabled (rblm bit in lincr1 set) the most recent message is discarded and the previous messa ge is available in the buffer. table 23-31. message buffer buffer data register lin mode uart mode bdrl[0:31] transmit/receive buffer data0[0:7] transmit buffer tx0 data1[0:7] tx1 data2[0:7] tx2 data3[0:7] tx3 bdrm[0:31] data4[0:7] receive buffer rx0 data5[0:7] rx1 data6[0:7] rx2 data7[0:7] rx3
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-41 preliminary?subject to change without notice an interrupt is generated if the boie bit in the linier is set. 23.8.1.4 clock gating the linflex clock can be gated from the mode entr y module (refer to ). in uart mode, the linflex controller acknowledges a clock ga ting request once the data transm ission and data reception are completed, that is, once the transmit buffer is empty and the receive buffer is full. 23.8.2 lin mode lin mode comprises four submodes: ? master mode ? slave mode ? slave mode with identifier filtering ? slave mode with automatic resynchronization these submodes are described in the following pages. 23.8.2.1 master mode in master mode the application uses the message buffer to handle the lin me ssages. master mode is selected when the mme bit in lincr1 is set. 23.8.2.1.1 lin header transmission according to the lin protocol any communication on the lin bus is triggered by the master sending a header. the header is transmitted by the master task while the data is transmitted by the slave task of a node. to transmit a header with linfle x the application must set up the id entifier, the data field length and configure the message (direction and checksum t ype) in the bidr before requesting the header transmission by setting the htrq bit in lincr2. 23.8.2.1.2 data transmission (transceiver as publisher) when the master node is publisher of the data corresponding to the identif ier sent in the header, then the slave task of the master has to send the data in the response part of the lin frame. therefore, the application must provide the data to linflex before requesting the header transmission. the application stores the data in the message buffer bdr. according to the data field length, li nflex transmits the data and the checksum. the application uses the ccs bit in the bidr to conf igure the checksum type (classic or enhanced) for each message. if the response has been sent successfully, the dtf bit in the linsr is set. in case of error, the dtf flag is not set and the corresponding error flag is set in the linesr (refer to section 23.8.2.1.6, error handling ). it is possible to handle frames with a response size larg er than 8 bytes of data (extended frames). if the data field length in the bidr is configured with a value higher than 8 data bytes, the dbef bit in the
pxd10 microcontroller reference manual, rev. 1 23-42 freescale semiconductor preliminary?subject to change without notice linsr is set once the first 8 bytes have been transm itted. the application ha s to update the buffer bdr before resetting the dbef bit. the transmission of the next bytes starts when the dbef bit is reset. once the last data byte (or the checksum byt e) has been sent, the dtf flag is set. the direction of the message buffer is controlled by the dir bit in the bidr. when the application sets this bit the response is sent by linflex (publisher). resetting this bit configures the message buffer as subscriber. 23.8.2.1.3 data reception (transceiver as subscriber) to receive data from a slave node, the master sends a header with the corresponding identifier. linflex stores the data received from the slave in the message buffer and stores the message status in the linsr. if the response has been received su ccessfully, the drf bit in the linsr is set. in case of error, the drf flag is not set and the corresponding error flag is set in the linesr (refer to section 23.8.2.1.6, error handling ). it is possible to handle frames with a response size larg er than 8 bytes of data (extended frames). if the data field length in the bidr is configured with a value higher than 8 data bytes, the dbff bit in the linsr is set once the first 8 bytes ha ve been received. the application has to read the buffer bdr before resetting the dbff bit. once the last data byte (or the check sum byte) has been received, the drf flag is set. 23.8.2.1.4 data discard to discard data from a slave, the dir bit in the bi dr must be reset and the ddrq bit in lincr2 must be set before starting the header transmission. 23.8.2.1.5 error detection linflex is able to detect and ha ndle lin communication errors. a code stored in the li n error status register (linesr) signals the errors to the software. in master mode, the follow ing errors are detected: ? bit error : during transmission, the value read back from the bus differs from the transmitted value. ? framing error : a dominant state has been sampled on th e stop bit of the currently received character (synch field, identi fier field or data field). ? checksum error : the computed checksum does not match the received one. ? response and frame timeout : refer to section 23.8.3, 8-bit timeout counter for more details. 23.8.2.1.6 error handling in case of bit error detection duri ng transmission, linflex stops the tr ansmission of the frame after the corrupted bit. linflex returns to idle state and an interrupt is generated if the beie bi t in the linier is set. during reception, a framing error leads linflex to discard the current frame. linflex returns immediately to idle state. an interrupt is ge nerated if the feie bit in the linier is set.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-43 preliminary?subject to change without notice during reception, a checksum error leads linflex to dis card the received frame. li nflex returns to idle state. an interrupt is generated if the ceie bit in the linier is set. 23.8.2.2 slave mode in slave mode the application uses the message buffer to handle the lin messages. slave mode is selected when the mme bit in lincr1 is cleared. 23.8.2.2.1 data transmission (transceiver as publisher) when linflex receives the identifier, the hrf bit in th e linsr is set and, if the hrie bit in the linier is set, an rx interrupt is generated. the software mu st read the received identifier in the bidr, fill the bdr registers, specify the data fi eld length using the dfl[0:2] bits in the bidr and trigger the data transmission by setting the dtrq bit in lincr2. one or several identifier filters can be configured for transmission by setti ng the dir bit in the ifcr x register(s) and activated by setting one or several bits in the ifer. when at least one identifier filter is configured in transmission and activated, and if the received identifier matches the filter, a specific tx interrupt (instead of an rx interrupt) is generated. typically, the application has to c opy the data from sram lo cations to the bdar. to copy the data to the right location, the application has to identify the data by means of the id entifier. to avoid this and to ease the access to the sram locations, the linflex controll er provides a filter matc h index. this index value is the number of the filter that matched the received identifier. the software can use the index in the ifmi register to directly access the pointer that points to the right data array in the sram area and copy this data to the bdar (see figure 23-31 ). using a filter avoids the software having to configure the direction, the data field length and the checksum type in the bdir. the software fills the bdar and tr iggers the data transmissi on by setting the dtrq bit in lincr2. if linflex cannot provide enough tx id entifier filters to handle all identi fiers the software has to transmit data for, then a filter can be c onfigured in mask mode (refer to section 23.8.2.3, slave mode with identifier filtering? ) in order to manage several identifiers with one filter only. 23.8.2.2.2 data reception (transceiver as subscriber) when linflex receives the identifier, the hrf bit in th e linsr is set and, if the hrie bit in the linier is set, an rx interrupt is generate d. the software must read the received identifier in the bidr and specify the data field length using the dfl[0:2] bits in the bd ir before receiving the stop bit of the first byte of data field. when the checksum reception is comp leted, an rx interrupt is generated to allow the software to read the received data in the bdr registers. one or several identifier filters can be configured for reception by resetting the dir bit in the ifcr x register(s) and activated by setting one or several bits in the ifer.
pxd10 microcontroller reference manual, rev. 1 23-44 freescale semiconductor preliminary?subject to change without notice when at least one identifier filter is configured in reception and activat ed, and if the received identifier matches the filter, an rx interrupt is ge nerated after the chec ksum reception only. typically, the application has to c opy the data from the bdar to sram locations. to copy the data to the right location, the application has to identify the data by means of the id entifier. to avoid this and to ease the access to the sram locations, the linflex controll er provides a filter matc h index. this index value is the number of the filter that matched the received identifier. the software can use the index in the ifmi register to directly access the pointer that points to the right data array in the sram area and copy this data from the bdar to the sram (see figure 23-31 ). using a filter avoids the software reading the id value in the bidr, and configuring the direction, the data field length and the checksum type in the bdir. if linflex cannot provide e nough rx identifier filters to handle all identifiers th e software has to receive the data for, then a filter can be configured in mask mode (refer to section 23.8.2.3, slave mode with identifier filtering? ) in order to manage several id entifiers with one filter only. 23.8.2.2.3 data discard when linflex receives the identifier, the hrf bit in th e linsr is set and, if the hrie bit in the linier is set, an rx interrupt is genera ted. if the received identifier does not concern the node, the software must set the ddrq bit in lincr2. linflex returns to idle state after bit ddrq is set. 23.8.2.2.4 error detection in slave mode, the following errors are detected: ? header error : an error occurred during header recepti on (break delimiter error, inconsistent synch field, header timeout). ? bit error : during transmission, the value r ead back from the bus differs from the transmitted value. ? framing error : a dominant state has been sampled on th e stop bit of the currently received character (synch field, identi fier field or data field). ? checksum error : the computed checksum does not match the received one. 23.8.2.2.5 error handling in case of bit error detection duri ng transmission, linflex stops the tr ansmission of the frame after the corrupted bit. linflex returns to idle state and an interrupt is generated if the beie bi t in the linier is set. during reception, a framing error leads linflex to discard the current frame. linflex returns immediately to idle state. an interrupt is ge nerated if the feie bit in the linier is set. during reception, a checksum error leads linflex to dis card the received frame. li nflex returns to idle state. an interrupt is generated if the ceie bit in the linier is set. during header reception, a break delimiter error, an inconsistent synch field or a timeout error leads linflex to discard the header. an interrupt is genera ted if the heie bit in the linier is set. linflex returns to idle state.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-45 preliminary?subject to change without notice 23.8.2.2.6 valid header a received header is considered as valid when it has been received corr ectly according to the lin protocol. if a valid break field and br eak delimiter come before th e end of the current header or at any time during a data field, the current header or data is discarded and the state m achine synchronizes on this new break. 23.8.2.2.7 valid message a received or transmitted message is considered as valid when the data has been received or transmitted without error according to the lin protocol. 23.8.2.2.8 overrun once the message buffer is full, the next valid message reception leads to an overr un and a message is lost. the hardware sets the bof bit in the linsr to signal the overrun condition. which message is lost depends on the configuration of the rx message buffer: ? if the buffer lock function is di sabled (rblm bit in lincr1 clear ed) the last message stored in the buffer is overwritten by the new incoming messa ge. in this case the latest message is always available to the application. ? if the buffer lock function is enabled (rblm bit in lincr1 set) the most recent message is discarded and the previous messa ge is available in the buffer. 23.8.2.3 slave mode with identifier filtering in the lin protocol the identifier of a message is not associated with the address of a node but related to the content of the message. consequent ly a transmitter broadcasts its mess age to all receivers. on header reception a slave node decides ? depending on the identifier value ? whether the software needs to receive or send a response. if the message does not target the node, it must be discarded without software intervention. to fulfill this requirement, the linflex controller provides configurable filters in order to request software intervention only if needed. this ha rdware filtering saves cpu resources that would otherwise be needed by software for filtering. 23.8.2.3.1 filter mode usually each of the eight ifcr regi sters filters one dedicated identifi er, but this limits the number of identifiers linflex can handle to th e number of ifcr register s implemented in the device. therefore, in order to be able to handle more identifiers, the filters can be configured in mask mode. in identifier list mode (the default mode), both filter registers ar e used as identifier re gisters. all bits of the incoming identifier must match the bi ts specified in the filter register. in mask mode , the identifier registers are a ssociated with mask registers specifying which bits of the identifier are handled as ?must ma tch? or as ?don?t care?. for the bit mapping and registers organization, please refer to figure 23-30 .
pxd10 microcontroller reference manual, rev. 1 23-46 freescale semiconductor preliminary?subject to change without notice figure 23-30. filter configur ation?register organization 23.8.2.3.2 identifier fi lter mode configuration the identifier filters ar e configured in the ifcr x registers. to configure an id entifier filter the filter must first be deactivated by clearing the fact bit in the ifer. the identifier list or identifier mask mode for the corresponding ifcr x registers is configured by the ifm bit in the ifmr. for each filter, the ifcr x register configures the id (or the ma sk), the direction (tx or rx), the data field length, and the checksum type. if no filter is active, an rx interrupt is generated on any received identifier event. if at least one active filter is conf igured as tx, all received identifiers matching this filter generate a tx interrupt. if at least one active filter is conf igured as rx, all received identifiers matching this filter generate an rx interrupt. if no active filter is configured as rx, all received identi fiers not matching tx filter(s) generate an rx interrupt. table 23-32. filter to interrupt vector correlation number of active filters number of active filters configured as tx number of active filters configured as rx interrupt vector 0 0 0 rx interrupt on all identifiers ifcr n identifier id bit mapping identifier filter register organization 15 0 dfl ccs dir identifier filter configuration ifcr2 n identifier identifier ifcr2 n +1 ifm = 0 identifier filter mode ifcr2 n identifier mask ifcr2 n +1 ifm = 1 identifier list mode mask mode [0:2] [0:5]
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-47 preliminary?subject to change without notice figure 23-31. identifier match index 23.8.2.4 slave mode with au tomatic resynchronization automatic resynchronization must be enabled in slave mode if f periph_set_1_clk tolerance is greater than 1.5%. this feature compensates a f periph_set_1_clk deviation up to 14%, as specified in lin standard. this mode is similar to sl ave mode as described in section 23.8.2.2, slave mode with the addition of automatic resynchroniza tion enabled by the lase bit. in this mode linflex adjusts the fractional baud rate generator after each synch field reception. automatic resynchronization method when automatic resynchronization is enabled, after each lin break, the time durat ion between five falling edges on rdi is sampled on f periph_set_1_clk and the result of this measuremen t is stored in an internal 19-bit register called sm (not user accessible) (see figure 23-32 ). then the lfdiv value (and its associated registers linibrr and linf brr) are automatically updated at the end of the fifth falling edge. during a (a > 0) a 0 ? tx interrupt on identifiers matching the filters, ? rx interrupt on all other identifiers if bf bit is set, no rx interrupt if bf bit is reset n (n = a + b) a (a > 0) b (b > 0) ? tx interrupt on identifiers matching the tx filters, ? rx interrupt on identifiers matching the rx filters, ? all other identifiers discarded (no interrupt) b (b > 0) 0 b ? rx interrupt on identifiers matching the filters, ? tx interrupt on all other identifiers if bf bit is set, no tx interrupt if bf bit is reset table 23-32. filter to interrupt vector correlation number of active filters number of active filters configured as tx number of active filters configured as rx interrupt vector ifmi message0 message1 message2 data pointers table sram @ +
pxd10 microcontroller reference manual, rev. 1 23-48 freescale semiconductor preliminary?subject to change without notice lin synch field measurement, the li nflex state machine is stopped and no data is transferred to the data register. figure 23-32. lin synch field measurement lfdiv is an unsigned fixed point number. the mantis sa is coded on 12 bits in the linibrr and the fraction is coded on 4 bits in the linfbrr. if lase bit = 1 then lfdiv is automatically updated at the end of each lin synch field. three internal registers (not user -accessible) manage the auto-update of the linflex divider (lfdiv): ? lfdiv_nom (nominal value written by soft ware at linibrr a nd linfbrr addresses) ? lfdiv_meas (results of the field synch measurement) ? lfdiv (used to genera te the local baud rate) on transition to idle, break or break delimiter state due to any error or on rece ption of a complete frame, hardware reloads lfdiv with lfdiv_nom. 23.8.2.4.1 deviation erro r on the synch field the deviation error is checke d by comparing the current baud rate (relative to the slave oscillator) with the received lin synch field (relative to the master os cillator). two checks ar e performed in parallel. the first check is based on a measurement between the fi rst falling edge and the last falling edge of the synch field: ? if d1 > 14.84%, lhe is set. ? if d1 < 14.06%, lhe is not set. ? if 14.06% < d1 < 14.84%, lhe can be either set or rese t depending on the de phasing between the signal on linflex_rx pin the f periph_set_1_clk clock. the second check is based on a meas urement of time between each fa lling edge of the synch field: ? if d2 > 18.75%, lhe is set. ? if d2 < 15.62%, lhe is not set. ? if 15.62% < d2 < 18.75%, lhe can be either set or rese t depending on the de phasing between the signal on linflex_rx pin the f periph_set_1_clk clock. lin break break bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit lin synch field measurement = 8.t br =sm.t periph_set_1_clk lfdiv(n) lfdiv(n+1) lfdiv = t br / (16.t periph_set_1_clk ) = rounding (sm / 128) t periph_set_1_clk = clock period t br = baud rate period t br t br = 16.lfdiv.t periph_set_1_clk sm = synch measurement register (19 bits) delim.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-49 preliminary?subject to change without notice note that the linflex does not need to check if the next edge occurs slow er than expected. this is covered by the check for deviation er ror on the full synch byte. 23.8.2.5 clock gating the linflex clock can be gated from the mode entr y module (see ). in lin mode, the li nflex controller acknowledges a clock gating request once the fr ame transmission or reception is completed. 23.8.3 8-bit timeout counter 23.8.3.1 lin timeout mode setting the ltom bit in the lint csr enables the lin timeout mode. the linocr becomes read-only, and oc1[0:7] and oc2[0:7] out put compare values in the linocr are automatically updated by hardware. this configuration detects header time out, response timeout, and frame timeout. depending on the lin mode (selected by the mme bit in lincr1), the 8-bit time out counter will behave differently. lin timeout mode must not be enab led during lin extended fr ames transmission or reception (that is, if the data field length in the bidr is configur ed with a value higher than 8 data bytes). 23.8.3.1.1 lin master mode field rto[0:3] in the lintocr can be used to tune response timeout and frame timeout values. header timeout value is fixed to hto[0:6] = 28-bit time. field oc1[0:7] checks t header and t response and field oc2[0:7] checks t frame (refer to figure 23-33 ). when linflex moves from br eak delimiter state to sync h field state (refer to section 23.7.2.3, lin status register (linsr) ): ? oc1[0:7] is updated with the value of oc header (oc header = cnt[0:7] + 28), ? oc2[0:7] is updated with the value of oc frame (oc frame = cnt[0:7] + 28 + rto[0:6] 9 (frame timeout value for an 8-byte frame), ? the toce bit is set. on the start bit of the first res ponse data byte (and if no error occurr ed during the header reception), oc1[0:7] is updated with the value of oc response (oc response = cnt[0:7] + rto[0:6] 9 (response timeout value for an 8-byte frame)). on the first response byte is received, oc1[0:7] and oc2[0:7] are automa tically updated to check t response and t frame according to rto[0:6] (tolerance) and dfl[0:2]. on the checksum reception or in case of error in the header or response, the toce bit is reset. if there is no response, frame timeout value does not take into account the dfl[0:2] value, and an 8-byte response (dfl = 7) is always assumed.
pxd10 microcontroller reference manual, rev. 1 23-50 freescale semiconductor preliminary?subject to change without notice 23.8.3.1.2 lin slave mode field rto[0:3] in the lintocr can be used to tune response timeout and frame timeout values. header timeout value is fixed to hto[0:6]. oc1[0:7] checks t header and t response and oc2[0:7] checks t frame (refer to figure 23-33 ). when linflex moves from break state to break delimiter state (refer to section 23.7.2.3, lin status register (linsr) ): ? oc1[0:7] is updated with the value of oc header (oc header = cnt[0:7] + hto[0:6]), ? oc2[0:7] is updated wi th the value of oc frame (oc frame = cnt[0:7] + hto[0:6] + rto[0:6] 9 (frame timeout value for an 8-byte frame)), ? the toce bit is set. on the start bit of the first res ponse data byte (and if no error occurr ed during the header reception), oc1[0:7] is updated with the value of oc response (oc response = cnt[0:7] + rto[0:7] 9 (response timeout value for an 8-byte frame)). once the first response byte is received, oc1[0:7] and oc2[0:7] are automatically updated to check t response and t frame according to rto[0:6] (tolerance) and dfl[0:2]. on the checksum reception or in case of error in the header or data field, the toce bit is reset. figure 23-33. header and response timeout 23.8.3.2 output compare mode resetting the ltom bit in the lintcsr enables the out put compare mode. this mode allows the user to fully customize the use of the counter. oc1[0:7] and oc2[0:7] output compare values can be updated in the lintocr by software. oc frame oc header oc response header response break frame oc1 oc2 response space [0:7] [0:7]
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-51 preliminary?subject to change without notice 23.8.4 interrupts table 23-33. linflex interrupt control interrupt event event flag bit enable control bit interrupt vector header received interrupt hrf hrie rxi 1 1 in slave mode, if at least one filter is configured as tx and enabled, header received interrupt vector is rxi or txi depending on the value of identifier received. data transmitted interrupt dtf dtie txi data received interrupt drf drie rxi data buffer empty interrupt dbef dbeie txi data buffer full interrupt dbff dbfie rxi wake-up interrupt wupf wupie rxi lin state interrupt 2 2 for debug and validation purposes lsf lsie rxi buffer overrun interrupt bof boie err framing error interrupt fef feie err header error interrupt hef heie err checksum error interrupt cef ceie err bit error interrupt bef beie err output compare interrupt ocf ocie err stuck at zero interrupt szf szie err
pxd10 microcontroller reference manual, rev. 1 23-52 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 23-53 preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 23-54 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 24-1 preliminary?subject to change without notice chapter 24 memory protection unit (mpu) 24.1 introduction the amba-ahb memory protection unit (mpu) pr ovides hardware access control for all memory references generated in the device . using preprogrammed region descri ptors which define memory spaces and their associated access rights, the mpu concurre ntly monitors all system bus transactions and evaluates the appropriateness of each tr ansfer. memory references that have sufficient access control rights are allowed to complete, while references that are not mapped to any region descript or or have insufficient rights are terminated with a protect ion error response. this module is commonly included as part of the platform. 24.1.1 overview the mpu module provides the following capabilities: ? support for 12 program-visible 128-bi t (4-word) region descriptors ? each region descriptor defi nes a modulo-32 byte space, al igned anywhere in memory ? region sizes can vary from a minimum of 32 bytes to a maximum of 4 gb ? two types of access control permissi ons defined in single descriptor word ? processors have separate {read, write, execute } attributes for supervisor and user accesses ? non-processor masters have {read, write} attributes ? hardware-assisted maintenance of the desc riptor valid bit minimi zes coherency issues ? alternate programming model view of the access control permissions word ? memory-mapped platform device ? interface to 4 slave ahb ports: flash controll er, system ram controller, ips peripherals bus, and quadspi module ? connections to the ahb addres s phase address and attributes ? typical location is immediately ?downstr eam? of the platform?s crossbar switch ? connection to the ips bus provides acc ess to the mpu?s programming model a simplified block diagram of the ahb_mpu module is shown in figure 24-1 . the ahb bus slave ports (s{0,1,2,3}_h*) are shown on the left side of the diagram, the region descriptor regi sters in the middle and the ips bus interface (ips_*) on the right side. th e evaluation macro contains the two magnitude comparators connected to the start and end address re gisters from each region descriptor (rgdn) as well as the combinational logic blocks to determine the region hit and the access protection error. for information on the details of the access evaluation macro, see section 24.3.1, access evaluation macro .
pxd10 microcontroller reference manual, rev. 1 24-2 freescale semiconductor preliminary?subject to change without notice figure 24-1. ahb_mpu block diagram ahb_mpu ips_wdata ips_addr decode mux ips bus 31 0 control rgd0 rgd1 rgd(n-1) hit_b start end error ips_rdata 31 0 hit_b start end error error_detail (edrn) error_address (earn) > > ahb_error_ap > > ahb bus slave ports address phase signals s{1,2,3}_h* s0_h* r,w,x r,w,x
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 24-3 preliminary?subject to change without notice 24.1.2 features the memory protection unit implemen ts a two-dimensional hardware ar ray of memory region descriptors and the crossbar slave ahb ports to continuously monitor the legality of every memory reference generated by each bus master in th e system. the feature set includes: ? support for 12 memory region descri ptors, each 128 bits in size ? specification of start and end a ddresses provide granularity for region sizes from 32 bytes to 4 gbytes ? access control definitions: 2 bus masters (proce ssor cores) support the tr aditional {r ead, write, execute} permissions with independent defini tions for supervisor and user mode accesses ? automatic hardware maintenance of the region de scriptor valid bit rem oves issues associated with maintaining a coherent image of the descriptor ? alternate memory view of the access control wo rd for each descriptor provides an efficient mechanism to dynamically alter only the access rights of a descriptor ? for overlapping region descript ors, priority is given to permission granting over access denying as this approach provides more flexibility to sy stem software. see section 24.3.2, putting it all together and ahb error terminations ? for details and section 24.5, application information ? for an example. ? support for 3 ahb slave port c onnections: flash controller, sy stem ram controller and ips peripherals bus ? mpu hardware continuously m onitors every ahb slave port access using the preprogrammed memory region descriptors ? an access protection error is det ected if a memory reference doe s not hit in any memory region or the reference is flagged as il legal in all memory regions where it does hit. in the event of an access error, the ahb reference is terminated wi th an error response and the mpu inhibits the bus cycle being sent to the targeted slave device. ? 64-bit error registers, one for each ahb slave port, capture the last faulting address, attributes and ?detail? information ? global mpu enable/disable control bit provides a mechanism to easily load region descriptors during system startup or allow complete a ccess rights during debug wi th the module disabled 24.1.3 modes of operation the mpu module does not support any special modes of operation. as a memory-mapped device located on the platform?s high-speed system bus, it responds based strictly on the memory addresses of the connected system buses. the ips bus is used to access the mpu?s programming model and the memory protection functions are evaluated on a reference-by-reference basis us ing the addresses from the ahb system bus port(s). power dissipation is minimized when the mp u?s global enable/disable bit is cleared (mpu_cesr[vld] = 0).
pxd10 microcontroller reference manual, rev. 1 24-4 freescale semiconductor preliminary?subject to change without notice 24.1.4 external signal description the mpu module does not include any external interf ace. the mpu?s internal in terfaces include an ips connection for accessing the programming model and multip le connections to the a ddress phase signals of the platform crossbar?s slave ah b ports. from a platform topology vi ewpoint, the mpu module appears to be directly connected ?downstream? from the cros sbar switch with interfaces to the ahb slave ports. 24.2 memory map and register description the mpu module provides an ips programming model mapped to an spp-standard on-platform 16 kbyte space. the programming model is partitioned into three groups: control/status regist ers, the data structure containing the region descriptors an d the alternate view of the regi on descriptor access control values. the programming model can onl y be referenced using 32- bit (word) accesses. atte mpted references using different access sizes, to undefined (r eserved) addresses, or with a non- supported access type (for example, a write to a read-only regi ster or a read of a write-only regist er) generate an ips error termination. finally, the programming m odel allocates space for an mpu definition with 8 re gion descriptors and up to 3 ahb slave ports, like flash controller, syst em ram controller a nd ips peripherals bus. 24.2.1 memory map the mpu programming model map is shown in table 24-1 . table 24-1. mpu memory map offset address register name register description size (bits) access location 0x0000 mpu_cesr mpu control/ error status register 32 r/ partial-w on page 5 0x0004? 0x000f reserved 0x0010 mpu_ear0 mpu error address register, slave port 0 32 r-only on page 6 0x0014 mpu_edr0 mpu error detail register, slave port 0 32 r-only on page 7 0x0018 mpu_ear1 mpu error address register, slave port 1 32 r-only on page 6 0x001c mpu_edr1 mpu error detail register, slave port 1 32 r-only on page 7 0x0020 mpu_ear2 mpu error address register, slave port 2 32 r-only on page 6 0x0024 mpu_edr2 mpu error detail register, slave port 2 32 r-only on page 7 0x0028 mpu_ear3 mpu error address register, slave port 3 32 r-only on page 6 0x002c mpu_edr3 mpu error detail register, slave port 3 32 r-only on page 7 0x0030? 0x03ff reserved 0x0400 mpu_rgd0 mpu region descriptor 0 128 r/w on page 8 0x0410 mpu_rgd1 mpu region descriptor 1 128 r/w on page 8
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 24-5 preliminary?subject to change without notice 24.2.2 register description the following sections detail the individual registers within the mpu?s programming model. 24.2.2.1 mpu control/error st atus register (mpu_cesr) the mpu_cesr provides one byte of error status plus three bytes of configur ation information. a global mpu enable/disable bit is also included in this register. 0x0420 mpu_rgd2 mpu region descriptor 2 128 r/w on page 8 0x0430 mpu_rgd3 mpu region descriptor 3 128 r/w on page 8 0x0440 mpu_rgd4 mpu region descriptor 4 128 r/w on page 8 0x0450 mpu_rgd5 mpu region descriptor 5 128 r/w on page 8 0x0460 mpu_rgd6 mpu region descriptor 6 128 r/w on page 8 0x0470 mpu_rgd7 mpu region descriptor 7 128 r/w on page 8 0x0480 mpu_rgd8 mpu region descriptor 8 128 r/w on page 8 0x0490 mpu_rgd9 mpu region descriptor 9 128 r/w on page 8 0x04a0 mpu_rgd10 mpu region descriptor 10 128 r/w on page 8 0x04b0 mpu_rgd11 mpu region descriptor 11 128 r/w on page 8 0x04c0? 0x07ff reserved 0x0800 mpu_rgdaac0 mpu rgd alternate access control 0 32 r/w on page 13 0x0804 mpu_rgdaac1 mpu rgd alternate access control 1 32 r/w on page 13 0x0808 mpu_rgdaac2 mpu rgd alternate access control 2 32 r/w on page 13 0x080c mpu_rgdaac3 mpu rgd alternate access control 3 32 r/w on page 13 0x0810 mpu_rgdaac4 mpu rgd alternate access control 4 32 r/w on page 13 0x0814 mpu_rgdaac5 mpu rgd alternate access control 5 32 r/w on page 13 0x0818 mpu_rgdaac6 mpu rgd alternate access control 6 32 r/w on page 13 0x081c mpu_rgdaac7 mpu rgd alternate access control 7 32 r/w on page 13 0x0820 mpu_rgdaac8 mpu rgd alternate access control 8 32 r/w on page 13 0x0824 mpu_rgdaac9 mpu rgd alternate access control 9 32 r/w on page 13 0x0828 mpu_rgdaac10 mpu rgd alternate access control 10 32 r/w on page 13 0x082c mpu_rgdaac11 mpu rgd alternate access control 11 32 r/w on page 13 0x0830? 0x3fff reserved table 24-1. mpu memory map (continued) offset address register name register description size (bits) access location
pxd10 microcontroller reference manual, rev. 1 24-6 freescale semiconductor preliminary?subject to change without notice 24.2.2.2 mpu error address regi ster, slave port n (mpu_earn) when the mpu detects an access error on slave port n, th e 32-bit reference address is captured in this read-only register and the corresponding bit in the mpu_cesr[sperr] field set. additional information about the faulting access is captured in the corresponding mpu_edrn re gister at the same time. note this register and the corresponding mpu_ed rn register contain the most r ecent access error; there are no hardware interlocks with the mpu_ cesr[sperr] field as the error re gisters are always loaded upon the occurrence of each pr otection violation. offset mpu_base + 0x000 access: read/partial write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sperr 1 0 0 0 hrl nsp nrgd 0 0 00 0 0 0vl d w w1c reset 000000001000* * * * * * * * * * * *00000000 figure 24-2. mpu control/error status register (mpu_cesr) table 24-2. mpu_cesr field descriptions field description 0?7 sperr slave port n error, where the slave port number matche s the bit number. each bit in this field represents a flag maintained by the mpu for signaling the pr esence of a captured error contained in the mpu_earn and mpu_edrn registers. the individual bi t is set when the hardware detects an error and records the faulting address and attributes. it is cleared when the corresponding bit is written as a logical one. if another error is ca ptured at the exact same cycle as a write of a logica l one, this flag remains set. a ?find first one? instruction (or equivalent) can be used to detect the presence of a captured error. 0 the corresponding mpu_earn/mpu_edrn registers do not contain a captured error. 1 the corresponding mpu_earn/mpu_edrn registers do contai n a captured error. 12?15 hrl hardware revision level. this 4-bit read-only field specifies the mpu?s hardware and definition revision level. it can be read by software to det ermine the functional defin ition of the module. 16?19 nsp number of slave ports. this 4-bit read-only field sp ecifies the number of slave ports [1-8] connected to the mpu. this field contains values of 0b0001 -0b1000, depending on the device configuration. 20?23 nrgd number of region descriptors. this 4-bit read-onl y field specifies the number of region descriptors implemented in the mpu. the defined encodings include: 0b00008 region descriptors 0b000112 region descriptors 0b001016 region descriptors 31 vld valid. this bit provides a global enable/disable for the mpu. 0 the mpu is disabled. 1 the mpu is enabled. while the mpu is disabled, all accesses from all bus masters are allowed.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 24-7 preliminary?subject to change without notice 24.2.2.3 mpu error detail register, slave port n (mpu_edrn) when the mpu detects an access error on slave port n, 32 bits of error deta il are captured in this read-only register and the corresponding bit in the mpu_cesr [sperr] field set. information on the faulting address is captured in the correspondi ng mpu_earn register at the same time. note this register and the corresponding mpu_earn register contain the most r ecent access error; there are no hardware interlocks with the mpu_cesr[sperr] field as the error regist ers are always loaded upon the occurrence of each protection violation. offset mpu_base + 0x010 (mpu_ear0) mpu_base + 0x018 (mpu_ear1) mpu_base + 0x020 (mpu_ear2) mpu_base + 0x028 (mpu_ear3) access: read read read read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eaddr w reset -------------------------------- figure 24-3. mpu error address register, slave port n (mpu_earn) table 24-3. mpu_earn field descriptions field description 0?31 eaddr error address. this read-only field is the referenc e address from slave port n that generated the access error. offset mpu_base + 0x014 (mpu_edr0) mpu_base + 0x01c (mpu_edr1) mpu_base + 0x024 (mpu_edr2) mpu_base + 0x02c (mpu_edr3) access: read read read read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eacd epid emn eattr erw w reset -------------------------------- figure 24-4. mpu error detail register, slave port n (mpu_edrn)
pxd10 microcontroller reference manual, rev. 1 24-8 freescale semiconductor preliminary?subject to change without notice 24.2.2.4 mpu region desc riptor n (mpu_rgdn) each 128-bit (16 byte) region descri ptor specifies a given memory space and the access attributes associated with that space. the desc riptor definition is the very esse nce of the operation of the memory protection unit. the region descriptors ar e organized sequentially in the mpu?s pr ogramming model and each of the four 32-bit words are detailed in the subsequent sections. 24.2.2.4.1 mpu region descriptor n, word 0 (mpu_rgdn.word0) the first word of the mpu region descriptor define s the 0-modulo-32 byte start address of the memory region. writes to this word clear th e region descriptor?s valid bit (see section 24.2.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) for more information). table 24-4. mpu_edrn field descriptions field description 0?15 eacd error access control detail. this 16-bit read-only field implements one bit per region descriptor and is an indication of the region descriptor hit logically anded with the access error indication. the mpu performs a reference-by-reference evaluation to deter mine the presence/absence of an access error. when an error is detected, the hit-qualified acce ss control vector is c aptured in this field. if the mpu_edrn register contains a captured error and the eacd field is all zeroes, this signals an access that did not hit in any region descriptor. all non-zero eacd values signal references that hit in a region descriptor(s), but failed due to a protection erro r as defined by the specific set bits. if only a single eacd bit is set, then the protection error was caused by a single non-overlapping region descriptor. if two or more eacd bits are set, then the protection error was caused in an overlapping set of region descriptors. 16?23 epid error process identification. this 8-bit read-only field records the process identifier of the faulting reference. the process identifier is typically driven onl y by processor cores; for other bus masters, this field is cleared. 24?27 emn error master number. this 4-bit read-only field records the logical master number of the faulting reference. this field is used to determine the bus master that generated the access error. 28?30 eattr error attributes. this 3-bit read-only field records a ttribute information about the faulting reference. the supported encodings are defined as: 0b000user mode, instruction access 0b001user mode, data access 0b010supervisor mode, instruction access 0b011supervisor mode, data access all other encodings are reserved. for non-core bus mast ers, the access attribute information is typically wired to supervisor, data (0b011). 31 erw error read/write. this 1-bit read-only field signals the access type (read, write) of the faulting reference. 0read 1write
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 24-9 preliminary?subject to change without notice 24.2.2.4.2 mpu region descriptor n, word 1 (mpu_rgdn.word1) the second word of the mpu region descriptor defines the 31-modulo-32 byte end address of the memory region. writes to this word clear th e region descriptor?s valid bit (see section 24.2.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) for more information). 24.2.2.4.3 mpu region descriptor n, word 2 (mpu_rgdn.word2) the third word of the mpu region de scriptor defines the access control rights of the memory region. the access control privileges are depende nt on two broad classifications of bus masters. bus masters 0-3 are typically reserved for processor cores and the corresponding access c ontrol is a 6-bit field defining separate privilege rights for user and supervisor mode accesses as we ll as the optional inclusion of a process identification field within the definition. bus ma sters 4-7 are typically rese rved for data movement engines and their capabilities are limited to separate read and write pe rmissions. for these fields, the bus master number refers to the l ogical master number defined as the ahb hmaster[3:0] signal. for the processor privilege rights, there are three flags associated with this functi on: {read, write, execute}. in this context, these flags follow the traditional definition: ? read ( r ) permission refers to the ability to access th e referenced memory address using an operand (data) fetch. offset mpu_base + 0x400 + (16*n) + 0x0 (mpu_rgdn.word0) access: r/w 012345678910111213141516171819202122232425262728293031 r srtaddr 0 0 0 00 w reset -------------------- -------00000 figure 24-5. mpu region descriptor, word 0 register (mpu_rgdn.word0) table 24-5. mpu_rgdn.word0 field descriptions field description 0?26 srtaddr start address. this field defines the most significant bits of the 0-modulo-32 byte start address of the memory region. offset mpu_base + 0x400 + (16*n) + 0x4 (mpu_rgdn.word1) access: r/w 012345678910111213141516171819202122232425262728293031 r endaddr 1 1 1 11 w reset -------------------- -------11111 figure 24-6. mpu region descriptor, word 1 register (mpu_rgdn.word1) table 24-6. mpu_rgdn.word1 field descriptions field description 0?26 endaddr end address. this field defines the most significant bits of the 31-modulo-32 byte end address of the memory region. there are no hardware checks to verify that endaddr >= srtaddr; it is software?s responsibility to properly load these region descriptor fields.
pxd10 microcontroller reference manual, rev. 1 24-10 freescale semiconductor preliminary?subject to change without notice ?write ( w ) permission refers to the ability to update the referenced memory address using a store (data) instruction. ? execute ( x ) permission refers to the ability to read the referenced memory address using an instruction fetch. the evaluation logic defines the processor access t ype based on multiple ahb signals, as hwrite and hprot[1:0]. for non-processor data movement engi nes (bus masters 4-7), the evaluati on logic simply uses hwrite to determine if the access is a read or write. writes to this word clear the re gion descriptor?s valid bit (see section 24.2.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) for more information). since it is al so expected that system software may adjust only the access controls with in a region descriptor (mpu_rgdn.wo rd2) as different tasks execute, an alternate programming view of th is 32-bit entity is provided. if only the access controls are being updated, this operation should be pe rformed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect the descri ptor?s valid bit. offset mpu_base + 0x400 + (16*n) + 0x8 (mpu_rgdn.word2) access: r/w 012345678 9101112131 4 15 16 17 18 19 2 0 21 22 23 24 25 2 6 27 28 29 30 31 r m 7 r e m 7 w e m 6 r e m 6 w e m 5 r e m 5 w e m 4 r e m 4 w e m 3 p e m3sm m3um r w x m 2 p e m2sm m2um r w x m 1 p e m1sm m1um r w x m 0 p e m0sm m0um r w x w reset --------------------------- ----- figure 24-7. mpu region descriptor, word 2 register (mpu_rgdn.word2) table 24-7. mpu_rgdn.word2 field descriptions field description 0 m7re bus master 7 read enable. if set, this flag allows bus master 7 to perform read operations. if cleared, any attempted read by bus master 7 terminates with an access error and the read is not performed. 1 m7we bus master 7 write enable. if set, this flag allows bus master 7 to perform write operations. if cleared, any attempted write by bus master 7 terminates with an access error and the write is not performed. 2 m6re bus master 6 read enable. if set, this flag allows bus master 6 to perform read operations. if cleared, any attempted read by bus master 6 terminates with an access error and the read is not performed. 3 m6we bus master 6 write enable. if set, this flag allows bus master 6 to perform write operations. if cleared, any attempted write by bus master 6 terminates with an access error and the write is not performed. 4 m5re bus master 5 read enable. if set, this flag allows bus master 5 to perform read operations. if cleared, any attempted read by bus master 5 terminates with an access error and the read is not performed. 5 m5we bus master 5 write enable. if set, this flag allows bus master 5 to perform write operations. if cleared, any attempted write by bus master 5 terminates with an access error and the write is not performed. 6 m4re bus master 4 read enable. if set, this flag allows bus master 4 to perform read operations. if cleared, any attempted read by bus master 4 terminates with an access error and the read is not performed. 7 m4we bus master 4 write enable. if set, this flag allows bus master 4 to perform write operations. if cleared, any attempted write by bus master 4 terminates with an access error and the write is not performed.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 24-11 preliminary?subject to change without notice 8 m3pe bus master 3 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 9?10 m3sm bus master 3 supervisor mode access control. this 2- bit field defines the access controls for bus master 3 when operating in supervisor mode. the m3sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m3um for user mode 11?13 m3um bus master 3 user mode access control. this 3-bit field defines the access controls for bus master 3 when operating in user mode. the m3um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allo ws the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. 14 m2pe bus master 2 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 15?16 m2sm bus master 2 supervisor mode access control. this 2- bit field defines the access controls for bus master 2 when operating in supervisor mode. the m2sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m2um for user mode 17?19 m2um bus master 2 user mode access control. this 3-bit field defines the access controls for bus master 2 when operating in user mode. the m2um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allo ws the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. 20 m1pe bus master 1 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 21?22 m1sm bus master 1 supervisor mode access control. this 2- bit field defines the access controls for bus master 1 when operating in supervisor mode. the m1sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m1um for user mode 23?25 m1um bus master 1 user mode access control. this 3-bit field defines the access controls for bus master 1 when operating in user mode. the m1um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allo ws the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. 26 m0pe bus master 0 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. table 24-7. mpu_rgdn.word2 field descriptions field description
pxd10 microcontroller reference manual, rev. 1 24-12 freescale semiconductor preliminary?subject to change without notice 24.2.2.4.4 mpu region descriptor n, word 3 (mpu_rgdn.word3) the fourth word of the mpu region descriptor contains the optional process identi fier and mask, plus the region descriptor?s valid bit. since the region descriptor is a 128-bi t entity, there are potential coherency issues as this structure is being updated since multiple writes are required to update the entire descriptor. ac cordingly, the mpu hardware assists in the operation of the descri ptor valid bit to preven t incoherent region desc riptors from generating spurious access errors. in pa rticular, it is expected th at a complete update of a re gion descriptor is typically done with sequential writes to mpu_rgdn.word0, then mpu_rgdn.word1,... and finally mpu_rgdn.word3. the mpu hardware automatically clears the valid bit on any writes to words {0,1,2} of the descriptor. writes to this word set/clear the valid bit in a normal manner. since it is also expected that system software may ad just only the access controls within a region descriptor (mpu_rgdn.word2) as different tasks execute, an alternate programming view of this 32-bit entity is provided. if only the access controls are being updated, this operation s hould be performed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect the descriptor?s valid bit. 27?28 m0sm bus master 0 supervisor mode access control. this 2- bit field defines the access controls for bus master 0 when operating in supervisor mode. the m0sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m0um for user mode 29?31 m0um bus master 0 user mode access control. this 3-bit field defines the access controls for bus master 0 when operating in user mode. the m0um field consis ts of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allo ws the given access type to occur; if cleared, an attempted access of that mode may be terminated wi th an access error (if not allowed by any other descriptor) and the access not performed. offset mpu_base + 0x400 + (16*n) + 0xc (mpu_rgdn.word3) access: r/w 012345678910111213141516171819202122232425262728293031 r pid pidmask 00 00000000 00 0 0 0vl d w reset ---------------- 00000 00000000000 figure 24-8. mpu region descriptor, word 3 register (mpu_rgdn.word3) table 24-7. mpu_rgdn.word2 field descriptions field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 24-13 preliminary?subject to change without notice 24.2.2.5 mpu region descri ptor alternate access control n (mpu_rgdaacn) as noted in section 24.2.2.4.3, mpu region descript or n, word 2 (mpu_rgdn.word2) , it is expected that since system software may adjust only the access controls within a region descriptor (mpu_rgdn.word2) as different tasks execute, an alternate programming view of this 32-bit entity is desired. if only the access controls are being update d, this operation should be performed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect the descriptor?s valid bit. the memory address therefore provides an alternate location for updating mpu_rgdn.word2. since the mpu_rgdaacn register is simply anot her memory mapping for mpu_rgdn.word2, the field definitions shown in table 24-9 are identical to those presented in table 24-7 . table 24-8. mpu_rgdn.word3 field descriptions field description 0?7 pid process identifier. this 8-bit field specifies that the optional process id entifier is to be included in the determination of whether the current access hits in th e region descriptor. this field is combined with the pidmask and included in the region hit deter mination if mpu_rgdn.word2[mxpe] is set. 8?15 pidmask process identifier mask. this 8-bit field provides a ma sking capability so that mu ltiple process identifiers can be included as part of the region hit determi nation. if a bit in the pidmask is set, then the corresponding bit of the pid is ignored in the comparison. this field is combined with the pid and included in the region hit determination if mpu_rg dn.word2[mxpe] is set. for more information on the handling of the pid and pidmask, see section 24.3.1.1, access ev aluation - hit determination . 31 vld valid. this bit signals the region descriptor is valid. any write to mpu_rgdn.word{0,1,2} clears this bit, while a write to mpu_rgdn.word3 sets or clears this bit depending on bit 31 of the write operand. 0 region descriptor is invalid 1 region descriptor is valid offset mpu_base + 0x800 + (4*n ) (mpu_rgdaacn) access: r/w 012345678 9101112131 4 15 16 17 18 19 2 0 21 22 23 24 25 2 6 27 28 29 30 31 r m 7 r e m 7 w e m 6 r e m 6 w e m 5 r e m 5 w e m 4 r e m 4 w e m 3 p e m3sm m3um r w x m 2 p e m2sm m2um r w x m 1 p e m1sm m1um r w x m 0 p e m0sm m0um r w x w reset --------------------------- ----- figure 24-9. mpu rgd alternate access control n (mpu_rgdaacn) table 24-9. mpu_rgdaacn field descriptions field description 0 m7re bus master 7 read enable. if set, this flag allows bu s master 7 to perform read operations. if cleared, any attempted read by bus master 7 terminates with an access error and the read is not performed. 1 m7we bus master 7 write enable. if set, this flag allows bus master 7 to perform write operations. if cleared, any attempted write by bus master 7 terminates with an access error and the write is not performed. 2 m6re bus master 6 read enable. if set, this flag allows bu s master 6 to perform read operations. if cleared, any attempted read by bus master 6 terminates with an access error and the read is not performed.
pxd10 microcontroller reference manual, rev. 1 24-14 freescale semiconductor preliminary?subject to change without notice 3 m6we bus master 6 write enable. if set, this flag allows bus master 6 to perform write operations. if cleared, any attempted write by bus master 6 terminates with an access error and the write is not performed. 4 m5re bus master 5 read enable. if set, this flag allows bu s master 5 to perform read operations. if cleared, any attempted read by bus master 5 terminates with an access error and the read is not performed. 5 m5we bus master 5 write enable. if set, this flag allows bus master 5 to perform write operations. if cleared, any attempted write by bus master 5 terminates with an access error and the write is not performed. 6 m4re bus master 4 read enable. if set, this flag allows bu s master 4 to perform read operations. if cleared, any attempted read by bus master 4 terminates with an access error and the read is not performed. 7 m4we bus master 4 write enable. if set, this flag allows bus master 4 to perform write operations. if cleared, any attempted write by bus master 4 terminates with an access error and the write is not performed. 8 m3pe bus master 3 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in th e region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 9?10 m3sm bus master 3 supervisor mode access control. this 2-bit field defines the access controls for bus master 3 when operating in supervisor mode. the m3sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m3um for user mode 11?13 m3um bus master 3 user mode access control. this 3-bit field defines the access controls for bus master 3 when operating in user mode. the m3um field cons ists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. 14 m2pe bus master 2 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in th e region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 15?16 m2sm bus master 2 supervisor mode access control. this 2-bit field defines the access controls for bus master 2 when operating in supervisor mode. the m2sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m2um for user mode 17?19 m2um bus master 2 user mode access control. this 3-bit field defines the access controls for bus master 2 when operating in user mode. the m2um field cons ists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. 20 m1pe bus master 1 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in th e region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. table 24-9. mpu_rgdaacn field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 24-15 preliminary?subject to change without notice 24.3 functional description in this section, the functional operati on of the mpu is detailed. in partic ular, subsequent sections discuss the operation of the access evaluation macro as well as the handling of error-terminated ahb bus cycles. 24.3.1 access evaluation macro as previously discussed, the basic operation of th e mpu is performed in the access evaluation macro, a hardware structure replicated in the two- dimensional connection matrix. as shown in figure 24-10 , the access evaluation macro inputs the ah b system bus address phase signals (ahb_ap) and the contents of a region descriptor (rgdn) and performs two majo r functions: region hit determination (hit_b) and detection of an access pr otection violation (error). 21?22 m1sm bus master 1 supervisor mode access control. this 2-bit field defines the access controls for bus master 1 when operating in supervisor mode. the m1sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m1um for user mode 23?25 m1um bus master 1 user mode access control. this 3-bit field defines the access controls for bus master 1 when operating in user mode. the m1um field cons ists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. 26 m0pe bus master 0 process identifier enable. if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in th e region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. 27?28 m0sm bus master 0 supervisor mode access control. this 2-bit field defines the access controls for bus master 0 when operating in supervisor mode. the m0sm field is defined as: 0b00 r, w, x = read, write and execute allowed 0b01 r, ?, x = read and execute allowed, but no write 0b10 r, w, ? = read and write allowed, but no execute 0b11 same access controls as that defined by m0um for user mode 29?31 m0um bus master 0 user mode access control. this 3-bit field defines the access controls for bus master 0 when operating in user mode. the m0um field cons ists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. table 24-9. mpu_rgdaacn field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 24-16 freescale semiconductor preliminary?subject to change without notice figure 24-10. mpu access evaluation macro figure 24-10 is not intended to be a schematic of th e actual access evaluation macro, but rather a generalized block diagram showing the majo r functions included in this logic block. 24.3.1.1 access evaluati on - hit determination to evaluate the region hit determination, the mpu us es two magnitude comparators in conjunction with the contents of a region descriptor : the current access must be include d between the region's "start" and "end" addresses and simult aneously the region's valid bit must be active. recall there are no hardware checks to verify that region's "end" a ddress is greater then region's "start" address, and it is software?s respons ibility to properly load appropriate values into these fields of the region descriptor. in addition to this, the optional process identifier is examined against the region descriptor?s pid and pidmask fields. in order to generate the pid_hit i ndication: the current pid with its pidmask must be equal to the region's pid with its pidm ask. also the process identifier enab le is take into account in this comparison so that the mpu forces the pid_hit term to be asserted in the case of ahb bus master does not provide its process identifier. 24.3.1.2 access evaluation - priv ilege violation determination while the access evaluation macro is making the region hit determinat ion, the logic is also evaluating if the current access is allowed by the permissions define d in the region descriptor . the protection violation hit_b start end error > > rgdn ahb_ap hit & error hit_b | error >= <= r,w,x
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 24-17 preliminary?subject to change without notice logic then evaluates the access against the effect ive permissions using the specification shown in table 24-10 . as shown in figure 24-10 , the output of the protection viol ation logic is the error signal. the access evaluation macro then uses the hit_b and error signals to form two outputs. the combined (hit_b | error) signal is used to signa l the current access is not allowed a nd (~hit_b & error) is used as the input to mpu_edrn (error detail re gister) in the event of an error. 24.3.2 putting it all together and ahb error terminations for each ahb slave port being monitored, the mpu perf orms a reduction-and of al l the individual (hit_b | error) terms from each access eval uation macro. this expression then terminates the bus cycle with an error and reports a protecti on error for three conditions: 1. if the access does not hit in any region descriptor, a protection error is reported. 2. if the access hits in a single region descriptor and that region si gnals a protection violation, then a protection error is reported. 3. if the access hits in multiple (overlapping) regions a nd all regions signal prot ection violations, then a protection error is reported. the third condition reflects that priority is given to permission granting over access denying for overlapping regions as this approach provides more flexibility to syst em software in region descriptor assignments. for an example of the use of overlapping region descriptors, see section 24.5, application information . in event of a protection error, th e mpu requires two distinct actions: 1. intercepts the error during the ahb address pha se (first cycle out of two) and cancels the transaction before it is seen by the slave device. 2. performs the required logic func tions to force the sta ndard 2-cycle ahb erro r response to properly terminate the bus transaction and then provides the right values to the crossbar switch to commit the ahb transaction to other portions of the platform. table 24-10. protection violation definition description inputs output eff_rg d[r] eff_rgd[w] eff_rgd[x] protection violation? inst fetch read - - 0 yes, no x permission inst fetch read - - 1 no, access is allowed data read 0 - - yes, no r permission data read 1 - - no, access is allowed data write - 0 - yes, no w permission data write - 1 - no, access is allowed
pxd10 microcontroller reference manual, rev. 1 24-18 freescale semiconductor preliminary?subject to change without notice if instead the access is allowed, then the mpu simply pa sses all "original" ahb si gnals to the slave device. in this case, from functionality point of view, the mpu is fully transparent.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 24-19 preliminary?subject to change without notice 24.4 initialization information the reset state of mpu_cesr[vld] disables the enti re module. recall while th e mpu is disabled, all accesses from all bus masters are allowed. this stat e also minimizes the power dissipation of the mpu. the power dissipation of each access evaluation macro is minimized when the associated region descriptor is marked as invalid or when mpu_cesr[vld] = 0. typically the appropriate number of region desc riptors (mpu_rgdn) are load ed at system startup, including the setting of the mpu_rgdn.word3[vld] bi ts, before mpu_cesr[vld] is set, enabling the module. this approach allows all the loaded region de scriptors to be enabled si multaneously. recall if a memory reference does not hit in an y region descriptor, the attempted acc ess is terminated with an error. 24.5 application information in an operational system, interfacing with the mpu can generally be classi fied into the following activities: 1. creation of a new memory region requires load ing the appropriate region descriptor into an available register location. when a new descriptor is loaded into a rgdn, it would typically be performed using four 32-bit wo rd writes. as discussed in section 24.2.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) ?, the hardware assists in the maintenance of the valid bit, so if this approach is foll owed, there are no coherency issues associated with the multi-cycle descriptor writes. deletion/remova l of an existing memory region is performed simply by clearing mpu_rgdn.word3[vld]. 2. if only the access rights for an existing region de scriptor need to change , a 32-bit write to the alternate version of the access control word (mpu_rgdaacn) would t ypically be performed. recall writes to the region descriptor using this alternate access control location do not affect the valid bit, so there are, by de finition, no coherency issues invol ved with the update. the access rights associated with the memory region switch in stantaneously to the new value as the ips write completes. 3. if the region?s start and end addresses are to be changed, this would typically be performed by writing a minimum of three words of the re gion descriptor: mpu_rgdn.word{0,1,3}, where the writes to word0 and word1 redefine the start and end addresses respectively and the write to word3 re-enables the region descri ptor valid bit. in many situati ons, all four words of the region descriptor would be rewritten. 4. typically, references to the mpu?s programming m odel would be restricted to supervisor mode accesses from a specific processor(s) , so a region descriptor would be specifically allocated for this purpose with attempted accesses from other masters or while in user mode terminated with an error. 5. when the mpu detects an access error, the curren t ahb bus cycle is terminated with an error response and information on the faulting reference captured in the mpu_earn and mpu_edrn registers. the error-terminated ahb bus cycle typical ly initiates some type of error response in the originating bus master. for example, a proce ssor core may respond with a bus error exception, while a data movement bus master may respond with an error interr upt. in any event, the processor can retrieve the captured error address and detail information simply be reading the mpu_e{a,d}rn registers. information on which er ror registers contain ca ptured fault data is signaled by mpu_cesr[sperr].
pxd10 microcontroller reference manual, rev. 1 24-20 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-1 preliminary?subject to change without notice chapter 25 mode entry module (mc_me) 25.1 introduction 25.1.1 overview the mc_me controls the device mode and mode transition sequences in all functional states. it also contains configuration, control and status registers accessible for the application. figure 25-1 depicts the mc_me block diagram.
pxd10 microcontroller reference manual, rev. 1 25-2 freescale semiconductor preliminary?subject to change without notice registers platform interface core mc_me figure 25-1. mc_meblock diagram mc_rgm fxosc fmpll0 fmpll1 firc mc_cgm mc_pcu peripherals flashes vreg device mode state machine wkpu
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-3 preliminary?subject to change without notice 25.1.2 features the mc_me includes the following features: ? control of the available modes by the me_me register ? definition of various device m ode configurations by the me_ _mc registers ? control of the actual devi ce mode by the me_mctl register ? capture of the current m ode and various res ource status within the cont ents of the me_gs register ? optional generation of various mode transition interrupts ? status bits for each cause of invalid mode transitions ? peripheral clock gating control base d on the me_run_pc0?7, me_lp_pc0?7, and me_pctl0?143 registers ? capture of current peripher al clock gated/enabled status 25.1.3 modes of operation the mc_me is based on several device modes corres ponding to different usage models of the device. each mode is configurable and ca n define a policy for energy and pr ocessing power management to fit particular system requirements. an application can easily switch fr om one mode to another depending on the current needs of the system. the operating modes controlled by the mc_me are divided into system and user modes. the system modes are modes such as reset, drun, safe, and test. these modes aim to ease the configurat ion and monitoring of the system. the user modes ar e modes such as run0?3, halt, stop, and standby which can be configured to meet the app lication requirements in terms of energy management and av ailable processing power. the mode s drun, safe, test, and run0?3 are the device software running modes. table 25-1 describes the mc_me modes. table 25-1. mc_me mode descriptions name description entry exit reset this is a chip-wide virtual mo de during which the application is not active. the system remains in this mode until all resources are available for the embedded software to take control of the device. it manages hardware initialization of chip configuration, voltage regulators, oscillators, plls, and flash modules. system reset assertion from mc_rgm system reset deassertion from mc_rgm drun this is the entry mode for the embedded software. it provides full accessibility to the system and e nables the configuration of the system at startup. it provides the unique gate to enter user modes. bam when present is executed in drun mode. system reset deassertion from mc_rgm, software request from safe, test and run0?3, wakeup request from standby system reset assertion, run0?3, test, standby via software, safe via software or hardware failure. safe this is a chip-wide service mode which may be entered on the detection of a recoverable error. it forces the system into a pre-defined safe configuration from which the system may try to recover. hardware failure, software request from drun, test, and run0?3 system reset assertion, drun via software
pxd10 microcontroller reference manual, rev. 1 25-4 freescale semiconductor preliminary?subject to change without notice 25.2 external signal description the mc_me has no connectio ns to any external pins . 25.3 memory map and register definition the mc_me contains registers for: ? mode selection and status reporting ? mode configuration ? mode transition interrupts status and mask control ? scalable number of peripheral sub-m ode selection and status reporting test this is a chip-wide service m ode which is intended to provide a control environment for device self-test. it may enable the application to run its own self-test like flash checksum, memory bist etc. software request from drun system reset assertion, drun via software run0?3 these are software running modes where most processing activity is done. these various run modes allow to enable different clock & power configurat ions of the system with respect to each other. software request from drun, interrupt event from halt, interrupt or wakeup event from stop system reset assertion, safe via software or hardware failure, other run0?3 modes, halt, stop, standby via software halt this is a reduced-activity low- power mode during which the clock to the core is disabled. it can be configured to switch off analog peripherals like pll, flash, main regulator etc. for efficient power management at the cost of higher wakeup latency. software request from run0?3 system reset assertion, safe on hardware failure, run0?3 on interrupt event stop this is an advanced low-power mode during which the clock to the core is disabled. it may be configured to switch off most of the peripherals including oscillator for efficient power management at the cost of higher wakeup latency. software request from run0?3 system reset assertion, safe on hardware failure, run0?3 on interrupt event or wakeup event standby this is a reduced-leakage low-power mode during which power supply is cut off from most of the device. wakeup from this mode takes a relatively long time, and content is lost or must be restored from backup. software request from run0?3, drun modes system reset assertion, drun on wakeup event table 25-1. mc_me mode descriptions (continued) name description entry exit
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-5 preliminary?subject to change without notice 25.3.1 memory map table 25-2. mc_me register description address name description size access 0xc3fd_c000 me_gs global status word read 0xc3fd_c004 me_mctl mode control word read/write 0xc3fd_c008 me_me mode enable word read/write 0xc3fd_c00c me_is interrupt status word read/write 0xc3fd_c010 me_im interrupt mask word read/write 0xc3fd_c014 me_imts invalid mode transition status word read/write 0xc3fd_c018 me_dmts debug mode transtion status word read 0xc3fd_c020 me_reset_mc reset mode configur ation word read 0xc3fd_c024 me_test_mc test mode configuration word read/write 0xc3fd_c028 me_safe_mc safe mode configuration word read/write 0xc3fd_c02c me_drun_mc drun mode configuration word read/write 0xc3fd_c030 me_run0_mc run0 mode configuration word read/write 0xc3fd_c034 me_run1_mc run1 mode configuration word read/write 0xc3fd_c038 me_run2_mc run2 mode configuration word read/write 0xc3fd_c03c me_run3_mc run3 mode configuration word read/write 0xc3fd_c040 me_halt_mc halt mode configuration word read/write 0xc3fd_c048 me_stop_mc stop mode configuration word read/write 0xc3fd_c054 me_standby_mc standby mode configuration word read/write 0xc3fd_c060 me_ps0 peripheral status 0 word read 0xc3fd_c064 me_ps1 peripheral status 1 word read 0xc3fd_c068 me_ps2 peripheral status 2 word read 0xc3fd_c06c me_ps3 peripheral status 3 word read 0xc3fd_c080 me_run_pc0 run peripheral configuration 0 word read/write 0xc3fd_c084 me_run_pc1 run peripheral configuration 1 word read/write ? 0xc3fd_c09c me_run_pc7 run peripheral configuration 7 word read/write 0xc3fd_c0a0 me_lp_pc0 low-power peripheral configuration 0 word read/write 0xc3fd_c0a4 me_lp_pc1 low-power peripheral configuration 1 word read/write ?
pxd10 microcontroller reference manual, rev. 1 25-6 freescale semiconductor preliminary?subject to change without notice note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content ? cause a transfer error 0xc3fd_c0bc me_lp_pc7 low-power peripheral configuration 7 word read/write 0xc3fd_c0c4 me_pctl4 dspi0 control byte read/write 0xc3fd_c0c5 me_pctl5 dspi1 control byte read/write 0xc3fd_c0ca me_pctl10 quadspi control byte read/write 0xc3fd_c0d0 me_pctl16 flexcan0 control byte read/write 0xc3fd_c0d1 me_pctl17 flexcan1 control byte read/write 0xc3fd_c0d7 me_pctl23 dma_ch_mux control byte read/write 0xc3fd_c0e0 me_pctl32 adc0 control byte read/write 0xc3fd_c0ec me_pctl44 i2c_dma0 control byte read/write 0xc3fd_c0ed me_pctl45 i2c_dma1 control byte read/write 0xc3fd_c0ee me_pctl46 i2c_dma2 control byte read/write 0xc3fd_c0ef me_pctl47 i2c_dma3 control byte read/write 0xc3fd_c0f0 me_pctl48 lin_flex0 control byte read/write 0xc3fd_c0f1 me_pctl49 lin_flex1 control byte read/write 0xc3fd_c0f8 me_pctl56 gaugedriver control byte read/write 0xc3fd_c0fc me_pctl60 cansampler control byte read/write 0xc3fd_c0fd me_pctl61 lcd control byte read/write 0xc3fd_c0fe me_pctl62 sgl control byte read/write 0xc3fd_c0ff me_pctl63 dcu control byte read/write 0xc3fd_c104 me_pctl68 siul control byte read/write 0xc3fd_c108 me_pctl72 emios0 control byte read/write 0xc3fd_c109 me_pctl73 emios1 control byte read/write 0xc3fd_c11b me_pctl91 rtc/api control byte read/write 0xc3fd_c11c me_pctl92 pit_rti control byte read/write 0xc3fd_c128 me_pctl104 cmu0 control byte read/write table 25-2. mc_me register description (continued) address name description size access
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-7 preliminary?subject to change without notice table 25-3. mc_me memory map address name 0123 4567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fd_c000 me_gs r s_current_mode s_mtrans 000 s_pdo 00 s_mvr s_dfla s_cfla w r s_fmpll1 s_fmpll0 s_fxosc s_firc s_sysclk w 0xc3fd_c004 me_mctl r ta r g e t _ m o d e 0000000 00000 w r1 0 1 0 0101000 01111 w key 0xc3fd_c008me_me r0 0 0 0 0000000 00000 w r0 0 standby 00 stop 0 halt run3 run2 run1 run0 drun safe test reset w 0xc3fd_c00cme_is r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 0 i_iconf i_imode i_safe i_mtc w w1c w1c w1c w1c 0xc3fd_c010me_im r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 0 m_iconf m_imode m_safe m_mtc w 0xc3fd_c014me_imts r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 s_mti s_mri s_dma s_nma s_sea w w1c w1c w1c w1c w1c
pxd10 microcontroller reference manual, rev. 1 25-8 freescale semiconductor preliminary?subject to change without notice 0xc3fd_c018 me_dmts r0 0 0 0 0000 mph_busy 00 pmc_prog core_dbg 00 smr w r0 fmpll0_sc fxosc_sc firc_sc ssclk_sc sysclk_sw dflash_sc cflash_sc cdp_prph_0_143 00 cdp_prph_96_127 cdp_prph_64_95 cdp_prph_32_63 cdp_prph_0_31 w 0xc3fd_c01c reserved 0xc3fd_c020 me_reset_mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd_c024 me_test_mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd_c028 me_safe_mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r fmpll1on fmpll0on fxoscon fircon sysclk w table 25-3. mc_me memory map (continued) address name 0123 4567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-9 preliminary?subject to change without notice 0xc3fd_c02c me_drun_mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd_c030 ? 0xc3fd_c03c me_run0?3_mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd_c040 me_halt_mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd_c044 reserved 0xc3fd_c048 me_stop_mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r0 0 0 0 0000 fmpll1on fmpll0on fxoscon fircon sys clk w 0xc3fd_c04c ? 0xc3fd_c050 reserved table 25-3. mc_me memory map (continued) address name 0123 4567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 25-10 freescale semiconductor preliminary?subject to change without notice 0xc3fd_c054 me_standby_mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r fmpll1on fmpll0on fxoscon fircon sysclk w 0xc3fd_c058 ? 0xc3fd_c05c reserved 0xc3fd_c060 me_ps0 r s_bam s_dma_ch_mux s_flexcan1 s_flexcan0 w r s_quadspi s_quadspi s_dspi1 s_dspi0 w 0xc3fd_c064 me_ps1 r s_dcu s_sgl s_lcd s_cansampler s_gaugedriver s_lin_flex1 s_lin_flex0 w r s_i2c_dma3 s_i2c_dma2 s_i2c_dma1 s_i2c_dma0 s_adc0 w table 25-3. mc_me memory map (continued) address name 0123 4567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-11 preliminary?subject to change without notice 0xc3fd_c068 me_ps2 r s_pit_rti s_rtc_api s_mc_pcu s_mc_rgm s_mc_cgm s_mc_me s_sscm w r s_cflash1 s_emios1 s_emios0 s_wkpu s_siul s_dflash0 s_cflash0 w 0xc3fd_c06c me_ps3 r w r s_cmu0 w 0xc3fd_c070 reserved 0xc3fd_c074 ? 0xc3fd_c07c reserved 0xc3fd_c080 ? 0xc3fd_c09c me_run_pc0?7 r0 0 0 0 0000000 00000 w r0 0 0 0 0000 run3 run2 run1 run0 drun safe test reset w 0xc3fd_c0a0 ? 0xc3fd_c0bc me_lp_pc0?7 r0 0 0 0 0000000 00000 w r0 0 standby 00 stop 0 halt 00000000 w table 25-3. mc_me memory map (continued) address name 0123 4567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 25-12 freescale semiconductor preliminary?subject to change without notice 25.3.2 register description unless otherwise noted, all registers may be accessed as 32-bit word s, 16-bit half-words, or 8-bit bytes. the bytes are ordered accor ding to big endian. for example, the me_run_pc0 register may be accessed as a word at address 0xc3fd_c080, as a half-word at address 0xc3f d_c082, or as a byte at address 0xc3fd_c083. 25.3.2.1 global status register (me_gs) this register contains global mode status. 0xc3fd_c0c0 ? 0xc3fd_c14c me_pctl0?143 r 0 dbg_f lp_cfg run_cfg 0 dbg_f lp_cfg run_cfg w r0 dbg_f lp_cfg run_cfg 0 dbg_f lp_cfg run_cfg w 0xc3fd_c150 ? 0xc3fd_fffc reserved address 0xc3fd_c000 access: supervisor read 0123456789101112131415 r s_current_mode s_mtrans 000 s_pdo 00 s_mvr s_dfla s_cfla w reset0000100000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r s_fmpll1 s_fmpll0 s_fxosc s_firc s_sysclk w reset0000000000010000 figure 25-2. global status register (me_gs) table 25-3. mc_me memory map (continued) address name 0123 4567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-13 preliminary?subject to change without notice table 25-4. global status register (me_gs) field descriptions field description s_curren t_mode current device mode status 0000 reset 0001 test 0010 safe 0011 drun 0100 run0 0101 run1 0110 run2 0111 run3 1000 halt 1001 reserved 1010 stop 1011 reserved 1100 reserved 1101 standby 1110 reserved 1111 reserved s_mtrans mode transition status 0 mode transition process is not active 1 mode transition is ongoing s_pdo output power-down status ? this bit specifies output power-down status of i/os. this bit is asserted whenever outputs of pads are forced to high impedance state or the pads power sequence driver is switched off. 0 no automatic safe gating of i/os used an d pads power sequence driver is enabled 1 in safe/test modes, outputs of pads are forced to high impedance stat e and pads power sequence driver is disabled. the inputs are level unchanged. in stop mode, only pad power sequence driver is disabled but the state of the output is kept. in standby mode, the power sequence driver and all pads except those mapped on wakeup lines are not powered and therefor e high impedance. wakeup lines configuration remains unchanged s_mvr main voltage regulator status 0 main voltage regulator is not ready 1 main voltage regulator is ready for use s_dfla data flash availability status 00 data flash is not available 01 data flash is in power-down mode 10 data flash is in low-power mode 11 data flash is in normal mode and available for use s_cfla code flash availability status 00 code flash is not available 01 code flash is in power-down mode 10 code flash is in low-power mode 11 code flash is in normal mode and available for use s_ssclk1 secondary system clock source 1 status 0 secondary system clock source 1 is not stable 1 secondary system clock source 1 is providing a stable clock s_fmpll1 secondary frequency modulated phase locked loop status 0 secondary frequency modulated phase locked loop is not stable 1 secondary frequency modulated phase locked loop is providing a stable clock s_fmpll0 primary frequency modulated phase locked loop status 0 primary frequency modulated phase locked loop is not stable 1 primary frequency modulated phase locked loop is providing a stable clock
pxd10 microcontroller reference manual, rev. 1 25-14 freescale semiconductor preliminary?subject to change without notice 25.3.2.2 mode control register (me_mctl) this register is used to trigger software-controlle d mode changes. depending on the modes as enabled by me_me register bits, configurati ons corresponding to unavailable mo des are reserved and access to me_ _mc registers must respect this for successful mode requests. s_fxosc fast external crystal oscillator (4-16mhz) status 0 fast external crystal oscillator (4-16mhz) is not stable 1 fast external crystal oscillator (4-16mhz) is providing a stable clock s_firc fast internal rc oscillator (16mhz) status 0 fast internal rc oscillator (16mhz) is not stable 1 fast internal rc oscillator (16mhz) is providing a stable clock s_sysclk system clock switch status ? these bits specify the system clock currently used by the system. 0000 16mhz int. rc osc. 0001 div. 16mhz int. rc osc. 0010 reserved 0011 div. 4-16mhz ext. osc. 0100 primary freq. mod. pll 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled address 0xc3fd_c004 access: supervisor read/write 0123456789101112131415 r ta r g e t _ m o d e 000000000000 w reset0011000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r1010010100001111 w key reset1010010100001111 figure 25-3. mode control register (me_mctl) table 25-4. global status register (me_gs) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-15 preliminary?subject to change without notice note byte and half-word write accesses are not allowed fo r this register as a predefined key is required to change its value. 25.3.2.3 mode enable register (me_me) table 25-5. mode control register (me_mctl) field descriptions field description ta r g e t _ m ode target device mode ? these bits provide the target device mode to be entered by software programming. the mechanism to enter into any mode by software requires t he write operation twice: first time with key, and second time with inverted key. these bits are automatically updated by hardware while entering safe on hardware request. also, while exiting from the halt and stop modes on hardware exit events, these are updated with the appropriate run0?3 mode value. 0000 reset 0001 test 0010 safe 0011 drun 0100 run0 0101 run1 0110 run2 0111 run3 1000 halt 1001 reserved 1010 stop 1011 reserved 1100 reserved 1101 standby 1110 reserved 1111 reserved key control key ? these bits enable writ e access to this register. any writ e access to the re gister with a value different from the keys is ignored. read access will always return inverted key. key: 0101101011110000 (0x5af0) inverted key: 1010010100001111 (0xa50f) address 0xc3fd_c008 access: supervisor read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00 standby 00 stop 0 halt run3 run2 run1 run0 drun safe test reset w reset0000000000011111 figure 25-4. mode enable register (me_me)
pxd10 microcontroller reference manual, rev. 1 25-16 freescale semiconductor preliminary?subject to change without notice this register allows a way to disable the device modes which are not required for a given device. reset , safe , drun , and run0 modes are always enabled. table 25-6. mode enable register (me_me) field descriptions field description standby standby mode enable 0 standby mode is disabled 1 standby mode is enabled stop stop mode enable 0 stop mode is disabled 1 stop mode is enabled halt halt mode enable 0 halt mode is disabled 1 halt mode is enabled run3 run3 mode enable 0 run3 mode is disabled 1 run3 mode is enabled run2 run2 mode enable 0 run2 mode is disabled 1 run2 mode is enabled run1 run1 mode enable 0 run1 mode is disabled 1 run1 mode is enabled run0 run0 mode enable 0 run0 mode is disabled 1 run0 mode is enabled drun drun mode enable 0 drun mode is disabled 1 drun mode is enabled safe safe mode enable 0 safe mode is disabled 1 safe mode is enabled test test mode enable 0 test mode is disabled 1 test mode is enabled reset reset mode enable 0 reset mode is disabled 1 reset mode is enabled
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-17 preliminary?subject to change without notice 25.3.2.4 interrupt status register (me_is) this register provides the current interrupt status. address 0xc3fd_c00c access: supervisor read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 i_iconf i_imode i_safe i_mtc w w1c w1c w1c w1c reset0000000000000000 figure 25-5. interrupt status register (me_is) table 25-7. interrupt status register (me_is) field descriptions field description i_iconf invalid mode configuration interrupt ? this bit is set whenever a write operation to me_< mode >_mc registers with invalid mode configur ation is attempted. it is clear ed by writing a ?1? to this bit. 0 no invalid mode configuration interrupt occurred 1 invalid mode configuration interrupt is pending i_imode invalid mode interrupt ? this bit is set whenever an invalid mode tr ansition is requested. it is cleared by writing a ?1? to this bit. 0 no invalid mode interrupt occurred 1 invalid mode interrupt is pending i_safe safe mode interrupt ? this bit is set whenever th e device enters safe mode on hardware requests generated in the system. it is cleared by writing a ?1? to this bit. 0 no safe mode interrupt occurred 1 safe mode interrupt is pending i_mtc mode transition co mplete interrupt ? this bit is set whenever the mode transition process completes (s_mtrans transits from 1 to 0). it is cleared by writing a ?1? to this bit. this mode transition interrupt bit will not be set while entering low-power modes halt, stop, or standby. 0 no mode transition complete interrupt occurred 1 mode transition complete interrupt is pending
pxd10 microcontroller reference manual, rev. 1 25-18 freescale semiconductor preliminary?subject to change without notice 25.3.2.5 interrupt mask register (me_im) this register controls whether an event generates an interrupt or not. address 0xc3fd_c010 access: supervisor read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 m_iconf m_imode m_safe m_mtc w reset0000000000000000 figure 25-6. interrupt mask register (me_im) table 25-8. interrupt mask register (me_im) field descriptions field description m_iconf invalid mode configuration interrupt mask 0 invalid mode interrupt is masked 1 invalid mode interrupt is enabled m_imode invalid mode interrupt mask 0 invalid mode interrupt is masked 1 invalid mode interrupt is enabled m_safe safe mode interrupt mask 0 safe mode interrupt is masked 1 safe mode interrupt is enabled m_mtc mode transition comp lete interrupt mask 0 mode transition complete interrupt is masked 1 mode transition complete interrupt is enabled
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-19 preliminary?subject to change without notice 25.3.2.6 invalid mode transiti on status register (me_imts) this register provides the st atus bits for each cause of invalid mode interrupt. address 0xc3fd_c014 access: supervisor read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000000 s_mti s_mri s_dma s_nma s_sea w w1cw1cw1cw1cw1c reset0000000000000000 figure 25-7. invalid mode transition status register (me_imts) table 25-9. invalid mode transition status register (me_imts) field descriptions field description s_mti mode transition illegal status ? this bit is set whenever a new mode is requested while some other mode transition process is active (s_mtrans is ?1?). please refer to section 25.4.5, mode transition interrupts for the exceptions to this behavior. it is cleared by writing a ?1? to this bit. 0 mode transition requested is not illegal 1 mode transition requested is illegal s_mri mode request illegal status ? this bit is set whenever the target mode requested is not a valid mode with respect to current mode. it is cleared by writing a ?1? to this bit. 0 target mode requested is not illegal with respect to current mode 1 target mode requested is illegal with respect to current mode s_dma disabled mode access status ? this bit is set whenever the target m ode requested is one of those disabled modes determined by me_me register. it is cleared by writing a ?1? to this bit. 0 target mode requested is not a disabled mode 1 target mode requested is a disabled mode s_nma non-existing mode access status ? this bit is set whenever the tar get mode requested is one of those non existing modes determined by me_me register. it is cleared by writing a ?1? to this bit. 0 target mode requested is an existing mode 1 target mode requested is a non-existing mode s_sea safe event active status ? this bit is set whenev er the device is in safe mode, safe event bit is pending and a new mode requested other than reset/safe modes. it is cleared by writing a ?1? to this bit. 0 no new mode requested other than re set/safe while safe event is pending 1 new mode requested other than r eset/safe while safe event is pending
pxd10 microcontroller reference manual, rev. 1 25-20 freescale semiconductor preliminary?subject to change without notice 25.3.2.7 debug mode transition status register (me_dmts) this register provides the status of different factors which influence mode transitions. it is used to give an indication of why a mode tran sition indicated by me_gs.s_mtra ns may be taking longer than expected. note the me_dmts register does not indi cate whether a mode transition is ongoing. therefore, some me_dmts bits may still be asserted after the mode transition has completed. address 0xc3fd_c018 access: supervisor read/write 0123456789101112131415 r 00000000 mph_busy 00 pmc_prog core_dbg 00 smr w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 fmpll0_sc fxosc_sc firc_sc ssclk_sc sysclk_sw dflash_sc cflash_sc cdp_prph_0_143 00 cdp_prph_96_127 cdp_prph_64_95 cdp_prph_32_63 cdp_prph_0_31 w reset0000000000000000 figure 25-8. debug mode transition status register (me_dmts) table 25-10. debug mode transition status register (me_dmts) field descriptions field description mph_busy mc_me/mc_pcu handshake busy indicator ? this bit is set if the mc_me has requested a mode change from the mc_pcu and the mc_pcu has not yet responded. it is cleared when the mc_pcu has responded. 0 handshake is not busy 1 handshake is busy pmc_prog mc_pcu mode change in progress indicator ? this bit is set if the mc_pcu is in the process of powering up or down power domains. it is cleared when all power-up/down processes have completed. 0 power-up/down transition is not in progress 1 power-up/down transition is in progress core_dbg processor is in debug mode indicator ? this bit is set while the processor is in debug mode. 0 the processor is not in debug mode 1 the processor is in debug mode
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-21 preliminary?subject to change without notice smr safe mode request from mc_rgm is active indicator ? this bit is set if a hardware safe mode request has been triggered. it is cleared when the hardware safe mode request has been cleared. 0 a safe mode request is not active 1 a safe mode request is active fmpll0_sc fmpll0 state change during mode transition indicato r ? this bit is set when the primary frequency modulated phase locked loop is requested to change its power up/d own state. it is cleared when the primary frequency modulated phase locked loop has completed its state change. 0 no state change is taking place 1 a state change is taking place fxosc_sc fxosc state change during mode transition indicator ? th is bit is set when the fast external crystal oscillator (4-16mhz) is requested to change its power up/down state. it is cleared when the fast external crystal oscillator (4-16mhz) has completed its state change. 0 no state change is taking place 1 a state change is taking place firc_sc firc state change during mode transition indicator ? this bit is set when the fast internal rc oscillator (16mhz) is requested to change its po wer up/down state. it is cleared when the fast internal rc oscillator (16mhz) has completed its state change. 0 no state change is taking place 1 a state change is taking place ssclk_sc secondary system clock sources state change during mode transition indicator ? this bit is set when a secondary system clock source is requested to change its power up/down state. it is cleared when all secondary system clock sources have completed their state changes. (a ?secondary system clock? source is a system clock source other than firc, fxosc, or fmpll0.) 0 no state change is taking place 1 a state change is taking place sysclk_s w system clock switching pending status ? 0 no system clock source switching is pending 1 a system clock source switching is pending dflash_sc dflash state change during mode transition indica tor ? this bit is set when the dflash is requested to change its power up/down state. it is cleared wh en the dflash has completed its state change. 0 no state change is taking place 1 a state change is taking place cflash_sc cflash state change during mode transition indica tor ? this bit is set when the cflash is requested to change its power up/down state. it is cleared wh en the dflash has completed its state change. 0 no state change is taking place 1 a state change is taking place cdp_prph _0_143 clock disable process pending status for peripherals 0?143 ? this bit is set when any peripheral has been requested to have its clock disabled. it is cleared when all the peripherals which have been requested to have their clocks disabled have entered the stat e in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph _96_127 clock disable process pending status for peripherals 96?127 ? this bit is set when any peripheral appearing in me_ps3 has been requested to have its clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral table 25-10. debug mode transition status regi ster (me_dmts) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 25-22 freescale semiconductor preliminary?subject to change without notice 25.3.2.8 reset mode configur ation register (me_reset_mc) this register configures system behavi or during reset mode. please refer to table 25-11 for details. cdp_prph _64_95 clock disable process pending status for peripherals 64?95 ? this bit is set when any peripheral appearing in me_ps2 has been requested to have its clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph _32_63 clock disable process pending status for peripherals 32?63 ? this bit is set when any peripheral appearing in me_ps1 has been requested to have its clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral cdp_prph _0_31 clock disable process pending status for peripherals 0?31 ? this bit is set when any peripheral appearing in me_ps0 has been requested to have its clock disabled. it is cleared when all these peripherals which have been requested to have their clocks disabled have entered the state in which their clocks may be disabled. 0 no peripheral clock disabling is pending 1 clock disabling is pending for at least one peripheral address 0xc3fd_c020 access: supervisor read/write 0123456789101112131415 r 00000000pdo00 mvron dflaon cflaon w reset0000000000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 25-9. invalid mode transition status register (me_imts) table 25-10. debug mode transition status regi ster (me_dmts) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-23 preliminary?subject to change without notice 25.3.2.9 test mode configuration regi ster (me_test_mc) this register configures system beha vior during test mode. please refer to table 25-11 for details. note byte and half-word write accesses ar e not allowed to this register. 25.3.2.10 safe mode configur ation register (me_safe_mc) this register configures system behavi or during safe mode. please refer to table 25-11 for details. address 0xc3fd_c024 access: supervisor read/write 0123456789101112131415 r 00000000 pdo 00 mvron dflaon cflaon w reset0000000000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 25-10. test mode configuration register (me_test_mc) address 0xc3fd_c028 access: supervisor read/write 0123456789101112131415 r 00000000 pdo 00 mvron dflaon cflaon w reset0000000010011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 25-11. safe mode confi guration register (me_safe_mc)
pxd10 microcontroller reference manual, rev. 1 25-24 freescale semiconductor preliminary?subject to change without notice note byte and half-word write accesses ar e not allowed to this register. 25.3.2.11 drun mode configuration register (me_drun_mc) this register configures system beha vior during drun mode. please refer to table 25-11 for details. note byte and half-word write accesses ar e not allowed to this register. note the values of fxoscon, fmpll1on, cflaon and dflaon are retained through standby mode. address 0xc3fd_c02c access: supervisor read/write 0123456789101112131415 r 00000000pdo00 mvron dflaon cflaon w reset0000000000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 25-12. drun mode configuration register (me_drun_mc)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-25 preliminary?subject to change without notice 25.3.2.12 run0?3 mode conf iguration registers (me_run0 ? 3_mc) this register configures system behavior during run 0?3 modes. please refer to table 25-11 for details. note byte and half-word write accesses ar e not allowed to this register. 25.3.2.13 halt mode configurat ion register (me_halt_mc) this register configures system beha vior during halt mode. please refer to table 25-11 for details. note byte and half-word write accesses ar e not allowed to this register. address 0xc3fd_c030 - 0xc3fd_c03c access: supervisor read/write 0123456789101112131415 r 00000000pdo00 mvron dflaon cflaon w reset0000000000011111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 25-13. run0?3 mode confi guration registers (me_run0?3_mc) address 0xc3fd_c040 access: supervisor read/write 0123456789101112131415 r00000000pdo00 mvron dflaon cflaon w reset0000000000011010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 25-14. halt mode configuration register (me_halt_mc)
pxd10 microcontroller reference manual, rev. 1 25-26 freescale semiconductor preliminary?subject to change without notice 25.3.2.14 stop mode configur ation register (me_stop_mc) this register configures system behavi or during stop mode. please refer to table 25-11 for details. note byte and half-word write accesses ar e not allowed to this register. 25.3.2.15 standby mode configur ation register (me_standby_mc) this register configures system behavi or during standby mode . please refer to table 25-11 for details. address 0xc3fd_c048 access: supervisor read/write 0123456789101112131415 r00000000 pdo 00 mvron dflaon cflaon w reset0000000000010101 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000010000 figure 25-15. stop mode configuration register (me_stop_mc) address 0xc3fd_c054 access: supervisor read/write 0123456789101112131415 r 00000000pdo00 mvron dflaon cflaon w reset0000000010000101 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fmpll1on fmpll0on fxoscon fircon sysclk w reset0000000000011111 figure 25-16. standby mode confi guration register (me_standby_mc)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-27 preliminary?subject to change without notice note byte and half-word write accesses ar e not allowed to this register. table 25-11. mode configuration registers (me_< mode >_mc) field descriptions field description pdo i/o output power-down control ? this bit controls the output power-down of i/os. 0 no automatic safe gating of i/os used an d pads power sequence driver is enabled 1 in safe/test modes, outputs of pads are forced to high impedance stat e and pads power sequence driver is disabled. the inputs are level unchanged. in stop mode, only pad power sequence driver is disabled but the state of the output is kept. in standby mode, po wer sequence driver and all pads except those mapped on wakeup lines are not powered and therefore hi gh impedance. wakeup line configuration remains unchanged. mvron main voltage regulator control ? this bit specifies whether main voltag e regulator is switched off or not while entering this mode. 0 main voltage regulator is switched off 1 main voltage regulator is switched on dflaon data flash power-down control ? this bit specifies the operating mode of the data flash after entering this mode. 00reserved 01 data flash is in power-down mode 10 data flash is in low-power mode 11 data flash is in normal mode cflaon code flash power-down control ? this bit specifies the operating mo de of the program flash after entering this mode. 00reserved 01code flash is in power-down mode 10code flash is in low-power mode 11code flash is in normal mode fmpll1on secondary frequency modulated phase locked loop control 0 secondary frequency modulated phase locked loop is switched off 1 secondary frequency modulated phase locked loop is switched on fmpll0on primary frequency modulated phase locked loop control 0 primary frequency modulated phase locked loop is switched off 1 primary frequency modulated phase locked loop is switched on fxoscon fast external crystal oscillator (4-16mhz) control 0 fast external crystal oscillator (4-16mhz) is switched off 1 fast external crystal oscillator (4-16mhz) is switched on
pxd10 microcontroller reference manual, rev. 1 25-28 freescale semiconductor preliminary?subject to change without notice 25.3.2.16 peripheral status register 0 (me_ps0) this register provides the status of the peripherals. please refer to table 25-12 for details. fircon fast internal rc osc illator (16mhz) control 0 fast internal rc oscillator (16mhz) is switched off 1 fast internal rc oscillator (16mhz) is switched on sysclk system clock switch control ? these bits specify the system clock to be used by the system. 0000 16mhz int. rc osc. 0001 div. 16mhz int. rc osc. 0010 reserved 0011 div. 4-16mhz ext. osc. 0100 primary freq. mod. pll 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled address 0xc3fd_c060 access: supervisor read 0123456789101112131415 r s_bam s_dma_ch_mux s_flexcan1 s_flexcan0 w reset1000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r s_quadspi s_quadspi s_dspi1 s_dspi0 w reset0000000000000000 figure 25-17. peripheral status register 0 (me_ps0) table 25-11. mode configuration registers (me_< mode >_mc) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-29 preliminary?subject to change without notice 25.3.2.17 peripheral status register 1 (me_ps1) this register provides the status of the peripherals. please refer to table 25-12 for details. address 0xc3fd_c064 access: supervisor read 0123456789101112131415 r s_dcu s_sgl s_lcd s_cansampler s_gaugedriver s_lin_flex1 s_lin_flex0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r s_i2c_dma3 s_i2c_dma2 s_i2c_dma1 s_i2c_dma0 s_adc0 w reset0000000000000000 figure 25-18. peripheral status register 1 (me_ps1)
pxd10 microcontroller reference manual, rev. 1 25-30 freescale semiconductor preliminary?subject to change without notice 25.3.2.18 peripheral status register 2 (me_ps2) this register provides the status of the peripherals. please refer to table 25-12 for details. 25.3.2.19 peripheral status register 3 (me_ps3) this register provides the status of the peripherals. please refer to table 25-12 for details. address 0xc3fd_c068 access: supervisor read 0123456789101112131415 r s_pit_rti s_rtc_api s_mc_pcu s_mc_rgm s_mc_cgm s_mc_me s_sscm w reset0000011111000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r s_cflash1 s_emios1 s_emios0 s_wkpu s_siul s_dflash0 s_cflash0 w reset0001000000001100 figure 25-19. peripheral status register 2 (me_ps2) address 0xc3fd_c06c access: supervisor read 0123456789101112131415 r w reset0000100000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r s_cmu0 w reset0000000001111101 figure 25-20. peripheral status register 3 (me_ps3)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-31 preliminary?subject to change without notice 25.3.2.20 run peripheral configuration registers (me_run_pc0 ? 7) these registers configure eight different t ypes of peripheral behavior during run modes. table 25-12. peripheral status registers 0?4 (me_ps0?4) field descriptions field description s_ peripheral status ? these bits specify the current status of the peripherals in the system. if no peripheral is mapped on a particular position, the corresponding bit is always read as ?0?. 0 peripheral is frozen 1 peripheral is active address 0xc3fd_c080 - 0xc3fd_c09c access: supervisor read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 run3 run2 run1 run0 drun safe test reset w reset0000000000000000 figure 25-21. run peripheral config uration registers (me_run_pc0?7) table 25-13. run peripheral configuration re gisters (me_run_pc0?7) field descriptions field description run3 peripheral control during run3 0 peripheral is frozen with clock gated 1 peripheral is active run2 peripheral control during run2 0 peripheral is frozen with clock gated 1 peripheral is active run1 peripheral control during run1 0 peripheral is frozen with clock gated 1 peripheral is active run0 peripheral control during run0 0 peripheral is frozen with clock gated 1 peripheral is active drun peripheral control during drun 0 peripheral is frozen with clock gated 1 peripheral is active
pxd10 microcontroller reference manual, rev. 1 25-32 freescale semiconductor preliminary?subject to change without notice 25.3.2.21 low-power peripheral conf iguration registers (me_lp_pc0 ? 7) these registers configure eight different types of periphera l behavior during non-run modes. safe peripheral control during safe 0 peripheral is frozen with clock gated 1 peripheral is active test peripheral control during test 0 peripheral is frozen with clock gated 1 peripheral is active reset peripheral control during reset 0 peripheral is frozen with clock gated 1 peripheral is active address 0xc3fd_c0a0 - 0xc3fd_c0bc access: supervisor read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 standby 00 stop 0 halt 00000000 w reset0000000000000000 figure 25-22. low-power peripheral configuration registers (me_lp_pc0?7) table 25-14. low-power peripheral configuratio n registers (me_lp_pc0?7) field descriptions field description standby peripheral control during standby 0 peripheral is frozen with clock gated 1 peripheral is active stop peripheral control during stop 0 peripheral is frozen with clock gated 1 peripheral is active halt peripheral control during halt 0 peripheral is frozen with clock gated 1 peripheral is active table 25-13. run peripheral configuration register s (me_run_pc0?7) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-33 preliminary?subject to change without notice 25.3.2.22 peripheral control registers (me_pctl0 ? 143) these registers select the conf igurations during run and non-run modes for each peripheral. 25.4 functional description 25.4.1 mode transition request the transition from one mode to another mode is normally handled by software by accessing the mode control me_mctl register. but in cas e of special events, mode transi tion can be automa tically managed address 0xc3fd_c0c0 - 0xc3fd_c14f access: supervisor read/write 01234 5 6 7 r 0 dbg_f lp_cfg run_cfg w reset0 0000 0 0 0 figure 25-23. peripheral control registers (me_pctl0?143) table 25-15. peripheral control registers (me_pctl0?143) field descriptions field description dbg_f peripheral control in debug mode ? this bit controls the state of the peripheral in debug mode. 0 peripheral state depends on run_cfg/lp _cfg bits and the device mode. 1 peripheral is frozen if not already frozen in device modes. note this feature is useful to fr eeze the peripheral state while entering debug. for example, this may be used to prevent a reference timer from running wh ile making a debug accesses. lp_cfg peripheral configuration select for non-run modes ? these bits associate a conf iguration as defined in the me_lp_pc0 ? 7 registers to the peripheral. 000 selects me_lp_pc0 configuration 001 selects me_lp_pc1 configuration 010 selects me_lp_pc2 configuration 011 selects me_lp_pc3 configuration 100 selects me_lp_pc4 configuration 101 selects me_lp_pc5 configuration 110 selects me_lp_pc6 configuration 111 selects me_lp_pc7 configuration run_cfg peripheral configuration select for run modes ? these bits associate a configuration as defined in the me_run_pc0 ? 7 registers to the peripheral. 000 selects me_run_pc0 configuration 001 selects me_run_pc1 configuration 010 selects me_run_pc2 configuration 011 selects me_run_pc3 configuration 100 selects me_run_pc4 configuration 101 selects me_run_pc5 configuration 110 selects me_run_pc6 configuration 111 selects me_run_pc7 configuration
pxd10 microcontroller reference manual, rev. 1 25-34 freescale semiconductor preliminary?subject to change without notice by hardware. in order to switch from one mode to another, the application should access me_mctl register twice by writing ? the first time with the value of the key (0x5af0) into the key bit field and the required target mode into the target_mode bit field, ? and the second time with the inverted value of the key (0xa50f) into the key bit field and the required target mode into the target_mode bit field. once a valid mode transition request is detected, the ta rget mode configuration in formation is loaded from the corresponding me_ _mc register. the mode transition reque st may require a number of cycles depending on the programmed configuration, and so ftware should check the s_current_mode bit field and the s_mtrans bit of the global status re gister me_gs to verify when the mode has been correctly entered and the tr ansition process has complete d. for a description of vali d mode requests, please refer to section 25.4.5, mode transition interrupts . any modification of the mode configur ation register of the currently sel ected mode will not be taken into account immediately but on th e next request to enter this mode. th is means that transition requests such as run0?3 ? run0?3, drun ? drun, safe ? safe, and test ? test are considered valid mode transition requests. as soon as the mode request is accepted as valid, the s_mtrans bit is set till the status in the me_gs register matches th e configuration programmed in the respective me_ _mc register. safe drun test reset run0 run1 halt stop system modes user modes software request non-recoverable failure recoverable hardware failure run2 run3 software request figure 25-24. mc_me mode diagram standby
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-35 preliminary?subject to change without notice 25.4.2 modes details 25.4.2.1 reset mode the device enters this mode whenever the system reset is asserted by the mc_rgm. transition to this mode is instantaneous, and the system remains in this mode until the reset seque nce is finished. all power domains are made activ e during this mode. 25.4.2.2 drun mode the device enters this m ode on the following events. ? automatically from reset mode af ter completion of the reset sequence ? from run0?3, safe, or test mode when th e target_mode bit fi eld of the me_mctl register is written with ?0011? ? from the standby mode after an external wakeup event or intern al wakeup alarm (e.g. ) as soon as any of the above events has occurred, a drun mode transi tion request is generated. the mode configuration information for this mode is provid ed by the me_drun_mc register. in this mode, the flashes, all clock sources, and the system clock configuration can be controlled by software as required. after system reset, the software ex ecution starts with the default conf iguration selecting the 16mhz int. rc osc. as the system clock. this mode is intended to be used by software ? to initialize all registers as per the system needs ? to execute small rou tines in a ?ping-pong? with the standby mode when this mode is entered from standby after a wakeup event, the me_drun_mc register content is restored to its pre-standby values, a nd the mode starts in that configuration. all power domains are active when this mode is en tered due to a system reset sequence initiated by a destructive reset event. in other cases of entry, su ch as the exit from standby after a wakeup event, a functional reset event like an ex ternal reset or a software reque st from run0?3, safe, or test mode, active power domains are determin ed by the power configuration regi ster pcu_pconf2 of the mc_pcu. all power domains except power dom ains #0 and #1 are configurable in this mode (see the mc_pcu chapter for details). note as flashes can be configured in lo w-power or power-down state in this mode, software must ensure that th e code executes from ram before changing to this mode. 25.4.2.3 safe mode the device enters this m ode on the following events: ? from drun, run0?3, or test mode when th e target_mode bit field of the me_mctl register is written with ?0010?
pxd10 microcontroller reference manual, rev. 1 25-36 freescale semiconductor preliminary?subject to change without notice ? from any mode except reset due to a safe mode request generated by the mc_rgm because of some hardware failure in the system (see the mc_rgm chapter for details) as soon as any of the above events has occurred, a safe m ode transition request is generated. the mode configuration information for this mode is provid ed by the me_safe_mc register. this mode has a pre-defined configurat ion, and the 16mhz int. rc osc. is selected as the syst em clock. all power domains are made active in this mode. if the safe mode is requested by software while some other mode transitio n process is ongoing, the new target mode becomes the safe mode regardless of other pending requests. in this case, the new mode request is not interpreted as an invalid request. note if software requests to change to th e safe mode and then requests to change back to the parent mode before the mode tr ansition is completed, the device?s final mode after mode transiti on will be the pare nt mode. however, this is not recommended so ftware behavior. it is recommended for software to wait until the s_mtrans bit is cl eared after requesting a change to safe before requesting another mode change. as long as a safe event is active, the system rema ins in the safe mode an d no write access is allowed to the me_mctl register. this mode is intended to be used by software ? to assess the severity of the caus e of failure and then to either ? re-initialize the device via the drun mode, or ? completely reset the de vice via the reset mode. if the outputs of the system i/os n eed to be forced to a high impeda nce state upon entering this mode, the pdo bit of the me_safe_mc register should be set. in this case , the pads? power seque nce driver cell is also disabled. the input levels remain unchanged. 25.4.2.4 test mode the device enters this m ode on the following events: ? from the drun mode when the target_mode bi t field of the me_mctl register is written with ?0001? as soon as any of the above events has occurred, a test mode transition request is generated. the mode configuration information for this mode is provided by the me_test_mc register. except for the main voltage regulator, all resource s of the system are configurable in th is mode. the system clock to the whole system can be stopped by programming th e sysclk bit field to ?1111?, a nd in this case, the only way to exit this mode is via a device reset. this mode is intended to be used by software ? to execute on-chip test routines
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-37 preliminary?subject to change without notice all power domains except power domai ns #0 and #1 are configurable in this mode. active power domains are determined by the power configurati on register pcu_pconf2 of the mc_pcu. note as flash modules can be configured to a low-power or power-down state in these modes, software must ensure th at the code will execute from ram before it changes to this mode. 25.4.2.5 run0?3 modes the device enters one of thes e modes on the following events: ? from the drun another run0?3 mode when th e target_mode bit field of the me_mctl register is written with ?0100?0111? ? from the halt mode by an interrupt event ? from the stop mode by an interrupt or wakeup event as soon as any of the above events occur, a ru n0?3 mode transition request is generated. the mode configuration information for these modes is pr ovided by me_run0?3_mc regist ers. in these modes, the flashes, all clock sources, and the system clock c onfiguration can be controll ed by software as required. these modes are intended to be used by software ? to execute application routines all power domains except power dom ains #0 and #1 are configurable in these modes in order to reduce leakage consumption. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. note as flash modules can be configured to a low-power or power-down state in these modes, software must ensure th at the code will execute from ram before it changes to this mode. 25.4.2.6 halt mode the device enters this m ode on the following events: ? from one of the run0?3 modes when the targ et_mode bit field of the me_mctl register is written with ?1000?. as soon as any of the above events occur, a ha lt mode transition request is generated. the mode configuration information for this mode is provid ed by me_halt_mc register. this mode is quite configurable, and the me_halt_mc re gister should be programmed acco rding to the system needs. the flashes can be put in power-down mode as needed. if there is a halt mode request while an interrupt request is active, the device mode does not change, and an invalid mode inte rrupt is not generated. this mode is intended as a fi rst level low-power mode with ? the core clock frozen ? only a few peripherals running
pxd10 microcontroller reference manual, rev. 1 25-38 freescale semiconductor preliminary?subject to change without notice and to be used by software ? to wait until it is required to do something and then to react quickly (i.e. wi thin a few system clock cycles of an interrupt event) all power domains except power dom ains #0 and #1 are configurable in this mode in order to reduce leakage consumption. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. 25.4.2.7 stop mode the device enters this m ode on the following events: ? from one of the run0?3 modes when the targ et_mode bit field of the me_mctl register is written with ?1010?. as soon as any of the above events occur, a st op mode transition request is generated. the mode configuration information for this mode is provided by the me_stop_mc register. this mode is fully configurable, and the me_stop_mc register should be progr ammed according to th e system needs. the fmpll0 is switched off in this mode. the flashes can be put in power-down mode as needed. if there is a stop mode request while any inte rrupt or wakeup event is active, th e device mode does not change, and an invalid mode interrupt is not generated. this can be used as an advanced low-power mode wi th the core clock frozen and almost all peripherals stopped. this mode is intended as an advanced low-power mode with ? the core clock frozen ? almost all peripherals stopped and to be used by software ? to wait until it is required to do something with no need to react quickly (e.g. allow for system clock source to be re-started) if the pads? power sequence driver cel l needs to be disabled while ente ring this mode, the pdo bit of the me_stop_mc register should be set. the state of the outputs is kept. this mode can be used to stop all clock sources, thus preser ving the device status. when exiting the stop mode, the fast internal rc oscillat or (16mhz) clock is sel ected as the system cloc k until the target clock is available. all power domains except power dom ains #0 and #1 are configurable in this mode in order to reduce leakage consumption. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. 25.4.2.8 standby mode the device enters this m ode on the following events: ? from the drun or one of the run0?3 mode s when the target_mode bit field of the me_mctl register is written with ?1101?.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-39 preliminary?subject to change without notice as soon as any of the above events occur, a sta ndby mode transition request is generated. the mode configuration information for this mode is provided by the me_standby _mc register. in this mode, the power supply is turned off for most of the device. by default the only parts of the device that are still powered during this mode are pa ds mapped on wakeup lines and power domain #0 which contains the mc_rgm, mc_pcu, wkpu, 8k ram, rtc_api, ca nsampler, sirc, firc, lcd, and device and user option bits. the firc can be optionally switched off. this is the lowest power consumption mode possible on the device. this mode is intended as an extreme low-power mode with ? the core, the flashes, and almost al l peripherals and memories powered down and to be used by software ? to wait until it is required to do something with no need to react quickly (i.e. allow for system power-up and system clock source to be re-started) the exit sequence of this mode is similar to the rese t sequence. if there is a standby mode request while any wakeup event is active, th e device mode does not change. all power domains except power dom ain #0 are configurable in this mode in order to reduce leakage consumption. active power domains are determined by the power configuration register pcu_pconf2 of the mc_pcu. 25.4.3 mode transition process the process of mode transition follows the follow ing steps in a pre-defined manner depending on the current device mode and the requested target mode. in many cases of m ode transition, not all steps need to be executed based on the mode control informat ion, and some steps may not be valid according to the mode definition itself. 25.4.3.1 target mode request the target mode is requested by accessing the me_m ctl register with the required keys. this mode transition request by software must be a valid request satisfying a set of pre-defined rules to initiate the process. if the request fails to satisfy these rules, it is ignored, and the ta rget_mode bit field is not updated. an optional interrupt can be generated for invali d mode requests. refer to section 25.4.5, mode transition interrupts for details. in the case of mode transitions occurring because of ha rdware events such as a reset, a safe mode request, or interrupt requests and wakeup ev ents to exit from low-power modes, the target_mode bit field of the me_mctl register is automatically updated with the appropriate target mode. the mode change process start is indicated by the setting of the mode transition status bi t s_mtrans of the me_gs register. a reset mode requested via the me_mctl register is passed to the mc_rgm, which generates a global system reset and initiates th e reset sequence. the reset mode re quest has the highest priority, and the mc_me is kept in the reset mode during the entire reset sequence.
pxd10 microcontroller reference manual, rev. 1 25-40 freescale semiconductor preliminary?subject to change without notice the safe mode request has the next highest priority after reset whic h can be generated by software via the me_mctl register from all software r unning modes including drun, run0?3, and test or by the mc_rgm after the detection of system hardware failures, which may occur in any mode. 25.4.3.2 target mode configuration loading on completion of the target mode request , the target mode c onfiguration from the me_ _mc register is loaded to st art the resources (voltage sour ces, clock sources, flashes, pads, etc.) co ntrol process. an overview of resource control possi bilities for each mode is shown in table 25-16 . a ? ? ? indicates that a given resource is configurable for a given mode. table 25-16. mc_me resource control overview resource mode reset test safe drun run0? 3 halt stop stand by firc ? ??? on always on on on on always on always on on fxosc ? ???? off off off off off off off off by default, but also writable fmpll0 ? ??? off off off off off off off off fmpll1 ? ???? off off off off off off off off cflash ? ???? normal normal normal normal normal low-power power- down power- down dflash ? ???? normal normal normal normal normal low-power power- down power- down mvreg ?? on on on on on on on off pdo ? ? ? off off on off off off off on
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-41 preliminary?subject to change without notice 25.4.3.3 peripheral clocks disable on completion of the target mode request , the mc_me requests each peripheral to enter its stop mode when: ? the peripheral is configured to be disabled via the target mode, the peripheral configuration registers me_run_pc0?7 and me_lp_pc0?7, and the peripheral control registers me_pctl0?143 warning the mc_me does not automatically reque st peripherals to enter their stop modes if the power domains in which th ey are residing are to be turned off due to a mode change. therefore, it is software?s responsibility to ensure that those peripherals that are to be powered down are configured in the mc_me to be frozen. each peripheral acknowledges its stop mode request after clos ing its internal activity. the mc_me then disables the corresponding clock(s) to this peripheral. in the case of a safe mode transition request, the mc_me does not wait for the peripherals to acknowledge the stop requests. the safe mode cloc k gating configuration is applied immediately regardless of the status of the peripherals? stop acknowledges. please refer to section 25.4.6, peripheral clock gating for more details. each peripheral that may block or disrupt a communication bus to which it is connected ensures that these outputs are forced to a safe or recessive st ate when the device enters the safe mode. 25.4.3.4 processor low-power mode entry if, on completion of the peripheral clocks disable , the mode transition is to the halt mode, the mc_me requests the processor to enter its halted state. th e processor acknowledges its halt state request after completing all outstandi ng bus transactions. if, on completion of the peripheral clocks disable , the mode transition is to the stop or standby mode, the mc_me requests the proces sor to enter its stopped state. the processor ac knowledges its stop state request after completing al l outstanding bus transactions. 25.4.3.5 processor and syst em memory clock disable if, on completion of the processor low-power mode entry , the mode transition is to the halt, stop, or standby mode and the processor is in its appropria te halted or stoppe d state, the mc_me disables the processor and system memory clocks to achieve further power saving. the clocks to the processor and system memories are unaffected for all transitions between software running modes including drun, run0?3, and safe. warning clocks to the whole device including the processor and system memories can be disabled in test mode.
pxd10 microcontroller reference manual, rev. 1 25-42 freescale semiconductor preliminary?subject to change without notice 25.4.3.6 clock sources switch-on on completion of the processor low-power mode entry , the mc_me controls all cl ock sources that affect the system clock based on the on bits of the me_ _mc and me_ _mc registers. the following system cloc k sources are controll ed at this step: ? the fast internal rc oscillator (16mhz) ? the fast external crystal oscillator (4-16mhz) ? the secondary frequency modulated phase locked loop note the primary frequency m odulated phase locked loop, which needs the main voltage regulator to be stable, is not controlled by this step. the clock sources that are required by the target mode are switched on. the duration required for the output clocks to be stable depends on the type of source, a nd all further steps of mode transition depending on one or more of these clocks waits for the stable st atus of the respective clocks . the availability status of these system clocks is updated in the s_ bits of me_gs register. the clock sources which need to be switched off are unaffecte d during this process in order to not disturb the system clock which might require one of these cl ocks before switching to a different target clock. 25.4.3.7 main voltage regulator switch-on on completion of the target mode request , if the main voltage regulator needs to be switched on from its off state based on the mvron bit of the me_ _mc and me_ _mc registers, the mc_me requests the mc_pcu to power up the regulator and waits for the output voltage stable status in order to update th e s_mvr bit of the me_gs register. this step is required only during the exit of the lo w-power modes halt and stop. in this step, the fast internal rc oscillator (16mhz) is switched on regardless of the target mode configurati on, as the main voltage regulator require s the 16mhz int. rc osc. du ring power-up in order to ge nerate the voltage status. during the standby exit sequence, the mc_pcu al one manages the power-up of the main voltage regulator, and the mc_me is kept in reset or s hut off (depending on the power domain #1 status). 25.4.3.8 flash modules switch-on on completion of the main voltage regulator switch-on , if a flash module needs to be switched to normal mode from its low-power or power-down mode ba sed on the cflaon and df laon bit fields of the me_ _mc and me_ _mc registers, the mc_me requests the flash to exit from its low-power/power-down mode . when the flash modules are avai lable for access, the s_cfla and s_dfla bit fields of the me_gs regist er are updated to ?11? by hardware. if the main regulator is also off in device low-power modes, then during the exit sequence, the flash is kept in its low-power state and is switched on only when the main voltage regulator switch-on process has completed.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-43 preliminary?subject to change without notice warning it is illegal to switch the flashes from low-power mode to power-down mode and from power-down mode to low- power mode. the mc_me, however, does not prevent this nor does it flag it. 25.4.3.9 fmpll0 switch-on on completion of the clock sources switch-on and main voltage regulator switch-on , if the fmpll0 is to be switched on from the off stat e based on the fmpll0on bit of the me_ _mc and me_ _mc registers, the mc_me re quests the fmpll0 digital in terface to start the phase locking process and waits for the fmpll0 to enter into the locked state. when the fmpll0 enters the locked state and starts providing a stable output cl ock, the s_fmpll0 bit of me_gs register is set. 25.4.3.10 power domain #2 switch-on on completion of the main voltage regulator switch-on , the mc_me indicates a mode change to the mc_pcu. the mc_pcu then determ ines whether a power-up sequence is required for power domain #2. only after the mc_pcu has exec uted all required power-ups does the mc_me complete the mode transition. 25.4.3.11 pad outputs-on on completion of the main voltage regulator switch-on , if the pdo bit of the me_ _mc register is cleared, then ? all pad outputs are enabled to return to their previous state ? the i/o pads power sequence driver is switched on 25.4.3.12 peripheral clocks enable based on the current and target de vice modes, the peripheral c onfiguration registers me_run_pc0?7, me_lp_pc0?7, and the peripheral co ntrol registers me_pctl0?143, th e mc_me enables the clocks for selected modules as required. this step is executed only after the main voltage regulator switch-on process is completed. also if a mode change translates to a power up of one or more power domains, the mc_pcu indicates the mc_me after completing the power-up sequence upon wh ich the mc_me may assert the peripheral clock enables of the peripherals re siding in those power domains. 25.4.3.13 processor and memory clock enable if the mode transition is from any of the low-power modes halt or st op to run0?3, the clocks to the processor and system memories are enabled. the pro cess of enabling these clocks is executed only after the flash modules switch-on process is completed.
pxd10 microcontroller reference manual, rev. 1 25-44 freescale semiconductor preliminary?subject to change without notice 25.4.3.14 processor low-power mode exit if the mode transition is from any of the low-power modes halt, stop, or standby to run0?3, the mc_me requests the processor to exit from its halted or stopped state. this step is executed only after the processor and memory clock enable process is completed. 25.4.3.15 system clock switching based on the sysclk bit field of the me_ _mc and me_ _mc registers, if the target and current system cl ock configurations differ, the follow ing method is implemented for clock switching. ? the target clock configuration for the 16mhz int. rc osc. is effective only when the s_firc bit of the me_gs register is set by hardware (i.e. the fast internal rc oscillator (16mhz) has stabilized). ? the target clock configuration fo r the div. 16mhz int. rc osc. is effective only when the s_firc bit of the me_gs register is set by hardware (i .e. the fast internal rc oscillator (16mhz) has stabilized). ? the target clock configuration fo r the div. 4-16mhz ext. osc. is effective only when the s_fxosc bit of the me_gs register is set by hardware (i.e the fast external crystal oscillator (4-16mhz) has stabilized). ? the target clock configuration for the primar y freq. mod. pll is effective only when the s_fmpll0 bit of the me_gs register is set by hardware (i.e. the prim ary frequency modulated phase locked loop has stabilized). ? if the clock is to be disabled, the sysclk bit field should be programmed with ?1111?. this is possible only in the stop and test modes. in the standby mode, the cl ock configuration is fixed, and the system clock is automatically forced to ?0?. the current system clock configurat ion can be observed by reading the s_sysclk bit field of the me_gs register, which is updated afte r every system clock switch ing. until the target clock is available, the system uses the previous clock configuration. system clock switchi ng starts only after ? the clock sources switch-on process has completed if the target system clock source needs to be switched on ? the fmpll0 switch-on process has complete d if the target sy stem clock is the primary freq. mod. pll ? the peripheral clocks disable process is completed in order not to change the system clock frequency before peripherals cl ose their internal activities an overview of system clock source selecti on possibilities for eac h mode is shown in table 25-17 . a ? ? ? indicates that a given clock source is selectable for a given mode.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-45 preliminary?subject to change without notice 25.4.3.16 power domain #2 switch-off based on the device mode and the mc_pcu?s power configuration register pcu_pconf2, the power domain #2 is controlled by the mc_pcu. if a mode change translates to a power-down of the power domain, then the mc_pcu starts the power-down sequence. the mc_pcu acknowledges th e completion of the power-down sequence with respect to the new mode, and the mc_me uses this in formation to update the mode transition status. this step is executed only after the peripheral clocks disable process has completed. 25.4.3.17 pad switch-off if the pdo bit of the me_ _mc register is ?1? then ? the outputs of the pads are forced to the high impedance state if the target mode is safe or test ? i/o pads power sequence dr iver is switched off if the target mode is one of safe, test, or stop modes in standby mode, the power sequen ce driver and all pads except the external reset and those mapped on wakeup lines are not powered and therefore high impedance. the wa keup line configuration remains unchanged. this step is executed only after the peripheral clocks disable process is completed. 25.4.3.18 fmpll0 switch-off based on the fmpll0 on bit of the me_ _mc and me_ _mc registers, if fmpll0 is to be switched off, the mc_me re quests the fmpll0 to power down and updates its availability status bit s_ fmpll0 of the me_gs regist er to ?0?. this step is executed only after the system clock switching process is completed. table 25-17. mc_me system clock selection overview system clock source mode reset test safe drun run0?3 halt stop standby 16mhz int. rc osc. ? (default) ? (default) ? (default) ? (default) ? (default) ? (default) ? (default) div. 16mhz int. rc osc. ? ???? div. 4-16mhz ext. osc. ? ???? primary freq. mod. pll ? ??? system clock is disabled ? ? 1 disabling the system clock during test mode will re quire a reset in order to exit test mode. ?? (default)
pxd10 microcontroller reference manual, rev. 1 25-46 freescale semiconductor preliminary?subject to change without notice 25.4.3.19 clock sources switch-off based on the device mode and the on bits of the me_ _mc registers, if a given clock source is to be switched off, the mc_me re quests the clock source to power down and updates its availability status bit s_ of the me_gs register to ?0?. this step is executed only after ? system clock switching process is completed in order not to lose the cu rrent system clock during mode transition. ? fmpll0 switch-off as the input reference clock of the fmpll0 can be among these clock sources. this is needed to prevent an unwanted lo ck transition when the fm pll0 is switched on. 25.4.3.20 flash switch-off based on the cflaon and dflaon bit fields of the me_ _mc and me_ _mc registers, if any of the flash modules is to be put in a low-power state, the mc_me requests the flash to enter the corresponding low-power state and waits for the deassertion of flash ready status signal. the exact low-power mode status of the flash modules is updated in the s_cfla and s_dfla bit fields of the me_gs regi ster. this step is executed only when processor and system memory clock disable process is completed. 25.4.3.21 main voltage regulator switch-off based on the mvron bit of the me_ _mc and me_ _mc registers, if the main voltage regulator is to be switched off, the mc_me requests it to power down and clears the availability status bit s_mvr of the me_gs register. this step is required only during the entry of low-power modes like halt and stop. this step is executed only after completing the following processes: ? fmpll0 switch-off ? flash switch-off ? power domain #2 switch-off ? power domain #2 switch-on ? the device consumption is less than the pre-defi ned threshold value (i.e. the s_dc bit of the me_gs register is ?0?). if the target mode is standby, the main voltage regulator is not switched off by the mc_me and the standby request is asserted afte r the above processes have comp leted upon which the mc_pcu takes control of the main regulator. as the mc_pcu needs the 16mhz int. rc osc., the fast internal rc oscillator (16mhz) remains active until all the stan dby steps are executed by the mc_pcu after which it may be switched off depending on the fi rcon bit of the me_standby_mc register. 25.4.3.22 current mode update the current mode status bit fiel d s_current_mode of the me_gs regi ster is updated with the target mode bit field target_mode of the me_mctl register when:
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-47 preliminary?subject to change without notice ? all the updated status bits in the me_gs regi ster match the configur ation specified in the me_ _mc register ? power sequences are done ? clock disable/enable process is finished ? processor low-power mode (halt/stop) entry and exit processes are finished software can monitor the mode transition status by reading the s_mtrans bit of the me_gs register. the mode transition latency can diff er from one mode to a nother depending on the re sources? availability before the new mode request and the target mode?s requirements.
pxd10 microcontroller reference manual, rev. 1 25-48 freescale semiconductor preliminary?subject to change without notice figure 25-25. mc_me transition diagram power domain switch-on power domain switch-off pll switch-on pll switch-off end target mode request write me_mctl register safe mode request interrupt/wakeup event peripheral clocks disable clock sources switch-on system clock switching main vreg switch-on flash switch-on pad processor low-power processor & pad peripheral clocks enable flash switch-off clock sources switch-off s_mtrans = ?1? analog on digital control analog off current mode update start s_mtrans = ?0? outputs -on outputs -off entry processor low-power exit clock disable memory processor & clock enable memory target standby standby request n y main vreg switch-off
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-49 preliminary?subject to change without notice 25.4.4 protection of mode configuration registers while programming the mode c onfiguration registers me_ _mc, the following rules must be respected. otherwise, the write opera tion is ignored and an invalid mode configuration interrupt may be generated. ? firc must be on if the system clock is one of the following: ? 16mhz int. rc osc. ? div. 16mhz int. rc osc. ? fxosc must be on if the system clock is one of the following: ? div. 4-16mhz ext. osc. note software must ensure to switch on th e clock source that provides the input reference clock to the fmpll0. there is no automatic protection mechanism to check this in the mc_me. ? fmpll0 must be on if the system clock is the primary freq. mod. pll. ? configuration ?00? for the cflaon and dflaon bit fields are reserved. ? mvreg must be on if any of the following is active: ? fmpll0 ?cflash ?dflash ? system clock configurations marked as ?reserved? may not be selected. ? configuration ?1111? for the sysclk bit field is allowed only for the stop and test modes, and only in this case may all syst em clock sources be turned off. warning if the system clock is stopped duri ng test mode, the device can exit only via a system reset. 25.4.5 mode transition interrupts the following are the three interrupts related to mode transition impl emented in the mc_me. 25.4.5.1 invalid mode configuration interrupt whenever a write operation is attempted to the me_ _mc registers violating the protection rules mentioned in the section 25.4.4, protection of mode configuration registers , the interrupt pending bit i_iconf of the me_is register is set and an interrupt request is generated if the mask bit m_iconf of me_im register is ?1?. 25.4.5.2 invalid mode transition interrupt the mode transition request is consider ed invalid under the following conditions:
pxd10 microcontroller reference manual, rev. 1 25-50 freescale semiconductor preliminary?subject to change without notice ? if the system is in the safe mode and the sa fe mode request from mc_r gm is active, and if the target mode requested is other than reset or safe, then this new mode request is considered to be invalid, and the s_sea bit of the me_imts register is set. ? if the target_mode bit field of the me_mctl re gister is written with a value different from the specified mode values (i.e. a non existing mode), an invalid mode transitio n event is generated. when such a non existing mode is requested, the s_ nma bit of the me_imts re gister is set. this condition is detected regardless of whether the proper key mechan ism is followed while writing the me_mctl register. ? if some of the device modes ar e disabled as programmed in th e me_me register, their respective configurations are considered reserved, and a ny access to the me_mctl register with those values results in an invalid mode transition reques t. when such a disabled mode is requested, the s_dma bit of the me_imts register is set. this condition is detected re gardless of whether the proper key mechanism is followed while writing the me_mctl register. ? if the target mode is not a valid mode with respect to current mode , the mode request illegal status bit s_mri of the me_imts register is set. this condition is detected only when the proper key mechanism is followed while writing the me_mc tl register. otherwise, the write operation is ignored. ? if further new mode requests occu r while a mode transition is in progress (the s_mtrans bit of the me_gs register is ?1?), the mode transition illegal status bi t s_mti of the me _imts register is set. this condition is detected only when th e proper key mechanism is followed while writing the me_mctl register. otherwise, the write operation is ignored. note as the causes of invalid mode transiti ons may overlap at the same time, the priority implemented for invalid m ode transition status bits of the me_imts register in the order from hi ghest to lowest is s_sea, s_nma, s_dma, s_mri, and s_mti. as an exception, the mode transition request is not considered as invalid under the following conditions: ? a new request is allowed to enter the reset or safe mode irrespective of the mode transition status. ? as the exit of halt and stop modes depends on the interrupts of the syst em which can occur at any instant, these requests to return to run0?3 modes are always valid. ? in order to avoid any unwanted lockup of the devi ce modes, software can abort a mode transition by requesting the parent mode if , for example, the mode transi tion has not completed after a software determined ?reasonable? amount of time for whatever r eason. the parent mode is the device mode before a valid mode request was made. ? self-transition requests (e.g. run0 ? run0) are not considered as invalid even when the mode transition process is active (i.e . s_mtrans is ?1?). during the lo w-power mode exit process, if the system is not able to enter the respective ru n0?3 mode properly (i.e. all status bits of the me_gs register match with c onfiguration bits in the me_ _mc register), then software can only request the safe or res et mode. it is not possible to re quest any other mode or to go back to the low-power mode again.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-51 preliminary?subject to change without notice whenever an invalid mode request is detected, the interrupt pending bi t i_imode of the me_is register is set, and an interrupt request is generated if the mask bit m_imode is me_im register is ?1?. 25.4.5.3 safe mode transition interrupt whenever the system enters the safe mode as a re sult of a safe mode reque st from the mc_rgm due to a hardware failure, the interrupt pending bit i_safe of the me_is register is set, and an interrupt is generated if the mask bit m_safe of me_im register is ?1?. the safe mode interrupt pending bit can be cleared only when the safe mode request is deasserted by the mc_rgm (see the mc_rgm chapte r for details on how to clear a safe mode request). if the system is already in safe mode, any ne w safe mode request by the mc_rgm also sets the interrupt pending bit i_safe. however, the safe mode interrupt pending bit is not set when the safe mode is entered by a software request (i.e. progr amming of me_mctl register). 25.4.5.4 mode transition complete interrupt whenever the system completes a mode transition fully (i.e. the s_mtrans bit of me_gs register transits from ?1? to ?0?), the interr upt pending bit i_mtc of the me_is regi ster is set, and interrupt request is generated if the mask bi t m_mtc of the me_im regist er is ?1?. the interrupt bit i_mtc is not set when entering low-power modes halt and stop in order to avoid the same event requesting the exit of these low-power modes. 25.4.6 peripheral clock gating during all device modes, certain peripherals can be associated with a partic ular clock gating policy determined by two groups of peri pheral configuration registers. the run peripheral configuration registers me_run_pc0?7 are chosen only during the software running modes drun, test, safe, and ru n0?3. all configurati ons are programmable by software according to the needs of application. each c onfiguration register contains a mode bit which determines whether or not a peripheral clock is to be gated. run configur ation selection for each peripheral is done by the run_cfg bit field of the me_pctl0?143 registers. the low-power peripheral configur ation registers me_lp_ pc0?7 are chosen only during the low-power modes halt, stop, and standby. al l configurations are programmable by softwa re according to the needs of the application. ea ch configuration regi ster contains a mode bit whic h determines whether or not a peripheral clock is to be gate d. low-power configurati on selection for each pe ripheral is done by the lp_cfg bit field of the me_pctl0?143 registers. any modifications to the me _run_pc0?7, me_lp_pc0?7, and me_pctl0?143 registers do not affect the clock gating beha vior until a new mode tran sition request is generated. whenever the processor enters a de bug session during any mode, the fo llowing occurs for the peripheral: ? the clock is gated if the dbg_f bit of the associated me_pctl0?1 43 register is set. otherwise, the peripheral clock gating stat us depends on the run_cfg a nd lp_cfg bits. any further modifications of the me_run_pc0?7, me_lp_pc0?7, and me_pctl0?143 registers during a debug session will take affect immediately without requiring any new mode request.
pxd10 microcontroller reference manual, rev. 1 25-52 freescale semiconductor preliminary?subject to change without notice 25.4.7 application example figure 25-26 shows an example application flow for requesting a mode cha nge and then waiting until the mode transition has completed.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 25-53 preliminary?subject to change without notice figure 25-26. mc_me application example flow diagram start of mode change config for target mode okay? write me__mc , me_run_pc0?7 , me_lp_pc0?7 , and me_pctl0?143 registers n y write me_mctl with target mode and key write me_mctl with target mode and inverted key start timer s_mtrans cleared? y timer expired? n y n write me_mctl with current or safe mode and key write me_mctl with current or safe mode and inverted key stop timer mode change done
pxd10 microcontroller reference manual, rev. 1 25-54 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 26-1 preliminary?subject to change without notice chapter 26 nexus development interface (ndi) 26.1 introduction the nexus development interface (n di) block provides real-time de velopment support capabilities for the pxd10 mcu in compliance with the ieee-i sto 5001-2003 standard. this development support is supplied for mcus without requiring external address and da ta pins for internal visibility. the ndi block is an integration of several individual nexus blocks th at are selected to provide the development support interface for pxd10. the ndi block interfaces to the e200z0, and internal buses to provide development support as per the ieee-isto 5001-2003 standard. the development support provided incl udes program trace, watchpoint messaging, ownership trace, watchpoi nt triggering, processor overrun c ontrol, run-time access to the mcu?s internal memory map, and access to the e200z 0 internal registers during halt, via the jtag port. 26.2 block diagram figure 26-1 shows a functional block diagram of the ndi. a simplified block diagram of the ndi illustrates th e functionality and interdependence of major blocks (see figure 26-2 ) and how the individual nexus blocks are combined to form the ndi. figure 26-1. ndi functional block diagram power-on tck evto mseo mdo reset message queue program trace ownership trace watchpoint trace cpu snoop message formatter arbiter divided system clock e200z1 trace information e200z0 trace information mcko input tap controller control registers to trace blocks tdo tdi tms evti reset control
pxd10 microcontroller reference manual, rev. 1 26-2 freescale semiconductor preliminary?subject to change without notice figure 26-2. ndi implementation block diagram 26.3 features the ndi module of the pxd10 is compliant with class 2 of the ieee-isto 5001-2003 standard, with additional class 3 and class 4 features availa ble.the following feat ures are implemented: ? program trace via branch trace messaging (btm). branch trace me ssaging displays program flow discontinuities (direct and indirect branches, exceptions, etc.), al lowing the development tool to interpolate what transpires between the discont inuities. thus static code may be traced. ? ownership trace via ownership trace messagi ng (otm). otm facilitates ownership trace by providing visibility of which pro cess id or operating system task is activated. an ownership trace message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow. ? watchpoint messaging via the auxiliary pins. ? watchpoint trigger enable of program trace messaging. ? auxiliary interface for higher data input/output. ? four message data out pins. tdo cross-bar power-on mcko evto mdo[3:0] mseo ppc reset bp/wp control once/ nexus1 ta p program/ ownership register control read/write access message fifo message transmitter nexus2+ interface auxiliary port arbitration/ muxing reset control ta p register control clock control e200z0 nexus port controller tdo muxing jtag controller tdi evti tms nexus development interface z0_tdo z0_tms z0_tdi tclk trace tdi ta p npc_tms z0_tdo z0_tms npc_tdo access auxiliary ta p npc_tdo npc_tms tdi, tclk tck
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 26-3 preliminary?subject to change without notice ? one message start/end out pins (mseo). ? one watchpoint event pin (evto). ? one event-in pin (evti). ? one message clock out pin (mcko). ? four pin jtag port (tdi, tdo, tms, and tck). ? registers for program trace, owners hip trace, and watc hpoint trigger. ? all features controllable and configurable via the jtag port. ? run-time access to the on-chip memory map via th e nexus read/write access protocol. this allows for enhanced download/upload capabilities. ? all features are independently configurable and controllable via the ieee 1149.1 i/o port. ? the ndi block reset is controlled with jcomp, power-on reset, and the tap state machine. all these sources are indepe ndent of system reset. ? support for internal censorship mode to prevent external access to flash memory contents when censorship is enabled. note if the e200z0 cores has executed a wa it instruction, then the nexus2+ controller clocks are gated off. while the core is in this state, it is not be possible to perform nexu s read/write operations. 26.4 modes of operation the ndi block is in reset when th e tap controller state machine is in the test-logic-reset state. the test-logic-reset state is entered on the asserti on of the power-on reset signal or through state machine transitions controlled by tms. ownership of the tap is achieved by loading the appropriate enable instruction for the de sired nexus client in the jt agc controller (jtagc) block. the npc transitions out of the reset state im mediately following negation of power-on reset. 26.4.1 nexus reset in nexus reset mode, the following actions occur: ? register values default back to their reset values. ? the message queues are marked as empty. ? the auxiliary output port pins are ne gated if the ndi controls the pads. ? the tdo output buffer is disabled if the ndi has control of the tap. ? the tdi, tms, and tck inputs are ignored. ? the ndi block indicates to the mcu that it is not using the auxiliary output port. this indication can be used to three-state the output pins or use them for another function.
pxd10 microcontroller reference manual, rev. 1 26-4 freescale semiconductor preliminary?subject to change without notice 26.4.2 operating mode in full-port mode, all availa ble mdo pins are used to transmit mess ages. all trace featur es are enabled or can be enabled by writing the conf iguration registers via the jtag port. four mdo pins are available in full-port mode. 26.4.2.1 disabled-port mode in disabled-port mode, message transmission is disa bled. any debug feature that generates messages can not be used. the primary features availabl e are class 1 features and read/write access. 26.4.2.2 censored mode the ndi supports internal flash censorship mode by preventing the transmissi on of trace messages and nexus access to memory-mapped resources when censorship is enabled. 26.4.2.3 stop mode stop mode logic is implemented in the nexus port cont roller (npc). when a request is made to enter stop mode, the ndi block completes monitoring of any pe nding bus transaction, transm its all messages already queued, and acknowledges the stop reque st. after the acknowledgment, the sy stem clock input are shut off by the clock driver on the device. wh ile the clocks are shut off, the development tool cannot access ndi registers via the jtag port. 26.5 external signal description all the signals are available in the 208bga without any mu ltiplexing scheme. refer to chapter 3, signal description for details. 26.5.1 nexus signal reset states table 26-1. ndi signal reset state name function nexus reset state pull evti event-in pin ? up evto event-out pin 0b1 ? mcko message clock out pin 0b0 ? mdo[3:0] message data out pins 0 ? mseo message start/end out pin 0b1 ?
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 26-5 preliminary?subject to change without notice 26.6 memory map and register description the ndi block contains no memory -mapped registers. nexus register s are accessed by a development tool via the jtag port using a client-select value and a re gister index. once registers are accessed by loading the appropriate value in the rs[0:6] field of the once command register (ocmd) via the jtag port. 26.6.1 nexus debug interface registers table 26-2 shows the ndi registers by client select a nd index values. once re gister addressing is documented in chapter 19, ieee 1149.1 test access port controller (jtagc) .? 26.6.2 register description this section lists the ndi registers and de scribes the registers and their bit fields. 26.6.2.1 nexus device id register (did) the npc device identifica tion register, shown in figure 26-3 , allows the part revision number, design center, part identificat ion number, and manufacturer id entity code of the device to be determined through the auxiliary output port, and serially th rough tdo. this register is read-only. table 26-2. nexus debug interface registers client select index register client-independent registers 0bxxxx 0 device id (did) 1 1 implemented in npc block. all other registers implemented in e200z0 nexus2+ block. 0bxxxx 127 port configuration register (pcr) 1 e200z0 control/status registers 0b0000 2 e200z0 development control1 (dc1) 0b0000 3 e200z0 development control2 (dc2) 0b0000 4 e200z0 development status (ds) 0b0000 7 read/write access control/status (rwcs) 0b0000 9 read/write access address (rwa) 0b0000 10 read/write access data (rwd) 0b0000 11 e200z0 watchpoint trigger (ppc_wt)
pxd10 microcontroller reference manual, rev. 1 26-6 freescale semiconductor preliminary?subject to change without notice 26.6.2.2 port configuration register (pcr) the pcr is used to select the npc mode of ope ration, enable mcko and se lect the mcko frequency, and enable or disable mcko gating. this register should be configured as soon as the ndi is enabled. the pcr register may be re written by the debug tool s ubsequent to the enabling of the npc for low power debug support. in this case, the debug tool may set and clear the lp_dbg_en, sleep_sync, and stop_sync bits, but must preserve the original state of the remaining bits in the register. note the mode or clock division must not be modified after mcko has been enabled. changing the mode or clock division while mcko is enabled can produce unpredictable results. reg index: 0 access: user read only 0123456789101112131415 r part revision number 1 1 part revision number default value is 0x0 for the device?s initial mask set and changes for each mask set revision. design center part identification number w reset 0000???????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r part identification number ( continued ) manufacturer identity code 1 w reset ????000001000001 figure 26-3. nexus device id register (did) table 26-3. did field descriptions field description 0?3 prn part revision number. contains the revision number of the part. this field changes with each revision of the device or module. 4?9 dc design center. 10?19 pin part identification number. contains the part number of the device. 20?30 mic manufacturer identity code. contains the reduced joint electron device engineering council (jedec) id: 0x20. 31 fixed per jtag 1149.1. always set to 1.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 26-7 preliminary?subject to change without notice reg index: 127 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r fpm mcko_gt mcko_en mcko_div evt_en 00000000 0 w reset 0 0 0 000000000000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r lp_dbg_en 0 0 000 sleep_sync stop_sync 0000000 pstat_en w reset 0 0 0 000000000000 0 figure 26-4. port configuration register (pcr) table 26-4. pcr field descriptions field description fpm full port mode.the value of the fpm bit determines if the auxiliary output port uses the full mdo port or a reduced mdo port to transmit messages. 0 a subset of mdo pins are used to transmit messages. 1 all mdo pins are used to transmit messages. mcko_gt mcko clock gating control.this bit is used to enable or disable mcko clock gating. if clock gating is enabled, the mcko clock is gated wh en the npc is in enabled mode but not actively transmitting messages on the auxiliary output port. when clock gating is disabled, mcko is allowed to run even if no auxiliary output port messages are being transmitted. 0 mcko gating is disabled. 1 mcko gating is enabled. mcko_en mcko enable. this bit enables the mcko clock to run. when enabled, the frequency of mcko is determined by the mcko_div field. 0 mcko clock is driven to zero. 1 mcko clock is enabled.
pxd10 microcontroller reference manual, rev. 1 26-8 freescale semiconductor preliminary?subject to change without notice 26.6.2.3 development control register 1, 2 (dc1, dc2) the development control regi sters are used to control the basic deve lopment features of the nexus module. figure 26-5 shows development control register 1 and table 26-5 describes the register?s fields. mcko_div mcko division factor. the value of this signal determines the frequency of mcko relative to the system clock frequency when mcko_en is assert ed. in this table, sys_clk represents the system clock frequency. evt_en evto/evti enable. this bit en ables the evto/evti port functions. 0 evto/evti port disabled. 1 evto/evti port enabled. lp_dbg_en low power debug enable. the lp_dbg_en bit enables debug functionality to support entry and exit from low power sleep and stop modes. 0 low power debug disabled. 1 low power debug enabled. sleep_sync sleep mode synchr onization. the sleep_sync bit is used to synchronize the entry into sleep mode between the device and debug tool. the device sets this bit before a pending entry into sleep mode. after reading sleep _sync as set, the debug tool then clears sleep_sync to acknowledge to the device that it may enter into sleep mode. 0 sleep mode entry acknowledge. 1 sleep mode entry pending. stop_sync stop mode synchronization. the stop_sync bi t is used to synchronize the entry into stop mode between the device and debug tool. the device sets this bit before a pending entry into stop mode. after reading stop_sync as set, the debug tool then clears stop_sync to acknowledge to the device that it may enter into stop mode. 0 stop mode entry acknowledge. 1 stop mode entry pending pstat_en processor status mode enable. table 26-4. pcr field descriptions (continued) field description mcko_div[2:0] mcko frequency 0b000 sysclk ? 1 0b001 sysclk ? 2 0b010 reserved 0b011 sys_clk ? 4 0b100 reserved 0b101 reserved 0b110 reserved 0b111 sys_clk ? 8
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 26-9 preliminary?subject to change without notice nexus reg: 0x0002 access: user read/write 0123456789101112131415 r opcmck_div eoc 0ptmwen00000000 w reset 00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ovc eic tm w reset 00000000 00000000 figure 26-5. development control register 1 (dc1) table 26-5. dc1 field descriptions field description 0 opc 1 output port mode control. 0 reduced-port mode configuration (2 mdo pins). 1 full-port mode configuration (4 mdo pins). 1?2 mck_div[1:0] 1 mcko clock divide ratio (see note 1). 00 mcko is 1x processor clock freq. 01 mcko is 1/2x processor clock freq. 10 mcko is 1/4x processor clock freq. 11 mcko is 1/8x processor clock freq. 3?4 eoc[1:0] evto control. 00 evto upon occurrence of watchpoints (configured in dc2). 01 evto upon entry into debug mode. 10 evto upon timestamping event. 11 reserved. 5 reserved. 6 ptm program trace method. 0 program trace uses traditional branch messages. 1 program trace uses branch history messages. 7 wen watchpoint trace enable. 0 watchpoint messaging disabled. 1 watchpoint messaging enabled. 8?23 reserved. 24?26 ovc[2:0] overrun control. 000 generate overrun messages. 001?010 reserved. 011 delay processor for btm / dtm / otm overruns. 1xx reserved.
pxd10 microcontroller reference manual, rev. 1 26-10 freescale semiconductor preliminary?subject to change without notice development control register 2 is shown in figure 26-6 and its fields are described in table 26-6 . 27?28 eic[1:0] evti control. 00 evti is used for synchronization (program trace/ data trace). 01 evti is used for debug request. 1x reserved. 29?31 tm[2:0] trace mode. any or all of the tm bits may set, enabling one or more traces. 000 no trace. 1xx program trace enabled. x1x data trace enabled (not supported mode) xx1 ownership trace enabled. 1 the output port mode control bit (opc) and mcko divide bits (mck_div) are shown for clarity. these functions are controlled globally by the npc port control register (p cr). these bits are writable in the pcr but have no effect. nexus reg: 0x0003 access: user read/write 0123456789101112131415 r ewc 00000000 w reset 00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 00000000 w reset 00000000 00000000 figure 26-6. development control register 2 (dc2) table 26-6. dc2 field descriptions field description 0?7 ewc[7:0] evto watchpoint configuration. any or all of the bits in ewc may be set to configure the evto watchpoint. 00000000 no watchpoints trigger evto 1xxxxxxx watchpoint #0 (iac1 from nexus1) triggers evto. x1xxxxxx watchpoint #1 (iac2 from nexus1) triggers evto. xx1xxxxx watchpoint #2 (iac3 from nexus1) triggers evto. xxx1xxxx watchpoint #3 (iac4 from nexus1) triggers evto. xxxx1xxx watchpoint #4 (dac1 from nexus1) triggers evto. xxxxx1xx watchpoint #5 (dac2 from nexus1) triggers evto. xxxxxx1x watchpoint #6 (dcnt1 from nexus1) triggers evto. xxxxxxx1 watchpoint #7 (dcnt2 from nexus1) triggers evto. 8?31 reserved. table 26-5. dc1 field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 26-11 preliminary?subject to change without notice note the eoc bits in dc1 must be progr ammed to trigger evto on watchpoint occurrence for the ewc bits to have any effect. 26.6.2.4 development status register (ds) the development status register is used to report system debug status. when debug mode is entered or exited, or a core-defined low-power mode is ente red, a debug status message is transmitted with ds[31:24]. the external tool can r ead this register at any time. nexus reg: 0x0004 access: user read only 0123456789101112131415 r dbg lps lpc chk0 00000000 w reset 00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 00000000 w reset 00000000 00000000 figure 26-7. development status register (ds) table 26-7. ds field descriptions field description 0 dbg cpu debug mode status. 0 cpu not in debug mode. 1 cpu in debug mode. 1?3 lps system low power status 000 normal (run) mode xx1 doze mode x1x nap mode 1xx sleep mode 4?5 lpc[1:0] cpu low-power mode status. 00 normal (run) mode. 01 cpu in halted state. 10 cpu in stopped state. 11 reserved. 6 chk cpu checkstop status. 0 cpu not in checkstop state. 1 cpu in checkstop state. 7?31 reserved.
pxd10 microcontroller reference manual, rev. 1 26-12 freescale semiconductor preliminary?subject to change without notice 26.6.2.5 read/write access control/status (rwcs) the read write access contro l/status register provide s control for read/write access. read /write access provides dma-like access to memory-mapped resources on the system bus while the processor is halted or during runtime. the rwcs regist er also provides read/write access status information as shown in table 26-9 . nexus reg: 0x0007 access: user read/write 0123456789101112131415 r acrw sz map pr 000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cnt err dv w reset 0000000000000000 figure 26-8. read/write access control/status register (rwcs) table 26-8. rwcs field description field description 0 ac access control. 0 end access. 1 start access. 1 rw read/write select. 0 read access. 1 write access. 2?4 sz[2:0] word size. 000 8-bit (byte.) 001 16-bit (halfword). 010 32-bit (word). 011 64-bit (doubleword?only in burst mode). 100?111 reserved (default to word). 5?7 map[2:0] map select. 000 primary memory map. 001-111 reserved. 8?9 pr[1:0] read/write access priority. 00 lowest access priority. 01 reserved (default to lowest priority). 10 reserved (default to lowest priority). 11 highest access priority. 10?15 reserved.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 26-13 preliminary?subject to change without notice table 26-9 details the stat us bit encodings. 26.6.2.6 read/write a ccess address (rwa) the read/write access address regist er provides the system bus address to be accessed when initiating a read or a write access. 26.6.2.7 read/write access data (rwd) the read/write access data register provides the data to/from system bus memory-mapped locations when initiating a read or a write access. 16?31 cnt[13:0] access control count. number of accesses of word size sz. 30 err read/write access error. see ta bl e 2 6 - 9 . 31 dv read/write access data valid. see table 26-9 . table 26-9. read/write access status bit encoding read action write action err dv read access has not completed write access completed without error 0 0 read access error has occurred wri te access error has occurred 1 0 read access completed without error w rite access has not completed 0 1 not allowed not allowed 1 1 nexus reg: 0x0009 access: user read/write 0123456789101112131415 r rwa[0-15] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rwa[16-31] w reset 0000000000000000 figure 26-9. read/write access address register (rwa) table 26-8. rwcs field description (continued) field description
pxd10 microcontroller reference manual, rev. 1 26-14 freescale semiconductor preliminary?subject to change without notice 26.6.2.8 watchpoint trigger register (wt) the watchpoint trigger regist er allows the watchpoints defined within the nexus1 logic to trigger actions. these watchpoints can control program and/or data trace enable and di sable. the wt bits can be used to produce an address-related window for triggering trace messages. table 26-10 details the watchpoint tr igger register fields. nexus reg: 0x000a access: user read/write 0123456789101112131415 r rwd[0-15] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rwd[16-31] w reset 0000000000000000 figure 26-10. read/write access data register (rwd) nexus reg: 0x000b access: user read/write 0123456789101112131415 r pts pte 0000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w reset 0000000000000000 figure 26-11. watchpoint trigger register (wt)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 26-15 preliminary?subject to change without notice 26.7 functional description the ndi block is implemented by integrati ng the following blocks on this device: ? nexus e200z0 development inte rface (once and nexus2p subblocks) ? nexus port controller (npc) block ? npc_hndshk module 26.7.1 npc_hndshk module this module enables debug entry/exit across low power modes(stop, halt, standby) . the npc_hndshk supports: ? setting and clearing of the npc pcr sync bit on low-power mode entry and exit ? putting the core into debug mode on low-power mode exit ? generating a falling edge on the jtag tdo pad on low-power mode exit on halt0, stop0, or standby0 m ode entry, the mc_me asserts th e lp_mode_entry_req input after the clock disable process has completed and before th e processor enters its halted or stopped state. the mode transition will then not proceed until the lp_mode_entry_ack output has been asserted. the notification to the debugger of a low- power mode entry consists of sett ing the low-power mode handshake bit in the port control register (read by th e debugger) via the lp_sync _in output. the debugger acknowledges that the transition in to a low-power mode may procee d by clearing the low-power mode handshake bit in the port control re gister (written by the de bugger), which results in the deassertion of the lp_sync_out input. table 26-10. wt field descriptions field description 0?2 pts[2:0] program trace start control. 000 trigger disabled. 001 use watchpoint #0 (iac1 from nexus1). 010 use watchpoint #1 (iac2 from nexus1). 011 use watchpoint #2 (iac3 from nexus1). 100 use watchpoint #3 (iac4 from nexus1). 101 use watchpoint #4 (dac1 from nexus1). 110 use watchpoint #5 (dac2 from nexus1). 111 use watchpoint #6 or #7 (dcnt1 or dcnt2 from nexus1). 3?5 pte[2:0] program trace end control. 000 trigger disabled. 001 use watchpoint #0 (iac1 from nexus1). 010 use watchpoint #1 (iac2 from nexus1). 011 use watchpoint #2 (iac3 from nexus1). 100 use watchpoint #3 (iac4 from nexus1). 101 use watchpoint #4 (dac1 from nexus1). 110 use watchpoint #5 (dac2 from nexus1). 111 use watchpoint #6 or #7 (dcnt1 or dcnt2 from nexus1). 12?31 reserved.
pxd10 microcontroller reference manual, rev. 1 26-16 freescale semiconductor preliminary?subject to change without notice in anticipation of the low-power mode exit notification, the tdo pa d is driven to `1'. on halt0 or stop0 mode exit, the mc_me asserts the lp_mode_exit_req input after ensuring that the regulator and memories are in normal mode and before the processor exits its halt ed or stopped state. the mode transition will then not proc eed until the lp_mode_exit_ack output has been asserted. the mc_rgm asserts the exit_from_standby input wh en executing a reset sequence due to a standby0 exit. the reset sequence will then not complete until the lp_mode_exit_ack output has been asserted. the notification to the debugger of a low-power mode exit consists of driving the tdo pad to `0'. the debugger acknowledges that the transiti on from a low-power mode can c ontinue by setting the low-power mode sync bit in the port control register (written by debugger), which results in the assertion of the lp_sync_out input. note the debugger clock multiplexer may not guarantee glitch free switching. therefore, tck should be disabled fr om when the debugger clears the sync bit in entry_clr until the debugger se nses the falling edge of tdo in tdo_set. 26.7.2 enabling nexus clients for tap access after the conditions have been met to bring the ndi out of the reset state, the loading of a specific instruction in the jtag controller (jtagc) block is re quired to grant the ndi owne rship of the tap. each nexus client has its own jtagc instruction opcode fo r ownership of the tap, granting that client the means to read/write its registers. the jtagc inst ruction opcode for each nexus client is shown in table 26-11 . after the jtagc opcode for a client has been loaded, the client is enabled by loading its nexus-enable instruction. the nexus-enable instruct ion opcode for each nexus client is listed in table 26-12 . opcodes for all other instructions supported by nexus clients can be found in the relevant sections of this chapter. table 26-11. jtagc instruction opcodes to enable nexus clients jtagc instruction opcode description access_aux_tap_npc 10000 enables a ccess to the npc tap controller. access_aux_tap_once 10001 enables access to the e200z0 tap controller. table 26-12. nexus client jtag instructions instruction description opcode npc jtag instruction opcodes nexus_enable opcode for npc nexus enable instruction (4-bits) 0x0 bypass opcode for the npc bypass instruction (4-bits) 0xf e200z0 once jtag instruction opcodes 1 nexus2_access opcode for e200z0 once nexus enable instruction (10-bits) 0x7c bypass opcode for the e200z0 once bypass instruction (10-bits) 0x7f
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 26-17 preliminary?subject to change without notice 26.7.3 configuring the ndi for nexus messaging the ndi is placed in disabled mode upon exit of re set. if message transmissi on via the auxiliary port is desired, a write to the port configuration register (pcr) located in the npc is then required to enable the ndi and select the mode of opera tion. asserting mcko_en in the pcr places the ndi in enabled mode and enables mcko. the frequency of mcko is selected by writing th e mcko_div field. asserting or negating the fpm bit selects full-por t or reduced-port mode, respectively. when writing to the pcr, the pcr lsb must be written to a logic zero. setting the lsb of the pcr enables factory debug mode and prevents the transmis sion of nexus messages. table 26-13 describes the ndi configuration options. 26.7.4 programmable mcko frequency mcko is an output clock to the de velopment tools used for the timi ng of mseo and mdo pin functions. mcko is derived from the system cl ock, and its frequency is determin ed by the value of the mcko_div field in the port configuration regi ster (pcr) located in the npc. po ssible operating frequencies include one-quarter and one-eighth system clock speed. figure 26-14 shows the mcko_div encodings. in this ta ble, sys_clk represents the system clock frequency. the default value selected if a reserved encoding is programmed is sys_clk ? 2 note on pxd10, the pad type used for the nexus2+ signals wi ll not support the default sysclk ? 2 and sysclk ??? setting, so the user must change the mcko frequency to be not faster than sysclk ? 4. 1 refer to the e200z0 reference manual for a complete list of available once instructions. table 26-13. ndi configuration options jcomp asserted mcko_en bit of the port configuration register fpm bit of the port configuration register configuration no x x reset ye s 0 x d i s a b l e d yes 1 1 full-port mode yes 1 0 reduced-port mode table 26-14. mcko_div values mcko_div[2:0] mcko frequency 0b000 sysclk ? 1 0b001 sysclk ? 2 0b010 reserved 0b011 sys_clk ? 4
pxd10 microcontroller reference manual, rev. 1 26-18 freescale semiconductor preliminary?subject to change without notice 26.7.5 nexus messaging most of the messages transmitted by the ndi include a src field. this field is used to identify which source generated the message. table 26-15 shows the values used for the s rc field by the different clients on the pxd10. these values are specific to the pxd10. the size of the src field in transmitted messages is 4 bits. this value is also specific to the pxd10. 26.7.6 evto sharing the npc block controls sharing of the evto output between all nexus clients that generate an evto signal. the sharing mechanism is a logical and of all incoming evto signals from nexus blocks, thereby asserting evto whenever a ny block drives its evto . when there is no active mcko, such as in disabled mode, the npc drives evto for two system clock periods. evto sharing is active as long as the ndi is not in reset. 26.7.7 debug mode control on pxd10, program breaks can be requested either by using the evti pin as a break request, or when a nexus event is triggered. 26.7.7.1 evti generated break request to use the evti pin as a debug request, the eic field in the e200z0 nexus2+ development control register 1 (dc1[4:3]) must be set to c onfigure the evti input as a debug request. 26.7.8 nexus reset control the jcomp input that is used as th e primary reset signal for the npc is also used by the npc to generate a single-bit reset signal for other nexus blocks. the si ngle bit reset signal functi ons much like the ieee 1149.1-2001 defined trst signal but has a default value of disabled (jcomp is pulled low during reset) the ieee 1149.1-2001 defines trst to be pulled up (enabled) by default. 0b100 reserved 0b101 reserved 0b110 reserved 0b111 sys_clk ? 8 table 26-15. src packet encodings src[3:0] pxd10 client 0b0000 e200z0 all other combinations reserved table 26-14. mcko_div values (continued) mcko_div[2:0] mcko frequency
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 26-19 preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 26-20 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 27-1 preliminary?subject to change without notice chapter 27 periodic interrupt timer (pit) 27.1 introduction 27.1.1 overview the pit is an array of timers that can be used to raise interrupts and trigger dma channels. this device has one pit module with four timer channels (pit channels 0 through 3). these are connected to the trigger input 0 through 3 of the dma mux. figure 27-1 shows the pit block diagram. figure 27-1. pit block diagram 27.1.2 features the main features of this block are: ? timers can generate dma trigger pulses ? timers can generate interrupts ? all interrupts are maskable timer 3 timer 0 . . . pit registers peripheral interrupts peripheral pit . . . triggers bus bus clock
pxd10 microcontroller reference manual, rev. 1 27-2 freescale semiconductor preliminary?subject to change without notice ? independent timeout periods for each timer 27.2 signal description the pit module has no external pins. 27.3 memory map and register description this section provides a detailed description of all registers accessi ble in the pit module. 27.3.1 memory map table 27-1 gives an overview on all pit registers. note register address = base address + a ddress offset, where the base address is defined at the mcu level and the a ddress offset is defined at the module level. note reserved registers will read as 0, writes will have no effect. table 27-1. pit memory map address offset use access 0x000 pit module control register r/w 0x004 - 0x0fc reserved r 0x100 - 0x10c timer channel 0 1 1 see ta b l e 2 7 - 2 0x110 - 0x11c timer channel 1 1 0x120 - 0x12c timer channel 2 1 0x130 - 0x13c timer channel 3 1 0x140 - 0x1fc reserved r table 27-2. timer channel n address offset use access channel + 0x00 timer load value register r/w channel + 0x04 current timer value register r channel + 0x08 timer control register r/w channel + 0x0c timer flag register r/w
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 27-3 preliminary?subject to change without notice 27.3.2 register descriptions this section describes in address order all the pit registers and their individual bits. 27.3.2.1 pit module control register (pitmcr) this register controls whether the timer clocks s hould be enabled and whether the timers should run in debug mode. table 27-3. pitmcr field descriptions 27.3.2.2 timer load value register (ldval) these registers select the timeout period for the timer interrupts. offset 0x000 access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000 0 0 0 0 0 mdis frz w reset0000000000000010 figure 27-2. pit module co ntrol registers (pitmcr) field description mdis module disable. this is used to disable the module clock. this bit should be enabled before any other setup is done. 0 clock for pit timers is enabled 1 clock for pit timers is disabled (default) frz freeze. allows the timers to be stopped when the device enters debug mode. 0 = timers continue to run in debug mode. 1 = timers are stopped in debug mode.
pxd10 microcontroller reference manual, rev. 1 27-4 freescale semiconductor preliminary?subject to change without notice 27.3.2.3 current timer value register (cval) these registers indicate th e current timer position. offset channel_base + 0x00 access: read/write 0123456789101112131415 r tsv31 tsv30 tsv29 tsv28 tsv27 tsv26 tsv25 tsv24 t sv23 tsv22 tsv21 tsv20 tsv19 tsv18 tsv17 tsv16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tsv15 tsv14 tsv13 tsv12 tsv11 tsv10 tsv9 tsv8 tsv7 tsv6 tsv5 tsv4 tsv3 tsv2 tsv1 tsv0 w reset0000000000000000 figure 27-3. timer load value register (ldval) table 27-4. ldval field descriptions field description tsv n time start value bits. these bits set the timer start value. the timer will count down until it reaches 0, then it will generate an interrupt and load this register value again. writing a new value to this register will not restart the timer, instead the value will be loaded once the timer expires. to abort the current cycle and start a timer peri od with the new value, the timer must be disabl ed and enabled again (see figure 27-8 ).
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 27-5 preliminary?subject to change without notice 27.3.2.4 timer contro l register (tctrl) these register contain the control bits for each timer. offset channel_base + 0x04 access: read/write 0123456789101112131415 r tvl31 tvl30 tvl29 tvl28 tvl27 tvl26 tvl25 tvl24 tvl23 tvl22 tvl21 tvl20 tvl19 tvl18 tvl17 tvl16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tvl15 tvl14 tvl13 tvl12 tvl11 tvl10 tvl9 tvl8 tvl7 tvl6 tvl5 tvl4 tvl3 tvl2 tvl1 tvl0 w reset0000000000000000 figure 27-4. current timer value register (cval) table 27-5. cval field descriptions field description tvl n current timer value. these bits represent the cu rrent timer value. note that the timer uses a downcounter. note: the timer values will be frozen in debug mode if the frz bit is set in the pit module control register (see figure 27-2 )
pxd10 microcontroller reference manual, rev. 1 27-6 freescale semiconductor preliminary?subject to change without notice 27.3.2.5 timer flag register (tflg) these registers hold the pit interrupt flags. offset channel_base + 0x08 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000000000 tie ten w reset0000000000000000 figure 27-5. timer control register (tctrl) table 27-6. tctrl field descriptions field description tie timer interrup t enable bit. 0 interrupt requests from timer x are disabled 1 interrupt will be requested whenever tif is set when an interrupt is pending (tif set), enabling the interrupt will immediately cause an interrupt event. to avoid this, the associated tif flag must be cleared first. ten timer enable bit. 0 timer will be disabled 1 timer will be active
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 27-7 preliminary?subject to change without notice 27.4 functional description 27.4.1 general this section gives detailed informat ion on the internal operati on of the module. each timer can be used to generate trigger pulses as well as to generate inte rrupts, each interrupt will be available on a separate interrupt line. 27.4.1.1 timers the timers generate triggers at periodic intervals, wh en enabled. they load their start values, as specified in their ldval registers, then count down until they reach 0. then they load their respective start value again. each time a timer reaches 0, it will gene rate a trigger pulse, and set the interrupt flag. all interrupts can be enabled or masked (by setting th e tie bits in the tctrl re gisters). a new interrupt can be generated only after th e previous one is cleared. if desired, the current counter value of the timer can be read via the cval registers. offset channel_base + 0x0c access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000000tif w w1c reset0000000000000000 figure 27-6. timer flag register (tflg) table 27-7. tflg field descriptions field description tif time interrupt flag. tif is set to 1 at the end of the timer period.this flag can be cleared only by writing it with a 1. writing a 0 has no effect. if enabled (tie = 1), tif causes an interrupt request. 0 time-out has not yet occurred 1 time-out has occurred
pxd10 microcontroller reference manual, rev. 1 27-8 freescale semiconductor preliminary?subject to change without notice the counter period can be restarte d, by first disabling, then enabling the timer with the ten bit (see figure 27-7 ). the counter period of a runni ng timer can be modified, by first disabli ng the timer, settin g a new load value and then enabling the timer again (see figure 27-8 ). it is also possible to change th e counter period without restarting the timer by wr iting the ldval register with the new load value. this value will then be loaded after the next trigger event (see figure 27-9 ). figure 27-7. stopping and starting a timer figure 27-8. modifying running timer period figure 27-9. dynamically setting a new load value 27.4.1.2 debug mode in debug mode the timers will be frozen - this is intended to aid software development, allowing the developer to halt the proces sor, investigate the current state of th e system (e.g. the timer values) and then continue the operation. 27.4.2 interrupts all of the timers support interrupt generation. refer to th e mcu specification for re lated vector addresses and priorities. p1 p1 timer enabled disable timer p1 start value = p1 trigger event p1 re-enable timer p1 timer enabled disable timer, start value = p1 trigger event re-enable timer p1 set new load value p2 p2 p2 p1 p1 timer enabled new start value p2 set p1 p2 start value = p1 p2 trigger event
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 27-9 preliminary?subject to change without notice timer interrupts can be disa bled by setting the tie bits to zero. the timer interrupt flags (tif) are set to 1 when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to that tif bit. 27.5 initialization and application information 27.5.1 example configuration in the example configuration: ? the pit clock has a frequency of 50 mhz ? timer 1 shall create an interrupt every 5.12 ms ? timer 3 shall create a trigger event every 30 ms first the pit module needs to be activated by writin g a 0 to the mdis bit in the pitctrl register. the 50 mhz clock frequency equates to a clock period of 20 ns . timer 1 needs to trigger every 5.12 ms/20 ns = 256000 cycles and timer 3 every 30 ms/20 ns = 1500000 cycles. the value for the ldval register trigger would be calculated as (period / clock period) -1. this means that ldval1 with 0003e7f f hex and ldval3 with 0016e35f hex. the interrupt for timer 1 is enabled by setting tie in the tctrl1 register. the ti mer is started by writing a 1 to bit ten in the tctrl1 register. timer 3 shall be used only for triggering. therefore ti mer 3 is started by writi ng a 1 to bit ten in the tctrl3 register, bit tie stays at 0. the following example code matches the described setup: // turn on pit pit_ctrl = 0x00; // rti pit_rti_ldval = 0x004c4b3f; // setup rti for 5000000 cycles pit_rti_tctrl = pit_tie; // let rti generate interrupts pit_rti_tctrl |= pit_ten; // start rti // timer 1 pit_ldval1 = 0x0003e7ff; // setup timer 1 for 256000 cycles pit_tctrl1 = tie; // enable timer 1 interrupts pit_tctrl1 |= ten; // start timer 1 // timer 3 pit_ldval3 = 0x0016e35f; // setup timer 3for 1500000 cycles pit_tctrl3 = ten; // start timer 3
pxd10 microcontroller reference manual, rev. 1 27-10 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 28-1 preliminary?subject to change without notice chapter 28 peripheral bridge (pbridge) 28.1 introduction the pbridge is the interface between the system bus a nd on-chip peripherals. it differs from that used on power architecture pr oducts in the fact that it has a hard-wired configurati on and cannot be configured in software. 28.1.1 overview pxd10 devices have one pbridge, which provides an interface between the system bus and all lower bandwidth peripherals. accesses that fall within the address space of th e pbridge are decoded to provide individual module selects for periphera l devices on the slave bus interface. 28.1.2 features the following list summarizes th e key features of the pbridge. ? supports the slave interface signals. this in terface is only meant for slave peripherals. ? supports 32-bit slave peripherals. (byte, halfwo rd, and word reads and writes are supported to each.) 28.1.3 modes of operation the pbridge has only one operating mode. 28.2 functional description the pbridge serves as an interface between a system bus and the peripheral (slave) bus. it functions as a protocol translator. acces ses that fall within the address space of the pbridge are decoded to provide individual module selects for periphera l devices on the slave bus interface. 28.2.1 access support aligned 32-bit word accesses, halfword accesses, and byte accesses are supported for the peripherals. peripheral registers must not be misaligned, although no explicit chec king is performe d by the pbridge. note data accesses that cross a 32 -bit boundary are not supported. 28.2.1.1 peripheral write buffering buffered writes are not supported by the pxd10 pbridge.
pxd10 microcontroller reference manual, rev. 1 28-2 freescale semiconductor preliminary?subject to change without notice 28.2.1.2 read cycles two-clock read accesses are possibl e with the pbridge when the reque sted access size is 32-bits or smaller, and is not misali gned across a 32-bit boundary. 28.2.1.3 write cycles three-clock write accesses are possibl e with the pbridge when the requested access size is 32-bits or smaller. misaligned writes that cr oss a 32-bit boundary are not supported. 28.2.2 general operation slave peripherals are modules that contain readable/wri table control and status re gisters. the system bus master reads and writes these re gisters through the pbridge. the p bridge generates module enables, the module address, transfer attribut es, byte enables, and writ e data as inputs to th e slave peripherals. the pbridge captures read data from the slave interface and dr ives it on the system bus. the pbridge occupies a 64 mb portion of the address space. the register maps of the slave peripherals are located on 16-kb boundaries. each slave peripheral is allocated one 16-kb block of the memory map, and is activated by one of the module enables from the pbridge. the pbridge is responsible for indicat ing to slave peripherals if an acces s is in supervisor or user mode.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 29-1 preliminary?subject to change without notice chapter 29 power control unit (mc_pcu) 29.1 introduction 29.1.1 overview the power control unit (mc_pcu) is used to reduc e the overall soc power consumption. power can be saved by disconnecting parts of the soc from the pow er supply via a power switc hing device. the soc is grouped into multiple parts ha ving this capability which are called ?power domains?. when a power domain is disconnected from the supply, the power consumpt ion is reduced to zero in that domain. any status information of such a power dom ain is lost. when re-conne cting a power domain to the supply voltage, the domai n draws an increased curr ent until the power domain reaches its operational voltage. power domains are controlled on a device mode basi s. for each mode, software can configure whether a power domain is connected to the supply voltage (power-up state) or disconnected (power-down state). maximum power saving is reache d by entering the standby mode. on each mode change request, the mc_pcu evalua tes the power domain settings in the power domain configuration registers and initia tes a power-down or a power-up sequence for each individual power domain. the power-up/down sequences are handled by fini te state machines to ensure a smooth and safe transition from one power state to the other. exiting the standby mode can only be done via a system wakeup event as all power domains other than power domain #0 are in the power-down state. in addition, the mc_pcu acts as a bridge for mapping the vreg pe ripheral to the mc_pcu address space. figure 29-1 depicts the mc_pcu block diagram.
pxd10 microcontroller reference manual, rev. 1 29-2 freescale semiconductor preliminary?subject to change without notice 29.1.2 features the mc_pcu includes the following features: ? support for 3 power domains ? support for device modes reset, drun, safe, test, run0?3, halt, stop, and standby (for further mode details , please see the mc_me chapter) ? power states updating on each mode change and on system wakeup ? a handshake mechanism for power state changes thus guarant eeing operable voltage ? maps the vreg registers to the mc_pcu address space 29.1.3 modes of operation the mc_pcu is available in all device modes. mc_me firc vreg wkpu power domains power domain state machines core registers platform interface mc_pcu figure 29-1. mc_pcu block diagram mapped module interface mapped peripheral
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 29-3 preliminary?subject to change without notice 29.2 external signal description the mc_pcu has no connections to any external pins . 29.3 memory map and register definition 29.3.1 memory map note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content ? cause a transfer error table 29-1. mc_pcu register description address name description size access 0xc3fe_8000 pcu_pconf0 power domain #0 configuration word read 0xc3fe_8004 pcu_pconf1 power domain #1 configuration word read 0xc3fe_8008 pcu_pconf2 power domain #2 configuration word read/write 0xc3fe_8040 pcu_pstat power domain status register word read table 29-2. mc_pcu memory map address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe_8000pcu_pconf0 r0 0 0 0 0000000 00000 w r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w 0xc3fe_8004pcu_pconf1 r0 0 0 0 0000000 00000 w r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w 0xc3fe_8008pcu_pconf2 r0 0 0 0 0000000 00000 w r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w
pxd10 microcontroller reference manual, rev. 1 29-4 freescale semiconductor preliminary?subject to change without notice 29.3.2 register descriptions all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. fo r example, the pd0 field of the pcu_psta t register may be accessed as a word at address 0xc3fe_8040, as a half-word at address 0xc3fe_8042, or as a byte at address 0xc3fe_8043. 29.3.2.1 power domain #0 configuration register (pcu_pconf0) 0xc3fe_800c ? 0xc3fe_803c reserved 0xc3fe_8040pcu_pstat r0 0 0 0 0000000 00000 w r pd2 pd1 pd0 w 0x044 ? 0x07c reserved 0xc3fe_8080 ? 0xc3fe_80fc vreg registers 0xc3fe_8100 ? 0xc3fe_bffc reserved address 0xc3fe_8000 access: supervisor read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0010010111111111 figure 29-2. power domain #0 conf iguration register (pcu_pconf0) table 29-2. mc_pcu memory map (continued) address name 012327 567891011 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 29-5 preliminary?subject to change without notice this register defines for power dom ain #0 whether it is on or off in each device mode. as power domain #0 is the always-on power domain (and includes the mc _pcu), none of its bits are programmable. this register is available for completeness reasons. table 29-3. power domain configur ation register field descriptions field description rst power domain cont rol during reset mode 0 power domain off 1 power domain on test power domain control during test mode 0 power domain off 1 power domain on safe power domain control during safe mode 0 power domain off 1 power domain on drun power domain control during drun mode 0 power domain off 1 power domain on run0 power domain control during run0 mode 0 power domain off 1 power domain on run1 power domain control during run1 mode 0 power domain off 1 power domain on run2 power domain control during run2 mode 0 power domain off 1 power domain on run3 power domain control during run3 mode 0 power domain off 1 power domain on halt power domain control during halt mode 0 power domain off 1 power domain on stop power domain control during stop mode 0 power domain off 1 power domain on stby0 power domain control during standby mode 0 power domain off 1 power domain on
pxd10 microcontroller reference manual, rev. 1 29-6 freescale semiconductor preliminary?subject to change without notice 29.3.2.2 power domain #1 configuration register (pcu_pconf1) this register defines for power domain #1 whether it is on or off in each device mode. the bit field description is the same as in table 29-3 . as the platform, clock generati on, and mode control reside in power domain #1, this power domai n is only powered down during the standby mode. therefore, none of the bits is programmable. this regist er is available for completeness reasons. the difference between pcu_pconf0 and pcu_pconf1 is the reset value of the stby0 bit: during the standby mode, power domain #1 is disconn ected from the power supply, and therefore pcu_pconf1.stby0 is always ?0?. powe r domain #0 is always on, and therefore pcu_pconf0.stby0 is ?1?. for further details about st andby mode, please refer to section 29.4.4.2, standby mode transition . 29.3.2.3 power domain #2 configuration register (pcu_pconf2) this register defines for power domain #2 whether it is on or off in each device mode. the bit field description is the same as in table 29-3 . address 0xc3fe_8004 access: supervisor read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0000010111111111 figure 29-3. power domain #1 conf iguration register (pcu_pconf1) address 0xc3fe_8008 access: supervisor read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0000010111111111 figure 29-4. power domain #2 conf iguration register (pcu_pconf2)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 29-7 preliminary?subject to change without notice 29.3.2.4 power domain status register (pcu_pstat) this register reflects the power stat us of all available power domains. 29.4 functional description 29.4.1 general the mc_pcu controls all available power domai ns on a device mode basis. the pcu_pconf n registers specify during which system/user modes a power domain is powered up. the power state for each individual power domain is reflected by the bits in the pcu_pstat register. on a mode change, the mc_pcu ev aluates which power domai n(s) must change power state. the power state is controlled by a st ate machine (fsm) for each individual power domain (see figure 3-1 ) which ensures a clean and safe state transition. 29.4.2 reset / power-on reset after any reset, the soc will tran sition to the reset mode during which all power domains are powered up (see the mc_me chapter). once the reset sequenc e has been completed, the drun mode is entered and software can begin th e mc_pcu configuration. 29.4.3 mc_pcu configuration per default, all power domains are powered in all modes other than st andby. software can change the configuration for each power domain on a mode basis by programming the pcu_pconf n registers. address 0xc3fe_8040 access: supervisor read 0 1 2 3 4 5 6 7 8 9 101112131415 r00000 00000000000 w reset00000 00000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pd2 pd1 pd0 w reset00000 00000000111 figure 29-5. power domain status register (pcu_pstat) table 29-4. power domain status register (pcu_pstat) field descriptions field description pd n power status for power domain # n 0 power domain is inoperable 1 power domain is operable
pxd10 microcontroller reference manual, rev. 1 29-8 freescale semiconductor preliminary?subject to change without notice each power domain which is powered down is held in a reset state. read/write accesses to peripherals in those power domains will re sult in a transfer error. 29.4.4 mode transitions on a mode change requested by the mc_me, the mc _pcu evaluates the power configurations for all power domains. it compares th e settings in the pcu_pconf n registers for the new m ode with the settings for the current mode. if the configuration for a pow er domain differs between the modes, a power state change request is generated. these requests are handled by a finite stat e machine to ensu re a smooth and safe transition from one power state to another. 29.4.4.1 drun, safe, test, run0?3, halt, and stop mode transition the drun, safe, test, run0?3, halt, and stop modes allow an increased power saving. the level of power saving is software-controll able via the settings in the pcu_pconf n registers for power domain #2 onwards. the settings fo r power domains #0 and #1 can not be changed. therefore, power domains #0 and #1 remain connected to the power supply for all modes beside standby. figure 29-6 shows an example for a mode tr ansition from run0 to halt a nd back, which will result in power domain #2 being powered down during the hal t mode. in this case, pcu_pconf2.halt is programmed to be ?0?. when the mc_pcu receives the mode change request to halt mode, it starts its power-down phase. during the power-down phase, clocks are disabled and the reset is asse rted resulting in a loss of all information for this power domain. then the power domain is disconnected fr om the power supply (power-down state). figure 29-6. mc_pcu events during power sequences (non-standby mode) when the mc_pcu receives a mode change request to run0, it starts its power-up phase if pcu_pconf2.run0 is ?1?. the power domain is re-c onnected to the power supply, and the voltage in new mode power-down run0 voltage in pstat.pd2 halt run0 notes: not drawn to scale; pconf2 .run0 = 1; pconf2.halt = 0 current mode power-up phase power domain #2 run0 halt run0 requested by me power-down state power-up state power-up state phase
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 29-9 preliminary?subject to change without notice power domain #2 will increas e slowly. once the voltage of power domain #2 is within an operable range, its clocks are enabled, and its resets are deasserted (power-up state). note it is possible that, due to a mode ch ange, power-up is requested before a power domain completed its power-dow n sequence. in this case, the information in that power domain is lost. 29.4.4.2 standby mode transition standby offers the maximum power saving. the level of pow er saving is software -controllable via the settings in the pcu_pconf n registers for power dom ain #2 onwards. power dom ain #0 stays connected to the power supply while power dom ain #1 is disconnected from the power supply. amongst others power domain #1 contains the platform and the mc_me. therefore this mode differs from all other user/system modes. once standby is entered it can onl y be left via a syst em wakeup. on exiting the standby mode, all power domains are powered up accordi ng to the settings in the pcu_pconf n registers, and the drun mode is entered. in drun mode, at least power domains #0 and #1 are powered. figure 29-7 shows an example for a mode transition fr om run0 to standby to drun. all power domains which have pcu_pconf n .stby0 cleared will enter power- down phase. in this example only power domain #1 will be disa bled during standby mode. when the mc_pcu receives the mode change request to standby mode it starts the power down phase for power domain #1. during the power dow n phase, clocks are disabled and reset is asserted resulting in a loss of all information for this power domain. then the power domain is disc onnected from the power supply (power-down state).
pxd10 microcontroller reference manual, rev. 1 29-10 freescale semiconductor preliminary?subject to change without notice figure 29-7. mc_pcu events during power sequences ( standby mode) when the mc_pcu receives a syst em wakeup request, it starts the power-up phase. the power domain is re-connected to the power supply and the voltage in power domain #1 will increase slowly. once the voltage is in an operable range, cl ocks are enabled and the reset is be deasserted (power-up state). note it is possible that due to a wakeup re quest, power-up is requested before a power domain completed its power-dow n sequence. in this case, the information in that power domain is lost. 29.4.4.3 power saving for me mories during standby mode all memories which are not powered down during standby mode automatica lly enter a power saving state. no software configuration is required to enable this power savi ng state. while a memory is residing in this state an increased power saving is achieved. data in the memories is retained. 29.5 initialization information to initialize the mc_pcu, the registers pcu_pconf2? should be programmed. after programming is done, those registers should no longer be changed. new mode power-down run0 voltage in pstat.pd1 standby notes: not drawn to scale; pconf1.r un0 = 1; pconf1.stby0 = 0 current mode power-up phase power domain #1 run0 standby drun requested by me power-down state power-up state power-up state phase mode set due to reset being asserted to power domain #1 wakeup request
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 29-11 preliminary?subject to change without notice 29.6 application information 29.6.1 standby mode considerations standby offers maximum power saving possibility. but power is only saved during the time a power domain is disconnected from the suppl y. increased power is required wh en a power domain is re-connected to the power supply. additional power is required during restoring the in formation (e.g. in the platform). care should be taken that the time during which the soc is operating in standby mode is significantly longer than the required time for restoring the information.
pxd10 microcontroller reference manual, rev. 1 29-12 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-1 preliminary?subject to change without notice chapter 30 quad serial peripheral interface (quadspi) 30.1 preface 30.1.1 conventions table 30-1 contains conventions used in this document. 30.1.2 acronyms and abbreviations table 30-2 contains acronyms and abbreviations used in this document. table 30-1. conventions terms description active_high names for signals that are active high are sh own in uppercase text without an overbar. signals that are active high are referred to as asserted when they are logic 1 and negated when they are logic 0. active_low a bar over a signal name indicates that the signal is active low. active-low signals are referred to as asserted when they are logic 0 and negated when they are logic 1. 0x0f hexadecimal numbers 0b0011 binary numbers x in certain contexts, such as a signal encoding, this indicates a don?t care. for example, if a field is binary coded 0bx001, the stat e of the first bit is a don?t care. reg[bit] denotes the bitfields bit in the register reg table 30-2. acronyms and abbreviations terms description ahb advanced high-performance bus, version of amba amba advanced microcontroller bus architecture cs chip select. dma direct memory access. eoq end of queue lsb least significant bit msb most significant bit pcs peripheral chip select qspi, quadspi quad serial peripheral interface sck serial communications clock spi serial peripheral interface
pxd10 microcontroller reference manual, rev. 1 30-2 freescale semiconductor preliminary?subject to change without notice 30.1.3 glossary for quadspi module ss slave select. signal from the spi master to the spi slave indicating which spi slave device the master want to communicate with. w1c write 1 to clear, writing a ?1 ? to this field resets the flag table 30-3. glossary term definition ahb command an ahb command is a sfm command tr iggered by a read access to the address range belonging to the memory mapped access defined in table 30-35 . refer to section 30.6.6.2, ahb bus related commands ? for details. asserted a signal that is asserted is in its active state. an active low signal changes from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one. baud rate rate of data trans mission in bits per second. clear to clear a bit or bits means to establish logic level zero on the bit or bits. clock phase determines when the data should be sampled relative to the active edge of sck clock polarity determines the idle state of the sck signal. deserialize to convert data from a serial format to a parallel format. drain to remove entries from a fifo by software or hardware. field two or more register bits grouped together. fifo entry fifo entries and fifo registers are used interchangeably. fill to add entries to a fifo by software or hardware. frame the data content of a serial transmis sion. also referred to as quadspi data. host refers to another functional block in the device containing the quadspi module instruction code 8 bits defining the type of command to be executed. ip command a ip command is a sfm command trigger ed by writing into the qspi_mcr[ic] field. logic level one the voltage that corresponds to boolean true (1) state. logic level zero the voltage that corresponds to boolean false (0) state. negated a signal that is negated is in its inactive st ate. an active low signal changes from logic level ?0? to logic level ?1? when negated, and an active high signal changes from logic level ?1? to logic level ?0?. rx fifo first-in-first-out buffer for received data serialize to convert data from a parallel format to a serial format. set to set a bit or bits means to establish logic level one on the bit or bits. table 30-2. acronyms and abbreviations terms description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-3 preliminary?subject to change without notice 30.2 introduction figure 30-1 is a block diagram of the quad serial peripheral interface (quadspi) module. sfm command applicable in sfm mode only: a sfm comma nd consists of an instruction code and all other parameters (e.g. size or mode bytes) needed for that specific instruction code. triggering a command either initiates a transaction on the external serial flash or results in an error. refer to table 30-50 for details. sfm mode the quadspi is set up to for an external serial flash device. spi command applicable in spi master mode only. a spi command is part of each tx fifo entry specifying the parameters for the tr ansmission of that specific entry. spi master mode the quadspi is set up as spi master to communicate with external spi slave devices. spi modes spi slave mode or spi master mode. spi slave mode the quadspi is set up as spi slave to communicate with an exte rnal spi master device. transaction a transaction consists of all flags, data and signals in either direction to execute a command for an attached serial flash device. it is a comb ination of chip select, sclk, instruction code, address, mode- and/or dummy bytes, transmit and/or receive data. transfer format the combination of sck polarity, sck phase, data msb/lsb first, and associated cs signal timing during a serial transmission tx fifo first-in-first-out buffer for transmit data table 30-3. glossary (continued) term definition
pxd10 microcontroller reference manual, rev. 1 30-4 freescale semiconductor preliminary?subject to change without notice figure 30-1. quadspi block diagram ahb bus ips bus/ipd bus read read_done ahb_serve fetch received (addr, size, type) (data) ahb_control qspi_ic_sfm ahbcommand (inst, addr, size) ready rdata ipcommand (inst, addr, size) ready rdata sfm mode ctrl_vector ready wdata qspi_if core clock domain sclk clock domain quadspi bus ipacc ahbacc wdata rdata qspi_if_core qspi_if_sclk cmd txdata ready tx_acc rxdata ready rx_acc events rx buffer tx buffer sfar icr address register instruct. register command_build & buffer control define rd_data (addr, cmd) wr_data (data) (data) ahb buffer ip_ctrl (addr, size) (data) rx fifo data data cmd tx fifo dma and interrupt control & dataflow control command ip_control baud rate, delay & transfer control spi shift register modemux so_io1 si_io0 pcs[7:0] pad_ctrl tx_data rx_data ctrl_if qspi_io[3:2] sck dma and interrupt control spi modes command processing clock domain crosser cmd txdata ready tx_acc rxdata ready rx_acc events spi functionality sfm
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-5 preliminary?subject to change without notice 30.2.1 overview basically the quad serial peripheral interface (q uadspi) block serves for two different interfacing purposes: when acting as a serial peripheral interface it provides a synchronous serial bus for communication with an external peri pheral device. alternatively the quad spi block can act as an interface to a spi serial flas h device. refer to section 30.2.3, quadspi modes of operation ? for a description of the different modes. 30.2.2 features when acting as spi the quadspi supports the following features ? full-duplex, three-wire synchronous transfers ? master and slave mode ? buffered transmit operation using the tx fifo with parameterized depth of 15 ? buffered receive operation using the rx fifo with parameterized depth of 15 ? programmable transfer attributes on a per-frame basis: ? parameterized number of transfer at tribute registers (from two to eight) ? serial clock with programmable polarity and phase ? various programmable delays ? programmable serial frame size of 4 to 16 bits, expa ndable by software control ? continuously held chip select capability ? 3 peripheral chip selects ? dma support for tx/rx path mutually exclusiv e with register interf ace. available status information: ? tx fifo is not full ? rx fifo is not empty ? 6 interrupt conditions: ? end of queue reached ? tx fifo is not full ? transfer of current frame complete ? attempt to transmit with an empty transmit fifo ? rx fifo is not empty ? frame received while rx fifo is full ? the 6 interrupt conditions ar e mapped to 5 interrupt lines ? continuous serial communications clock when acting as interface to a serial flash devi ce the quadspi supports the following features: ? compatible with winbond tm spi serial flash s upporting single, dual and quad mode of operation. ? one chip select signal dedicated fo r usage with a serial flash device. ? dma support to read rx buffer data via amba ahb bus.
pxd10 microcontroller reference manual, rev. 1 30-6 freescale semiconductor preliminary?subject to change without notice ? 9 interrupt conditions ? the 9 interrupt conditions are mappe d to 5 different interrupt lines ? memory mapped read access to flash memo ry content in separate address range: ? supports flash devices of various sizes. ? appropriate command sequence for flash read triggered automatically by read access. ? automatic divide by 2 of the se rial flash device clock for co mmands not supporting the full frequency range. additionally the following features for power saving purposes are availa ble independent from the external device the quadspi is interfacing with: ? support for global signal stop mode ? support for global signal doze mode 30.2.3 quadspi modes of operation 30.2.3.1 spi master mode in the spi master mode the quadspi can initiate tr ansmission and reception of serial data to/from the external spi device.refer to section 30.5.2.2, master mode ? for a detailed description. in this mode the quadspi uses the system cl ock as its timing reference. 30.2.3.2 spi slave mode the slave mode allows the quadspi to communicate with an external spi bus master. refer to section 30.5.2.3, slave mode ? for a detailed description. 30.2.3.3 serial flash mode in this mode an external serial flash memory devi ce can be accessed. further de tails about this mode of operation can be found in section 30.5.3, sfm (serial flash) mode ?. in this mode the quadspi uses the auxiliary clock as its timing reference. 30.2.3.4 module disable mode the module disable mode is used for power management of the devi ce containing the quadspi module, it is controlled by signals external to the quad spi. the clock to the non-memory mapped logic in the quadspi can be stopped while in the module disable mode. see section 30.5.4.2, module disable mode ?. 30.2.3.5 stop mode the stop mode is also used for power management. when a request is made to enter stop mode, the quadspi block completes the action currently processed. then the request is acknowledged.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-7 preliminary?subject to change without notice 30.2.3.6 debug mode (spi modes only) the debug mode is used for system development and debugging, it is contro lled by additional logic outside of the module. when the mcu is stoppe d by a debugger and the qspi_mcr[frz] bit is set quadspi stops all serial transfers. 30.3 external signal description 30.3.1 overview table 30-4 lists the signals of the external signals bel onging to the quadspi module in conjunction with the different modes of operation. table 30-5 shows how the signals are connect ed on the pxd10 in spi and seri al flash modes. serial flash mode is selected by setting qspi _mcr[qmode]. using a quad flash me mory as an spi device on the fly (that is, on-the-fly change of mode from sfm to spi or vice versa) may no t be possible for all flash memories. check i/o compatibility before using this. table 30-4. signal properties signal name function & direction spi master mode spi sla ve mode serial flash mode pcs0_2 peripheral chip select 0 output slave select input peripheral chip select output pcs2_2, pcs1_2 peripheral chip select 1 - 2 output unused unused sin_2 serial data in input serial data in input serial i/o 0 bidir sout_2 serial data out output serial data out tr i s t a t e 1 1 driven only when the module is sele cted by the spi master; hiz otherwise. serial i/o 1 bidir qspi_io2 unused unused serial i/o 2 bidir qspi_io3 unused unused serial i/o 3 bidir sck_2 serial clock output serial clock input serial clock output table 30-5. connectivity of signals on this device chip signal spi mode 1 serial flash mode 2 pf[10] cs_0 (chip select) pcs (chip select out) pf[11] cs_1 (chip select) io2 (bidir) pf[12] cs_2 io3 (bidir) pf[13] sin (serial data in) io0
pxd10 microcontroller reference manual, rev. 1 30-8 freescale semiconductor preliminary?subject to change without notice 30.3.2 detailed signal description the following paragraphs describe th e function of the signals given in table 30-4 in more detail. only the modes relevant to the specific signal are mentioned according to table 30-4 . 30.3.2.1 pcs_c0 ? peripheral chip select/slave select in spi master mode, the pcs0 signal is a peripheral chip select output th at selects which slave device the current transmission is intended for. in spi slave mode, the ss signal is a slave select input signal th at allows a spi master to select the quadspi as the target for transmission. in serial flash mode this signal is the chip select for the serial flash device. 30.3.2.2 pcs[3:1] ? periphe ral chip selects 1 - 3 pcs[3:1] are peripheral chip select output signals in spi master mode. 30.3.2.3 pcs4 ? peripheral chip select 4 in spi master mode, pcs4 is a pe ripheral chip select output signal. 30.3.2.4 pcs[7:5] ? periphe ral chip selects 5 - 7 pcs[7:5] are peripheral chip select output signals in spi master mode. 30.3.2.5 si_io0 ? serial in put, quadspi data io_0 si is a serial data input signal in the spi master and spi slave mode. in the serial flash mode it is used as i/o bit 0. 30.3.2.6 so_io1 ? serial ou tput, quadspi data io_1 so is a serial data output signal in the spi master and spi slave mode. note th at the output buffer enable signal belonging to the so output is driven by the slave select input si gnal ss to allow for several slaves driving one single so line. the so output line is high impedance when in spi slave mode the quadspi module is not selected by the spi master. pf[14] sout (serial data out) io1 pf[15] sck (serial clock) clock out 1 when connecting to an external spi device, th ese definitions should be used as reference. 2 when connection to a quad serial flash, th ese definitions should be used as reference. table 30-5. connectivity of signals on this device (continued) chip signal spi mode 1 serial flash mode 2
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-9 preliminary?subject to change without notice in the serial flash mode it is used as i/o bit 1. 30.3.2.7 qspi_io2 - quadspi data io_2 in serial flash mode this signal is used as i/o bit 2. 30.3.2.8 qspi_io3 - quadspi data io_3 in serial flash mode this signal is used as i/o bit 3. 30.3.2.9 sck ? serial clock sck is a serial communication cloc k signal. in spi master mode, th e quadspi generates the sck from the system clock. in spi slave mode, sck is an input from an external bus master. in serial flash mode this signal is the serial clock output to the serial flash device and is based on the auxiliary clock. 30.4 memory map and register definition 30.4.1 ip bus register memory map table 30-6 shows the quadspi memory map. table 30-6. quadspi ip bus memory map address register name global register for spi modes and sfm mode qspi_base+0x000 module configur ation register (qspi_mcr) qspi_base+0x004 reserved registers valid in spi modes only 1 qspi_base+0x008 transfer count register (qspi_tcr) qspi_base+0x00c ? qspi_base+0x010 clock and transfer attributes registers 0 ? 1 (qspi_ctar0 ? qspi_ctar1) qspi_base+0x014 ? qspi_base+0x028 reserved qspi_base+0x02c spi status register (qspi_spisr) qspi_base+0x030 spi interrupt and dma request select and enab le register (qspi_spirser) fifo registers qspi_base+0x034 push tx fifo register (qspi_pushr)
pxd10 microcontroller reference manual, rev. 1 30-10 freescale semiconductor preliminary?subject to change without notice 30.4.2 amba bus register memory map qspi_amba_base defines the address to be used as start address of th e serial flash device. qspi_base+0x038 pop rx fifo register (qspi_popr) qspi_base+0x03c ? qspi_base+0x074 transmit fifo registers 0 ? 14 (qspi_txfr0 ? qspi_txfr14) qspi_base+0x078 reserved qspi_base+0x07c ? qspi_base+0x0b4 rx fifo registers 0 ? 14 (qspi_rxfr0 ? qspi_rxfr14) qspi_base+0x0b8 ? qspi_base+0x0fc reserved registers valid in sfm mode only 2 qspi_base+0x100 serial flash a ddress register (qspi_sfar) qspi_base+0x104 instruction code register (qspi_icr) qspi_base+0x108 sampling register (qspi_smpr) qspi_base+0x10c rx buffer st atus register (qspi_rbsr) qspi_base+0x110 ? qspi_base+0x148 rx buffer data register s 0?14 (qspi_rbdr0?qspi_rbdr14) qspi_base+0x14c reserved qspi_base+0x150 tx buffer status register (qspi_tbsr) qspi_base+0x154 tx buffer da ta register (qspi_tbdr) qspi_base+0x158 amba control register (qspi_acr) qspi_base+0x15c serial flash mode status regist er (qspi_sfmsr) qspi_base+0x160 serial flash mode flag register (qspi_sfmfr) qspi_base+0x164 sfm interrupt and dma request select and enab le register (qspi_sfmrser) qspi_base+0x168 ? qspi_base+0x1fc reserved 1 these registers must not be written if the quadspi module is in sfm mode 2 these registers must not be written if the quadspi module is in spi master or spi slave mode table 30-6. quadspi ip bus memory map (continued) address register name
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-11 preliminary?subject to change without notice 30.4.3 ip bus register descriptions 30.4.3.1 register write access this section describes the write access restri ction terms that apply to all registers. 30.4.3.1.1 register write access restriction for each register bit and register fi eld, the write access conditions are sp ecified in the detailed register description. a description of the wr ite access conditions is given in table 30-8 . if, for a specific register bit or field, none of the given write access conditions is fulfilled, any writ e attempt to this register bit or field is ignored without any not ification. the values of the bi ts or fields are not changed. the condition term [a or b] indicates that the register or field can be written to if at least one of the conditions is fulfilled. 30.4.3.1.2 register write access requirements all registers can be accessed with 8-bit, 16-bit and 32- bit wide operations. for some of the registers, at least a 16/32-bit wide write access is required to ensure correct operation. this write access requirement is stated in the detailed register description for each register affected 30.4.3.2 module configurat ion register (qspi_mcr) the qspi_mcr contains bits whic h configure various attributes as sociated with quadspi operation. table 30-7. quadspi amba bus memory map address register name memory mapped serial flash data (qspi_sfd) qspi_amba_base + 0x000_0000 serial flash data [0x000_0000] qspi_amba_base + 0x000_0004 serial flash data [0x000_0004] ... ... qspi_amba_base + 0x7ff_fff4 seria l flash data [0x7ff_fff4] qspi_amba_base + 0x7ff_fff8 seria l flash data [0x7ff_fff8] ahb rx data buffer (qspi_ardb) qspi_amba_base + 0x7ff_fffc ahb rx data buffer (qspi_ardb) table 30-8. register write access restrictions condition description anytime no write access restriction. disabled mode write access only if the module is in module disable mode . enabled mode write access only if the module is in spi master mode or spi slave mode or serial flash mode . spi mode write access only if the module is in spi master mode or spi slave mode . serial flash mode write access only if the module is in serial flash mode .
pxd10 microcontroller reference manual, rev. 1 30-12 freescale semiconductor preliminary?subject to change without notice note configuration data depending from th e value of the qmode bit must be left at their reset values when they are not applicable. address: qspi_base + 0x000 write: qmode: disabled mode dis_txf, dis_rxf: enabled mode all other: anytime 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r mstr cont_scke 00 frz mtf e pcsse rooe pcsis7 pcsis6 pcsis5 pcsis4 pcsis3 pcsis2 pcsis1 pcsis0 w reset0 00000 0 000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r doze mdis dis_txf dis_rxf 00 smpl_pt qmode vmid 00 halt w clr_txf clr_rxf reset0 10000 0 000000001 figure 30-2. module configuration register (qspi_mcr) table 30-9. qspi_mcr field descriptions field description mstr master/slave mode select. only applicable if qmode is cleared . the mstr bit configures the quadspi for either spi master mode or spi slave mode. 0 quadspi is in spi slave mode 1 quadspi is in spi master mode cont_sck e continuous sck enable. only applicable if qmode is cleared . the cont_scke bit enables the serial communication clock (sck) to run continuously. see section 30.5.2.9, continuous serial communications clock ,? for details. 0 continuous sck disabled 1 continuous sck enabled frz freeze. only applicable if qmode is cleared . the frz bit enables the quadspi transfers to be stopped on the next frame boundary when the mcu is stopped by a debugger. 0 do not halt serial transfers 1 halt serial transfers mtfe modified timing format enable. only applicable if qmode is cleared . the mtfe bit enables a modified transfer format to be used. see section 30.5.2.8.4, modified spi transfer format (mtfe = 1, cpha = 1) ,? for more information. 0 modified spi transfer format disabled 1 modified spi transfer format enabled
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-13 preliminary?subject to change without notice pcsse peripheral chip se lect strobe enable. only applicable if qmode is cleared . the pcsse bit enables the pcs[5]/pcss to operate as an pcs strobe output signal. see section 30.5.2.7.5, peripheral chip select strobe enable (pcss) ,? for more information. 0 pcs5/pcss is used as the peripheral chip select[5] signal 1 pcs5/pcss is used as an active-low pcs strobe signal rooe rx fifo overflow overwrite enable. only applicable if qmode is cleared. the rooe bit enables an rx fifo overflow condition to either ignore the incoming serial data or to overwrite existing data. if the rx fifo is full and new data is received, the data from the transfer that generated the overflow is either ignored or shifted in to the shift register . if the rooe bit is asserted, the incoming data is shifted in to the shift register. if the rooe bit is negated, the incoming data is ignored. see section 30.5.2.10.6, rx fifo overflow interrupt request ,? for more information. 0 incoming data is ignored 1 incoming data is shifted in to the shift register pcsis x peripheral chip select inactive state. only applicable if qmode is cleared. the pcsis bit determines the inactive state of the pcs x signal. 0 the inactive state of pcs x is low 1 the inactive state of pcs x is high doze doze enable. the doze bit provides support for externally controlled doze mode power-saving mechanism. see section 30.5.4, power saving features ,? for details. 0 a doze request will be ignored by the quadspi module 1 a doze request will be processed by the quadspi module mdis module disable. the mdis bit allows the clock to be stopped to the non-memory mapped logic in the quadspi effectively putting the quadspi in a software controlled power-saving state. see section 30.5.4, power saving features ? and section 30.5.2.1, start an d stop of spi transfers ? for more information. 0 enable quadspi clocks. 1 allow external logic to disable quadspi clocks. dis_txf disable tx fifo. only applicable if qmode is cleared. the dis_txf bit provides a mechanism to disable the tx fifo. when the tx fifo is disa bled, the transmit part of the quadspi operates as a simplified double-buffered spi. see section 30.5.2.4, fifo disable operation ,? for details. 0 tx fifo is enabled 1 tx fifo is disabled dis_rxf disable rx fifo. only applicable if qmode is cleared. the dis_rxf bit provides a mechanism to disable the rx fifo. when the rx fifo is disabl ed, the receive part of the quadspi operates as a simplified double-buffered spi. see section 30.5.2.4, fifo disable operation ,? for details. 0 rx fifo is enabled 1 rx fifo is disabled clr_txf clear tx fifo/buffer. dep ending from the qmode bit clr_txf is used to invalidate the tx fifo or the tx buffer content. 0 no action 1 (qmode bit cleared) : read and write pointers of rx fifo are reset to 0. qspi_spisr[txctr] and qspi_spisr[txnxtpt r] are reset to 0. 1 (qmode bit set ): read and write pointers of the rx bu ffer are reset to 0. qspi_tbsr[trctr] is reset to 0. table 30-9. qspi_mcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 30-14 freescale semiconductor preliminary?subject to change without notice 30.4.3.3 transfer count register (qspi_tcr) the qspi_tcr contains a counter th at indicates the number of spi tran sfers made. the transfer counter is intended to assist in queue management. clr_rxf clear rx fifo. depending from the qmode bit cl r_rxf is used to invalidate the rx fifo or the rx buffer. 0 no action 1 (qmode bit cleared) : read and write pointers of the rx fifo are reset to 0. qspi_spisr[rxctr] and qspi_spisr[popnxtptr] are reset to 0. 1 (qmode bit set) : read and write pointers of the rx buffer are reset to 0. qspi_rbsr[rdbfl] is reset to 0. smpl_pt smpl_pt ? only applicable if qmode is cleared . sample point. smpl_pt allows the host software to select when the quadspi master samp les si in modified transfer format. the table below lists the various delayed sample points. 00 0 system clock cycles 01 1 system clock cycle 10 2 system clock cycles 11 reserved qmode qmode ? quadspi mode: when this bit is cleared the quadspi block is in spi master or spi slave mode. when this bit is set the quadspi block is in serial flash mode. 0 module is in spi master or spi slave mode 1 module is in sfm mode vmid vmid ? vendor model id. only applicable if qmode is set. 0000 reserved 0001 winbond othersreserved halt halt. only applicable if qmode is cleared. the halt bit provides a mechanism by software to start and stop quadspi transfers. see section 30.5.2.1, start and stop of spi transfers ? for details about the operation of this bit. 0 start transfers 1 stop transfers address: qspi_base + 0x008 0123456789101112131415 r spi_tcnt w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 30-3. transfer count register (qspi_tcr) table 30-9. qspi_mcr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-15 preliminary?subject to change without notice 30.4.3.4 clock and transfer attributes registers 0 ? 1 (qspi_ctar0 ? qspi_ctar1) the qspi_ctar registers are used to define different transfer attribute configur ations for the spi master mode and the spi slave mode. spi tr ansfers select which one of the q spi_ctars to get their transfer attributes from. in the cu rrent implementation there are 2 different qspi_ctars selectable. the user must not write to the qspi_ctar registers while the quadspi is in the running state. in master mode, the qspi_ctar0 - qspi_ctar7 regist ers define combinations of transfer attributes such as frame size, clock phase and polarity, data bit ordering, baud rate, and various delays. in slave mode, a subset of the bitfields in the qspi_ctar0 and qspi_ctar1 re gisters are used to set the slave transfer attributes. see the individua l bit descriptions for details on wh ich bits are used in slave modes. when the quadspi is configured as a spi master, the ctas field in the command po rtion of the tx fifo entry selects which of the qspi_cta r register is used. when the quad spi is configured as a spi bus slave, the qspi_ctar0 register is used. table 30-10. qspi_tcr field descriptions field description spi_tcnt spi transfer counter. spi_tcnt is used to k eep track of the number of spi transfers made. the spi_tcnt field counts the number of spi transfe rs the quadspi makes. the spi_tcnt field is incremented every time the last bit of a spi frame is transmitted. a value written to spi_tcnt presets the counter to that value. spi_tcnt is reset to zero at the beginning of the frame when the ctcnt field is set in the executing spi command. the tr ansfer counter wraps around, i.e., incrementing the counter past 0xffff resets the counter to zero. address: qspi_base + 0x00c (qspi_ctar0) qspi_base + 0x010 (qspi_ctar1) write: anytime 0 1 2 3 4 5 6 7 8 9 10 1112131415 r dbr fmsz cpo l cpha lsbfe pcssck pasc pdt pbr w reset011110 0 0 0 0 0 00000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cssck asc dt br w reset000000 0 0 0 0 0 00000 figure 30-4. clock and transfer attributes registers 0 ? 1 (qspi_ctar0 ? qspi_ctar1)
pxd10 microcontroller reference manual, rev. 1 30-16 freescale semiconductor preliminary?subject to change without notice table 30-11. qspi_ctar n field descriptions field descriptions dbr double baud rate. the dbr bit doubles the effective baud rate of the serial communications clock (sck). this field is only used in master mode. it effectively halves the baud rate division ratio supporting faster frequencies and odd division rati os for the serial communications clock (sck). when the dbr bit is set, the duty cycle of the se rial communications clock (sck) depends on the value in the baud rate prescaler and the clock phase bit as listed in table 30-12 . see the br[0:3] field description for details on how to compute the baud rate. if the overall baud rate is divide by two or divide by three of the system clock then neither the continuous sck enable or the modified timing format enable bits should be set. 0 the baud rate is computed norm ally with a 50/50 duty cycle 1 the baud rate is doubled with the duty cycle depending on the baud rate prescaler fmsz frame size. the fmsz field selects the number of bits transferred per frame. the fmsz field is used in master mode and slave mode. table 30-13 lists the frame size encodings. cpol clock polarity. the cpol bit selects the inactive state of the serial communications clock (sck). this bit is used in both master and slave mode. for successful communication between serial devices, the devices must have identical clock polarities. when the continuous selection format is selected, switching between clock polarities without stopping the quadspi can cause errors in the transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge. 0 the inactive state value of sck is low 1 the inactive state value of sck is high cpha clock phase. the cpha bit selects which edge of sck causes data to change and which edge causes data to be captured. this bit is used in both master and slave mode. for successful communication between serial devices, the devices must have identical clock phase settings. continuous sck is only supported for cpha=1. 0 data is captured on the leading edge of sck and changed on the following edge 1 data is changed on the leading edge of sck and captured on the following edge lsbfe lsb first. the lsbfe bit selects if the lsb or msb of the frame is transferred first. this bit is only used in master mode. 0 data is transferred msb first 1 data is transferred lsb first pcssck pcs to sck delay prescaler. the pcssck field selects the prescaler value for the delay between assertion of pcs and the first edge of the sc k. this field is only used in master mode. table 30-14 lists the prescaler values and the associated bit settings. see the cssck[0:3] field description for details on how to compute the pcs to sck delay. 00 prescaler value 1 01 prescaler value 3 10 prescaler value 5 11 prescaler value 7 pasc after sck delay prescaler. the pasc field selects the prescaler value for the delay between the last edge of sck and the negation of pcs. th is field is only used in master mode. table 30-15 lists the prescaler values. see the asc[0:3] field description for details on how to compute the after sck delay. 00 prescaler value 1 01 prescaler value 3 10 prescaler value 5 11 prescaler value 7
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-17 preliminary?subject to change without notice pdt delay after transfer prescaler. the pdt field se lects the prescaler value for the delay between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. the pdt field is only used in master mode. table 30-16 lists the prescaler values. see the dt[0:3] field description for details on how to compute the delay after transfer. 00 delay after transfer prescaler value 1 01 delay after transfer prescaler value 3 10 delay after transfer prescaler value 5 11 delay after transfer prescaler value 7 pbr baud rate prescaler. the pbr field selects the prescaler value for the baud rate. this field is only used in master mode. the baud rate is the fr equency of the serial communications clock (sck). the system clock is divided by the prescaler value before the baud rate selection takes place. the baud rate prescaler values are listed in table 30-17 . see the br[0:3] field description for details on how to compute the baud rate. 00 baud rate prescaler value 1 01 baud rate prescaler value 3 10 baud rate prescaler value 5 11 baud rate prescaler value 7 cssck pcs to sck delay scaler. the cssck field sele cts the scaler value for the pcs to sck delay. this field is only used in master mode. the pcs to sck delay is the delay between the assertion of pcs and the first edge of the sck. table 30-14 list the scaler values.the pcs to sck delay is a multiple of the system clock period and it is co mputed according to the following equation: eqn. 30-1 see section 30.5.2.7.2, pc s to sck delay (tcsc) ,? for more details. asc after sck delay scaler. the asc field selects the scaler value for the after sck delay. this field is only used in master mode. the after sck delay is the delay between the last edge of sck and the negation of pcs. table 30-15 list the scaler values.the after sck delay is a multiple of the system clock period, and it is computed according to the following equation: eqn. 30-2 see section 30.5.2.7.3, af ter sck delay (tasc) ,? for more details. dt delay after transfer scaler. the dt field selects the delay after transfer scaler. this field is only used in master mode. the delay after transfer is the time between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. table 30-16 lists the scaler values. in the continuous serial communications clock operation the dt value is fixed to one tsck. eqn. 30-3 see section 30.5.2.7.4, delay after transfer (tdt) ,? for more details. br baud rate scaler. the br field selects the scaler value for the baud rate. this field is only used in master mode. the pre-scaled system clock is divi ded by the baud rate scaler to generate the frequency of the sck. table 30-17 lists the baud rate scaler values. the baud rate is computed according to the following equation: eqn. 30-4 see section 30.5.2.7.1, baud rate generator ,? for more details. table 30-11. qspi_ctar n field descriptions (continued) field descriptions t csc 1 f sys ---------- - pcssck cssck ? ? = t asc 1 f sys ----------- pasc ? asc ? = t dt 1 f sys ----------- pdt ? dt ? = sck baud rate f sys pbr ----------- - 1dbr + br --------------------- - ? =
pxd10 microcontroller reference manual, rev. 1 30-18 freescale semiconductor preliminary?subject to change without notice table 30-12. sck duty cycle dbr cpha pbr sck duty cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43 table 30-13. transfer frame size fmsz framesize fmsz framesize 0000 reserved 1000 9 0001 reserved 1001 10 0010 reserved 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16 table 30-14. pcs to sck delay scaler cssck pcs to sck delay scaler value c ssck pcs to sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-19 preliminary?subject to change without notice table 30-15. after sck delay scaler asc after sck delay scaler value asc after sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 30-16. after transfer scaler dt delay after transfer scaler value dt delay after transfer scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 30-17. baud rate scaler br baud rate scaler value br baud rate scaler value 0000 2 1000 256 0001 4 1001 512 0010 6 1010 1024 0011 8 1011 2048 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 32768
pxd10 microcontroller reference manual, rev. 1 30-20 freescale semiconductor preliminary?subject to change without notice 30.4.3.5 spi status register (qspi_spisr) the qspi_spisr contains stat us and flag bits. the bits reflect the status of the quadspi and indicate the occurrence of events that can generate interrupt or dma requests. software can clear flag bits in the qspi_spisr by writing a ?1? to it. writ ing a ?0? to a flag bit has no effect. this register may not be writable in mdis mode due to the us e of power saving mechanisms. address: qspi_base + 0x02c write: enabled mode 0123456789101112131415 r 1 1 when in sfm mode all 0s are read. tcf txr xs 0 eoq f tfu f 0tfff00000 rfo f 0 rfd f 0 ww1c w1c w1c w1c w1c w1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 1 txctr txnxtptr rxctr popnxtptr w reset0000000000000000 figure 30-5. spi status register (qspi_spisr) table 30-18. qspi_spisr field descriptions field description tcf transfer complete flag. the tcf bit indicates that all bits in a frame have been shifted out. the tcf bit is set at the end of the frame transfer. t he tcf bit remains set until cleared by software. 0 transfer not complete 1 transfer complete txrxs tx & rx status. the txrxs bit reflects the status of the quadspi. see section 30.5.2.1, start and stop of spi transfers ? for information on how what causes this bit to be negated or asserted. 0 tx and rx operations are disabled (quadspi is in stopped state) 1 tx and rx operations are enabled (quadspi is in running state) eoqf end of queue flag. the eoqf bit indicates that tr ansmission in progress is the last entry in a queue. the eoqf bit is set when tx fi fo entry has the eoq bit set in the command halfword and the end of the transfer is reached. the eoqf bit remains set until cleared by software. when the eoqf bit is set, the txrxs bit is automatically cleared. 0 eoq is not set in the executing command 1 eoq bit is set in the executing spi command tfuf tx fifo underrun flag. the tfuf bit indicates that an underrun condition in the tx fifo has occurred. the transmit underrun condition is detect ed only in spi slave mode. the tfuf bit is set when the tx fifo of a quadspi operating in spi slav e mode is empty, and a transfer is initiated by an external spi master. the tfuf bit remains set until cleared by software. 0 tx fifo underrun has not occurred 1 tx fifo underrun has occurred
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-21 preliminary?subject to change without notice 30.4.3.6 spi interrupt and dma requ est select and enable register (qspi_spirser) the qspi_spirser serves two purposes. it enables flag bits in the qspi_spisr to generate dma requests or interrupt request s. the qspi_spirser also selects the type of request to be gene rated. see the individual bit descriptions for inform ation on the types of requests the bits support. the user must not write to the qspi_spirser while the quadspi is in the running state. tfff tx fifo fill flag. the tfff bit provides a method for the quadspi to request more entries to be added to the tx fifo. the tfff bit is set while the tx fifo is not full. the tfff bit can be cleared by host software or an acknowledgement from the dma controller when the tx fifo is full. 0 tx fifo is full 1 tx fifo is not full rfof rx fifo overflow flag. the rfof bit indicates that an overflow condition in the rx fifo has occurred. the bit is set when the rx fifo and shift regi ster are full and a transfer is initiated. the bit remains set until cleared by software. 0 rx fifo overflow has not occurred 1 rx fifo overflow has occurred rfdf rx fifo drain flag. the rfdf bit provides a method for the quadspi to request that entries be removed from the rx fifo. the bit is set while the rx fifo is not empty. the rfdf bit can be cleared by host software or an acknowledgement from the dma controller when the rx fifo is empty. 0 rx fifo is empty 1 rx fifo is not empty txctr tx fifo counter. the txctr field indicates the number of valid entries in the tx fifo. the txctr is incremented every time the qspi_pushr is writ ten. the txctr is decremented every time a spi command is executed and the spi data is transferred to the shift register. txnxtptr transmit next pointer. the txnxtptr field in dicates which tx fifo entry will be transmitted during the next transfer. the txnxtptr field is updated every time spi data is transferred from the tx fifo to the shift register. see section 30.5.2.10.4, transmit fi fo underrun interrupt request ,? fo r more details. rxctr rx fifo counter. the rxctr field indicates the number of entries in the rx fifo. the rxctr is decremented every time the qspi_popr is read. the rxctr is incremented every time data is transferred from the shift register to the rx fifo. popnxtpt r pop next pointer. the popnxtptr field contains a po inter to the rx fifo entry that will be returned when the qspi_popr is read. t he popnxtptr is updated when the qspi_popr is read. see section 30.5.2.6, receive first in first out (rx fifo) buffering mechanism ,? for more details. table 30-18. qspi_spisr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 30-22 freescale semiconductor preliminary?subject to change without notice address: qspi_base + 0x030 write: anytime 0123456789101112131415 r tcf_ie 00 eoqf_ie tfuf_ie 0 tfff_re tfff _dirs 0000 rfof_ie 0 rfdf_re rfdf_dirs w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 30-6. spi interrupt and dma request se lect and enable register (qspi_spirser) table 30-19. qspi_spir ser field descriptions field description tcf_ie transmission complete irq enable. the tcf_ie bit enables the tcf flag in the qspi_spisr to generate an interrupt request. 0 tcf interrupt requests are disabled 1 tcf interrupt requests are enabled eoqf_re quadspi finished irq enable . the eoqf_ie bit enables the eoqf flag in the qspi_spisr to generate an interrupt request. 0 eoqf interrupt requests are disabled 1 eoqf interrupt requests are enabled tfuf_re tx fifo underrun irq enable. the tfuf_ie bit enables the tfuf flag in the qspi_spisr to generate an interrupt request. 0 tfuf interrupt requests are disabled 1 tfuf interrupt requests are enabled tfff_re tx fifo fill request enable . the tfff_re bit enables the tfff flag in the qspi_spisr to generate a request. the tfff_dirs bit selects between generating an interrupt request or a dma requests. 0 tfff interrupt requests or dma requests are disabled 1 tfff interrupt requests or dma requests are enabled tfff_dirs tx fifo fill dma or interrupt request sele ct. the tfff_dirs bit sele cts between generating a dma request or an interrupt request. when the tfff flag bit in the qspi_spisr is set, and the tfff_re bit in the qspi_ spirser register is set, this bit selects between generating an interrupt request or a dma request. 0 interrupt request will be generated 1 dma request will be generated rfof_ie rx fifo overflow irq enable. the rfof_ie bit enables the rfof flag in the qspi_spisr to generate an interrupt requests. 0 rfof interrupt requests are disabled 1 rfof interrupt requests are enabled
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-23 preliminary?subject to change without notice 30.4.3.7 push tx fifo register (qspi_pushr) the qspi_pushr provides a means to write to the tx fifo and to configure the parameters for the spi transmission. data written to the txdata field is transferred to the tx fifo. see section 30.5.2.5, transmit first in first out (tx fifo) buffering mechanism ,? for more information and table 30-45 for the byte ordering. rfdf_re rx fifo drain request enab le. the rfdf_re bit enables the rfdf flag in the qspi_spisr to generate a request. the rfdf_dirs bit selects between generating an interrupt request or a dma request. 0 rfdf interrupt requests or dma requests are disabled 1 rfdf interrupt requests or dma requests are enabled rfdf_dirs rx fifo drain dma or interrupt request select. the rfdf_dirs bit selects between generating a dma request or an interrupt request. when the rf df flag bit in the qspi _spisr is set, and the rfdf_re bit in the qspi_s pirser register is set, the rfdf _dirs bit selects between generating an interrupt request or a dma request. 0 interrupt request will be generated 1 dma request will be generated address: qspi_base + 0x034 32-bit write access required write: spi mode 0123456789101112131415 r con t ctas eoq ctc nt 00 pcs 7 pcs 6 pcs 5 pcs 4 pcs 3 pcs 2 pcs 1 pcs 0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txdata w reset0000000000000000 figure 30-7. push tx fifo register (qspi_pushr) table 30-19. qspi_spirser field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 30-24 freescale semiconductor preliminary?subject to change without notice 30.4.3.8 pop rx fifo register (qspi_popr) the qspi_popr provides a means to read the rx fifo. see section 30.5.2.6, receive first in first out (rx fifo) buffering mechanism ,? for a description of the rx fifo operations. eight or sixteen bit read accesses to the qspi_popr will read from the rx fifo and update the counter and pointer. refer to table 30-45 for the byte ordering scheme. table 30-20. qspi_pushr field descriptions field descriptions cont continuous peripheral chip select enable. the cont bit selects a continuous selection format. the bit is used in spi master mo de. the bit enables the selected pcs signals to remain asserted between transfers. see section 30.5.2.8.5, cont inuous selection format ,? for more information. 0 return peripheral chip select signals to their inactive state between transfers 1 keep peripheral chip select signals asserted between transfers ctas clock and transfer attributes select. the ctas fi eld selects which of the qspi_ctar register is used to set the clock and transfer attributes for the associated spi frame. the field is only used in spi master mode. in spi slave mode qspi_ctar0 is used. the table below shows how the ctas values map to the qspi_ctar registers. all values not given below are reserved. 000 qspi_ctar0 001 qspi_ctar1 eoq end of queue. the eoq bit provides a means for host software to signal to the quadspi that the current spi transfer is the last in a queue. at the end of the transfer the eo qf bit in the qspi_spisr is set. 0 the spi data is not the last data to transfer 1 the spi data is the last data to transfer ctcnt clear spi_tcnt. the ctcnt provid es a means for host software to clear the spi transfer counter. the ctcnt bit clears the spi_tcnt field in the q spi_tcr register. the spi _tcnt field is cleared before transmission of the current spi frame begins. 0 do not clear spi_tcnt field in the qspi_tcr 1 clear spi_tcnt field in the qspi_tcr pcs x peripheral chip select 0?7. the pcs bits select which pcs signals will be asserted for the transfer. 0 negate the pcsx signal 1 assert the pcsx signal txdata tx data. writing the txdata field pushed the spi da ta to be transferred onto the tx fifo. reading the txdata field provides the value which wa s written most recently into the txdata field. after the tx fifo has been clea red the result is undefined.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-25 preliminary?subject to change without notice 30.4.3.9 transmit fifo registers 0 ? 14 (qspi_txfr0 ? qspi_txfr14) the qspi_txfr0 - qspi_txfr14 regi sters provide visibility into th e tx fifo for debugging purposes. each register is an entry in the tx fifo. th e registers are read-only and cannot be modified. address: qspi_base + 0x038 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r00 00000000000000 w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxdata w reset00 00000000000000 figure 30-8. pop rx fifo register (qspi_popr) table 30-21. qspi_popr field descriptions field description rxdata rx data. the rxdata field contains the spi data from the rx fifo entry pointed to by the pop next data pointer. address: qspi_base+0x03c (qspi_txfr0) ... qspi_base+0x074 (qspi_txfr14) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rtxcmd w reset00 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtxdata w reset00 00000000000000 figure 30-9. transmit fifo registers 0 ? 14 (qspi_txfr0 ? qspi_txfr14)
pxd10 microcontroller reference manual, rev. 1 30-26 freescale semiconductor preliminary?subject to change without notice 30.4.3.10 rx fifo registers 0 ? 14 (qspi_rxfr0 ? qspi_rxfr14) the qspi_rxfr0 - qspi_rxf r14 registers provide visibility into the rx fifo for debugging purposes. each register is an entry in the rx fifo. th e qspi_rxfr registers are read-only. reading the qspi_rxfrx registers does not alter the state of th e rx fifo. the rx fifo implemented has a depth of 15 entries, so the highest address us able belongs to qs pi_rxfr14. refer to table 30-45 for the byte ordering scheme. 30.4.3.11 serial flash addr ess register (qspi_sfar) the serial flash address register c ontains the address for the next ip command. the number of bits used from this register depend on the inst ruction code of the sfm command. see section 30.5.3, sfm (serial flash) mode ? for details. table 30-22. qspi_txfr n field descriptions field description txcmd tx command. the txcmd field contains the command that sets the transfer attributes for the spi data. see section 30.4.3.7, push tx fifo register (qspi_pushr) ,? for details on the command field. txdata tx data. the txdata field cont ains the spi data to be shifted out. address: qspi_base + 0x07c (qspi_rxfr0) ... qspi_base + 0x0b4 (qspi_rxfr14) 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rxdata w reset0000000000000000 figure 30-10. rx fifo registers 0 ? 14 (qspi_rxfr0 ? qspi_rxfr14) table 30-23. qspi_rxfr n field descriptions field description rxdata rx data. the rxdata field contains the received spi data.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-27 preliminary?subject to change without notice 30.4.3.12 instruction code register (qspi_icr) the instruction code register consis ts of the generic instruction code (ic) and an additional parameter section (ico). this co ntains additional options to parameterize the command as shown in table 30-53 . if the ic field is written successfully - while the module is in serial flash mode and not busy - a new command to the external serial flash device is started with that inst ruction code if this code is supported by the module (see section 30.7.1, supported instruction codes in winbond devices ). the qspi_icr register is wr iteable only in sfm mode. refer to section 30.5.3.1, issuing sfm commands , for further details about the triggering of ip commands. address: qspi_base + 0x100 w rite: qspi_sfmsr[ip_acc] = 0 0123456789101112131415 r sfadr w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sfadr w reset0000000000000000 figure 30-11. serial flash address register (qspi_sfar) table 30-24. qspi_sfar field descriptions field description sfadr serial flash address, register content is used as address for all following ip commands.
pxd10 microcontroller reference manual, rev. 1 30-28 freescale semiconductor preliminary?subject to change without notice 30.4.3.13 sampling re gister (qspi_smpr) the sampling register allows configur ation of the scheme how the incomi ng data from an external serial flash device are sampled in the quadspi module. its fields are relevant in sfm mode only. address: qspi_base + 0x104 write: ico: qspi_sfmsr[ip_ acc] = 0 and qspi_mcr[qmode] = 1 ic: qspi_sfmsr[ip_acc] = 0 and qspi_sfmsr[ahb_acc] = 0 and qspi_mcr[qmode] = 1 0123456789101112131415 r ico w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ico ic w reset0000000000000000 figure 30-12. instruction code register (qspi_icr) table 30-25. qspi_icr field descriptions field description ico instruction code options, additional parameters for the ic instruction specif ied in the ic field. meaning of the individual bits vary for each instruction code and vendor, detailed description in table 30-53 . only applicable in sfm mode ic write access: instruction code of the sfm command to be executed next. read access: instruction code of the la st sfm command succe ssfully written. upon writing this byte a new command sequence is star ted to the external serial flash device, if the module is in serial flash mode. only applicable in sfm mode
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-29 preliminary?subject to change without notice 30.4.3.14 rx buffer status register (qspi_rbsr) this register contains information related to the receive data buffer. address: qspi_base + 0x108 write: disabled mode 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000 fsdly fsphs 00 hsdly hsphs hsena w reset0000000000000000 figure 30-13. sampling register (qspi_smpr) table 30-26. qspi_smpr field descriptions field description fsdly full speed delay selection. select the delay with respect to the reference edge for the sample point valid for full speed commands: 0: one clock cycle delay 1: two clock cycles delay fsphs full speed phase selection. select the edge of the sampling clock valid for full speed commands: 0: select sampling at non-inverted clock 1: select sampling at inverted clock hsdly half speed delay selection. only relevant when hsena bit is set . select the dela y with respect to the reference edge for the sample point valid for half speed commands: 0: one clock cycle delay 1: two clock cycles delay hsphs half speed phase selection. only relevant when hsena bit is set . select the edge of the sampling clock valid for half speed commands: 0: select sampling at non-inverted clock 1: select sampling at inverted clock hsena half speed serial flash clock enable: this bit enables the divide by 2 of the clock to the external serial flash device for specific commands. refer to section 30.7.2, serial flash clock frequency limitations ? for details. 0: disable divide by 2 of serial flash clock for half speed commands 1: enable divide by 2 of serial flash clock for half speed commands
pxd10 microcontroller reference manual, rev. 1 30-30 freescale semiconductor preliminary?subject to change without notice 30.4.3.15 rx buffer data registers 0?14 (qspi_rbdr0?qspi_rbdr14) the qspi_rbdr registers provide access to the individual entries in the rx buffer. refer to table 30-45 for the byte ordering scheme. address: qspi_base + 0x10c 0123456789101112131415 r rdctr w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rdbfl 00000000 w reset0000000000000000 figure 30-14. rx buffer status register (qspi_rbsr) table 30-27. qspi_rbsr field descriptions field description rdctr read counter, indicates how many bytes have been removed from the rx buffer by host accesses. it is incremented by 4 on each successful write on the qspi_sfmfr[rbdf] bit. for further details please refer to section 30.4.4.3, ahb rx data buffer (qspi_ardb) ? and section 30.5.3.3.2, host read of the quadspi module internal buffers ?. rbbfl rx buffer fill level, indicates how many bytes are still available for read in the rx buffer.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-31 preliminary?subject to change without notice 30.4.3.16 tx buffer status register (qspi_tbsr) this register contains information re lated to the transmit data buffer. address: qspi_base + 0x110 (qspi_rbdr0) ... qspi_base + 0x148 (qspi_rbdr14) 0123456789101112131415 r rxdata[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rxdata[15:0] w reset0000000000000000 figure 30-15. rx buffer data regi sters 0?14 (qspi_rbdr0?qspi_rbdr14) table 30-28. qspi_rbdr field descriptions field description rxdata rx data. the rxdata field contains the received data. address: qspi_base + 0x150 0123456789101112131415 r0000000 trctr w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r trbfl 00000000 w reset0000000000000000 figure 30-16. tx buffer status register (qspi_tbsr)
pxd10 microcontroller reference manual, rev. 1 30-32 freescale semiconductor preliminary?subject to change without notice 30.4.3.17 tx buffer data register (qspi_tbdr) the qspi_tbdr register provides access to the circular tx buffer. this buffer provides the data written into it as write data for the page programming commands to the serial flash device. refer to table 30-45 for the byte ordering scheme. 30.4.3.18 amba control register (qspi_acr) the qspi_acr register defines th e command that is used for following ahb commands. the read commands allowed are given in section 30.7.1, supported instruction codes in winbond devices . the execution of the command itself is triggered by an ahb read to the a ddress range assigned to the memory mapped serial flash data. for further details refer to section 30.6.7, command arbitration - sfm mode only . table 30-29. qspi_tbsr field descriptions field description trctr transmit counter. this field indicates how many bytes have been written into the tx buffer by host accesses. it is reset to 0 when a 1 is written in to the qspi_mcr[clr_txf] bit. it is incremented on each write access to the qspi_tbdr register by the number of bytes pushed onto the tx buffer. when it is not cleared the trctr field wraps around to 0. refer to section 30.4.3.17, tx buffer data register (qspi_tbdr) ? for details. trbfl tx buffer fill level. the trbfl field contains t he number of bytes available in the tx buffer for the quadspi module to transmit to the serial flash device. address: qspi_base + 0x154 write: qspi_mcr[qmode] = 1 and qspi_sfmsr[txfull] = 0 32-bit write access required 0123456789101112131415 r0000000000000000 w txdata[31:16] reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w txdata[15:0] reset0000000000000000 figure 30-17. tx buffer (qspi_tbdr) table 30-30. qspi_tbdr field descriptions field description txdata tx data. on write access the data are written into the next available entry of the tx buffer and the qpsi_tbsr[trbfl] field is updated accordingly.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-33 preliminary?subject to change without notice 30.4.3.19 serial flash mode st atus register (qspi_sfmsr) the qspi_sfmsr register provides all available status information about sfm command execution and arbitration, the rx buffer and tx buffer and the ahb buffer. address: qspi_base + 0x158 write: anytime 0123456789101112131415 r00000000 armb w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 arsz 00 aric w reset0000010000000011 figure 30-18. amba control register (qspi_acr) table 30-31. qspi_acr field descriptions field description armb amba read mode byte. instruction code option for aric for continuos mode ( ta b l e 3 0 - 5 3 , m7-m0). arsz amba read size. defines size of read burst to the external serial flash device for any starting address not found in the fifo by a new amba ahb read acce ss. the number of bytes read from the external serial flash device is the value in arsz * 4. legal values for arsz are in the range from 1 to 16, resulting in 4 up to 64 bytes read from the external serial flash. aric amba read instruction code. selects the read command to be used for any read access to the external serial flash device. the reset value of the aric field is the read_data command with a size of 4 bytes.
pxd10 microcontroller reference manual, rev. 1 30-34 freescale semiconductor preliminary?subject to change without notice address: qspi_base + 0x15c 0123456789101112131415 r 0000 txfull 00 txne 0000 rxfull 00 rxne w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 ahbfull 00 ahbne 0000 contmode ahb_acc ip_acc busy w reset0000000000000000 figure 30-19. serial flash mode status register (qspi_sfmsr) table 30-32. qspi_sfmsr field descriptions field description tx buffer related status information txfull tx buffer full: asserted when no more data can be stored. txne tx buffer not empty: asserted when tx buffer contains data. rx buffer related status information rxfull rx buffer full: asserted when rx buffer is full. rxne rx buffer not empty: asserted when rx buffer contains data. ahb buffer related status information ahbfull ahb buffer full: asserted when ahb buffer is full. ahbne ahb buffer not empty: assert ed when ahb buffer contains data. sfm command related status information contmode continuous mode: asserted when last command was of type ?continuous read mode? 1 . it is asserted at the end of the execution of the related command together with the qspi_sfmfr[tff] flag. ahb_acc ahb access: asserted when the transaction currently executed was initiated by ahb bus. ip_acc ip access: asserted when transaction cu rrently executed was initiated by ip bus. busy module busy: asserted when module is currently busy handling a transaction to an external flash device.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-35 preliminary?subject to change without notice 30.4.3.20 serial flash mode flag register (qspi_sfmfr) the qspi_sfmfr register provide s all available flags about sfm command execution and arbitration which may serve as source for the gene ration of interrupt service requests. note that the error flags in this register do not relate directly to the execution of the transaction in the se rial flash device itself but only to the behavior and conditions visible in the quadspi module. 1 there are special, vendor-dependent co mmands that use a special access mode of the attached serial flash device. once this mode is enabled in the serial flash device ther e are only certain sfm commands allowed until this mode is explicitly disabled. refer to the serial flash device specification for further details. note that a mode bit collision is det ected if other sfm command s are sent than those com patible with the special access mode. address: qspi_base + 0x160 write: enabled mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 1 1 when not in sfm mode all 0s are read 0000tbfftbuf00000000 rbof rbdf w w1c w1c w1c w1c reset0000100000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 1 0 0 0 0 0 0 abof 0 ipaef ipief icef 0 0 00tff w w1c w1c w1c w1c w1c reset0000000000000000 figure 30-20. serial flash mode flag register (qspi_sfmfr) table 30-33. qspi_sfmfr field descriptions field description tx buffer related flags tbff tx buffer fill flag: set when th e tx buffer is not full. refer to section 30.5.3.6, tx buffer operation ? for details. tbuf tx buffer underrun flag: set when fsm qspi_if tried to pull data although tx buffer was empty. the command leading to the tx buffer underrun is terminated without further write to the serial flash. the application must clear the tx buffer in re sponse to this event by writing a 1 into the qspi_mcr[clr_txf] bit. rx buffer related flags rbof rx buffer overflow flag: set when not all the dat a read from the serial flash device could be pushed into the rx buffer. if the command leading to the rx buffer overflow is still running it is terminated without further reads from the serial flash. th e content of the rx buffer is not changed.
pxd10 microcontroller reference manual, rev. 1 30-36 freescale semiconductor preliminary?subject to change without notice additional details about the error flags cont ained in that register can be found in table 30-50 . rbdf rx buffer drain flag: will be set if the qspi_sfm sr[rxne] status bit is asserted, i.e., the rx buffer is not empty. refer to section 30.5.3.5.2, receive buffer drain interrupt or dma request ? for details. writing a 1 into that bit triggers a rx buffer pop event. if the rx buffer is empt y writing 1 into that bit clears the flag. ahb buffer related flags abof ahb buffer overflow flag: set when state machine qspi_if tried to push data although ahb buffer was full. sfm command related flags ipaef ip command trigger during ahb access error flag. set when the following condition occurs: ? a write access occurs to the qspi_icr regist er and the qspi_sfmfr[ahb_acc] bit is set. any command leading to the assertion of the ipaef flag is ignored ipief ip command trigger during ip access error flag. set on any of the following conditions: ? a write access occurs to the qspi_icr register and the qspi_sfmfr[ip_acc] bit is set. any command leading to the assertion of the ipief flag is ignored ? a write access occurs to the qspi_sfar re gister and the qspi_sfmfr [ip_acc] bit is set. icef instruction code error flag: set when a wrong inst ruction code is encountered or in case of mode bit collision 1 . the instruction which led to the assertion of the icef flag is not executed. wrong commands issued via the ahb interface are not detected. tff transaction finished flag: set when the quadspi module has finished a transaction on the external flash device. if an error occurred or the transaction was terminated the related error flags are valid at the latest in the same clock cycle when the tff flag is asserted. 1 refer to section 30.4.3.19, serial flash mode status register (qspi_sfmsr) sfmsr[contmode] for the description of a mode bit collision table 30-33. qspi_sfmfr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-37 preliminary?subject to change without notice 30.4.3.21 sfm interrupt and dma requ est select and enable register (qspi_sfmrser) the qspi_sfmrser register provides enables and se lectors for all interrupts in serial flash mode. 30.4.4 ahb bus register memory map descriptions this chapter contains definitions of registers in the amba address space. address: qspi_base + 0x164 write: anytime 0123456789101112131415 r0 0 0 0 tbfie tbuie 0000 rbdde 000 rboie rbdie w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 aboie 0 ipaeie ipieie iceie 0 0 00 tfie w reset0000000000000000 figure 30-21. sfm interrupt and dma request select and enable register (qspi_sfmrser) table 30-34. qspi_sfmrser field descriptions field description tbfie tx buffer fill interrupt enable tbuie tx buffer underrun interrupt enable rbdde rx buffer drain dma enable: enables generation of dma requests for rx buffer drain. when this bit is set dma requests via the ipd_req_rfdf line are generated as long as the qspi_sfmsr[rxne] status bit is set. 0 no dma request will be generated 1 dma request will be generated rboie rx buffer overflow interrupt enable rbdie rx buffer drain interrupt enable: enables gener ation of irq requests for rx buffer drain. when this bit is set the ipi_int_rfdf line is asserted as long as the qspi_sfmsr[rbdf] flag is set. 0 no rbdf interrupt will be generated 1 rbdf interrupt will be generated aboie ahb buffer overflow interrupt enable ipaeie ip command trigger during ahb access error interrupt enable ipieie ip command trigger during ip access error interrupt enable iceie instruction code error interrupt enable tfie transaction finis hed interrupt enable
pxd10 microcontroller reference manual, rev. 1 30-38 freescale semiconductor preliminary?subject to change without notice 30.4.4.1 ahb bus access considerations it has to be noted that all logic in the quadspi m odule implementing the ahb bus access is related to read the content of an external serial flash device. ther efore the following restrictions apply to the quadspi module with respect to accesses to the ahb bus: ? in the spi modes all accesses to the ahb interface are served without errors and undefined values are returned on read. ? any write access in sfm mode is answered wi th the error condition according to the amba ahb specification. no write occurs. ? ahb bus access types fully supp orted are nonseq and busy. in fact access type busy is treated in the same way like nonseq. ? ahb access type seq is treated in the same way like nonseq. refer to the amba ahb specification for further details. 30.4.4.2 memory mapped serial flash data (qspi_sfd) starting with address qspi_amba_ba se the content of the external serial flash is mapped into the address space of the device containing the quadspi module. serial flash address byte address 0x0 corresponds to bus address qspi_amba_ba se with increasing order. refer to table 30-35 below for details. the available address range depends from the size of the external se rial flash device. any access beyond the size of the external serial flash provides undefined results. note that for serial flash devices of 128mb size th e last 4 bytes are not accessi ble via the memory mapped interface. for details concerning th e read process refer to section 30.5.3.3, flash read ?. 30.4.4.3 ahb rx data buffer (qspi_ardb) the ahb rx data buffer regi ster is used to read the buffer conten t of the rx buffer. any read access is redirected to the rx buffer regi ster entry corresponding to the current value of the read pointer. the increment of the read pointer depends from the access scheme (dma or flag-driven). refer to section 30.5.3.3.2, host read of the quadspi module internal buffers ? topic rx buffer, data read via register interface and ahb read for the description of successive acce sses to the rx buffer content. refer also to section 30.5.3.4, byte ordering of serial flash data ? for the byte ordering scheme. table 30-35. memory mapped serial flash address scheme memory mapped address 1 1 access scheme is limited to 32 bit data width serial flash byte address qspi_amba_base +0x000_0000 0x000_0000 0x000_0001 0x000_0002 0x000_0003 qspi_amba_base + 0x000_0004 0x000_0004 0x000_0005 0x000_0006 0x000_0007 ... ... ... ... ... qspi_amba_base + 0x7ff_fff8 0x7ff_fff 8 0x7ff_fff9 0x7ff_fffa 07ff_fffb
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-39 preliminary?subject to change without notice 30.5 functional description the quad serial peripheral interface (quadspi) bloc k can be used for two different types (mutually exclusive) of serial communications: ? it supports standard spi full- duplex, synchronous serial communica tions with peri pheral devices. ? it acts as an interface to external serial fl ash devices via up to 4 bi directional data lines. 30.5.1 modes of operation refer to section 30.2.3, quadspi modes of operation for an overview over the possible operational modes of the quadspi block. ? spi master mode: in master mode the quadspi can initiate spi communi cations with peripheral devices. see section 30.5.2.2, master mode ,? for more details. ? spi slave mode: in slave mode the quadspi responds to spi transfers initiated by an external spi master. see section 30.5.2.3, slave mode .? for more details. ? serial flash mode can be used for write or r ead accesses to an external serial flash device. ? serial flash write: data can be programmed into the flash of th e serial flash device. refer to section 30.5.3.2, flash programming ? for further details. ? serial flash read: read the contents of the seri al flash device. two sepa rate read channels are available via rx buffer and ahb buffer, see section 30.5.3.3, flash read ?. ? stop mode: the mode is used fo r power management. when a request is made to enter stop mode, the quadspi block acknowledges the request and co mpletes the transfer in progress, then the system clocks to the quadspi block may be shut off, see section 30.5.4.1, stop mode . address: qspi_amba_base + 0x07ff fffc 0123456789101112131415 r arxd[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rarxd[15:0] w reset0000000000000000 figure 30-22. ahb rx data buffer (qspi_ardb) table 30-36. qspi_ardb field descriptions field description arxd amba provided rx buffer data. byte order (endianess) is identical to the rx buffer data registers.
pxd10 microcontroller reference manual, rev. 1 30-40 freescale semiconductor preliminary?subject to change without notice ? module disable mode: the mode is used for power management. the clock to the non-memory mapped logic in the quadspi can be stopped whil e in module disable m ode.the module enters the mode by setting qspi_mcr[mdis] or when a request is asserted by an external controller while qspi_mcr[doze] is set. see section 30.5.4.2, module disable mode ,? for more details. 30.5.2 spi (serial periph eral interface) modes in the spi master and spi slave mode serial data are transferred using a shift re gister and a selection of programmable transfer attributes. the spi frames can be from four to sixteen bits long. the data to be transmitted can come from queues stored in ram ex ternal to the quadspi. host software or a dma controller can transfer the spi data from the queues to a first-in first-out (fifo) buffer. the received data is stored in entries in the rx fifo. host software or a dma controll er transfer the received data from the rx fifo to memory external to the quad spi. the fifo buffer operations are described in section 30.5.2.5, transmit first in first out (tx fifo) buffering mechanism ,? and section 30.5.2.6, receive first in first out (r x fifo) buffering mechanism .? the interrupt and dma request conditions are described in section 30.5.2.10, spi mode interrupt and dma requests .? there are two different spi modes: master mode and slave mode. th e fifo operations are similar for the master mode and slave mode. th e main difference is that in mast er mode the quadspi initiates and controls the transfer according to th e fields in the spi comm and field of the tx fifo entry. in slave mode the quadspi only responds to transfers initiated by a bus master external to the quadspi and the spi command field of the tx fifo entry is ignored. the 16-bit shift register in the master and the 16-bit sh ift register in the slave are linked by the so and si signals to form a distributed 32-bit register. when a da ta transfer operation is pe rformed, data is serially shifted a pre-determined number of bit positions. b ecause the registers are linked, data is exchanged between the master and the slave; the da ta that was in the master?s shift re gister is now in the shift register of the slave, and vice versa. at th e end of a transfer, the tcf bit in th e qspi_spisr is set to indicate a completed transfer. figure 30-23 illustrates how master and slave data is exchanged. figure 30-23. spi serial protocol overview the quadspi has eight peripheral chip select (pcs) signals that are used to select which of the slaves to communicate with. shift register baud rate generator shift register si si so so sck sck ss pcsx spi master spi slave
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-41 preliminary?subject to change without notice both spi modes and the sfm mode sh are transfer protocol and timing properties so they are described independently of the mode in section 30.5.2.8, spi transfer formats ?. the transfer rate and delay settings are described in section 30.5.2.7, baud rate and clock delay generation .? the qspi_ctar0 - qspi_ctar7 registers hold clock a nd transfer attributes. in the spi master mode the user can select which ctar to use on a frame by frame basis by setting a field in the spi command. see section 30.4.3.4, clock and transfer attributes registers 0 ? 1 (qspi_ctar0 ? qspi_ctar1) ,? for information on the fields of the qspi_ctar registers. see section 30.5.4, power saving features ,? for information on the power-saving features of the quadspi. 30.5.2.1 start and stop of spi transfers the quadspi in spi master or slave mode ha s two operating states; stopped and running. the default state is stopped. in the stopped state no se rial transfers are initiate d in master mode and no transfers are responded to in slave mode. the stopped state is also a safe state for writing the various configuration registers of the quadspi without causing undetermined results. the txrxs bit in the qspi_spisr is negated in this stat e. in the running state se rial transfers take pl ace. the txrxs bit in the qspi_spisr is asserted in the running state. figure 30-24 shows a state diagram of the start and stop mechanism. the transi tions are described in table 30-37 . figure 30-24. quadspi start and stop state diagram table 30-37. state transitions for start and stop of quadspi transfers transition # current state next state description 0 reset stopped generic power-on-reset transition 1 stopped running the quadspi is started (s pi state transitions to running) when all of the following conditions are true: ? eoqf bit is clear ? halt bit is clear ? ipg_debug is clear or frz is clear 2 running stopped the quadspi stops (trans itions from running to stopped) after the current frame for any one of the following conditions: ? eoqf bit is set ? halt bit is set ? ipg_debug is set and frz is set reset stopped running power on txrxs=0 txrxs=1 reset 2 1 0
pxd10 microcontroller reference manual, rev. 1 30-42 freescale semiconductor preliminary?subject to change without notice state transitions from running to stopped occur on the next frame boundary if a transfer is in progress, or on the next system clock cycle if no transfers are in progress. 30.5.2.2 master mode in spi master mode (mstr bit in th e qspi_mcr is set) the quadspi ope rates as bus master and initiates the serial transfers by controlling the serial communicati ons clock (sck) and the peripheral chip select (pcs) signals. the spi command field ctas in the executing tx fifo entry determines which ctar register will be used to set the tran sfer attributes and which pcs signal to assert. the comm and fields also contains various bits that help with queue management and transfer protocol. see section 30.4.3.7, push tx fifo register (qspi_pushr) ? for details on the spi command fiel ds. the data field in the executing tx fifo entry is loaded into the shift register and shifted out on the serial out (so) pin. in spi master mode, each spi frame to be transmit ted has a command associated with it allowing for transfer attribute control on a frame by frame basis. 30.5.2.3 slave mode in spi slave mode (mstr bit in th e qspi_mcr register is not set) the quadspi responds to transfers initiated by an external spi bus master and cannot ini tiate transfers. the quadsp i slave is selected by a bus master by having the slave?s ss asserted. in slave mode the sck is provided by the bus master. all transfer attributes are controlled by the bus master bu t clock polarity, clock phase and numbers of bits to transfer must still be configured in the quadspi sl ave for proper communications with an external spi master. in spi slave mode the slave transfer attributes are set in the qspi_ctar0. the quadspi transfers the msb first. the lsbfe field of the associated ctar is ignored. 30.5.2.4 fifo disable operation the fifo disable mechanisms allow spi transfers without us ing the tx fifo or rx fifo. the quadspi operates as a double-buffered simplified spi when th e fifos are disabled. the tx and rx fifos are disabled separately. the tx fifo is disabled by writing a ?1? to th e dis_txf bit in the qspi_mcr. the rx fifo is disabled by writing a ?1? to the dis_rxf bit in the qspi_mcr. the fifo disable mechanisms are transparent to the user and to host software; transmit data and commands are written to the qs pi_pushr and received data is read from the qspi_popr. when the tx fifo is disabled the tfff, tfuf and tx ctr fields in qspi_spisr behave as if there is a one-entry fifo but the contents of the qspi_t xfr registers and txnxtpt r are undefined. when the rx fifo is disabled the rfdf, rfof and rxctr fiel ds in the qspi_spisr be have as if there is a one-entry fifo but the conten ts of the qspi_rxfr register s and popnxtptr are undefined. 30.5.2.5 transmit first in first ou t (tx fifo) buffering mechanism the tx fifo functions as a buffer of spi data and spi commands fo r transmission. the tx fifo holds in total 15 entries, each consisti ng of a command field and a data fiel d. spi commands and data are added to the tx fifo by writing to the push tx fifo register (qspi_pushr ). tx fifo entries can only be removed from the tx fifo by being sh ifted out or by flushing the tx fifo.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-43 preliminary?subject to change without notice the tx fifo counter field (txctr ) in the spi status register (q spi_spisr) indicates the number of valid entries in the tx fifo. the txctr is updated every time the qu adspi _pushr is written or spi data is transferred into the sh ift register from the tx fifo. the txnxtptr field indicates which tx fifo entry will be transmitted during the next transfer. the txnxtptr contains the positive offs et from qspi_txfr0 in number of 32-bit registers. for example, txnxtptr equal to two means that the qspi_txfr2 contains the spi data and command for the next transfer. the txnxtptr field is incr emented every time spi da ta is transferred from the tx fifo to the shift register. 30.5.2.5.1 filling the tx fifo host software or other intelligent blocks can add (push) entries to the tx fifo by writing to the qspi_pushr. when the tx fifo is not full, the tx fi fo fill flag (tfff) in the qspi_spisr is set. the tfff bit is cleared when tx fifo is full a nd the dma controller indi cates that a write to qspi_pushr is complete or by host software writi ng a ?1? to the tfff in the qspi_spisr. the tfff can generate a dma request or an interrupt request. see section 30.5.3.5.1, transmit buffer fill interrupt request ,? for details. the quadspi ignores attempts to push data to a full tx fifo, i.e., the state of the tx fifo is unchanged. no error condition is indicated. 30.5.2.5.2 draining the tx fifo the tx fifo entries are re moved (drained) by shifting spi data out through the sh ift register. entries are transferred from the tx fifo to the shift register and shifted out as l ong as there are valid entries in the tx fifo. every time an entry is transferred from the tx fifo to the shift regi ster, the tx fifo counter is decremented by one. at the end of a transfer, the tcf bit in the qspi_spisr is set to indicate the completion of a transfer. the tx fifo is cleared by writing a ?1? to the clr_txf bit in qspi_mcr. if an external bus master initiate s a transfer with a quadspi slave while the slave?s quadspi tx fifo is empty, the transmit fifo underrun flag (tfuf) in the slave?s q spi_spisr is set. see section section 30.5.2.10.4, transmit fifo underrun interrupt request ,? for details. 30.5.2.6 receive first in first ou t (rx fifo) buffering mechanism the rx fifo functions as a buffer for data received on the si pin. the rx fifo holds in total 15 received spi data frames. spi data is added to the rx fifo at the completion of a transfer when the received data in the shift register is transferred into the rx fi fo. spi data are removed (popped) from the rx fifo by reading the pop rx fifo register (qspi_popr). rx fifo entries ca n only be removed from the rx fifo by reading the qspi_popr or by flushing the rx fifo. the rx fifo counter field (rxctr ) in the spi status register (q spi_spisr) indicates the number of valid entries in the rx fifo. the rxctr is updated every time the qspi_popr is read or spi data is copied from the shift re gister to the rx fifo. the popnxtptr field in the qspi_spisr points to the rx fifo entry that is returned when the qspi_popr is read. the popnxtptr contains the positive offset from qspi_rxfr0 in number of 32-bit registers. for example, popnxtptr equal to two means that the qspi_rxfr2 contains the
pxd10 microcontroller reference manual, rev. 1 30-44 freescale semiconductor preliminary?subject to change without notice received spi data that will be retu rned when qspi_popr is read. th e popnxtptr field is incremented every time the qspi_popr is read. 30.5.2.6.1 filling the rx fifo the rx fifo is filled with the rece ived spi data from the shift regist er. while the rx fifo is not full, spi frames from the shift register are transferred to th e rx fifo. every time a sp i frame is transferred to the rx fifo the rx fifo counter is incremented by one. if the rx fifo and shift register are full and a transf er is initiated, the rfof bit in the qspi_spisr is asserted indicating an overflow c ondition. depending on the state of the rooe bit in the qspi_mcr, the data from the transfer that generated the overflow is either ignored or shif ted in to the shift register. if the rooe bit is asserted, the incoming data is shifted in to the shift regist er. if the rooe bit is negated, the incoming data is ignored. 30.5.2.6.2 draining the rx fifo host software or other intelligent blocks can remove (pop) entries fr om the rx fifo by reading the pop rx fifo register (qspi_popr). a read of the qspi_popr decremen ts the rx fifo counter by one. attempts to pop data from an empty rx fifo are ignored, the rx fifo counter remains unchanged. the data returned from reading an empty rx fifo is undetermined. when the rx fifo is not empty, th e rx fifo drain flag (rfdf) in the qspi_spisr is set. the rfdf bit is cleared when the rx fifo is empty and the dm a controller indicates that a read from qspi_popr is complete or by host software writing a ?1? to the rfdf. 30.5.2.7 baud rate and clock delay generation the sck frequency and the delay values for serial tr ansfer are generated by dividing the system clock frequency by a prescaler and a scaler wi th the option for doubling the baud rate. figure 30-25 shows conceptually how the sck signal is generated. figure 30-25. communications clock prescalers and scalers 30.5.2.7.1 baud rate generator the baud rate is the frequency of the serial comm unication clock (sck). the system clock is divided by a prescaler (pbr) and scal er (br) to produce sck with the possibi lity of halving the scaler division. the dbr, pbr and br fields in the qspi_ctar regist ers select the frequency of sck by the formula in the br[0:3] field description. table 30-38 shows an example of how to compute the baud rate. sck system clock prescaler 1 scaler 1+dbr
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-45 preliminary?subject to change without notice 30.5.2.7.2 pcs to sck delay (t csc ) the pcs to sck delay is the length of time from as sertion of the pcs signal to the first sck edge. see figure 30-27 and figure 30-28 for an illustration of the pcs to sck delay. the pcssck and cssck fields in the qspi_ctarx register s select the pcs to sck delay by th e formula in the cssck[0:3] bit description. table 30-39 shows an example of how to compute the pcs to sck delay. 30.5.2.7.3 after sck delay (t asc ) the after sck delay is the length of time between th e last edge of sck and the negation of pcs. see figure 30-36 for illustrations of the after sck delay. the pasc and asc fields in the qspi_ctarx registers select the after sck delay by the formula in the asc[0:3] field description. table 30-40 shows an example of how to compute the after sck delay. 30.5.2.7.4 delay after transfer (t dt ) the delay after transfer is the length of time be tween negation of the pcs signal for a frame and the assertion of the pcs signal for the next frame. see figure 30-27 for an illustration of the delay after transfer. the pdt and dt fields in the qspi_ctarx registers select the delay after transfer by the formula in the dt[0:3] field description. table 30-41 shows an example of how to compute the delay after transfer. when in non-continuous clock mode the t dt delay can be configured as outlined in the qspi_ctarx registers. when in continuous clock m ode the delay is fixed at 1 sck period. table 30-38. baud rate computation example pbr prescaler br scaler dbr fsys baud rate 0b00 2 0b0000 2 0 100 mhz 25 mb/s 0b00 2 0b0000 2 1 20 mhz 10 mb/s table 30-39. pcs to sck delay computation example pcssck prescaler cssck scale r fsys pcs to sck delay 0b01 3 0b0100 32 100 mhz 0.96 ? s table 30-40. after sck delay computation example pasc prescaler asc scaler fsys after sck delay 0b01 3 0b0100 32 100 mhz 0.96 ? s table 30-41. delay after transfer computation example pdt prescaler dt scaler fsys delay after transfer 0b01 3 0b1110 32768 100 mhz 0.98 ms
pxd10 microcontroller reference manual, rev. 1 30-46 freescale semiconductor preliminary?subject to change without notice 30.5.2.7.5 peripheral chip se lect strobe enable (pcss ) the pcss signal provides a delay to allow the pcs signals to settle after a transition occurs thereby avoiding glitches. when the quadspi is in master mode and pcsse bit is set in the qspi_mcr, pcss provides a signal for an external demu ltiplexer to decode the pcs[4:0] and pcs[7:6] signals into as many as 128 glitch-free pcs signals. figure 30-26 shows the timing of the pcss signal relative to pcs signals. figure 30-26. peripheral chip select strobe timing the delay between the assertion of the pcs signals and the assertion of pcss is selected by the pcssck field in the qspi_ctar based on the following formula: eqn. 30-5 at the end of the transf er the delay between pcss negation and pcs negation is selected by the pasc field in the qspi_ctar based on the following formula: eqn. 30-6 table 30-42 shows an example of how to compute the t pcssck delay. table 30-43 shows an example of how to compute the t pasc delay. the pcss signal is not supported when continuous serial communicati on sck is enabled (cont_scke=1). 30.5.2.8 spi transfer formats the spi serial communication is c ontrolled by the serial communicat ions clock (sck) signal and the pcs signals. the sck signal provided by the master device synchronizes sh ifting and sampling of the data on the si and so pins. the pcs signals serve as enable signals for the slave devices. table 30-42. peripheral chip select strobe assert computation example pcssck prescaler fsys delay before transfer 0b11 7 100 mhz 70.0 ns table 30-43. peripheral chip select strobe negate computation example pasc prescaler fsys delay after transfer 0b11 7 100 mhz 70.0 ns t pcssck pcss pcsx t pasc t pcssck 1 f sys ---------- pcssck ? = t pasc 1 f sys ---------- pasc ? =
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-47 preliminary?subject to change without notice when the quadspi is the bus master, the cpol a nd cpha bits in the quadspi clock and transfer attributes registers (qspi_ ctarx) select the polarity and phase of the serial clock, sck. the polarity bit selects the idle state of the sck. the clock phase bit selects if the da ta on so is valid before or on the first sck edge. when the quadspi is the bus slave, cpol and cpha bits in the qspi_ctar0 select the polarity and phase of the serial clock. for spi slaves the qspi_c tar0 is used, and for dsi slaves the qspi_ctar1 is used. even though the bus slave doe s not control the sck si gnal, clock polarity, clock phase and number of bits to transfer must be identical for the ma ster device and the slave device to ensure proper transmission. the quadspi supports four di fferent transfer formats: ? classic spi with cpha=0 ? classic spi with cpha=1 ? modified transfer format with cpha = 0 ? modified transfer format with cpha = 1 a modified transfer format is supported to allow for high-speed communication with peripherals that require longer setup times. the qu adspi can sample the incoming data later than halfway through the cycle to give the peripheral more setup time. the mtfe bit in the qs pi_mcr selects between classic spi format and modified transfer format. th e classic spi formats are described in section 30.5.2.8.1, classic spi transfer format (cpha = 0) ,? and section 30.5.2.8.2, classic spi tr ansfer format (cpha = 1) .? the modified transfer formats are described in section 30.5.2.8.3, modified spi transfer format (mtfe = 1, cpha = 0) ,? and section 30.5.2.8.4, modified spi transf er format (mtfe = 1, cpha = 1) .? in spi master mode and spi slave mode the quad spi provides the option of keeping the pcs signals asserted between frames. see section 30.5.2.8.5, continuous selection format ,? for details. 30.5.2.8.1 classic spi tr ansfer format (cpha = 0) the transfer format shown in figure 30-27 is used to communicate with peripheral spi slave devices where the first data bit is available on the first clock edge. in this format , the master and slave sample their si pins on the odd-numbered sck edges and change the data on thei r so pins on the even-numbered sck edges.
pxd10 microcontroller reference manual, rev. 1 30-48 freescale semiconductor preliminary?subject to change without notice figure 30-27. quadspi transfer timing diagram (mtfe=0, cpha=0, fmsz=8) the master initiates the transfer by placing its first data bit on the so pin a nd asserting the appropriate peripheral chip select signals to th e slave device. the slave responds by placing its fi rst data bit on its so pin. after the t csc delay has elapsed, the master out puts the first edge of sck. th is is the edge used by the master and slave devices to sample the first input data bit on their serial data input signals. at the second edge of the sck the master and slav e devices place their second data bit on their serial data output signals. for the rest of the frame the master and the slave sample their si pins on the odd-numbered clock edges and changes the data on their so pins on the even-numbe red clock edges. after the last clock edge occurs a delay of t asc is inserted before the master ne gates the pcs signals. a delay of t dt is inserted before a new frame transfer can be initiated by the master. 30.5.2.8.2 classic spi tr ansfer format (cpha = 1) this transfer format shown in figure 30-28 is used to communicate with pe ripheral spi slav e devices that require the first sck edge before th e first data bit becomes available on the slave so pin. in this format the master and slave devices change the data on their so pins on th e odd-numbered sck edges and sample the data on their si pins on the even-numbered sck edges t csc sck master and slave pcsx/ss sck msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 master so/ master si/ t dt t csc t csc = pcs to sck delay t dt = delay after transfer (minimum cs idle time) (cpol = 0) (cpol = 1) t asc slave si slave so 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sample t asc = after sck delay
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-49 preliminary?subject to change without notice figure 30-28. quadspi transfer timing diagram (mtfe=0, cpha=1, fmsz=8) the master initiates the tran sfer by asserting the pcs signal to the slave. after the t csc delay has elapsed, the master generates the first sck ed ge and at the same ti me places valid data on the master so pin. the slave responds to the first sck edge by placing its first data bit on its slave so pin. at the second edge of the sck the master and slave sa mple their si pins. for th e rest of the frame the master and the slave change the da ta on their so pins on the odd-numbe red clock edges and sample their si pins on the even-numbered clock edges. af ter the last clock edge occurs a delay of t asc is inserted before the master negates the pc s signal. a delay of t dt is inserted before a new fr ame transfer can be initiated by the master. 30.5.2.8.3 modified spi transfer format (mtfe = 1, cpha = 0) in this modified transfer format both the master and the slave sample later in the sck period than in the classical modes to allow for delays in device pads and board traces. these delays become a more significant fraction of the sck period as the sck period decrea ses with increasing baud rates. the master and the slave places data on the so pins at the assertion of the pcs signal. after the pcs to sck delay has elapsed the first sck edge is generated. the slave samp les the master so signal on every odd numbered sck edge. the slave al so places new data on the slav e so on every odd numbered clock edge. t csc t dt sck sck msb first (lsbfe = 0): lsb first (lsbfe = 1): msb lsb lsb msb bit 5 bit 2 bit 6 bit 1 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 t csc = pcs to sck delay t dt = delay after transfer (minimum cs negation time) (cpol = 0) (cpol = 1) t asc master so/ master si/ slave si slave so 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pcsx/ss master and slave sample t asc = after sck delay
pxd10 microcontroller reference manual, rev. 1 30-50 freescale semiconductor preliminary?subject to change without notice the master places its second data bit on the so line one system clock after odd numbered sck edge. the point where the master samples the slave so is selected by writing to th e smpl_pt field in the qspi_mcr. the smpl_pt field description in table 30-9 lists the number of system clock cycles between the active edge of sck and the master sample point. the master sample point can be delayed by one or two system clock cycles. figure 30-29 shows the modified transfer format for cp ha = 0. only the condition where cpol = 0 is illustrated. the delayed master sample points are indicated with a lighter shaded arrow. figure 30-29. quadspi modified transfer format (mtfe=1, cpha=0, fsck = fsys/4) 30.5.2.8.4 modified spi transfer format (mtfe = 1, cpha = 1) figure 30-30 shows the modified transfer format for cp ha = 1. only the conditio n where cpol = 0 is described. at the start of a transfer the quadspi asse rts the pcs signal to the sl ave device. after the pcs to sck delay has elapsed the master and the slave put da ta on their so pins at th e first edge of sck. the slave samples the master so signal on the even numbe red edges of sck. the master samples the slave so signal on the odd numbered sck edge s starting with the 3r d sck edge. the slave samples the last bit on the last edge of the sck. the master samples the last slave so bit one half sck cycle after the last edge of sck. no clock edge will be visible on the ma ster sck pin during the samp ling of the last bit. the sck to pcs delay must be greater or equal to half of the sck period. t csc sck system master slave pcs t csc = pcs to sck delay so master so sample slave sample sys 1 2 3 4 5 6 clock t asc clk sys clk t asc = after sck delay
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-51 preliminary?subject to change without notice figure 30-30. quadspi modified transfer format (mtfe=1, cpha=1, fsck = fsys/4) 30.5.2.8.5 continuous selection format some peripherals must be deselected between every transfer. other peripherals must remain selected between several sequential se rial transfers. the continuous selecti on format provides the flexibility to handle both cases. the continuous sel ection format is enabled for bot h spi modes by setting the cont bit in the spi command. when the cont bit = 0, the quadspi drives the asserted chip select signals to their idle states in between frames. the idle states of the ch ip select signals are selected by the pcsis field in the qspi_mcr. figure 30-31 shows the timing diagram for two four-bit transfers with cpha = 1 and cont = 0. t csc sck system clock master slave pcs slave master so so sample sample t csc = pcs to sck delay t asc t asc = after sck delay 1 2 3 4 5 6
pxd10 microcontroller reference manual, rev. 1 30-52 freescale semiconductor preliminary?subject to change without notice figure 30-31. example of non-continuous format (cpha=1, cont=0) when the cont bit = 1, the pcs signal remains asserted for the duration of the two transfers. the delay between transfers (t dt) is not inserted between the transfers. figure 30-32 shows the timing diagram for two four-bit transfers with cpha = 1 and cont = 1. figure 30-32. example of continuous transfer (cpha=1, cont=1) switching ctar registers or changing which pcs si gnals are asserted betw een frames while using continuous selection can cause errors in the transfer. the pcs signal s hould be negated before ctar is switched or different pcs signals are selected. t csc t dt t csc sck pcsx sck master so master si t csc = pcs to sck delay t dt = delay after transfer (minimum cs negation time) (cpol = 0) (cpol = 1) t asc t asc = after sck delay t csc t csc sck pcs sck master so master si t csc = pcs to sck delay (cpol = 0) (cpol = 1) t asc (cpol = 0) sck t asc = after sck delay
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-53 preliminary?subject to change without notice 30.5.2.9 continuous serial communications clock the quadspi provides the option of ge nerating a continuous sc k signal for slave peri pherals that require a continuous clock. continuous sck is enabled by setting the cont_sck e bit in the qspi_mcr. co ntinuous sck is valid in both spi modes. continuous sck is only s upported for cpha=1. setting cpha=0 will be ignored if th e cont_scke bit is set. continuous sck is supporte d for modified transfer format. clock and transfer attributes fo r the continuous sck mode are set according to the following rules: ? in both spi modes ctar0 shall be used initially. at the start of each spi fr ame transfer, the ctar specified by the ctas for the frame shall be used. ? in both spi modes the currently selected ctar sha ll remain in use until the start of a frame with a different ctar specified, or the continuous sck mode is terminated. it is recommended that the baud rate is the same fo r all transfers made while using the continuous sck. switching clock polarity between frames while using continuous sck can cause errors in the transfer. continuous sck operation is not guara nteed if the quadspi is put into the stop mode or module disable mode. enabling continuous sck disables the pcs to sck delay and the delay after transfer (t dt ) is fixed at one t sck cycle. figure 30-33 shows timing diagram for conti nuous sck format with continuous selection disabled. figure 30-33. continuous s ck timing diagram (cont=0) if the cont bit in the tx fifo en try is set pcs remains asserted be tween the transfers. under certain conditions, sck can continue with pcs asserted, but with no data being shifted out of so (so pulled high). this can cause the slave to receive incorrect data. thos e conditions include: ? continuous sck with cont bit set, but no data in the transmit fifo. ? continuous sck with cont bit set a nd entering stopped state (refer to section 30.5.2.1, start and stop of spi transfers ?). t dt sck pcs sck master so master si (cpol = 0) (cpol = 1)
pxd10 microcontroller reference manual, rev. 1 30-54 freescale semiconductor preliminary?subject to change without notice ? continuous sck with cont bit set and en tering stop mode or module disable mode. figure 30-34 shows timing diagram for continuous sck fo rmat with continuous selection enabled. figure 30-34. continuous s ck timing diagram (cont=1) 30.5.2.10 spi mode interrupt and dma requests in both spi modes the quadspi has four conditions that can only generate in terrupt requests and two conditions that can generate interr upt or dma request alternatively. table 30-44 lists the six conditions. note that the flags mentioned in the table re late to the spi status register qspi_spisr each condition has a flag bit in the spi status register (qspi_spisr) an d a request enable bit in the spi interrupt and dma request se lect and enable register (qspi_spirser ). the tx fifo fill flag (tfff) and rx fifo drain flag (rfdf) generate inte rrupt requests or dma requests depending on the tfff_dirs and rfdf_dirs b its in the qspi_spirser. 30.5.2.10.1 end of q ueue interrupt request the end of queue request indicates that the end of a transmit queue is reached. the end of queue request is generated when the eoq bit in the executing spi command is asserted and the eoqf_re bit in the qspi_spirser is asserted. table 30-44. spi mode interrupt and dma request conditions condition flag (qspi_spisr) interrupt dma end of queue (eoq) eoqf x tx fifo fill tfff x x transfer complete tcf x tx fifo underrun tfuf x rx fifo drain rfdf x x rx fifo overflow rfof x sck pcs sck master so master si (cpol = 0) (cpol = 1) transfer 1 transfer 2
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-55 preliminary?subject to change without notice 30.5.2.10.2 transmit fifo fill interrupt or dma request the transmit fifo fill reque st indicates that the tx fifo is not fu ll. the transmit fifo fill request is generated when the number of entries in the tx fifo is less than the maximum number of possible entries, and the tfff_re bit in the qspi_spirser is a sserted. the tfff_dirs bit in the qspi_spirser selects whether a dma request or an interrupt request is generated. 30.5.2.10.3 transfer comp lete interrupt request the transfer complete request indicates the end of th e transfer of a serial frame. the transfer complete request is generated at th e end of each frame transf er when the tcf_re bit is set in the qspi_spirser. 30.5.2.10.4 transmit fifo underrun interrupt request the transmit fifo underrun request indicates that an underrun conditi on in the tx fifo has occurred. the transmit underrun condition is detected only in spi slave mode. the tfuf bit is set when the tx fifo is empty, and a transfer is in itiated from an external spi master . if the tfuf bit is set while the tfuf_re bit in the qspi_spirser is asse rted, an interrupt request is generated. 30.5.2.10.5 rx fifo drain interrupt or dma request the rx fifo drain request indicates that the rx fi fo is not empty. the rx fifo drain request is generated when the number of entries in the rx fifo is not zero, and the rfdf_re bit in the qspi_spirser is asserted. the rf df_dirs bit in the qspi_spirser selects whether a dma request or an interrupt request is generated. 30.5.2.10.6 rx fifo over flow interrupt request the rx fifo overflow request indi cates that an overflow condition in the rx fifo has occurred. a rx fifo overflow request is generated when rx fifo and shift register ar e full and a transfer is initiated. the rfof_re bit in the qspi_spirser must be set for the interrupt re quest to be generated. depending on the state of the rooe bit in the qspi_mcr, the data from the transfer that generated the overflow is either ignored or shifted in to the shift re gister. if the rooe bit is set, the incoming data is shifted in to the shift register. if the rooe bit is negated, the incoming data is ignored. 30.5.3 sfm (serial flash) mode this mode is used to allow communication with an exte rnal serial flash device. compared to the standard spi protocol, this communication method uses up to 4 bidirectional data li nes operating at high data rates. the communication to the external seri al flash device consists of an instruction code and optional address, mode, dummy and data transfers. all operations to the external serial flash device may use only instruction codes listed in section 30.7, serial flash devices ?. note that all the information given in this paragraph is applicable only if the qspi_mcr[qmode] bit is set.
pxd10 microcontroller reference manual, rev. 1 30-56 freescale semiconductor preliminary?subject to change without notice 30.5.3.1 issuing sfm commands each access to the external device follows the same sequence: 1. the user must provide the required componen ts of a sfm command to the quadspi module. 2. from these components the complete transaction is built. the transaction starts and the status bit qspi_sfmsr[busy] is set. 3. communication with the external serial flash de vice is started and the transaction is executed. 4. when the transaction is finished (all transmit- and receive operations with the external serial flash device are finished) or terminated (an error condition occurred during the transaction) the status bit qspi_sfmsr[busy] is reset and th e qspi_sfmfr[tff] flag is set. further details are given in below in section 30.5.3.2, flash programming ? and section 30.5.3.3, flash read ?. note that there are 2 diffe rent ways to trigger the processing of sfm commands in the quadspi module. 30.5.3.1.1 ip commands for ip commands the required components need to be written into the following registers: ? read address of the serial fl ash into qspi_sfar, refer to section 30.4.3.11, serial flash address register (qspi_sfar) ?. ? instruction code options belonging to the ip command into the qspi_icr[ico] field. ? instruction code belonging to the ip command into the qspi_icr[ic] field. note that the write into the qspi_icr[ic] field must be the last step of th e sequence. it is possible to combine both fields of the qspi _icr into one single write. refer to section 30.4.3.12, instruction code register (qspi_icr) ? for details. note that there are some conditions were no ip command is executed af ter writing the qspi_icr[ic] field and the write operation itself is ignored. they are described in section 30.6.7, command arbitration - sfm mode only ?. 30.5.3.1.2 ahb commands note that the required components of the ahb commands are located in different registers w.r.t. the ip commands. they need to be written into the qspi_acr register like described in section 30.4.3.18, amba control register (qspi_acr) ?. the ahb command itself is triggered by a read acces s of the host into the memory mapped serial flash data, like described in section 30.4.4.2, memory mapped se rial flash data (qspi_sfd) ?. again the possible error c onditions are described in section 30.6.7, command arbitration - sfm mode only ?.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-57 preliminary?subject to change without notice 30.5.3.2 flash programming in all cases the memory sector to be written needs to be erased first. the pr ogramming sequence itself is then initiated in the following way: 1. check that the tx buffer is em pty. if the qspi_sfmsr[txne] bit is set the tx buffer must be cleared by writing 1 into the qspi_mcr[clr_txf] bit. 2. program the address related to the command in the qspi_sfar register. optionally one can clear the qspi_tbsr[trctr] field by writ ing 1 into qspi_mcr[clr_txf]. 3. provide initial data for the program command into the circular buffer via re gister tx buffer data register (qspi_tbdr). at least one word of data must be written into the tx buffer. 4. program the required instruction code options (i.e . size of data) into the qspi_icr[ico] register. 5. trigger the ip command to program the serial flash devi ce by writing the instruction code into the qspi_icr[ic] register. 6. depending from the amount of data required step 3 must be repeated until all the required data have been written into the qspi_tbd r register. at any time the q spi_tbdr[trctr] field can be read to check how many words have been written actually into the tx buffer. steps 4 and 5 may be executed together. upon writing the qspi_icr[i c] field (refer to step 5) the quadspi module will start to execute the command by transferring instruction c ode, address and then data to the external device. the data are fetched from the tx buffer. it consists of 15 entries wi th 32-bit and is organized as a circular fifo, whose read pointer is incremented after e ach fetch. when all data are transmitted, the quadspi module will return from ?busy? to ?idle?. however, this is not true for the external device since the internal programming is still ongoing. it is up to the user to monitor the relevant status informat ion available from the serial flash device and to ensure that the pr ogramming is finished properly. 30.5.3.3 flash read host access to the data stored in the external serial flash device is done in two st eps: first the data must be read into the internal buffers and in the second st ep these internal buffers can be read by the host. 30.5.3.3.1 reading seri al flash data into the quadspi module read access to the external serial flash de vice can be triggered in two different ways: ? ip command read : for flash read via the register interface the user must provide the required components of a sfm command to the qspi_sfar a nd the qspi_icr register s. all available read commands supported by the external serial flash are possible. optionally it is possible to clear the rx buffer pointer prior to triggering the ip command by writing a 1 into the qspi_mcr[clr_rxf] bit. from these inputs the complete transaction is bui lt when the qspi_icr[ic] field is written. the transaction related to the read access starts and the requested number of bytes is fetched from the external serial flash device into the rx buffer. since the read access is tr iggered via the register interface the ip_acc status bit is set driving in turn the busy bit (both are located in the qspi_sfmsr register).
pxd10 microcontroller reference manual, rev. 1 30-58 freescale semiconductor preliminary?subject to change without notice the communication with the external serial flas h is stopped when the specified number of bytes has been read (successful completion of the transa ction) or if the rx bu ffer overrun condition is detected (signalled by set ting the qspi_sfmfr[rbof] flag). in this case the transaction leading to the rx buffer overrun is terminated. ? ahb command read : for a memory mapped flash read the user must setup a read access to the address range were the ex ternal serial flash device is mapped to by programming the qspi_acr register with the requested data not alre ady available in the ahb buffer . on each ahb read access to the memory mapped area the valid data in the ahb buffer are checked against the address requested in the act ual read. when the ahb read request can?t be served from the content of the ahb buffer the co mplete transaction to access the external serial flash device is built from the qspi_acr regist er contents and started. the requested number of bytes defined in the qspi_acr[arsz] field is then fetched from th e external serial flash device into the internal ahb buffer. since the read access is triggered via the ahb bus the ahb_acc status bit is set driving in turn the busy bit (b oth are located in the qspi_sfmsr register) until the transaction is finished. the communication with the external se rial flash is stopped when the specified number of bytes has been read. basically the ahb buffer behaves similar to a cac he memory with a size of one single line. 30.5.3.3.2 host read of the quad spi module inte rnal buffers the data read out from the external serial flash de vice by the quadspi module are stored in the internal buffers. depending from the buffer to which the data from the external serial flas h has been loaded there are several different ways to access these data in the internal buffers: ? flag-based data read of the 1rx buffer is done by reading the address qspi_ardb, see section 30.4.4.3, ahb rx data buffer (qspi_ardb) ?. the qspi_sfmsr[rxne] bit indicates that data ar e available in the rx buffer and can be read by ahb read access to address qspi_ardb. the rx buffer is implemented as circular buffer. this means that after the increment of the read point er the next read accesses to that (same) address provides the next data word from th e serial flash device. the incremen t of the read pointer itself is done by writing a ?1? into the qspi_sfmfr[rbdf] bit. for the remaining status related bits qspi_s pisr[rfof] and qspi_s pisr[rfdf] refer to section 30.4.3.5, spi status register (qspi_spisr) ?. it?s up to the user to decide whether the relevant flags are polled by software or to drive the data read by the interrupt capabilities of the quadspi module. ? dma triggered data read of the rx buffer is done by reading a ddress qspi_ardb, see section 30.4.4.3, ahb rx data buffer (qspi_ardb) ? by using the dma capabilities of the quadspi and the device containing the quadspi module. the circular buf fer pointer is updated automatically without inter action from the application. refer to reference semiconductor reuse standard v3.2 section 04 ip interf ace for details about the dma usage. the application must ensure that the dma controller of the related device is programmed appropriately. ? rx buffer, data read via ips registers : by reading the rx buffer data registers 0?14 (qspi_rbdr0?qspi_rbdr14) the individual entr ies in the rx buffer can be accessed
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-59 preliminary?subject to change without notice arbitrarily. refer to section 30.4.3.15, rx buffer data registers 0?14 (qspi_rbdr0?qspi_rbdr14) ? for details. note that after clearing the rx bu ffer the next entry is written in to qspi_rbdr0. aside from that there is no information available about the curren t positions of the rx buffer read and write pointers. it is not recommended to use this access scheme for subsequent read s of more than 15 data words. ? ahb buffer data read vi a memory mapped access : this kind of access is done by reading one of the addresses assigned to th e external serial flash device within the range given in table 30-35 under the condition that the data reque sted are already present in the ahb buffer or it is currently read from the serial flash device . if this is not the case a memory mapped read of the ahb buffer is triggered like descri bed above). as long as the requested da ta are already available in the ahb buffer they are provided to the host. the host can re ad the available data out of the ahb buffer in any order. if the address requested by the current read is the one currently fetched by the quadspi module from the serial flash the execution of the curr ent command remains running with the ahb read access stalled. as soon as the da ta from the requested address have been read by the quadspi module the ahb read access is serv ed. so it?s possible to run seque ntial read from the ahb buffer at arbitrary speed without the need to monitor a ny information about the av ailability of the data. nevertheless this access scheme stalls the ahb bus for the time required to read the data from the serial flash device. as long as the host restricts its accesses to the da ta already in the buffer and the data currently fetched from the serial flash it is possible to run the host read from the ahb buffer in parallel to the serial flash read into the ahb buffer. 30.5.3.4 byte ordering of serial flash data table 30-45 below gives the byte ordering scheme how the byte oriented data space of the serial flash device is mapped into the data space of the external serial flash. this scheme is valid for all read and write operations. refer to the individual register descriptions for deta ils like misaligned or part ial accesses to the quadspi address space representing serial flash read data. table 30-45. byte ordering of serial flash data in the quadspi module serial flash byte address [1:0] 00 01 10 11 quadspi register bi t position [31:0] (32 bit data width) [7:0] [15:8] [23:16] [31:24] example data 0x0123_4567 0x01 0x23 0x45 0x67
pxd10 microcontroller reference manual, rev. 1 30-60 freescale semiconductor preliminary?subject to change without notice 30.5.3.5 serial flash mode interrupt and dma requests in serial flash mode the quadspi has 8 different fl ags that can only generate interrupt requests and one flag that can generate interr upt as well as dma requests. table 30-46 lists the eight conditions. note that the flags mentioned in the table relate to the serial flash mode flag register (qspi_sfmfr). each condition has a flag bit in the serial flash mode flag register (qspi_sfmfr) and a request enable bit in the sfm interrupt and dma request select a nd enable register (qspi_ sfmrser). the rx buffer drain flag (rbdf) has separate enable bits for ge nerating irq and dma requests. note that not each single flag is represented by an individual irq line. 30.5.3.5.1 transmit buff er fill interrupt request the transmit buffer fill irq indica tes that the tx buffer can accept new data. it is asserted if the qspi_sfmfr[tbff] flag is assert ed and if the corresponding enable bit (qsip_sfmrser[tbfie]) is set. refer to section 30.5.3.6, tx buffer operation ? for details about the assertion of the qspi_sfmfr[tbff] flag. 30.5.3.5.2 receive buffer dr ain interrupt or dma request the receive buffer drain irq derive d from the qspi_sfmfr[rbdf] flag indicates that the rx buffer of the quadspi module has data available from the serial flash device to be read by the host. it remains set as long as the rx buffer is not empty. the qspi _sfmrser[rbdie] bit enables the related irq.aside from the irq it is possible to handle rx buffer drain by dma. if the qspi_sfmrser[rbdde] bit is set each write of the module into the rx buffer triggers a dma reque st. the application must set the environment appropriately (for example, th e dma controller) for the dma transfers. 30.5.3.5.3 buffer overflow/ underrun interrupt request the buffer overflow/underrun irq is a combinati on of the following flags (all located in the qspi_spifr register with the related enab le bits in the qspi_spirser register): table 30-46. serial flash mode interrupt and dma request conditions condition flag (qspi_spisr) dma tx buffer fill tbff tx buffer underrun tbuf rx buffer drain rbdf x rx buffer overflow rbof ahb buffer overflow abof ip command trigger during ahb access error ipaef ip command trigger during ip access ipief instruction code error icef transaction finished tff
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-61 preliminary?subject to change without notice ? tbuf - tx buffer underrun, enabled by tbu_ie ? rbof - rx buffer overflow, enabled by rbo_ie ? abof - ahb buffer overflow, enabled by abo_ie the transmit buffer underrun indicates that an under run condition in the tx buff er has occurred. it is generated when the tx buffer is empty, a tran sfer to the serial flash is initiated and the qspi_spirser[tfuf_ie] bit is set. the receive buffer overflow indicates that an overf low condition in the rx buffer has occurred. it is generated when the rx buffer is full, an additional read transfer attempts to write into the rx buffer and the qspi_sfmrser[rbo_ie] bit is set. the ahb buffer overflow indicates that an overflow condition in the ahb buffer has occurred. it is generated when the ahb buffer is fu ll, an additional read transfer atte mpts to write into the ahb buffer and the qspi_sfmrser[abo_ie] bit is set. the data from the transfers that generated the individual overflow conditions are ignored. 30.5.3.5.4 serial flash communi cation error interrupt request the ipaef, ipief or icef flags in the qspi_sfmsr and the related interrupt enable bits in the qspi_sfmrser determine the asserti on of the sfmerrirq interrupt line. 30.5.3.5.5 transaction fi nished interrupt request the transaction finished irq indicates the comple tion of the current command. it is masked by the qspi_sfmsr[tf_ie] bit. 30.5.3.6 tx buffer operation the tx buffer provides the data used for page programming. for prope r operation it is re quired to provide at least one entry in the tx buffer prior to starting the execution of the page programming command. the application must ensure that the required number of da ta bytes is written into the tx buffer fast enough as long as the command is executed wi thout a tx buffer overflow or underrun. the quadspi module sets the qspi_sfmfr[tbff] fl ag initially when ente ring the sfm mode and subsequently as long as the tx buffer ca n accept more data to be written into. when the quadspi module tries to pull data out of an empty tx buffer the tx buffer underrun is signalled by the qspi_sfmfr[tbuf] flag and th e current instruction is terminated without further write access to the serial flash and consequently no further assertions of the qs pi_sfmfr[tbff] flag. the tx buffer overflow isn?t signalled explicitly, bu t the tx buffer fill level can be monitored by the qspi_tbsr[trbfl] field. refer to section 30.4.3.16, tx buffer stat us register (qspi_tbsr) ? and section 30.4.3.20, serial flash mode flag register (qspi_sfmfr) ? for details about the tx buff er related registers and to section 30.5.3.5.1, transmit buffer fill interrupt request ? for details about the us age of the associated interrupt.
pxd10 microcontroller reference manual, rev. 1 30-62 freescale semiconductor preliminary?subject to change without notice 30.5.4 power saving features the quadspi supports three power-saving strategies: ? stop mode ? module disable mode - clock ga ting of non-memory mapped logic ? clock gating of slave bus signals and clock to memory-mapped logic like all power saving features th e stop mode requires logic external to the quadspi module for power management and clock gating control. figure 30-35 shows an example on how the quadspi power saving features can be used: figure 30-35. quadspi module with power management block 30.5.4.1 stop mode the quadspi supports the global signal stop mode protocolusing the ipg_stop -> ipg_stop_ack handshake. by default the i pg_stop_ack signal is de-ass erted. when a request is made to enter stop mode, the quadspi block acknowledges the re quest by asserting ipg_st op_ack when it is rea dy to have its clocks shut off. depending from the mode of operation the following conditions must be met for the assertion of ipg_stop_ack: ? if a serial transfer is in pr ogress in one of the spi modes th e quadspi waits until it reaches the frame boundary before a sserting ipg_stop_ack. ? if a sfm command is currently executed in sfm mode the assertion of the ipg_stop_ack is postponed until this command is finished. system clock ipg_clk ipg_stop ipg_enable_clk d q ips_module_en ips_addr, ips_byte_en, ips_rwb, ips_wdata ipg_stop_ack power management ipg_clk_s ipg_doze block non-memory mapped area memory mapped area quadspi power saving logic doze mdis & & & & & & &
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-63 preliminary?subject to change without notice while the clocks are shut off, th e quadspi memory-mapped logic is not accessible. the states of the interrupt and dma request signals ca nnot be changed while in stop mode. note that the following actions are illegal in sfm mode during the time starting with raising the request to enter stop mode and ending with leaving the stop mode: ? issue a new sfm command ? issue a new ahb request 30.5.4.2 module disable mode module disable mode is a block-specific mode that the quadspi can enter to save power. there are two possibilities to request ente ring the module disable mode: ? host software can initiate the module disable mode by writing a ?1? to the mdis bit in the qspi_mcr. ? the module disable mode can al so be initiated by hardware. a power management block can initiate module disable mode by asserting the ipg_doze signal while the doze bit in the qspi_mcr is asserted. when a request is encountered to enter the module disable mode the quadspi negates ipg_enable_clk when it is ready to enter the m odule disable mode. dependi ng from the mode of op eration the following conditions must be met for the negation of ipg_enable_clk: ? if a serial transfer is in pr ogress in one of the spi modes th e quadspi waits until it reaches the frame boundary before negating ipg_enable_clk. ? if a sfm command is currently executed in sfm mode the negation of ipg_enable_clk is postponed until this command is finished. note that there is only a limited possibility to read back whether the quadspi block is waiting for the completion of these conditions or whether it has al ready negated the ipg_enabl e_clk. the host software can read the qspi_sfmsr[busy] bit to check for pending execution of a sfm command, but there is no possibility to check pe nding dma or cpu read re quests on the ahb buffer. if implemented, the ipg_enable_cl k signal can stop the clock to th e non-memory mapped logic. when ipg_enable_clk is negated, the quadsp i is in a dormant state, but the memory mapped registers are still accessible. certain read or write operations have a different effect when the quadspi is in the module disable mode. clearing either of th e fifos will not have any effect in the module disable mode. in the module disable mode, all status bits and register flags in th e quadspi will return th e correct values when read, but writing to them will ha ve no effect. writing to the qspi_tcr during module disable mode will not have any effect. interrupt a nd dma request signals cannot be cl eared while in the module disable mode. it is not allowed to write to th e fifo registers in this mode. note that the following actions are illegal in sfm mode during the time starting with raising the request to enter module disable mode and ending with leaving the module disable mode: ? issue a new sfm command ? issue a new ahb request
pxd10 microcontroller reference manual, rev. 1 30-64 freescale semiconductor preliminary?subject to change without notice 30.5.4.3 leaving power saving modes in the stop mode and the module disable mode the cl ocks to the quadspi module are switched off by external circuitry. note that after the quadspi modul e has left these power savi ng modes and has returned to normal operation in sfm mode the execution of th e first sfm command is deferred until the clock to drive that part of the module related to the serial flash device is available. depending from the point in time when the first sfm command is programmed the actual execution of that comm and will start with a slight delay w.r.t. the re-enabling of the clock signal. 30.5.4.4 slave bus signal gating the quadspi?s module enable signal is used to gate slave bus signals such as address, byte enable, read/write and data. this prevents toggling slave bus signals from propagat ing through parts of the quadspi?s combinational logic and consuming power unless it is a quadspi access. the module enable signal can also be used to gate the cl ock (ipg_clk_s) to the memory-mapped logic. 30.6 initialization/application information 30.6.1 how to change qu eues - spi modes only this section presents an example of how to change queues for the quad spi. the queues are not part of the quadspi, but the quadspi includes features in suppor t of queue management. queues are supported in both spi modes. 1. only the last command word fr om a queue is execute d. the eoq bit in the command word is set to indicate to the quadspi that this is the last entry in the queue. 2. at the end of the tran sfer, corresponding to the command word with eoq set is sampled, the eoq flag (eoqf) in the qspi_spisr is set. 3. the setting of the eoqf flag wi ll disable both serial transmissi on, and serial reception of data, putting the quadspi in the stoppe d state. the txrxs bit is nega ted to indicate the stopped state. 4. the dma will continue to fill tx fifo until it is full or step 5 occurs. 5. disable quadspi dma transfer s by disabling the dma enable request for the dma channel assigned to tx fifo and rx fifo. this is done by clearing the corresponding dma enable request bits in the dma controller. 6. ensure all received data in rx fifo has been transferred to me mory receive queue by reading the rxcnt in qspi_spisr or by checking rfdf in th e qspi_spisr after each read operation of the qspi_popr. 7. modify dma descriptor of tx and rx channels for ?new? queues 8. flush tx fifo by writing a ?1? to the clr_tx f bit in the qspi_mcr, flush rx fifo by writing a ?1? to the clr_rxf bit in the qspi_mcr. 9. clear transfer count eith er by setting ctcnt bit in the command word of the first entry in the new queue or via cpu writing directly to spi_tcnt field in the qspi_tcr.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-65 preliminary?subject to change without notice 10. enable dma channel by enabling the dma enable request for th e dma channel assigned to the quadspi tx fifo, and rx fifo by setting the corresponding dma set enable request bit. 11. enable serial transmission and serial reception of data by clearing the eoqf bit. 30.6.2 baud rate sett ings - spi modes only table 30-47 shows the baud rate that is ge nerated based on the combination of the baud rate prescaler pbr and the baud rate scaler br in th e qspi_ctar registers. the values calculated cover the most usual bus frequencies. they assume that the double baud rate dbr bit is clear . note that they are rounded appropriately. 30.6.3 delay settings - spi modes only table 30-48 shows the values for the delay after transfer (t dt ) and cs to sck delay (t csc ) that can be generated based on the prescaler values and the scaler values set in th e qspi_ctar registers. the values reflect the bus frequencies most commonly used, they are rounded appropriately. table 30-47. baud rate values bus clock 64 mhz bus clock 100 mhz baud rate divider prescaler values baud rate divider prescaler values 23572357 baud rate scaler values 2 16 m 10.7 m 6.4 m 4.57 m 25.0 m 16.7 m 10.0 m 7.14 m 4 8 m 5.33 m 3.2 m 2.29 m 12.5 m 8.33 m 5.00 m 3.57 m 6 5.33 m 3.56 m 2.13 m 1.52 m 8.33 m 5.56 m 3.33 m 2.38 m 8 4 m 2.67 m 1.6 m 1.14 m 6.25 m 4.17 m 2.50 m 1.79 m 16 2 m 1.33 m 800 k 571.4 k 3.12 m 2.08 m 1.25 m 893 k 32 1 m 666.7 k 400 k 285.7 k 1.56 m 1.04 m 625 k 446 k 64 500 k 333.3 k 200 k 142.9 k 781 k 521 k 312 k 223 k 128 250 k 166.7 k 100 k 71.4 k 391 k 260 k 156 k 112 k 256 125 k 83.3 k 50 k 35.7 k 195 k 130 k 78.1 k 55.8 k 512 62.5 k 41.7 k 25 k 19.9 k 97.7 k 65.1 k 39.1 k 27.9 k 1024 31.3 k 20.8 k 12.5 k 8.9 k 48.8 k 32.6 k 19.5 k 14.0 k 2048 15.6 k 10.4 k 6.3 k 4.5 k 24.4 k 16.3 k 9.77 k 6.98 k 4096 7.8 k 5.2 k 3.1 k 2.2 k 12.2 k 8.14 k 4.88 k 3.49 k 8192 3.9k 2.6k 1.6k 1.1k 6.10k 4.07k 2.44k 1.74k 16384 2.0 k 1.3 k 781 558 3.05 k 2.04 k 1.22 k 872 32768 977 651 391 279 1.53 k 1.02 k 610 436
pxd10 microcontroller reference manual, rev. 1 30-66 freescale semiconductor preliminary?subject to change without notice 30.6.4 oak family compatibility with the quadspi - spi modes only table 30-49 shows the translation of commands writte n to the tx fifo command halfword with commands written to the command ra m of the oak family qspi. the ta ble illustrates how to configure the qspi_ctar registers to match the default cases for the possible combinations of the oak family control bits in its command ram. the defaults fo r the oak family are base d on a system clock of 40mhz. all delay variables be low will generate the same delay, or as close a possible, from the quadspi 100mhz system clock that an oak fa mily part would generate from its 40mhz system clock. for other system clock frequenc ies, the customer can recompute the values using delay settings - spi modes only. ? for bitse = 0 ? 8 bits per transfer ? for dt = 0 ? 0.425 ? s delay: for this value, the closest value in the quadspi is 0.480 ? s ? for dsck = 0 ? 1/2 sck period: for this value, the value for the quadspi is 20ns table 30-48. delay values bus clock 64 mhz bus clock 100 mhz delay prescaler values delay prescaler values 13571357 delay scaler values 2 31.25 ns 93.75 ns 156.25 ns 218.7 5 ns 20.0 ns 60.0 ns 100.0 ns 140.0 ns 4 62.5 ns 187.5 ns 312.5 ns 437.5 ns 40.0 ns 120.0 ns 200.0 ns 280.0 ns 8 125 ns 375 ns 625 ns 875 ns 80.0 ns 240.0 ns 400.0 ns 560.0 ns 16 250 ns 750 ns 1.25 ? s1.75 ? s 160.0 ns 480.0 ns 800.0 ns 1.1 ? s 32 500 ns 1.5 ? s2.5 ? s3.5 ? s 320.0 ns 960.0 ns 1.6 ? s2.2 ? s 64 1 ? s3 ? s5 ? s7 ? s 640.0 ns 1.9 ? s3.2 ? s4.5 ? s 128 2 ? s6 ? s10 ? s14 ? s1.3 ? s3.8 ? s6.4 ? s9.0 ? s 256 4 ? s12 ? s20 ? s28 ? s2.6 ? s7.7 ? s12.8 ? s 17.9 ? s 512 8 ? s24 ? s40 ? s56 ? s5.1 ? s15.4 ? s25.6 ? s 35.8 ? s 1024 16 ? s48 ? s80 ? s 112 ? s10.2 ? s30.7 ? s51.2 ? s 71.7 ? s 2048 32 ? s96 ? s160 ? s 224 ? s20.5 ? s61.4 ? s 102.4 ? s143.4 ? s 4096 64 ? s192 ? s320 ? s 448 ? s41.0 ? s 122.9 ? s 204.8 ? s286.7 ? s 8192 128 ? s384 ? s640 ? s 896 ? s81.9 ? s 245.8 ? s 409.6 ? s573.4 ? s 16384 256 ? s768 ? s 1.28 ms 1.8 ms 163.8 ? s 491.5 ? s 819.2 ? s1.1ms 32768 512 ? s 1.5 ms 2.6 ms 3.6 ms 327.7 ? s 983.0 ? s1.6ms 2.3ms 65536 1 ms 3.1 ms 5.1 ms 7.2 ms 655.4 ? s 2.0 ms 3.3 ms 4.6 ms
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-67 preliminary?subject to change without notice 30.6.5 calculation of fifo pointer addresses - spi modes only the user has complete visibility of the tx and rx fifo contents th rough the fifo registers, and valid entries can be identified through a memory mapped pointer and a memory mapped counter for each fifo. the pointer to the first-in entry in each fifo is me mory mapped. for the tx fifo the first-in pointer is the transmit next pointer (txnxtptr). for the rx fi fo the first-in pointer is the pop next pointer (popnxtptr). figure 30-36 illustrates the concept of first-in and last-in fifo entries along with the fifo counter. the tx fifo is chosen for the illust ration, but the concepts carry over to the rx fifo. see section 30.5.2.5, transmit firs t in first out (tx fifo ) buffering mechanism ,? and section 30.5.2.6, receive first in first out (rx fifo) buffering mechanism ,? for details on the fifo operation. table 30-49. oak family quadspi compatibility with the quadspi oak family control bits quadspi corresponding control bits corresponding qspi_ctar register setting bits e ctas[0 ] dt ctas[1 ] dsck ctas[2 ] qspi_ctar x fmsz pdt dt pcssc k cssck 0 0 0 0 1111 10 0011 00 0000 0 0 1 1 1111 10 0011 user user 0 1 0 2 1111 user 1 1 selected by user user 00 0000 0 1 1 3 1111 user user user user 1 0 0 4 user 10 0011 00 0000 1 0 1 5 user 10 0011 user user 1 1 0 6 user user user 00 0000 1 1 1 7 user user user user user
pxd10 microcontroller reference manual, rev. 1 30-68 freescale semiconductor preliminary?subject to change without notice figure 30-36. tx fifo pointers and counter 30.6.5.1 address calculation for the firs t-in entry and last-i n entry in the tx fifo the memory address of the first-in entry in th e tx fifo is computed by the following equation: eqn. 30-7 the memory address of the last-in entry in the tx fifo is computed by the following equation: eqn. 30-8 tx fifo base - base address of tx fifo txctr - tx fifo counter txnxtptr - transmit next pointer tx fifo depth - implementation specific 30.6.5.2 address calculation for the firs t-in entry and last-i n entry in the rx fifo the memory address of the first-in entry in th e rx fifo is computed by the following equation: eqn. 30-9 the memory address of the last-in entry in th e rx fifo is computed by the following equation: eqn. 30-10 rx fifo base - base address of rx fifo - - entry a (first in) entry b entry c entry d (last in) - - push tx fifo register transmit next data pointer shift register so +1 -1 tx fifo counter tx fifo base first-in entry address tx fifo base 4 txnxtptr ? ?? + = last-in entry address tx fifo base 4 modulo tx fifo depth txctr txnxtptr 1 ? + ?? ? + = first-in entry address rx fifo base 4 popnxtptr ? ?? + = last-in entry address rx fifo base 4 modulo rx fifo depth rxctr popnxtptr 1 ? + ?? ? + =
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-69 preliminary?subject to change without notice rxctr - rx fifo counter popnxtptr - pop next pointer rx fifo depth - im plementation specific 30.6.6 available status/flag in formation - sfm mode only this paragraph gives an overview over the different status and flag info rmation in the sfm mode and their interdependencies for different use cases. related registers are qspi_sfmsr and qspi_sfmfr. refer to the related descriptions how to set up the quadspi module appropriately. 30.6.6.1 ip bus related commands refer to section 30.4.3.12, instruction code register (qspi_icr) ? for additional details not explicitly covered in this paragraph. 30.6.6.1.1 ip bus related co mmands - normal operation writing the qspi_icr[ic] field triggers the executi on of a new command. given that this is a legal command the qspi_sfmsr[ipacc] a nd the qspi_sfmsr[busy] bits are asserted simultaneously immediately after the execution is started. when the instruction on the serial flash device has been finished these bits are de-asserted and the qspi_sfmfr[tff] flag is set. 30.6.6.1.2 ip bus related co mmands - error situations refer to table 30-50 below. 30.6.6.2 ahb bus related commands refer to section 30.5.3.3.1, reading serial flas h data into the quadspi module ? for additional details not explicitly covered in this paragraph. 30.6.6.2.1 ahb bus related co mmands - normal operation memory mapped read access to a serial flash address not covered in the ahb buffer triggers the execution of an ahb command. given that this is a le gal command the qspi_sfmsr[ahbacc] and the qspi_sfmsr[busy] bits are asserted simultaneous ly immediately after th e execution is started. when the instruction on the serial flash device has been finished these bits are de-asserted and the qspi_sfmfr[tff] flag is set. 30.6.6.2.2 ip bus related co mmands - error situations refer to table 30-50 below.
pxd10 microcontroller reference manual, rev. 1 30-70 freescale semiconductor preliminary?subject to change without notice 30.6.6.3 overview of error flags table 30-50 below gives an overview of the different er ror flags in the qspi_sfmfr register and additional error-related details. note that only the buffer related errors are related to a transaction on the external serial fl ash. all the other errors do not trigger an actual transaction. 30.6.6.4 ip bus and ahb a ccess command collisions there are two flags related to this topic, the qspi_sfmfr[ipaef] and qspi_sfmfr[ipief]. refer to section 30.5.3.3.1, reading serial flash data into the quadspi module ? for a description of the flags itself and to section 30.6.7, command arb itration - sfm mode only ? for details about possible command collisions. 30.6.7 command arbitration - sfm mode only in case of coinciding or overlapping commands the arbi tration scheme is as follows: during the execution of an ip bus related command the running command can?t be terminated by issuing another ip bus or ahb table 30-50. overview of qspi_sfmfr error flags error category error flag in qspi_sfmfr command execution on serial flash device tff behavior description command arbitration errors ipief no ? tff not asserted in conjunction with that command ? ip command already running, another ip command could not be executed. ? ip command already running, write attempt to qspi_icr register. ? ip command already running, write attempt to qspi_sfar register. ipaef ? ahb command already running, another ip command could not be executed. ? ahb command already running, write attempt to qspi_icr[ic] field. instruction code error icef no ? tff not asserted in conjunction with that command ? instruction code error or mode bit collision 1 1 refer to section 30.4.3.19, serial flash mode status register (qspi_sfmsr) sfmsr[contmode] for the description of a mode bit collision buffer related errors rbof yes ? tff is asserted on completion ? rx buffer overrun tbuf ? tx buffer underrun abof ? ahb buffer overrun
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-71 preliminary?subject to change without notice bus related command. the qspi_sfmfr[ipi ef] flag is asserted when the host tries to trigger an ip bus related command. when the host triggers an ahb bus related command (refer to section 30.5.3.3.1, reading serial flash data into the quadspi module ? for details) this command is stalled until the currently running ip bus rela ted command is finished. during the execution of an ahb bus related comm and the running command can?t be terminated by issuing an ip bus related command. the command is ignored and the qspi_sfmfr[ipaef] flag is asserted. refer to section 30.4.3.20, serial flash mode flag register (qspi_sfmfr) ? for the description of these flags. when another ahb bus related command is trigge red the address of the memory mapped access is considered. if the requested address is currently read from the serial flash device the running command is continued. if this is not the case the currently running command is terminat ed and another ahb bus related command related to the requested addre ss is executed. refer to section 30.5.3.3.1, reading serial flash data into the quadspi module ? for further details. the commands ignored in case of command collision will not re sult in the assertion of the qspi_sfmfr[tff] flag. it?s up to the application to watch the error flags provided to assign the assertions of the tff flag to the appropriate commands. 30.6.8 dma usage for the complete description of the dma module refer to the related chapter. in this paragraph only the details specific to the dma usage rela ted to the quadspi module are given. 30.6.8.1 dma usage in spi slave mode 30.6.8.1.1 dma setup in spi slave mode when using the dma in the spi slave mode the standa rd ip dma interface protoc ol is used. for proper operation the dma controller must be set up in the following way: ? size of the source minor loop must be set to 2, corresponding to the width of the qspi_popr[rxdata] field. ? size of the source major loop must be set to th e number of bytes which ar e expected from the spi master. ? source address must be set to the address of the qspi_popr register. ? source address increment must be set to 0. ? remaining dma controller setup depends from the application. 30.6.8.2 dma usage in sfm mode 30.6.8.2.1 bandwidth consi derations in sfm mode careful consideration of the throughput rate of th e entire chain (serial flash -> ahb bus -> dma controller) involved in the read data process is essential fo r proper operation. such an alysis must take into
pxd10 microcontroller reference manual, rev. 1 30-72 freescale semiconductor preliminary?subject to change without notice account not only the datarate provided by the serial fl ash but also the datarate of the ahb bus and the performance of the dma controller in reading data from the rx buffer. depending from the clock fr equency of the serial flash and from the clock frequency of the ahb bus it may be that the serial flash read bandwidth is higher th an the data are read out fr om the rx buffer. if this is the case the rx buffer will be fi lled up continuously. the limiting factor is the number of bytes read out from the serial flash, this read out must be finished before the rx buff er is forced in the overrun condition. this is illustrated in the examples belo w, the common setup for both of them is: ? ahb bus clock frequency 64 mhz ? rx buffer read rate (two successive reads of the rx buffer by dma) 11 cycles ? serial flash clock identical to ahb bus clock (64 mhz) ? no other dma transfers slowing down the dm a channel assigned to the quadspi module ? 14 out of the 15 entries in the rx buffer available fo r actual buffering from table 30-51 above it can be seen that despite the a ssumed undisturbed dma transfers the transfer length is limited to e.g. 16 words wh en reading the serial fl ash in quad i/o mode. ca reful analysis of the dma usage in the entire device c ontaining the quadspi m odule is required to a void rx buffer overrun. it is highly recommended to enable the interrupt a ssociated with the qspi_sfm fr[rbof] to notice this overrun condition. when running the serial flash in dual i/o mode the rx buffer read rate is higher than the data from the serial flash are written to the rx buffer so the rx buffer overrun can only happe n if the dma channel of the quadspi is stalled for more than (16 * 14) = 224 cycles in sequence or if the average dma transfer rate is lengthened from 11 cycles to more than 16 cycles. 30.7 serial flash devices currently flash memory devices with serial flash bus are developed by several vendors. most standard commands currently have the same in struction code for all vendors, so me commands are however unique for one vendor. the currently supported list of instruction codes and the required instruction code options are provided in this chapter. table 30-51. dma example in sfm mode fast read dual i/o fast read quad i/o number of cycles to read 4 bytes from serial flash 16 8 number of cycles to tran sfer 4 bytes via dma 11 number of bytes available for buffering (14 * 4) 56 number of cycles to fill up available buffer n/a 3 ? (14 ? 4) = 168 number of 4 byte words read from serial flash in that time n/a 168 / 8 = 21
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-73 preliminary?subject to change without notice 30.7.1 supported instructio n codes in winbond devices table 30-52. winbond instruction codes command instruction code required input data / parameters output data options qspi_icr[[ico] address [qspi_sfad] data [tx buffer] status / data [rx buffer] write enable 06h write disable 04h read status reg1 05h size s7 - s0 [8] read status reg2 35h size s15 - s8 [8] write status reg 01h size s15 - s0 page program 02h size a23 - a0 [24] size * (d7 - d0) 1 quad page program 32h size a23 - a0 [24] size * (d7 - d0) 32k block erase 52h a23 - a0 [24] 64k block erase d8h a23 - a0 [24] sector erase 20h a23 - a0 [24] chip erase c7h / 60h erase suspend 75h erase resume 7ah power down b9h high performance mode a3h read data 03h 2 size a23 - a0 [24] size * (d7 - d0) 1 fast read 0bh size a23 - a0 [24] size * (d7 - d0) fast read dual output 3bh size a23 - a0 [24] size * (d7 - d0) fast read dual i/o bbh m7 - m0, size a23 - a0 [24] size * (d7 - d0) fast read quad output 6bh size a23 - a0 [24] size * (d7 - d0) fast read quad i/o ebh m7 - m0, size a23 - a0 [24] size * (d7 - d0) octal word read quad i/o e3h m7 - m0, size a23 - a0 [24] size * (d7 - d0) (continuos read) mode bit reset ffh (ffh), size release powerdown/highperf.mode (optional): read device id abh (opt.): read size (opt.): id7 - id0 read manufacturer/device id 90h size a23 - a0 [24] = 0h / 1h manid7 - manid 0, devid7 - dev0
pxd10 microcontroller reference manual, rev. 1 30-74 freescale semiconductor preliminary?subject to change without notice the following table shows only the upper 3 bytes of re gister qspi_icr, byte 0 contains the instruction code . all sizes in byte 2 are interpreted as the number of bytes, the number of sclk clocks required in the transaction will be calculated by multiplying with 8 and divi ding by number of data lines. read unique id 4bh size uniqid63 - uniqi d0 read jedec id 9fh size manid7 - manid 0, memid7 - mem0, capid7 - capid0 1 denotes that size-times one byte is transferred on the se rial flash data bus. total number of bytes must be pro- vided in the tx buffer or can be read from the rx buffer 2 according to winbond documentation this command only supports a maximum clock speed of 50 mhz. if the serial flash is operated at a higher clock frequency, the clock frequency for this command must be decreased. refer to section 30.7.2, serial flash clock frequency limitations for details. table 30-53. instruction code options on winbond devices instruction code byte 3 byte 2 byte 1 76543210765432107654321 0 01h size 02h size (bytes to be written) 05h size 32h size (bytes to be written) 35h size 03h size (bytes to be read) 0bh size (bytes to be read) 3bh size (bytes to be read) bbh size (bytes to be read) m7 - m0 6bh size (bytes to be read) e3h size (bytes to be read) m7 - m0 ebh size (bytes to be read) m7 - m0 abh read 1 90h size 4bh size (bytes) table 30-52. winbond instruction codes command instruction code required input data / parameters output data options qspi_icr[[ico] address [qspi_sfad] data [tx buffer] status / data [rx buffer]
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-75 preliminary?subject to change without notice 30.7.2 serial flash clock frequency limitations certain commands of the winbond serial flash devices are limited in the frequenc y applied to the serial flash device on command execution. to allow for hi gher clock speeds for the remaining commands the serial flash device clock can be divided by 2 (hal f speed) when executing such a command limited in frequency by setting the qspi_s mpr[hsena] bit. refer to table 30-52 for the commands affected. 30.8 internal sampling of serial flash input data depending from the actual implemen tation there is a delay between the internal clocking in the quadspi module and the external serial flash device. this means that the incoming data from the serial flash appear this delay later in time at the quadspi sampling logic w.r.t. internal re ference clock. refer to figure 30-37 for an overview of this scheme. figure 30-37. serial flash sampling clock overview note the arrival of the serial flash data in the sampling stage of the quadspi module are given in fig figure 30-38 below. note that the amount of the total delay t del,total is very specific to the characteristics of the actual implementation. 9fh size ffh size opt. ffh 2 1 ?read? bit controls if 8 sclk clocks are added to read the device id, equivalent to size = 1 (1byte to read) 2 to reset continuous read mode while in dual i/o operation s, set size to ?1? and byte 1 to ffh (icr = 0001ffffh). to reset the continuous read mode while in quad i/ o operations, only instruction ffh is required (icr = 000000ffh). table 30-53. instruction code options on winbond devices (continued) instruction code byte 3 byte 2 byte 1 76543210765432107654321 0 quadspi sck - serial flash clock sfm sampling sfm clock gen serial flash data out clock si_io[0:3] - serial flash data 1 2 3 4 5
pxd10 microcontroller reference manual, rev. 1 30-76 freescale semiconductor preliminary?subject to change without notice note also that the serial flash devi ce clock sck is inverted w.r.t. the quadspi internal reference clock. figure 30-38. serial flash sampling clock timing the rising edge of the internal refere nce clock is taken as timing referen ce for the data output of the serial flash. after a time of t del,total the data arrive at the internal sampling stage of the quadspi module. according to figure 30-37 the following parts of the delay chain contribute to t del,total : 1. output delay of the serial flash clock out put of the device containing the quadspi module 2. wire delay of applicat ion/pcb from the device containing th e quadspi module to the external serial flash device 3. clock to data out delay of the external seri al flash device, including input and output delays 4. wire delay of applicati on/pcb from the external serial flash device to the devi ce containing the quadspi module 5. input delay belonging to the data in input the possible points in time for th e sampling of the incoming data ar e denoted as n/1, i/1, n/2 and i/2 above. the sampling point relevant for the internal sampling is configured in the qspi_smpr register, refer to section 30.4.3.13, sampling register (qspi_smpr) ? for details. note that the falling edges of the reference clock are not actually use d, instead the inverted clock is us ed for sampling at these positions. table 30-54 below gives an overview of th e available configura tions for the commands running at regular (full) speed: internal ref clock serial flash data internal reference for serial flash data sampling t del,total n/1 n/2 i/1 i/2 possible sampling points sck - serial flash clock
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 30-77 preliminary?subject to change without notice depending from the actual delay a nd the serial flash clock frequency the appropriate sampling point can be chosen. the following remarks should be consid ered when selecting the appropriate setting: ? theoretically there should be 2 se ttings possible to capture the corr ect data since the serial flash output is valid for 1 clock cycle, disregarding rise and fall times a nd timing uncertainties. ? depending from the timing uncertainties it may tu rn out in actual applications that only one possible sample positions remains. this is subject to care ful consideration depending from the actual implementation. ? the delay t del,total is an absolute size to shift the point in time when the serial flash date get valid at the quadspi input. ? for decreasing frequency of the se rial flash clock the distance betw een the edges increases. so for large differences in the frequency the required setting may change. ? for commands running at half of the regular serial flash clock (qspi_smpr[hsena] bit set) the sampling point must be figured separately to allo w for the compensation of the absolute shift in time w.r.t. the sample-relative setting in the qspi_spmpr register. table 30-54. sampling configuration sampling point description delay [fsdly] [hsdly] phase [fsphs] [hsphs] qspi_smpr for full speed setting 1 1 x is not considered here n/1 sampling with non-inverted clock, 1 sample delay 0 0 0x0000000x i/1 sampling with inverted clock, 1 sample delay 0 1 0x0000002x n/2 sampling with non-inverted clock, 2 samples delay 1 0 0x0000004x i/2 sampling with inverted clock, 2 samples delay 1 1 0x0000006x
pxd10 microcontroller reference manual, rev. 1 30-78 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 31-1 preliminary?subject to change without notice chapter 31 real-time clock (rtc/api) 31.1 overview the rtc is a free running counter used for time k eeping applications. the rt c may be configured to generate an interrupt at a predefin ed interval independent of the mode of operation (run mode or low power mode). if in a low power mode when the rtc interval is reached, the rtc will first generate a wakeup and then assert the interrupt request. the rtc also supports an autonomous periodic interrupt (api) function used to generate a period ic wakeup request to exit a low power mode or an interrupt request. 31.2 features features of the rtc include: ? 4 selectable counter clock sources ? 4?16 mhz fxosc ? 128 khz sirc ? 32 khz sxosc ? 16 mhz firc ? optional 512 prescaler and optional 32 prescaler ? 32-bit counter ? supports times up to 1.5 mont hs with 1 ms resolution ? runs in all modes of operation ? reset when disabled by software and by por ? 12-bit compare value to support interrupt intervals of 1s up to greater than 1 hr with 1s resolution ? rtc compare value changeable while counter is running ? rtc status and control re gister are reset only by por ? autonomous periodic interrupt (api) ? 10-bit compare value to support wa keup intervals of 1.0 ms to 1 s ? compare value changeable while counter is running ? configurable interrupt for rtc ma tch, api match, and rtc rollover ? configurable wakeup event for rtc match, api match, and rtc rollover
pxd10 microcontroller reference manual, rev. 1 31-2 freescale semiconductor preliminary?subject to change without notice figure 31-1. rtc/api block diagram 0 1 2 clksel[0:1] 3 128 khz sirc 16 mhz firc 32 khz == cnten rtccnt rtcval 10:21 rtcf rtcie rtc interrupt offset reg == 22:31 api wakeup + load 22:31 apival apien reset reset 32-bit counter sync sync rtc wakeup apif apiie api sync interrupt rovrf sync 4-16 mhz div512 div32 div32en div512en rtcie rovren fxosc sxosc
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 31-3 preliminary?subject to change without notice figure 31-2. clock gating for rtc clocks 31.3 device specific information for this device: ? fxosc, sxosc, firc and sirc clocks are provided as counter clocks for the rtc. default clock on reset is sirc divided by 4. ? the rtc will be reset on dest ructive reset, with the excep tion of software watchdog reset. ? the rtc provides a configurable divider by 512 to be optionally used when fxosc source is selected. 31.4 modes of operation there are two functional modes of operation for th e rtc: normal operation and low power mode. in normal operation, all rtc registers can read or writte n and the input isolation is disabled. the rtc/api and associated interrupts ar e optionally enabled. in low power mode, the bus in terface is disabled and the input isolation is enabled. the rtc/api is enabled if enabled prior to entry into low power mode. 32-bit counter cell c.g. en 128 khz sirc (cnten & clksel== 2?b00) cell en 32 khz sxosc (cnten & clksel== 2?b01) cell en 16 mhz firc (cnten & clksel== 2?b10) cell c.g. en 4-16 mhz fxosc (cnten & clksel== 2?b11) c.g. c.g. 0 1 2 clksel[0:1] 3 cell c.g. en 1 0 div 512 cell c.g. en 1 0 div 32 div512en div32en cnten
pxd10 microcontroller reference manual, rev. 1 31-4 freescale semiconductor preliminary?subject to change without notice 31.5 debug support to simplify software development it is possible to temporarily suspend the rtc counter while the mcu is stopped by a debugger. while the mcu is running th e rtc counter runs norma lly. this feature is enabled by setting the rtcc[frz] bit and is only available when the cp u has debug mode active (see the cpu reference manual for more info rmation on debug mode and support). 31.6 register descriptions 31.6.1 rtc supervisor control register (rtcsupv) the rtcsupv register contains the supv bit which de termines whether other re gisters are accessible in supervisor mode or user mode. note rtcsupv register is accessible only in supervisor mode. figure 31-3. rtc supervisor control register (rtcsupv) offset: rtc_base + 0x0000 0 1 2 34567891 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 r sup v w por 1 0 0 00000000000000000000000000000 table 31-1. rtcsupv regist er bit/field descriptions field description 0 supv rtc supervisor bit 0 all registers are accessible in both user as well as supervisor mode. 1 all other registers are accessi ble in supervisor mode only.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 31-5 preliminary?subject to change without notice 31.6.2 rtc control register (rtcc) the rtcc register contains: ? rtc counter enable ? rtc interrupt enable ? rtc clock source select ? rtc compare value ?api enable ? api interrupt enable ? api compare value figure 31-4. rtc control register (rtcc) offset rtc_base + 0x0004 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r cnt en rtci e frz en rovr en rtcval w por0 0 0 0 0 00000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r api en apiie clksel div51 2 en div3 2en apival w por0 0 0 0 0 00000000000 table 31-2. rtcc field descriptions field description cnten counter enable the cnten bit enables the rtc counter. making cnten bit 1?b0 has the effect of asynchronously resetting (synchronous reset negat ion) all the rtc logic. this allows for the rtc configuration and clock source selection to be updated without causing synchronization issues. 1 counter enabled 0 counter disabled rtcie rtc interrupt enable the rtcie bit enables interr upts requests to the system if rtcf is asserted. 1 rtc interrupts enabled 0 rtc interrupts disabled frzen freeze enable bit the counter freezes when the mcu is stopped by a debugger on the last valid count value if the frzen bit is set. after coming of the debug mode counter starts from the frozen value. 0 counter does not freeze in debug mode. 1 counter freezes in debug mode.
pxd10 microcontroller reference manual, rev. 1 31-6 freescale semiconductor preliminary?subject to change without notice rovren counter roll over interrupt enable the rovren bit enables interrupt requests when the rtc has rolled over from 0xffff_ffff to 0x0000_0000. the rtcie bit must also be set in or der to generate an interrupt from a counter rollover. 1 rtc rollover interrupt enabled 0 rtc rollover interrupt disabled rtcval rtc compare value the rtcval bits are compared to bits 10:21 of the rtc counter and if match sets rtcf. rtcval may only be updated when cnten is 0. note: rtcval should not be set to 0. apien autonomous periodic interrupt enable the apien bit enables the autonomous periodic interrupt function. 1 api enabled 0 api disabled apiie api interrupt enable the apiie bit enables interrupts requests to the system if apif is asserted. 1 api interrupts enabled 0 api interrupts disabled clksel clock select the clksel[0:1] bits select the clock source for the rtc. clks el may only be updated when cnten is 0. the user should ensure that oscill ator is enabled before selecting it as a clock source for rtc. 00 32 khz sxosc 01 128 khz sirc 10 16 mhz firc 11 16 mhz fxosc div512en divide by 512 enable the div512en bit enables the 512 clock divi der. div512en may only be updated when cnten is 0. 0 divide by 512 is disabled. 1 divide by 512 is enabled. div32en divide by 32 enable the div32en bit enables the 32 clock divider. div32en may only be updated when cnten is 0. 0 divide by 32 is disabled. 1 divide by 32 is enabled. apival api compare value the apival bits are compared to an offset val ue based on bits 22:31 of the rtc counter and if match asserts an interrupt/wakeup request. apival may only be updated when apien is 0 or api function is undefined. note: api functionality starts only when apival is nonzero. the first api interrupt takes two more cycles because of synchroni zation of apival to the rtc clock. afte r that, interrupts are periodic in nature. the minimum supported value of apival is 4. table 31-2. rtcc field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 31-7 preliminary?subject to change without notice 31.6.3 rtc status register (rtcs) the rtcs register contains: ? rtc interrupt flag ? api interrupt flag ? rollovr flag figure 31-5. rtc status register (rtcs) table 31-3. rtcs field descriptions offset rtc_base + 0x0008 access: user read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r rtc f w w1c por000 0 000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r api f rov rf w w1c w1c por000 0 000000000000 field description 2 rtcf rtc interrupt flag the rtcf bit indicates that the rtc counter has reached the counter value matching rtcval. rtcf is cleared by writing a 1 to rtcf. writing a 0 to rtcf has no effect. 1 rtc interrupt 0 no rtc interrupt note: rtcf is not set if rtcval is 12'b0. 18 apif api interrupt flag the apif bit indicates that the rtc counter has r eached the counter value matching api offset value. apif is cleared by writing a 1 to apif. writing a 0 to apif has no effect. 1 api interrupt 0 no api interrupt note: the periodic interrupt comes after apival[0:9] + 1?b1 rtc counts 21 rovrf counter roll over interrupt flag the rovrf bit indicates that the rtc has rolled over from 0xffff_ffff to 0x0000_0000. rovrf is cleared by writing a 1 to rovrf. 1 rtc has rolled over. 0 rtc has not rolled over.
pxd10 microcontroller reference manual, rev. 1 31-8 freescale semiconductor preliminary?subject to change without notice 31.6.4 rtc counter register (rtccnt) the rtccnt register contains the current value of the rtc counter. 31.7 rtc functional description the rtc consists of a 32-bit free running counter enabled with the rtcc[cnten] bit (cnten when negated asynchronously resets the c ounter and synchronously enables the counter when enabled). the value of the counter may be read via the rtccnt regi ster. note that due to the clock synchronization, the rtccnt value may actually represen t a previous counter value. the di fference between the counter and the read value depends on ratio of counter clock and ipg_c lk. maximum possible di fference between the two is 6 count values. the clock source to the counter is selected with the rtcc[clksel] fi eld, which gives four options for clocking the rtc/api. the four cl ock sources are assumed to be two 16 mhz sour ces, one 32 khz source and one 128 khz source. the output of the clock m ux can be optionally divi ded by combination of 512 and 32 to give a 1 ms rtc/api count period for different clock sources . note that the rtcc[cnten] bit must be disabled when the rt c/api clock source is switched. when the counter value for counte r bits 10:21 match the 12-bit value in the rtcc[rtcval] field, then the rtcs[rtcf] interrupt flag bit is set (after proper clock synchronization). if the rtcc[rtcie] interrupt enable bit is set, then the rtc interrupt request is generate d. the rtc supports interrupt requests in the range of 1s to 40 96s (> 1 hr.) with a 1s resolution. the rtcc[rtcval ] field may only be updated when the rtcc[cnten] bit is cleared to disable the c ounter. if there is a match while in low power mode then the rtc will first generate a wakeup request to force a wakeup to r un mode, then the rtcf flag will be set. rtcc[rtcval]=0x000 is invalid. a rollover interrupt can be generated when the rtc transitions from a count of 0xffff_ffff to 0x0000_0000. the rollover flag is enabled by setting the rtcc[rovren] bit. an interrupt request is generated for an rtc counter rollover when both the rtcc[rovren] and rt cc[rtcie] bits are set. all the flags and counter values ar e synchronized with ipg_clk. it is assumed that ipg_clk frequency is always more than or equal to the rtc_clk used to run the counter. figure 31-6. rtc counter register (rtccnt) offset: rtc_base + 0x000c 012345678910111213141516171819202122232425262728293031 r rtccnt[0:31] w por00000000000000000000000000000000 table 31-4. rtccnt register bit/field descriptions field description 0:31 rtccnt[0:31] rtc counter value due to the clock synchronization, the rtccnt val ue may actually represent a previous counter value.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 31-9 preliminary?subject to change without notice 31.8 api functional description setting rtcc[apien] bit enables the autonomous in terrupt function. the 10-bit rtcc[apival] field selects the time interval for trigge ring an interrupt and/or wakeup ev ent. since the rtc is a free running counter, the apival is added to the current count to calculate an offset. when the counter reaches (offset count + 1), a interrupt and/or wakeup request is generated. then the offset value is recalculated and again retriggers a new request when the new value is reached. apival may onl y be updated when apien is disabled. when a compare is reached, the rtcs[api f] interrupt flag bit is set (after proper clock synchronization). if the rt cc[apiie] interrupt enable bit is set, then the api interrupt request is generated. if there is a match while in low power mode, then the api wi ll first generate a wakeup request to force a wakeup into normal operation, then the apif flag will be set.
pxd10 microcontroller reference manual, rev. 1 31-10 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 32-1 preliminary?subject to change without notice chapter 32 reset generation module (mc_rgm) 32.1 introduction 32.1.1 overview the reset generation module (mc_rgm) centralizes the different rese t sources and manages the reset sequence of the device. it provides a register interface and the reset sequencer . the different registers are available to monitor and control the device reset seque nce. the reset sequencer is a state machine which controls the different phases (phase0, phase1, ph ase2, phase3, and idle) of the reset sequence and control the reset signals generated in the system. figure 32-1 depicts the mc_rgm block diagram.
pxd10 microcontroller reference manual, rev. 1 32-2 freescale semiconductor preliminary?subject to change without notice 32.1.2 features the mc_rgm contains the functiona lity for the following features: ? ?destructive? resets management ? ?functional? resets management ? signalling of reset events after each reset sequence (reset status flags) ? conversion of reset events to safe mode or inte rrupt request events (for further mode details, please see the mc_me chapter) pad[22:21] reset registers platform interface core mc_rgm figure 32-1. mc_rgmblock diagram mc_me power-on 1.2v low-voltage detected (power domain #0) 1.2v low-voltage detected (power domain #1) software watchdog timer 2.7v low-voltage detected jtag initiated reset core reset software reset checkstop reset fmpll0 fail fxosc frequency lower than reference cmu0 clock frequency higher/lower than reference 4.5v low-voltage detected code or data flash fatal error functional reset filter boot mode capture destructive reset filter reset state machine sscm peripherals mc_cgm
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 32-3 preliminary?subject to change without notice ? short reset sequence configuration ? bidirectional reset be havior configuration ? selection of alternate boot via th e backup ram on standby mode exit (for further mode details, please see the mc_me chapter) ? boot mode capture on reset deassertion 32.1.3 modes of operation the different reset sources are organized into two families: ?destructive? and ?functional?. ? a ?destructive? reset source is as sociated with an event related to a critical - usually hardware - error or dysfunction. when a ?destr uctive? reset event occurs, the fu ll reset sequence is applied to the device starting from phase0. th is resets the full device ensu ring a safe start- up state for both digital and analog modules. ?destructive? resets are ? power-on reset ? 1.2v low-voltage detected (power domain #0) ? 1.2v low-voltage detected (power domain #1) ? software watchdog timer ? 2.7v low-voltage detected ? a ?functional? reset source is associated with an event related to a less-critical - usually non-hardware - error or dysfunction. when a ?func tional? reset event occurs, a partial reset sequence is applied to th e device starting from phas e1. in this case, most digital modules are reset normally, while analog modules or specific di gital modules? (e.g. debug modules, flash modules) state is preserved. ?functional? resets are ? external reset ? jtag initiated reset ? core reset ? software reset ? checkstop reset ? fmpll0 fail ? fxosc frequency lower than reference ? cmu0 clock frequency higher/lower than reference ? 4.5v low-voltage detected ? code or data flash fatal error when a reset is triggered, the mc_rgm state mach ine is activated and proceeds through the different phases (i.e. phasen states). each pha se is associated with a particular device reset being provided to the system. a phase is completed when all corresponding phase completion ga tes from either the system or internal to the mc_rgm are acknowledged. the device re set associated with the phase is then released, and the state machine proceeds to the next phase up to entering the idle phase. du ring this entire process, the mc_me state machine is held in reset mode. only at the end of the reset sequence, when the idle phase is reached, does the mc_me enter the drun mode.
pxd10 microcontroller reference manual, rev. 1 32-4 freescale semiconductor preliminary?subject to change without notice alternatively, it is possibl e for software to configure some reset source events to be converted from a reset to either a safe mode request issued to the mc _me or to an interrupt issued to the core (see section 32.3.1.4, destructive event reset disable register (rgm_derd) and section 32.3.1.6, destructive event alternate request register (rgm_dear) for ?destructive? resets and section 32.3.1.3, functional event reset disa ble register (rgm_ferd) and section 32.3.1.5, functiona l event alternate request register (rgm_fear) for ?functional? resets). 32.2 external signal description the mc_rgm interfaces to the bidirectional reset pin reset and the boot mode pins pad[22:21] . 32.3 memory map and register definition note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content ? cause a transfer error table 32-1. mc_rgm register description address name description size access 0xc3fe_4000 rgm_fes functional ev ent status half-word read/write 1 0xc3fe_4002 rgm_des destructive ev ent status half-word read/write 1 1 individual bits cleared on writing ?1? 0xc3fe_4004 rgm_ferd functional event reset disable half-word read/write 2 2 write once: ?0? = disable, ?1? = enable. 0xc3fe_4006 rgm_derd destructive ev ent reset disable half-word read 0xc3fe_4010 rgm_fear functional event al ternate request half-word read/write 0xc3fe_4012 rgm_dear destructive even t alternate request half-word read 0xc3fe_4018 rgm_fess functional event short sequence half-word read/write 0xc3fe_401a rgm_stdby standby reset sequence half-word read/write 0xc3fe_401c rgm_fbre functional bidirect ional reset enable half-word read/write
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 32-5 preliminary?subject to change without notice table 32-2. mc_rgm memory map address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe_4000 rgm_fes / rgm_des r f_exr f_flash f_lvd45 f_cmu0_fhl f_cmu0_olr f_fmpll0 f_chkstop f_soft f_core f_jtag ww1c r f_por f_lvd27 f_swt f_lvd12_pd1 f_lvd12_pd0 ww1c 0xc3fe_4004 rgm_ferd / rgm_derd r d_exr d_flash d_lvd45 d_cmu0_fhl d_cmu0_olr d_fmpll0 d_chkstop d_soft d_core d_jtag w r0 d_lvd27 d_swt d_lvd12_pd1 d_lvd12_pd0 w 0xc3fe_4008 ? 0xc3fe_400c reserved 0xc3fe_4010 rgm_fear / rgm_dear r ar_exr ar_flash ar_lvd45 ar_cmu0_fhl ar_cmu0_olr ar_fmpll0 ar_chkstop ar_soft ar_core ar_jtag w r0 ar_lvd27 ar_swt ar_lvd12_pd1 ar_lvd12_pd0 w 0xc3fe_4014 reserved w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
pxd10 microcontroller reference manual, rev. 1 32-6 freescale semiconductor preliminary?subject to change without notice 32.3.1 register descriptions unless otherwise noted, all registers may be accessed as 32-bit word s, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for ex ample, the rgm_stdby regi ster may be accessed as a word at address 0xc3fe_4018, as a half-word at address 0xc3fe_401a, or as a byte at address 0xc3fe_401b. 0xc3fe_4018 rgm_fess / rgm_stdby r ss_exr ss_flash ss_lvd45 ss_cmu0_fhl ss_cmu0_olr ss_fmpll0 ss_chkstop ss_soft ss_core ss_jtag w r00000000 boot_from_bkp_ram 0000000 w 0xc3fe_401c rgm_fbre r be_exr be_flash be_lvd45 be_cmu0_fhl be_cmu0_olr be_fmpll0 be_chkstop be_soft be_core be_jtag w 0xc3fe_4020 ? 0xc3fe_7ffc reserved table 32-2. mc_rgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 32-7 preliminary?subject to change without notice 32.3.1.1 functional event status register (rgm_fes) this register contains the st atus of the last asserted f unctional reset sources . it can be accessed in read/write on either supervisor mode or test mode . register bits are cleared on write ?1?. address 0xc3fe_4000 access: supervisor read/write 0123456789101112131415 r f_exr f_flash f_lvd45 f_cmu0_fhl f_cmu0_olr f_fmpll0 f_chkstop f_soft f_core f_jtag ww1c por0000000000000000 figure 32-2. functional event status register (rgm_fes) table 32-3. functional event status register (rgm_fes) field descriptions field description f_exr flag for external reset 0 no external reset event has occurred since either the last clear or the last de structive reset assertion 1 an external reset event has occurred f_flash flag for code or data flash fatal error 0 no code or data flash fatal error event has occurred si nce either the last clear or the last destructive reset assertion 1 a code or data flash fatal error event has occurred f_lvd45 flag for 4.5v low-voltage detected 0 no 4.5v low-voltage detected event has occurred since ei ther the last clear or th e last destructive reset assertion 1 a 4.5v low-voltage detected event has occurred f_cmu0_fh l flag for cmu0 clock frequency higher/lower than reference 0 no cmu0 clock frequency higher/lower than reference ev ent has occurred since either the last clear or the last destructive reset assertion 1 a cmu0 clock frequency higher/lower than reference event has occurred f_cmu0_ol r flag for fxosc frequency lower than reference 0 no fxosc frequency lower than reference event has o ccurred since either the last clear or the last destructive reset assertion 1 a fxosc frequency lower than reference event has occurred f_fmpll0 flag for fmpll0 fail 0 no fmpll0 fail event has occurred since either the last clear or the last destructive reset assertion 1 a fmpll0 fail event has occurred f_chkstop flag for checkstop reset 0 no checkstop reset event has occurred since either the last clear or the last de structive reset assertion 1 a checkstop reset event has occurred f_soft flag for software reset 0 no software reset event has occurred since either the last clear or the last destructive reset assertion 1 a software reset event has occurred w1c w1c w1c w1c w1c w1c w1c w1c w1c
pxd10 microcontroller reference manual, rev. 1 32-8 freescale semiconductor preliminary?subject to change without notice 32.3.1.2 destructive event st atus register (rgm_des) this register contains the status of the last asserted destructive re set sources. it can be accessed in read/write on either supervisor mode or test mode. register bits ar e cleared on write ?1?. f_core flag for core reset 0 no core reset event has occurred since either the last clear or the last de structive reset assertion 1 a core reset event has occurred f_jtag flag for jtag initiated reset 0 no jtag initiated reset event has occurred since either the last clear or the last destructive reset assertion 1 a jtag initiated reset event has occurred address 0xc3fe_4002 access: supervisor read/write 0123456789101112131415 r f_por f_lvd27 f_swt f_lvd12_pd1 f_lvd12_pd0 ww1c por1000000000000000 figure 32-3. destructive event status register (rgm_des) table 32-4. destructive event status register (rgm_des) field descriptions field description f_por flag for power-on reset 0 no power-on event has occurred since the last clear (due to either a software clear or a low-voltage detection) 1 a power-on event has occurred f_lvd27 flag for 2.7v low-voltage detected 0 no 2.7v low-voltage detected event has occurred since either the last clear or the last power-on reset assertion 1 a 2.7v low-voltage detected event has occurred f_swt flag for software watchdog timer 0 no software watchdog timer event has occurred since eit her the last clear or the last power-on reset assertion 1 a software watchdog timer event has occurred f_lvd12_p d1 flag for 1.2v low-voltage de tected (power domain #1) 0 no 1.2v low-voltage detected (power domain #1) event has occurred since either the last clear or the last power-on reset assertion 1 a 1.2v low-voltage detected (power domain #1) event has occurred f_lvd12_p d0 flag for 1.2v low-voltage de tected (power domain #0) 0 no 1.2v low-voltage detected (power domain #0) event has occurred since either the last clear or the last power-on reset assertion 1 a 1.2v low-voltage detected (power domain #0) event has occurred table 32-3. functional event status regist er (rgm_fes) field descriptions (continued) field description w1c w1c w1c w1c
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 32-9 preliminary?subject to change without notice note the f_por flag is automatically clear ed on a 1.2v low-voltage detected (power domain #0 or #1) or a 2.7v low-voltage detected (vreg). this means that if the power-up sequence is not monotonic (i.e the voltage rises and then drops enough to tr igger a low-voltage detection), the f_por flag may not be set but instead the f_lvd12_pd0 , f_lvd12_pd1 , or f_lvd27_vreg flag is set on exiting the rese t sequence. therefore, if the f_por, f_lvd12_pd0 , f_lvd12_pd1 , or f_lvd27_vreg flags are set on reset exit, software should interpret the reset cause as power-on. note in contrast to all other reset sources, the 1.2v low- voltage detected (power domain #0) event is captured on its deas sertion. therefore, the status bit f_lvd12_pd0 is also asserted on the reset?s deassertion. in case an alternate event is selecte d, the safe mode or interr upt request are similarly asserted on the reset?s deassertion. 32.3.1.3 functional event reset disable register (rgm_ferd) this register provides dedicated bits to disable functional reset source s.when a functional reset source is disabled, the associated functional ev ent will trigger either a safe mode request or an interrupt request (see section 32.3.1.5, functional event altern ate request register (rgm_fear) ). it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read only in user mode. each byte can be written only on ce after power-on reset. address 0xc3fe_4004 access: supervisor read/write 0123456789101112131415 r d_exr d_flash d_lvd45 d_cmu0_fhl d_cmu0_olr d_fmpll0 d_chkstop d_soft d_core d_jtag w por0000000000000000 figure 32-4. functional event reset disable register (rgm_ferd) table 32-5. functional event reset disable register (rgm_ferd) field descriptions field description d_exr disable external reset 0 an external reset event triggers a reset sequence 1 an external reset event generates a safe mode request d_flash disable code or data flash fatal error 0 a code or data flash fatal error event triggers a reset sequence 1 a code or data flash fatal error event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_flash
pxd10 microcontroller reference manual, rev. 1 32-10 freescale semiconductor preliminary?subject to change without notice d_lvd45 disable 4.5v low-voltage detected 0 a 4.5v low-voltage detected event triggers a reset sequence 1 a 4.5v low-voltage detected event generates eit her a safe mode or an interrupt request depending on the value of rgm_f ear.ar_lvd45 d_cmu0_f hl disable cmu0 clock frequency higher/lower than reference 0 a cmu0 clock frequency higher/lower than reference event triggers a reset sequence 1 a cmu0 clock frequency higher/lower than reference event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_cmu0_fhl d_cmu0_o lr disable fxosc frequency lower than reference 0 a fxosc frequency lower than reference event triggers a reset sequence 1 a fxosc frequency lower than reference event gener ates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_cmu0_olr d_fmpll0 disable fmpll0 fail 0 a fmpll0 fail event triggers a reset sequence 1 a fmpll0 fail event generates either a safe m ode or an interrupt request depending on the value of rgm_fear.ar_fmpll0 d_chksto p disable checkstop reset 0 a checkstop reset event triggers a reset sequence 1 a checkstop reset event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_chkstop d_soft disable software reset 0 a software reset event triggers a reset sequence 1 a software reset event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_soft d_core disable core reset 0 a core reset event triggers a reset sequence 1 a core reset event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_core d_jtag disable jtag initiated reset 0 a jtag initiated reset event triggers a reset sequence 1 a jtag initiated reset event generates either a safe mode or an interrupt request depending on the value of rgm_fear.ar_jtag table 32-5. functional event reset disable register (rgm_ferd) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 32-11 preliminary?subject to change without notice 32.3.1.4 destructive event reset disable register (rgm_derd) this register provides dedicated bits to disable particular destructiv e reset sources. when a destructive reset source is disabled, the associated destructive ev ent will trigger either a safe mode request or an interrupt request (see section 32.3.1.6, destructive event altern ate request regi ster (rgm_dear) ). it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in r ead only in user mode. each byte can be writte n only once after power-on reset. address 0xc3fe_4006 access: supervisor read 0123456789101112131415 r 0 d_lvd27 d_swt d_lvd12_pd1 d_lvd12_pd0 w por0000000000000000 figure 32-5. destructive event reset disable register (rgm_derd) table 32-6. destructive event reset disable register (rgm_derd) field descriptions field description d_lvd27 disable 2.7v low-voltage detected 0 a 2.7v low-voltage detected event triggers a reset sequence 1 a 2.7v low-voltage detected event generates eit her a safe mode or an interrupt request depending on the value of rgm_dear.ar_lvd27 d_swt disable software watchdog timer 0 a software watchdog timer event triggers a reset sequence 1 a software watchdog timer event generates either a safe mode or an interrupt request depending on the value of rgm_dear.ar_swt d_lvd12_p d1 disable 1.2v low-voltage detected (power domain #1) 0 a 1.2v low-voltage detected (power domain #1) event triggers a reset sequence 1 a 1.2v low-voltage detec ted (power domain #1) event generates ei ther a safe mode or an interrupt request depending on the value of rgm_dear.ar_lvd12_pd1 d_lvd12_p d0 disable 1.2v low-voltage detected (power domain #0) 0 a 1.2v low-voltage detected (power domain #0) event triggers a reset sequence 1 a 1.2v low-voltage detec ted (power domain #0) event generates ei ther a safe mode or an interrupt request depending on the value of rgm_dear.ar_lvd12_pd0
pxd10 microcontroller reference manual, rev. 1 32-12 freescale semiconductor preliminary?subject to change without notice 32.3.1.5 functional event alternat e request register (rgm_fear) this register defines an alternat e request to be generated when a reset on a functional event has been disabled. the alternate reque st can be either a safe mode request to mc_me or an interrupt request to the system. it can be accessed in read /write in either supervisor mode or test mode. it can be accessed in read only in user mode. address 0xc3fe_4010 access: supervisor read/write 0123456789101112131415 r ar_exr ar_flash ar_lvd45 ar_cmu0_fhl ar_cmu0_olr ar_fmpll0 ar_chkstop ar_soft ar_core ar_jtag w por0000000000000000 figure 32-6. functional event altern ate request register (rgm_fear) table 32-7. functional event alternate request register (rgm_fear) field descriptions field description ar_exr alternate request for external reset 0 generate a safe mode request on an external reset event if the reset is disabled 1 generate an interrupt request on an external reset event if the reset is disabled ar_flash alternate request for code or data flash fatal error 0 generate a safe mode request on a code or data flash fatal error event if the reset is disabled 1 generate an interrupt request on a code or data flash fatal error event if the reset is disabled ar_lvd45 alternate request for 4.5v low-voltage detected 0 generate a safe mode request on a 4.5v low-volt age detected event if the reset is disabled 1 generate an interrupt request on a 4.5v low-voltage detected event if the reset is disabled ar_cmu0_f hl alternate request for cmu0 clock frequency higher/lower than reference 0 generate a safe mode request on a cmu0 clock frequency higher/lower than reference event if the reset is disabled 1 generate an interrupt request on a cmu0 clock frequen cy higher/lower than reference event if the reset is disabled ar_cmu0_ olr alternate request for fxosc frequency lower than reference 0 generate a safe mode request on a fxosc frequency lower than reference event if the reset is disabled 1 generate an interrupt request on a fxosc frequency lower than reference event if the reset is disabled ar_fmpll0 alternate request for fmpll0 fail 0 generate a safe mode request on a fmpll0 fail event if the reset is disabled 1 generate an interrupt request on a fmpll0 fail event if the reset is disabled ar_chkst op alternate request for checkstop reset 0 generate a safe mode request on a checkstop reset event if the reset is disabled 1 generate an interrupt request on a checkstop reset event if the reset is disabled ar_soft alternate request for software reset 0 generate a safe mode request on a software reset event if the reset is disabled 1 generate an interrupt request on a software reset event if the reset is disabled
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 32-13 preliminary?subject to change without notice 32.3.1.6 destructive ev ent alternate request register (rgm_dear) this register defines an alternate request to be generated when a re set on a destructive event has been disabled. the alternate reque st can be either a safe mode request to mc_me or an interrupt request to the system. it can be accessed in read /write in either supervisor mode or test mode. it can be accessed in read only in user mode. ar_core alternate request for core reset 0 generate a safe mode request on a core reset event if the reset is disabled 1 generate an interrupt request on a core reset event if the reset is disabled ar_jtag alternate request for jtag initiated reset 0 generate a safe mode request on a jtag initiated reset event if the reset is disabled 1 generate an interrupt request on a jtag initiated reset event if the reset is disabled 0123456789101112131415 r 0 ar_lvd27 ar_swt ar_lvd12_pd1 ar_lvd12_pd0 w por0000000000000000 figure 32-7. destructive event alternate request register (rgm_dear) table 32-8. destructive event alternate request register (rgm_dear) field descriptions field description ar_lvd27 alternate request for 2.7v low-voltage detected 0 generate a safe mode request on a 2.7v low-volt age detected event if the reset is disabled 1 generate an interrupt request on a 2.7v low-voltage detected event if the reset is disabled ar_swt alternate request for so ftware watchdog timer 0 generate a safe mode request on a software watchdog timer event if the reset is disabled 1 generate an interrupt request on a software watchdog timer event if the reset is disabled ar_lvd12_ pd1 alternate request for 1.2v low-voltage detected (power domain #1) 0 generate a safe mode request on a 1.2v low-voltage detected (power domain #1) event if the reset is disabled 1 generate an interrupt request on a 1.2v low-voltage de tected (power domain #1) event if the reset is disabled ar_lvd12_ pd0 alternate request for 1.2v low-voltage detected (power domain #0) 0 generate a safe mode request on a 1.2v low-voltage detected (power domain #0) event if the reset is disabled 1 generate an interrupt request on a 1.2v low-voltage de tected (power domain #0) event if the reset is disabled table 32-7. functional event alternate request re gister (rgm_fear) field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 32-14 freescale semiconductor preliminary?subject to change without notice 32.3.1.7 functional event short sequence register (rgm_fess) this register define s which reset sequence will be done when a functional reset sequen ce is triggered.the functional reset sequence can either start from phase1 or from phase3, skipping phase1 and phase2. note this could be useful for fast reset se quence, for example to skip flash reset. it can be accessed in read/write in ei ther supervisor mode or test mode. it can be accessed in read in user mode. address 0xc3fe_4018 access: supervisor read/write 0123456789101112131415 r ss_exr ss_flash ss_lvd45 ss_cmu0_fhl ss_cmu0_olr ss_fmpll0 ss_chkstop ss_soft ss_core ss_jtag w por0000000000000000 figure 32-8. functi onal event short sequence register (rgm_fess) table 32-9. functional event short sequence register (rgm_fess) field descriptions field description ss_exr short sequence for external reset 0 the reset sequence triggered by an external reset event will start from phase1 1 the reset sequence triggered by an external reset event will start from phase3, skipping phase1 and phase2 ss_flash short sequence for code or data flash fatal error 0 the reset sequence triggered by a code or data flash fatal error event will start from phase1 1 the reset sequence triggered by a code or data flash fatal error event will start from phase3, skipping phase1 and phase2 ss_lvd45 short sequence for 4.5v low-voltage detected 0 the reset sequence triggered by a 4.5v low-voltage detected event will start from phase1 1 the reset sequence triggered by a 4.5v low-voltage detected event will start from phase3, skipping phase1 and phase2 ss_cmu0_f hl short sequence for cmu0 clock frequency higher/lower than reference 0 the reset sequence triggered by a cmu0 clock freque ncy higher/lower than reference event will start from phase1 1 the reset sequence triggered by a cmu0 clock freque ncy higher/lower than reference event will start from phase3, skipping phase1 and phase2 ss_cmu0_ olr short sequence for fxosc frequency lower than reference 0 the reset sequence triggered by a fxosc frequency lower than reference event will start from phase1 1 the reset sequence triggered by a fxosc frequency lower than reference event will start from phase3, skipping phase1 and phase2
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 32-15 preliminary?subject to change without notice 32.3.1.8 standby reset sequence register (rgm_stdby) this register defines reset sequence to be applied on standby mode exit. it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read only in user mode. ss_fmpll0 short sequence for fmpll0 fail 0 the reset sequence triggered by a fmpll0 fail event will start from phase1 1 the reset sequence triggered by a fmpll0 fail event will start from phase3, skipping phase1 and phase2 ss_chkst op short sequence for checkstop reset 0 the reset sequence triggered by a checkstop reset event will start from phase1 1 the reset sequence triggered by a checkstop reset event will start from phase3, skipping phase1 and phase2 ss_soft short sequence for software reset 0 the reset sequence triggered by a software reset event will start from phase1 1 the reset sequence triggered by a software reset event will start from phase3, skipping phase1 and phase2 ss_core short sequence for core reset 0 the reset sequence triggered by a core reset event will start from phase1 1 the reset sequence trig gered by a core reset ev ent will start from phase3 , skipping phase1 and phase2 ss_jtag short sequence for jtag initiated reset 0 the reset sequence triggered by a jtag initiated reset event will start from phase1 1 the reset sequence triggered by a jtag initiat ed reset event will start from phase3, skipping phase1 and phase2 address 0xc3fe_401a access: supervisor read/write 0123456789101112131415 r 00000000 boot_from_bkp_ram 0000000 w reset0000000000000000 figure 32-9. standby reset sequence register (rgm_stdby) table 32-10. standby reset sequence regi ster (rgm_stdby) field descriptions field description boot_ from_ bkp_ram boot from backup ram indicator ? this bit indicates whether the system will boot from backup ram or flash out of standby exit. 0 boot from flash on standby exit 1 boot from backup ram on standby exit table 32-9. functional event short sequence regi ster (rgm_fess) field de scriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 32-16 freescale semiconductor preliminary?subject to change without notice note this register is reset on any enabled ?destructive? or ?functional? reset event. 32.3.1.9 functional bidirectional r eset enable register (rgm_fbre) this register enables the ge neration of an external rese t on functional reset. it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read in user mode. address 0xc3fe_401c access: supervisor read/write 0123456789101112131415 r be_exr be_flash be_lvd45 be_cmu0_fhl be_cmu0_olr be_fmpll0 be_core be_jtag w por0000000000000000 figure 32-10. functional bidirectional reset enable register (rgm_fbre) table 32-11. functional bidirectional reset en able register (rgm_fbre) field descriptions field description be_exr bidirectional reset enable for external reset 0 reset is asserted on an external re set event if the reset is enabled 1 reset is not asserted on an external reset event be_flash bidirectional reset enable for co de or data flash fatal error 0 reset is asserted on a code or data flash fatal error event if the reset is enabled 1 reset is not asserted on a code or data flash fatal error event be_lvd45 bidirectional reset enable fo r 4.5v low-voltage detected 0 reset is asserted on a 4.5v low-volta ge detected event if the reset is enabled 1 reset is not asserted on a 4.5v low-voltage detected event be_cmu0_f hl bidirectional reset enable for cmu0 cloc k frequency higher/lower than reference 0 reset is asserted on a cmu0 clock frequency higher/l ower than reference event if the reset is enabled 1 reset is not asserted on a cmu0 clock frequency higher/lower than reference event be_cmu0_ olr bidirectional reset enable for fxosc frequency lower than reference 0 reset is asserted on a fxosc frequency lower than reference event if the reset is enabled 1 reset is not asserted on a fxosc frequency lower than reference event be_fmpll0 bidirectional reset enable for fmpll0 fail 0 reset is asserted on a fmpll0 fa il event if the reset is enabled 1 reset is not asserted on a fmpll0 fail event be_core bidirectional reset enable for core reset 0 reset is asserted on a core rese t event if the reset is enabled 1 reset is not asserted on a core reset event be_jtag bidirectional reset enable for jtag initiated reset 0 reset is asserted on a jtag initiated reset event if the reset is enabled 1 reset is not asserted on a jtag initiated reset event
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 32-17 preliminary?subject to change without notice 32.4 functional description 32.4.1 reset state machine the main role of mc_rgm is the ge neration of the reset se quence which ensures that the correct parts of the device are reset based on the reset source event. this is summarized in table 32-12 . note jtag logic has its own independent rese t control and is not controlled by the mc_rgm in any way. the reset sequence is comprised of five phases managed by a state machin e, which ensures that all phases are correctly processed thr ough waiting for a minimum dur ation and until al l processes that need to occur during that phase have been completed before proceeding to the next phase. the state machine used to produce the reset sequence is shown in figure 32-11 . table 32-12. mc_rgm reset implications source what gets reset external reset assertion boot mode capture power-on reset all yes yes ?destructive? resets all except some clock/reset management yes yes external reset all except some clock/reset management and debug yes yes ?functional? resets all except some clock/reset management and debug programmable 1 1 the assertion of the external reset is controlled via the rgm_fbre register programmable 2 2 the boot mode is captured if the external reset is asserted shortened ?functional? resets 3 3 the short sequence is enabled via the rgm_fess register flip-flops except some clock/reset management programmable 1 programmable 2
pxd10 microcontroller reference manual, rev. 1 32-18 freescale semiconductor preliminary?subject to change without notice x 32.4.1.1 phase0 phase this phase is entered immediately from any phase on a power-on or enab led ?destructive? reset event. the reset state machine exits phase0 and enters phase1 on verification of the following: figure 32-11. mc_rgm state machine phase0 phase1 phase2 phase3 idle duration ? 3 fast internal rc oscillator (16mhz) clock cycles firc stable, vreg voltage okay done duration ? 350 fast internal rc oscillator (16mhz) clock cycles duration ???? fast internal rc oscill ator (16mhz) clock cycles code and data flash initialization done duration ?? 40 ? fast internal rc oscillator (16mhz) clock cycles code and data flash initialization done fast internal rc oscillator (16mhz) clock is running power-up has completed power-on or enabled ?destructive? reset enabled non-shortened external or ?functional? reset 1 enabled shortened external or ?functional? reset code and data flash initialization done reset released
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 32-19 preliminary?subject to change without notice ? power-up has completed ? fast internal rc oscillator (16mhz) clock is running ? all enabled ?destructive? re sets have been processed ? all processes that need to be done in phase0 are completed ? firc stable, vreg voltage okay ? a minimum of 3 fast intern al rc oscillator (16mhz) clock cycles have elapsed since power-up completion and the last enabled ?destructive? reset event 32.4.1.2 phase1 phase this phase is entered either on exit from phase0 or immediately from phase2, phase3, or idle on a non-masked external or ?functional? re set event if it has not been confi gured to trigger a ?short? sequence. the reset state machine exits phase1 and ente rs phase2 on verificat ion of the following: ? all enabled, non-shortened ?functiona l? resets have been processed ? a minimum of 350 fast intern al rc oscillator (16mhz) clock cycles have elapsed since the last enabled external or non-shorte ned ?functional? reset event 32.4.1.3 phase2 phase this phase is entered on exit from phase1. the rese t state machine exits phase2 and enters phase3 on verification of the following: ? all processes that need to be done in phase2 are completed ? code and data flash initialization ? a minimum of 8 fast internal rc oscillator (16m hz) clock cycles have elapsed since entering phase2 32.4.1.4 phase3 phase this phase is a entered either on exit from phase2 or immediately from idle on an enabled, shortened ?functional? reset event. the reset state machine ex its phase3 and enters idle on verification of the following: ? all processes that need to be done in phase3 are completed ? code and data flash initialization ? a minimum of 40 fast intern al rc oscillator (16mhz) clock cycles have elapsed since the last enabled, shortened ?functional? reset event 32.4.1.5 idle phase this is the final phase and is entered on exit from phase3. when this phase is reached, the mc_rgm releases control of the system to the platform and waits for new reset events that can trigger a reset sequence.
pxd10 microcontroller reference manual, rev. 1 32-20 freescale semiconductor preliminary?subject to change without notice 32.4.2 destructive resets a ?destructive? reset indicates that an event has occu rred after which critical re gister or memory content can no longer be guaranteed. the status flag associated with a given ?destructive ? reset event (rgm_des.f_ bit) is set when the ?destructive? re set is asserted and the power-on reset is not asserted. it is possible for multiple status bits to be set simultaneously , and it is software?s responsibility to determine which reset source is the most critical for the application. the ?destructive? reset can be optionall y disabled by writing bit rgm_derd.d_ . note the rgm_derd register can be wr itten only once between two power-on reset events. the device?s low-voltage detector th reshold ensures that, when 1.2v lo w-voltage detected (power domain #0) is enabled, the supply is sufficie nt to have the destruct ive event correctly propagated through the digital logic. therefore, if a gi ven ?destructive? reset is enabled, the mc _rgm ensures that the associated reset event will be correctly tri ggered to the full system. however, if the given ?destructive? re set is disabled and the voltage goes below the digital functional thres hold, functionality can no l onger be ensured, and the reset may or may not be asserted. an enabled destructive reset will trigger a rese t sequence starting from the beginning of phase0. 32.4.3 external reset the mc_rgm manages the external reset coming from reset. the det ection of a falling edge on reset will start the reset sequence from the beginning of phase1. the status flag associated with the external reset falling edge event (rgm_fes .f_exr bit) is set when the external reset is asserted and the power-on reset is not asserted. the external reset can optionally be di sabled by writing bit rgm_ferd.d_exr. note the rgm_ferd register can be wr itten only once between two power-on reset events. an enabled external reset will normally trigger a reset sequence starting from the beginning of phase1. nevertheless, the rgm_fess register enables the furt her configuring of the re set sequence triggered by the external reset. when rgm_fess.ss_exr is set, the external reset will trigger a reset sequence starting directly from the beginning of phase3, sk ipping phase1 and phase2. this can be useful especially when an external reset should not reset the flash. the mc_rgm may also assert the external reset if the reset sequence was triggered by one of the following: ? a power-on reset ? a ?destructive? reset event
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 32-21 preliminary?subject to change without notice ? an external reset event ? a ?functional? reset event configured via the rg m_fbre register to assert the external reset in this case, the external reset is asserted until the end of phase3. 32.4.4 functional resets a ?functional? reset indicates that an event has occurr ed after which it can be guaranteed that critical register and memory content is still intact. the status flag associated with a gi ven ?functional? reset event (rgm_fes.f_ bit) is set when the ?functional? reset is asse rted and the power-on reset is not a sserted. it is possible for multiple status bits to be set simultaneously , and it is software?s responsibility to determine which reset source is the most critical for the application. the ?functional? reset can be optionally disabled by software writing bit rgm_ferd.d_ . note the rgm_ferd register can be wr itten only once between two power-on reset events. an enabled functional reset will nor mally trigger a reset sequence star ting from the beginning of phase1. nevertheless, the rgm_fess register enables the furt her configuring of the re set sequence triggered by a functional reset. when rgm_fess.ss_ is set, the associated ?functional? reset will trigger a reset sequence starting di rectly from the beginning of phas e3, skipping phase1 and phase2. this can be useful especially in case a f unctional reset should not reset the flash module. 32.4.5 standby entry sequence standby mode can be entered only when the mc_rgm is in idle. on standby entry, the mc_rgm moves to phase1. the minimum duration c ounter in phase1 does not start until standby mode is exited. on entry to phase1 due to stand by mode entry, the rese ts for all power domains except power domain #0 are asserted. du ring this time, reset is not assert ed as the external reset can act as a wakeup for the device. there is an option to keep the fl ash inaccessible and in low-power m ode on standby exit by configuring the drun mode before standby entry so that the fl ash is in power-down or low-power mode. if the flash is to be inaccessible, the phase2 and phase3 states do not wait for the flash to complete initialization before exiting, and the reset to the flash remains asserted. see the mc_me chapter for detail s on the standby and drun modes. 32.4.6 alternate event generation the mc_rgm provides alternative events to be genera ted on reset source asserti on. when a reset source is asserted, the mc_rgm normally enters the reset seque nce. alternatively, it is possible for each reset
pxd10 microcontroller reference manual, rev. 1 32-22 freescale semiconductor preliminary?subject to change without notice source event (except the power-on reset event) to be converted from a rese t to either a safe mode request issued to the mc_me or to an interrupt request issued to the core. alternate event selection for a given reset source is made via the rgm_f/derd and rgm_f/dear registers as shown in table 32-13 . the alternate event is cleared by deas serting the source of the request (i .e. at the reset source that caused the alternate request) and also cleari ng the appropriate rgm_f/des status bit. note alternate requests (safe m ode as well as interrupt requests) are generated asynchronously. note if a masked ?destructive? reset event which is configured to generate a safe mode/interrupt request occurs during phase0, it is ignored, and the mc_rgm will not send any safe mode /interrupt request to the mc_me. the same is true for masked ?functional? reset events during phase1. 32.4.7 boot mode capturing the mc_rgm provides samp ling of the boot mode pad[22:21] for use by the system to determine the boot mode. this sampling is done five fast internal rc osci llator (16mhz) clock cycles before the rising edge of reset . the result of the sampling is then provided to the system. for each bit, a value of ?1? is produced only if each of the oldest th ree of the five samples have the valu e ?1?, otherwise a value of ?0? is produced. note in order to ensure that the boot mode is correctly captured, the application needs to apply the valid boot mode valu e to the device at least five fast internal rc oscillator (16mhz) clock periods before the external reset deassertion crosses the v ih threshold. note reset can be low as a consequence of the internal reset generation. this will force re-sampling of the boot mode pins. table 32-13. mc_rgm alternate event selection rgm_f/derd bit value rgm_f/dear bit value generated event 0 x reset 1 0 safe mode request 1 1 interrupt request
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 33-1 preliminary?subject to change without notice chapter 33 sound generation logic (sgl) 33.1 introduction this document describes the sound generation logic (sgl) module. refer to figure 33-1 for the detailed block diagram of the sgl. 33.1.1 overview the sgl provides a single output to the speaker or buzzer interface. it selects outputs from the pwm cha nnels being used for sound genera tion. in case of monotonic sound, two pwm channels are required while, in the case of polyphonic sound, only one pwm channel is required. monotonic / polyphonic sound can be selected through the signal mono/poly_b. a 32-bit counter value determines the dur ation for which sound will be played. note in this document, the term ?pol yphonic? refers to pcm-based sound generation as described in section 33.4, functional description. figure 33-1. block diagram pwm_ch0 to speaker/ buzzer pwm_ch0 pwm_ch15 mux c 2x1 sound_out mux b mux a pwm_ch15 and gate ch2_sel ch1_sel mono/poly_b mode_sel reserved field reserved field and gate sound_control_logic ipi_int_sgl clk programmable prescaler (1 to 128)
pxd10 microcontroller reference manual, rev. 1 33-2 freescale semiconductor preliminary?subject to change without notice 33.1.2 features the sgl has the following basic features: ? it can be used to produce two type s of sounds ? monotonic and polyphonic sound. ? it selects the pwm channels be ing used for sound generation and provides the pwm output from single channel or anded output from 2 pwm channels depending on whether polyphonic or monotonic sound is to be produced. ? it provides programmability to generate periodic or continuous sound, for desired duration which may be predefined. ? it has the facility for enabling/di sabling the genera tion of interrupts. 33.2 external signal description figure 33-2. sgl external signal description 33.2.1 detailed signal descriptions table 33-1. detailed signal descriptions name function i/o reset 1 1 this is the value which the output si gnals will have when the module is reset. clock system clock i pwm_ch0 to pwm_ch15 pwm channel output (0?1 5) signal coming from emios0 unified channel #16 to unified channel #23, emios1 unified channel #16 to unified channel #23. this signal can have variable duty cycle as well as variable frequency i sound_out output signal carrying the generated sound which will be fed into the speaker interface o?0? ipi_int_sgl interrupt signal generated by sgl whenever sound_duration counter reaches ?0? o?0? pwm_ch0 pwm_ch15 sgl top level sound_out clock ipi_int_sgl ...
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 33-3 preliminary?subject to change without notice 33.3 memory map and register definition 33.3.1 memory map 33.3.2 register summary the conventions in figure 33-3 serve as a key for the register summ ary and individual register diagrams. 33.3.3 register descriptions 33.3.3.1 mode_sel register table 33-2. sgl memory map address offset register access reset value 0x00 mode_sel register r/w 1 1 note that r/w registers may contain some read-only or write-only bits. 0x0000_0000 0x04 sound_duration register r/w 0x0000_0000 0x08 high_period register r/w 0x0000_0000 0x0c low_period register r/w 0x0000_0000 0x10 sgl_status register r 0x00 always reads 1 1 always reads 0 0 r/w bit bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 33-3. key to register fields offset 0x00 access: user read/write 0123456789101112131415 r m_p sound_ctrl sdcie ch2_sel w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pre ch1_sel w reset00000000 00000000 figure 33-4. mode_sel register
pxd10 microcontroller reference manual, rev. 1 33-4 freescale semiconductor preliminary?subject to change without notice 33.3.3.2 sound_duration register table 33-3. mode_sel field descriptions field description 0 m_p selects output corresponding to monophonic or polyphonic sound. 1 output from and gate will be selected to produce monotonic sound 0 output from mux a will be selected to produce polyphonic sound 1?3 sound_c trl sound control bits. see ta bl e 3 3 - 9 for a detailed description. 4 sdcie sound duration complete interrrupt enable bit. enables or disables the interrupt ipi_int_sgl output signal. 1 interrupt ipi_int_sgl is enabled 0 interrupt ipi_int_sgl is not enabled 12?15 ch2_sel pwm channel select (mux b). used to select specific pwm channel to be used by mux b for sound generation. 16?22 pre clock divider value for the prescaler. see table 33-4 for a detailed description. 28?31 ch1_sel pwm channel select (mux a). used to select specific pwm channel to be used by mux a for sound generation. table 33-4. prescaler clock divider pre divide ratio 0000000 1 0000001 2 0000010 3 0000011-1111110 4-127 1111111 128 offset 0x04 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 00000000 0 0 0 0 00000000 0 000 0 0 0 w sound_duration reset00000000000000000000000000000000 figure 33-5. sound_duration register table 33-5. sound_durati on field descriptions field description 0?31 sound_duration 32-bit value which is loaded into bits [0:31] of sound_duration counter
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 33-5 preliminary?subject to change without notice 33.3.3.3 high_period register 33.3.3.4 low_period register offset 0x08 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 00000000 0 0 0 0 00000000 0 000 0 0 0 w high_period reset00000000000000000000000000000000 figure 33-6. high_period register table 33-6. high_period field descriptions field description 0?31 high_period 32-bit value loaded into bits [0:31] of the high_period counter. it defines the on period for sound when operating in periodic mode (that is, when bit 2 of mode_sel[sound_ctrl] is 0b1). offset 0x0c access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 00000000 0 0 0 0 00000000 0 000 0 0 0 wlow_period reset00000000000000000000000000000000 figure 33-7. low_period register table 33-7. low_period field descriptions field description 0?31 low_period 32-bit value loaded into bits [0:31] of the lo w_period counter. it defines the off period for sound when operating in periodic mode (that is, when bit 2 of mode_sel[sound_ctrl] is 0b1).
pxd10 microcontroller reference manual, rev. 1 33-6 freescale semiconductor preliminary?subject to change without notice 33.3.3.5 sgl_status register 33.4 functional description the sgl can be used to produce two types of sounds as described below: ? monotonic sound the tone amplitude modulation is based on two different mixed signals.the first of these two signals has a variable frequency and fixed duty cycle (signal1 in figure 33-9 ). the second signal has a fixed frequency and a variable pulse widt h for generation of the amplitude (signal2 in figure 33-9 ). the duty cycle of this signal represents the amplitude of the generated sound. the sound generator is generally a pwm that generate s 2 different signals and a mixer to generate a tone at the output as shown in signal 3 of figure 33-9 . it is passed through a first-order low-pass filter to produce signal4 in figure 33-9 . this signal can be fed to the speaker interface. offset 0x10 access: user read/write 0123456789101112131415 r w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sdcif w w1c reset00000000 00000000 figure 33-8. sgl_status register table 33-8. sgl_status field descriptions field description sdcif sound duration complete interrrupt flag bit. reflects the status of the interrupt. 1 sdcif set event has occurred due to generation of interrupt 0 sdcif cleared
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 33-7 preliminary?subject to change without notice figure 33-9. monotonic sound generation ? polyphonic sound for polyphonic sound, pcm coded samp les which reside in system memory, are loaded into the pwm registers at the pcm sample frequency(for example, 16 khz) . so, for a given time period (1/16 khz), the pwm output has a fi xed duty cycle and frequency. a ne w sample is loaded into the pwm register (at the rate of 16 khz), which resu lts in a corresponding change in the duty cycle and frequency (both of wh ich will remain fixed until the load ing of new pcm coded sample). the resulting pwm signal gives polyphonic sound as an output. the output must be filtered by a low-pass filter. the quality and the order of the lo w-pass filter will have a direct impact on the quality of the produced sound. the sgl takes outputs of the 16 pwm channels being used for sound gene ration as inputs and processes them accordingly, depending on whether monotonic or polyphonic sound is to be generated, to give sound_out as the output signal. the select lines for multiplexers come from a regi ster (mode_sel) which is configured by software. the type of sound output (monotonic or polyphonic) is controlled by mode_sel[m_p]. the value of mode_sel[sound_ctrl] determines the duration of sound and whethe r the sound output is periodic or continuous. each duration register (high_period, low_peri od and sound_duration) has a total size of 32 bits. the clock on which their counters opera te is provided by a programmable prescaler (mode_sel[pre] can be configured to divide clk by valu es as shown in figure 33-1 ), so that the duration for which sound can be produced becomes significant. the fixed prescaler brings down the time base at 64 mhz system cloc k frequency to 1 microsecond, which can be further prescaled by us ing the programmable prescaler. the high_period, low_period and sound_durat ion registers must be reprogrammed each time sound needs to be generated, with a new configuration of mode_sel[sound_ctrl]. see table 33-9 for a detailed description of how the so und_ctrl bits affect the generated sound. signal1 signal2 signal3 signal4 signal1: signal with fixed duty cycle and variable frequency signal2: tone signal with fixed frequency (refer to falling edges) and variable duty cycle signal4: sound_out after passing through the low pass filter (external to the sgl) signal3: anded output (sound_out) of signal1 and signal2 coming from the mixer
pxd10 microcontroller reference manual, rev. 1 33-8 freescale semiconductor preliminary?subject to change without notice in case the user needs to contro l the sound duration through software, then sound_ctrl[1] needs to be set to ?1?. sound_ctrl[1] can be forced to zero (?0?) at any point of time by softwa re through the ips interface if the sound generation needs to be st opped. this feature handles the case in which sound generation needs to be stopped after a time that cannot be predetermined. an example of this is the warning sound that should be generated when a car door is left open, which should stop as soon as the car door is closed. the sound generation continues as long as sou nd_ctrl[1] is ?1? (that is, when the car door is open) and stops as soon as it is set to zero (when the car door is closed). it is advisable to choose the values for hi gh_period, low_period a nd sound_duration in such a way that sound_duration is an integr al multiple of the sum of low_period and high_period. the high_period and low_period registers can al so be used as a volume control for monotonic sound when sound_ctrl[2] is ?1?. in case where monotonic sound is to be generated, the software configures the mode_sel register through ips interface such that the set of 4 bits (ch1_sel[0:3]) can be us ed to select out put from one of the pwm channels being used for s ound generation. this output will be the one having variable duty cycle and fixed frequency. table 33-9. truth table for mode_sel[sound_ctrl] sound_ ctrl[2] (periodic/ continuous) sound_ ctrl[1] (begin/end) sound_ ctrl[0] (counter enable) result x 0 0 no sound generation 0 0 1 continuous sound is generated until the counter loaded with the value in the sound_duration register reaches ?0?. there is no dependency on high_period and low_period register values. 0 1 x continuous sound is generated. there is no dependency on sound_duration, high_period, or low_period register values. 1 0 1 sound high (i.e. sound is on) and sound low (i.e. sound is off) are generated until the counter loaded with the value in the sound_duration register reaches ?0?. duration for sound high and sound low depend on high_period and low_period_msb register values respectively. the high_period counter and low_period counter are reloaded automatically as long as the sound_duration counter does not reach ?0? . 1 1 x sound high (i.e. sound is on) and sound low (i.e. sound is off) are generated . duration for sound high and sound low depend on high_period and low_period register values respectively. the high_period counter and low_period counter are reloaded automatically. there is no dependency on the value in the sound_duration register in this mode.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 33-9 preliminary?subject to change without notice similarly, the 4 bits configured by the software comprise the signal ch2_s el[0:3], thus leading to selection of output from the second pwm channel being used for sound genereation. this output from second channel will be the one having fixe d duty cycle and variable frequency. simultaneously, mono/poly_b is configured such that for monotonic sound generation its value will be one, and hence the output from the and gate will be selected i.e. the anding of signals from muxa (variable duty cycle, fixed frequency) and muxb (fi xed duty cycle, variable frequency) will produce monotonic sound. in case where polyphonic sound is to be generated, th e software configures the mode_sel register through the ips interface such that the set of 4 bits (c h1_sel[0:3]) can be used to select output from the pwm channel being used for sound generation. simultaneously, mono/poly_b is configured such th at for polyphonic sound genera tion its value will be zero, and hence the output corresponding to the si gnal producing polyphonic s ound will be selected. the suggested sequence of even ts for sound generation controlled by sound_ctrl[0:2] is: 1. initially sound_ctrl[0:2] is 3?b000. 2. program the sound_dura tion/ high_period/low_peri od registers? values, depending on the mode of sound generation which is desired. 3. program the sound_ctrl[0:2] bits to th e new value depending on the mode desired. 4. edge detector detects the ch ange on sound_ctrl[0:2] bits. 5. on the next clock edge after the edge detection, the sound generation starts. 6. in cases where the sound duration depends on the value in sound_duration register, the sound generation stops wh en sound_duration count er reaches zero. an interrupt is raised as soon as the sound_duration counter reaches zero. in these cases, the isr changes the sound_ctrl[0:2] to 3?b000 from the present value. in other cases, where sound_durati on counter has no role to play , the sound generation stops when the sound_ctrl[0:2] bits are change d asynchronously by the software. 33.4.1 interrupts sgl generates the interrupt signal ipi_int_sgl. the generation of this interrupt is enabled if the mode_sel[sdcie] bit is ?1?. if this bit is ?0?, then the interrupt is disabled. the interrupt is generated whenever the sound_du ration counter reaches ?0? in cases where sound is being generated for a predeter mined duration of time (ie . s ound_duration register value is controlling sound duration). the sgl_status[sdcif] bit indicates the generation of interr upt. it is set whenev er an interrupt is generated irrespective of the value of the sdcie bit. it can be cleare d by writing ?1? to it. the interrupt signal ipi_int_sgl is asserted if the sdcif flag is set and the sdcie bit is set.
pxd10 microcontroller reference manual, rev. 1 33-10 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 34-1 preliminary?subject to change without notice chapter 34 static ram (sram) 34.1 introduction the pxd10 family offers 24 kb or 48 kb of general purpose system sram (with ecc protection). some family members also include 160 kb of graphics sram (without ecc protection). details of the sram areas and their features for eac h family member are shown in table 34-1 . 34.2 general-purpose sram the general-purpose sram comprises 8 kb of standby sram plus 16 kb or 40 kb of sram that may or may not be enabled in standby mode. th e sram provides the following features: ? sram can be read/writte n from any bus master ? byte, halfword and word addressable ? ecc protected with single-bit correction and double-bit detection 34.3 graphics sram the 160 kb of graphics sram has no ecc protect ion and is not powered during standby mode. 34.4 low power configuration in order to reduce leakage, only an 8 kb portion of the sram remains powered by default during standby mode. table 34-1. sram memory map address range size [kb] 5602s 5604s 5606s region 0x40000000 0x40001fff 8 yes yes yes sram (ecc protection, standby support) 0x40002000 0x40005fff 16 yes yes yes sram (ecc protection, standby support is programmable) 0x40006000 0x4000bfff 24 no yes yes sram (ecc protection, standby support is programmable) 0x4000c000 0x5fffffff 524240 ? ? ? reserved 0x60000000 0x60027fff 160 no no yes graphics sram (no ecc protection, no standby support) 0x60028000 0x7fffffff 524128 ? ? ? reserved
pxd10 microcontroller reference manual, rev. 1 34-2 freescale semiconductor preliminary?subject to change without notice 34.5 register memory map the internal sram has no regist ers. registers for the sram ecc are located in the ecsm. 34.6 sram ecc mechanism the sram ecc detects the following condi tions and produces the following results: ? detects and corrects all 1-bit errors ? detects and flags all 2-bit erro rs as non-correctable errors ? detects 39-bit reads (32-bit data bus plus the 7-bit ecc) that return all zeros or all ones, asserts an error indicator on the bus cycle, and sets the error flag sram does not detect all er rors greater than 2 bits. internal sram write operations are pe rformed on the following byte boundaries: ? 1 byte (0:7 bits) ? 2 bytes (0:15 bits) ? 4 bytes or 1 word (0:31 bits) if the entire 32 data bits are written to sram, no re ad operation is performed and the ecc is calculated across the 32-bit data bus. the 8-bit ecc is appe nded to the data segment and written to sram. if the write operation is less than the entire 32-bit data width (1-, or 2-byte segment), the following occurs: 1. the ecc mechanism checks the entire 32-bit data bus for errors, detecting and either correcting or flagging errors. 2. the write data bytes (1-, or 2- byte segment) are merged with the corrected 32 bits on the data bus. 3. the ecc is then calculated on the resulti ng 32 bits formed in the previous step. 4. the 7-bit ecc result is appended to the 32 bits from the data bus, and th e 39-bit value is then written to sram. 34.6.1 access timing the system bus is a two-stage pipe lined bus, which makes the timing of any access dependent on the access during the previous clock. table 34-3 lists the various combinations of read and write operations to sram and the number of wait states used for the each operation. the table columns contain the following information: ? current operation: lists the type of sram operation ex ecuting currently table 34-2. low power configuration mode configuration run, test, safe and stop all general purpose and graphics sram is powered and operational. standby (1) only 8 kb of the sram remains powered. upper ram is disabled by the mc_pcu. standby (2) all system sram remains powere d. upper ram is enabled by the mc_pcu.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 34-3 preliminary?subject to change without notice ? previous operation: lists the va lid types of sram operations th at can precede the current sram operation (valid operation during the preceding clock) ? wait states: lists the number of wait states (bus clocks) the operation requires which depends on the combination of the current and previous operation 34.6.2 reset effects on sram accesses asynchronous reset will possibly corrupt ram if it a sserts during a read or wr ite operation to sram. the completion of that access depends on the cycle at whic h the reset occurs. data read from or written to sram before the reset event occurred is retained, and no other address locations are accessed or changed. in case of no access ongoing when reset oc curs, the ram corruption does not happen. instead synchronous reset (sw reset) should be used in controlled function (without ram accesses) in case initialization procedure is needed without ram initialization. 34.7 functional description ecc checks are performed during the read portion of an sram ecc read/wri te (r/w) operation, and ecc calculations are performed dur ing the write portion of a read/w rite (r/w) operation. because the ecc bits can contain random data after the device is powered on, the sram must be initialized by table 34-3. number of wait states required for sram operations current operation previous operatio n number of wait states required read operation read idle 1 pipelined read 8-, 16-, or 32-bit write 0 (read from the same address) 1 (read from a different address) pipelined read read 0 write operation 8-, or 16-bit write idle 1 read pipelined 8-, or 16-bit write 2 32-bit write 8-, or 16-bit write 0 (write to the same address) pipelined 8-, 16-, or 32-bit write 8-, 16-, or 32-bit write 0 32-bit write idle 0 32-bit write read
pxd10 microcontroller reference manual, rev. 1 34-4 freescale semiconductor preliminary?subject to change without notice executing 32-bit write operations prior any read accesses. this is also true for implicit read accesses caused by any write accesses of less than 32-bit as discussed in section 34.6, sram ecc mechanism. 34.8 initialization and application information to use the sram, the ecc must check all bits that require initialization after power on. all writes must specify an even number of regist ers performed on 32-bit word-aligned boundaries. if the write is not the entire 32 bits (8 or 16 bits), a read / modify / writ e operation is generated that checks the ecc value upon the read.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-1 preliminary?subject to change without notice chapter 35 stepper motor controller (smc) 35.1 introduction the smc block is a pwm motor controll er suitable for driving small ste pper and air core motors used in instrumentation applications. the m odule can also be used for other mo tor control or pwm applications that match the frequency, resolution and output driv e capabilities of the module. the smc has 12 pwm channels associated with two pins each (24 pins in total). 35.1.1 features the smc includes the following features: ? 10/11-bit pwm counter ? 11-bit resolution with select able pwm dithering function ? left, right, or center aligned pwm ? short-circuit detection in each pw m channel with programmable time-out 35.1.2 modes of operation 35.1.2.1 functional modes 35.1.2.1.1 dither function dither function can be selected or deselected by setting or clearing the mcctl0 [dith] bit. this bit influences all pwm channels. for details, please refer to section 35.4.1.3.5, dither bit (mcctl0[dith]) . 35.1.2.2 pwm channel configuration modes the 12 pwm channels can operate in three functional modes. those mode s are, with some restrictions, selectable for each ch annel independently. 35.1.2.2.1 dual full h-bridge mode this mode is suitable to dr ive a stepper motor or a 360 o air gauge instrument. for details, please refer to section 35.4.1.1.1, dual full h-bridge mode? . in this mode two adjacent pwm channels are combined, and two pwm channels drive four pins. 35.1.2.2.2 full h-bridge mode this mode is suitable to drive a ny load requiring a pwm signal in a h- bridge configurati on using two pins. for details please refer to section 35.4.1.1.2, full h-bridge mode? .
pxd10 microcontroller reference manual, rev. 1 35-2 freescale semiconductor preliminary?subject to change without notice 35.1.2.2.3 half h-bridge mode this mode is suitable to drive a 90 o instrument driven by one pin. for details, please refer to section 35.4.1.1.3, half h-bridge mode? . 35.1.2.3 pwm alignment modes each pwm channel can operate indepe ndently in three differ ent alignment modes. fo r details, please refer to section 35.4.1.3.1, pwm alignment modes? . 35.1.2.4 low-power mode the behavior of the smc when it is disabled by the mc_me module is programmabl e. for details, please refer to section 35.4.5, operation in smc stop mode? .
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-3 preliminary?subject to change without notice 35.1.3 block diagram figure 35-1. smc block diagram period register mcper 11-bit timer/counter duty register mcdc0 comparator m0c0m m0c0p duty register mcdc1 comparator m0c1m m0c1p duty register mcdc2 comparator m1c0m m1c0p duty register mcdc3 comparator m1c1m m1c1p duty register mcdc4 comparator m2c0m m2c0p duty register mcdc5 comparator m2c1m m2c1p duty register mcdc6 comparator m3c0m m3c0p duty register mcdc7 comparator m3c1m m3c1p control registers mcctl0[dith] 11 pwm channel pair pwm channel duty register mcdc8 comparator m4c0m m4c0p duty register mcdc9 comparator m4c1m m4c1p duty register mcdc10 comparator m5c0m m5c0p duty register mcdc11 comparator m5c1m m5c1p
pxd10 microcontroller reference manual, rev. 1 35-4 freescale semiconductor preliminary?subject to change without notice 35.2 external signal description the smc is associated with 24 pins. table 35-1 lists the relationship betw een the pwm channels, signal pins, pwm channel pairs (motor numbers), coils and node s they are supposed to dr ive if all channels are set to dual full h-br idge configuration. 35.2.1 m0c0m/m0c0p/m0c1m/m0c1p ? pwm output pins for motor 0 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 0. pwm output on m0c0m results in a positive cu rrent flow through coil 0 when m0c0p is driven to a logic high state. pwm output on m0c1m results in a positive current flow through coil 1 when m0c1p is driven to a logic high state (for details refer to section 35.4.1, modes of operation ?). table 35-1. pwm channel and pin assignment pin name pwm channel pwm channel pair 1 1 a pwm channel pair always consists of pwm channel x and pwm channel x+1 (x = 2 ? n). the term ?pwm channel pair? is equivalent to the term ?motor?. for example, channel pair 0 is equivalent to motor 0. coil node m0c0m 0 0 0 minus m0c0p plus m0c1m 1 1 minus m0c1p plus m1c0m 2 1 0 minus m1c0p plus m1c1m 3 1 minus m1c1p plus m2c0m 4 2 0 minus m2c0p plus m2c1m 5 1 minus m2c1p plus m3c0m 6 3 0 minus m3c0p plus m3c1m 7 1 minus m3c1p plus m4c0m 8 4 0 minus m4c0p plus m4c1m 9 1 minus m4c1p plus m5c0m 10 5 0 minus m5c0p plus m5c1m 11 1 minus m5c1p plus
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-5 preliminary?subject to change without notice 35.2.2 m1c0m/m1c0p/m1c1m/m1c1p ? pwm output pins for motor 1 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 1. pwm output on m1c0m results in a positive cu rrent flow through coil 0 when m1c0p is driven to a logic high state. pwm output on m1c1m results in a positive current flow through coil 1 when m1c1p is driven to a logic high state (for details refer to section 35.4.1, modes of operation ?). 35.2.3 m2c0m/m2c0p/m2c1m/m2c1p ? pwm output pins for motor 2 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 2. pwm output on m2c0m results in a positive cu rrent flow through coil 0 when m2c0p is driven to a logic high state. pwm output on m2c1m results in a positive current flow through coil 1 when m2c1p is driven to a logic high state (for details refer to section 35.4.1, modes of operation ?). 35.2.4 m3c0m/m3c0p/m3c1m/m3c1p ? pwm output pins for motor 3 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 3. pwm output on m3c0m results in a positive cu rrent flow through coil 0 when m3c0p is driven to a logic high state. pwm output on m3c1m results in a positive current flow through coil 1 when m3c1p is driven to a logic high state (for details refer to section 35.4.1, modes of operation ?). 35.2.5 m4c0m/m4c0p/m4c1m/m4c1p ? pwm output pins for motor 4 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 4. pwm output on m4c0m results in a positive cu rrent flow through coil 0 when m4c0p is driven to a logic high state. pwm output on m4c1m results in a positive current flow through coil 1 when m4c1p is driven to a logic high state (for details refer to section 35.4.1, modes of operation ?). 35.2.6 m5c0m/m5c0p/m5c1m/m5c1p ? pwm output pins for motor 5 high current pwm output pins that can be used for motor drive. these pins interface to the coils of motor 5. pwm output on m5c0m results in a positive cu rrent flow through coil 0 when m5c0p is driven to a logic high state. pwm output on m5c1m results in a positive current flow through coil 1 when m5c1p is driven to a logic high state (for details refer to section 35.4.1, modes of operation ?). 35.3 memory map and register definition this section provides a detailed description of all registers of the 10-bit 12-channel smc module. 35.3.1 module memory map table 35-2 shows the memory map of the 10-bit 12-channel smc module. access type can be ? rw: read and write
pxd10 microcontroller reference manual, rev. 1 35-6 freescale semiconductor preliminary?subject to change without notice ? data access type is 8,16 or 32 bit. it is recommende d to access the various register using the access types shown in table 35-2 for consistent write operations. table 35-2. smc - memory map address offset use recommende d access type location 0x00 motor controller control register 0 (mcctl0) rw, 8 bit on page 8 0x01 motor controller control register 1 (mcctl1) rw, 8 bit on page 9 0x02 motor controller period register (mcper) rw, 16 bit on page 10 0x04 reserved - 0x05 reserved - 0x06 reserved - 0x07 reserved - 0x08 reserved - 0x09 reserved - 0x0a reserved - 0x0b reserved - 0x0c reserved - 0x0d reserved - 0x0e reserved - 0x0f reserved - 0x10 motor controller channel control register 0 (mccc0) rw, 8 bit on page 10 0x11 motor controller channel control register 1 (mccc1) rw, 8 bit on page 10 0x12 motor controller channel control register 2 (mccc2) rw, 8 bit on page 10 0x13 motor controller channel control register 3 (mccc3) rw, 8 bit on page 10 0x14 motor controller channel control register 4 (mccc4) rw, 8 bit on page 10 0x15 motor controller channel control register 5 (mccc5) rw, 8 bit on page 10 0x16 motor controller channel control register 6 (mccc6) rw, 8 bit on page 10 0x17 motor controller channel control register 7 (mccc7) rw, 8 bit on page 10 0x18 motor controller channel control register 8 (mccc8) rw, 8 bit on page 10 0x19 motor controller channel control register 9 (mccc9) rw, 8 bit on page 10 0x1a motor controller channel control register 10 (mccc10) rw, 8 bit on page 10 0x1b motor controller channel control register 11 (mccc11) rw, 8 bit on page 10 0x1c reserved - 0x1d reserved - 0x1e reserved - 0x1f reserved - 0x20 motor controller duty cycle register 0 (mcdc0) rw, 16 bit on page 11 0x22 motor controller duty cycle register 1 (mcdc1) rw, 16 bit on page 11 0x24 motor controller duty cycle register 2 (mcdc2) rw, 16 bit on page 11 0x26 motor controller duty cycle register 3 (mcdc3) rw, 16 bit on page 11 0x28 motor controller duty cycle register 4 (mcdc4) rw, 16 bit on page 11 0x2a motor controller duty cycle register 5 (mcdc5) rw, 16 bit on page 11 0x2c motor controller duty cycle register 6 (mcdc6) rw, 16 bit on page 11 0x2e motor controller duty cycle register 7 (mcdc7) rw, 16 bit on page 11
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-7 preliminary?subject to change without notice 35.3.2 register description this section provides detailed descriptions of all registers in ascending address order. table 35-3 provides a key for the register figur es and register tables. 0x30 motor controller duty cycle register 8 (mcdc8) rw, 16 bit on page 11 0x32 motor controller duty cycle register 9 (mcdc9) rw, 16 bit on page 11 0x34 motor controller duty cycle register 10 (mcdc10) rw, 16 bit on page 11 0x36 motor controller duty cycle register 11 (mcdc11) rw, 16 bit on page 11 0x38 reserved - 0x39 reserved - 0x3a reserved - 0x3b reserved - 0x3c reserved - 0x3d reserved - 0x3e reserved - 0x3f reserved - 0x40 short-circuit detector time-out register (mcsdto) rw, 8 bit on page 13 0x41 reserved - 0x42 reserved - 0x43 reserved - 0x44 short-circuit detector enable register 0 (mcsde0) rw, 8 bit on page 13 0x45 short-circuit detector enable register 1 (mcsde1) rw, 8 bit on page 14 0x46 short-circuit detector enable register 2 (mcsde2) rw, 8 bit on page 14 0x47 reserved - 0x48 short-circuit detector interrupt enable register 0 (mcsdien0) rw, 8 bit on page 15 0x49 short-circuit detector interrupt enable register 1 (mcsdien1) rw, 8 bit on page 15 0x4a short-circuit detector interrupt enable register 2 (mcsdien2) rw, 8 bit on page 16 0x4b reserved - 0x4c short-circuit detector interrupt register 0 (mcsdi0) r/mw, 8 bit on page 16 0x4d short-circuit detector interrupt register 1 (mcsdi1) r/mw, 8 bit on page 17 0x4e short-circuit detector interrupt register 2 (mcsdi2) r/mw, 8 bit on page 17 0x4f reserved - table 35-3. register access conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types table 35-2. smc - memory map (continued) address offset use recommende d access type location
pxd10 microcontroller reference manual, rev. 1 35-8 freescale semiconductor preliminary?subject to change without notice 35.3.2.1 motor controller control register 0 (mcctl0) this register controls the ope rating mode of the smc module. . rwm a read/write bit that may be modified by hardware in some fashion other than by a reset. w1c write one to clear. a flag bit that can be read, is cleared by writing a one, writing 0 has no effect. reset value 0 resets to zero. 1 resets to one. offset module base + 0x0000 01234567 r0 mcpre 00 dith 0mctoif w w1c reset00000000 figure 35-2. motor controller control register 0 (mcctl0) table 35-4. mcctl0 field descriptions field description mcpre motor controller prescaler select ? mcpre determines the prescaler value that sets the motor controller timer counter clock frequency (f tc ). the clock source for the prescaler is the peripheral bus clock (f bus ) as shown in figure 35-32 . writes to mcpre will not affect the timer counter clock frequency f tc until the start of the next pwm period. 00 f tc = f bus 01 f tc = f bus /2 10 f tc = f bus /4 11 f tc = f bus /8 dith motor control/driver di ther feature enable (refer to section 35.4.1.3.5, dither bit (mcctl0[dith])? ) 0 dither feature is disabled. 1 dither feature is enabled. mctoif motor controller timer coun ter overflow interrupt flag ? this bit is set when a motor controller timer counter overflow occurs. the bit is cleared by writing a 1 to the bit. 0 a motor controller timer counter overflow has not occurred since the last reset or since the bit was cleared. 1 a motor controller timer co unter overflow has occurred. table 35-3. register access conventions (continued) convention description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-9 preliminary?subject to change without notice 35.3.2.2 motor controller control register 1 (mcctl1) this register controls the behavior of the analog se ction of the smc as well as the interrupt enables. offset module base + 0x0001 01234567 r recirc 000000 mctoie w reset00000000 figure 35-3. motor controller control register 1 (mcctl1) table 35-5. mcctl1 field descriptions field description recirc recirculation in (dual) full h-bridge mode (refer to section 35.4.1.3.3, recirculation bit (mcctl1[recirc])? ) ? recirc only affects the outputs in (dual) full h-bridge modes. in half h-bridge mode, the pwm output is always active low. recirc = 1 will also invert the effect of the mcdcx [sign] bits (refer to section 35.4.1.3.2, si gn bit (mcdcx[sign])? ) in (dual) full h-bridge modes. recirc must be changed only while no pwm channel is operating in (dual) full h-bridge mode; otherwise, erroneous output pattern may occur. 0 recirculation on the high side transistors. acti ve state for pwm output is logic low, the static channel will output logic high. 1 recirculation on the low side transistors. active state for pwm output is logic high, the static channel will output logic low. mctoie motor controller timer counte r overflow interrupt enable 0 interrupt disabled. 1 interrupt enabled. an interrupt will be generated when the motor controller timer counter overflow interrupt flag ( mcctl0 [mctoif]) is set.
pxd10 microcontroller reference manual, rev. 1 35-10 freescale semiconductor preliminary?subject to change without notice 35.3.2.3 motor controller period register (mcper) setting per to 0 will shut off all pwm channels as if mcccx [mcam] is set to 0 in all channel control registers after the next period timer counter overflow. in this case, the mo tor controller releases all pins. note programming per to 1 and setting the mcctl0 [dith] bit will be managed as if per is programmed to 0. all pwm channels will be shut off after the next period timer counter overflow. 35.3.2.4 motor controller channe l control register (mccc0..11) each pwm channel has one associat ed control register to control output delay, pwm alignment, and output mode. the number of each re gister refers directly the pwm channel it controls. the relation between channels, pin names and register names is shown in table 35-19 . offset module base + 0x0002, 0x0003 0123456789101112131415 r00000 per w reset0000000000 000000 figure 35-4. motor controller period register (mcper) table 35-6. mcper field descriptions field description per pwm period ? per defines the number of motor controller timer counter clocks a pwm period lasts. the motor controller timer counter is clocked with the frequency f tc . if dither mode is enabled ( mcctl0 [dith] = 1, refer to section 35.4.1.3.5, dither bit (mcctl0[dith])? ), per[0] is ignored and reads as a 0. in this case per = 2 * mcdcx [duty[10:1]]. offset module base + 0x0010 . . . 0x001b 01234567 r mcom mcam 00 cd w reset00000000 figure 35-5. motor controller channel control register (mccc0..11)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-11 preliminary?subject to change without notice note the smc will release the pins after the next pwm timer counter overflow without accommodating any channel de lay if a single channel has been disabled or if the period re gister has been cleared or all channels have been disabled. program one or more inac tive pwm frames (duty cycle = 0) before writing a configurat ion that disables a single channel or the entire smc. 35.3.2.5 motor controller duty cycle register (mcdc0..11) each duty cycle register sets the sign and duty functionality for the respective pwm channel. the number of each register refires directly the pwm channel it controls. the re lation between channels, pin names and register names is shown in table 35-19 . table 35-7. mcccx field descriptions field description mcom output mode ? mcom controls the pwm channel?s output mode. 00 half h-bridge mode, pwm on pin mncxm, pin mncxp is released 01 half h-bridge mode, pwm on pin mncxp, pin mncxm is released 10 full h-bridge mode 11 dual full h-bridge mode mcam pwm channel a lignment mode ? mcam controls the pwm channel?s pwm alignment mode and operation. mcam and mcom are double buffered. the values used for the generation of the output waveform will be copied to the working registers either at once (if all pwm channels are disabled or mcper [per] is set to 0) or if a timer counter overflow occurs. reads of the register return the most recent written value, which are not necessarily the currently active values. 00 channel disabled 01 left aligned 10 right aligned 11 center aligned cd pwm channel delay ? each pwm channel can be individually delayed by a programmable number of pwm timer counter clocks. the delay will be n/f tc . 00 zero pwm clocks channel delay 01 one pwm clock channel delay 10 two pwm clocks channel delay 11 three pwm clocks channel delay offset module base + 0x0020 . . . 0x0037 0123456789101112131415 r sign [4] sign[3:0] duty w reset0000000000 000000 figure 35-6. motor cont roller duty cycle register (mcdc0..11)
pxd10 microcontroller reference manual, rev. 1 35-12 freescale semiconductor preliminary?subject to change without notice to prevent the output from incons istent signals, the duty cycle re gisters are double buffered. the smc module will use working registers to generate the out put signals. the working re gisters are copied from the bus accessible registers at the following conditions: ? mcper [per] is set to 0 (all channe ls are disabled in this case) ? mcccx [mcam] of the respective channel is set to 0 (channel is disabled) ? a pwm timer counter overflow occurs while in half h-bridge or full h-bridge mode ? a pwm channel pair is configured to work in dual full h-bridge mode and a pwm timer counter overflow occurs after the odd 1 duty cycle register of the ch annel pair has been written. in this way, the output of the pwm will always be either the old pwm waveform or the new pwm waveform, not some variation in between. reads of this register return the mo st recent value wr itten. reads do not necessarily return the value of the currently active sign, duty cycle, and dither fu nctionality due to the double buffering scheme. table 35-8. mcdcx field descriptions field description sign[4] sign bit ? the sign[4] bit is used to define which out put will drive the pwm signal in (dual) full-h-bridge modes. the sign[4] bit has no effect in half-bridge modes. see section 35.4.1.3.2, sign bit (mcdcx[sign])? and table 35-20 for detailed information about the impact of mcctl1 [recirc] and sign[4] bit on the pwm output. sign[3:0] sign bit extension ? replicates the sign[4] bit towards t he duty field to make the whole register a signed representation for the duty cycle length. duty duty cycle length ? duty defines the number of motor controller timer counter clocks the corresponding output is driven low ( mcctl1 [recirc] = 0) or is driven high ( mcctl1 [recirc] = 1). setting all bits to 0 will give a static high output in case of mcctl1 [recirc] = 0; otherwise, a static low output. values greater than or equal to the conten ts of the period register will generate a static low output in case of mcctl1 [recirc] = 0, or a static high output if mcctl1 [recirc] = 1. 1. odd duty cycle register: mcdcx +1, x = 2 ? n
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-13 preliminary?subject to change without notice 35.3.2.6 short-circuit detector time-out register (mcsdto) 35.3.2.7 short-circuit detector enable register 0 (mcsde0) offset module base + 0x0040 0123 5 7 r tout w reset00000000 figure 35-7. short-circuit detector time-out register (mcsdto) table 35-9. mcsdto field descriptions field description tout time-out ? the value tout is an unsigned 8-bit number . this value is used as load value for the short-circuit detection counters. this value is applied to all 24 short-circuit detection blocks. due to synchronization and sampling, tout must always be larger than 2 (see also section 35.4.6, short-circuit detection ?). offset module base + 0x0044 01234567 r sden w reset00000000 figure 35-8. short-circuit detector enable register 0 (mcsde0) table 35-10. mcsde0 field description field description sden short-circuit detector enable ? each short-circuit detector can be enabled or disabled according to the mapping described in ta b l e 3 5 - 2 3 . the short-circuit detector of a given pin is enabled if the related enable bit is set to 1.
pxd10 microcontroller reference manual, rev. 1 35-14 freescale semiconductor preliminary?subject to change without notice 35.3.2.8 short-circuit detector enable register 1 (mcsde1) 35.3.2.9 short-circuit detector enable register 2 (mcsde2) offset module base + 0x0045 01234567 r sden w reset00000000 figure 35-9. short-circuit detector enable register 1 (mcsde1) table 35-11. mcsde1 field description field description sden short-circuit detector enable ? each short-circuit detector can be enabled or disabled according to the mapping described in ta b l e 3 5 - 2 3 . the short-circuit detector of a given pin is enabled if the related enable bit is set to 1. offset module base + 0x0046 01234567 r sden w reset00000000 figure 35-10. short-circuit detector enable register 2 (mcsde2) table 35-12. mcsde2 field description field description sden short-circuit detector enable ? each short-circuit detector can be enabled or disabled according to the mapping described in ta b l e 3 5 - 2 3 . the short-circuit detector of a given pin is enabled if the related enable bit is set to 1.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-15 preliminary?subject to change without notice 35.3.2.10 short-circuit detector inte rrupt enable register 0 (mcsdien0) 35.3.2.11 short-circuit detector inte rrupt enable register 1 (mcsdien1) offset module base + 0x0048 01234567 r sdie w reset00000000 figure 35-11. short-circuit detector interrupt enable register 0 (mcsdien0) table 35-13. mcsdien0 field descriptions field description sdie short-circuit detect or interrupt enable ? the interrupt of each short-circuit detector can individually be enabled or disabled according to the mapping described in table 35-23 . the short-circuit detector interrupt of a given pin is enab led if the related interrupt enable bit is set to 1. offset module base + 0x0049 01234567 r sdie w reset00000000 figure 35-12. short-circuit detector interrupt enable register 1 (mcsdien1) table 35-14. mcsdien1 field descriptions field description sdie short-circuit detect or interrupt enable ? the interrupt of each short-circuit detector can individually be enabled or disabled according to the mapping described in table 35-23 . the short-circuit detector interrupt of a given pin is enab led if the related interrupt enable bit is set to 1.
pxd10 microcontroller reference manual, rev. 1 35-16 freescale semiconductor preliminary?subject to change without notice 35.3.2.12 short-circuit detector inte rrupt enable register 2 (mcsdien2) 35.3.2.13 short-circuit detector interrupt register 0 (mcsdi0) offset module base + 0x004a 01234567 r sdie w reset00000000 figure 35-13. short-circuit detector interrupt enable register 2 (mcsdien2) table 35-15. mcsdien2 field descriptions field description sdie short-circuit detect or interrupt enable ? the interrupt of each short-circuit detector can individually be enabled or disabled according to the mapping described in table 35-23 . the short-circuit detector interrupt of a given pin is enab led if the related interrupt enable bit is set to 1. offset module base + 0x004c 01234567 rsdif w rwm rwm rwm rwm rwm rwm rwm rwm reset00000000 figure 35-14. short-circuit detector interrupt register 0 (mcsdi0) table 35-16. mcsdi0 field descriptions field description sdif short-circuit detector interrupt flag ? in case of a detected shor t-circuit, the corresponding bit according to the mapping in table 35-23 is set in the short-circuit detector interrupt register. if this specific interrupt is also ena bled in the interrupt enable register mcsdien0 , than this event will rise an external interrupt.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-17 preliminary?subject to change without notice 35.3.2.14 short-circuit detector interrupt register 1 (mcsdi1) 35.3.2.15 short-circuit detector interrupt register 2 (mcsdi2) offset module base + 0x004d 01234567 rsdif w rwm rwm rwm rwm rwm rwm rwm rwm reset00000000 figure 35-15. short-circuit detector interrupt register 1 (mcsdi1) table 35-17. mcsdi1 field descriptions field description sdif short-circuit detector interrupt flag ? in case of a detected shor t-circuit, the corresponding bit according to the mapping in table 35-23 is set in the short-circuit detector interrupt register. if this specific interrupt is also ena bled in the interrupt enable register mcsdien1 , than this event will rise an external interrupt. offset module base + 0x004e 01234567 rsdif w rwm rwm rwm rwm rwm rwm rwm rwm reset00000000 figure 35-16. short-circuit detector interrupt register 2 (mcsdi2) table 35-18. mcsdi2 field descriptions field descriptions sdif short-circuit detector interrupt flag ? in case of a detected shor t-circuit, the corresponding bit according to the mapping in table 35-23 is set in the short-circuit detector interrupt register. if this specific interrupt is also ena bled in the interrupt enable register mcsdien2 , than this event will rise an external interrupt.
pxd10 microcontroller reference manual, rev. 1 35-18 freescale semiconductor preliminary?subject to change without notice 35.4 functional description 35.4.1 modes of operation 35.4.1.1 pwm output modes the smc is configured between three output modes. ? dual full h-bridge mode can be used to control either a stepper motor or a 360 ? air core instrument. in this case two pwm channels are combined. ? in full h-bridge mode, each pw m channel is updated independently. ? in half h-bridge mode, one pin of the pwm ch annel can generate a pwm signal to control a 90 ? air core instrument (or other load requiri ng a pwm signal) and the other pin is unused. the mode of operation for pwm channel x is determined by th e output mode bits mcccx [mcom]. after a reset occurs, each pwm channel will be disabled, the corresponding pins are released. each pwm channel consists of tw o pins. one output pin will genera te a pwm signal. the other will operate as logic high or low output dependi ng on the state of the recirculation bit mcctl1 [recirc] (refer to section 35.4.1.3.3, recirculati on bit (mcctl1[recirc])? ), while in (dual) full h-bridge mode, or will be released, whil e in half h-bridge mode. the state of the sign bit mcdcx [sign[4]] in the duty cycle register determines the pin where the pwm signal is driven in full h-bri dge mode. while in half h-bridge mode, the state of the released pin is de termined by other modules as sociated with this pin. associated with each pwm cha nnel pair n are two pwm channels, x and x + 1, where x = 2 * n and n (0,1,2... 5) is the pwm channel pair number. duty cycl e register x controls the sign of the pwm signal (which pin drives the pwm signal) and the duty cy cle of the pwm signal for smc channel x. the pins associated with pwm channel x are mnc0p and mnc0m. similarly, duty cycle register x + 1 controls the sign of the pwm signal and the duty cycle of the pwm signal for channel x + 1. the pins associated with pwm channel x + 1 are mnc1p and mnc1m. this is summarized in table 35-19 . table 35-19. corresponding registers and pin names for each pwm channel pair pwm channel pair number pwm channel control register duty cycle register channel number pin names n mcccx mcdcx pwm channel x, x = 2 ? n mnc0m mnc0p mcccx +1 mcdcx +1 pwm channel x+1, x = 2 ? n mnc1m mnc1p 0 mccc0 mcdc0 pwm channel 0 m0c0m m0c0p mccc1 mcdc1 pwm channel 1 m0c1m m0c1p
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-19 preliminary?subject to change without notice 35.4.1.1.1 dual full h-bridge mode pwm channel pairs x and x + 1 operate in dual full h-bridge mode if both channels are enabled ( mcccx [mcam]=0x1, 0x2, or 0x3) and the output mode bits mcccx [mcom] in both pwm channel control registers are set to 0x3. a typical configuration in dual fu ll h-bridge mode is shown in figure 35-17 . pwm channel x drives the pwm output signal on either mnc0p or mnc0m. if mnc0p drives the pwm signal, mnc0m will be output either high or low depending on the mcctl1 [recirc] bit. if mnc0m drives the pwm signal, mnc0p will be an output high or low. pwm channel x + 1 drives the pwm output signal on either mnc1p or mnc1m. if mnc1p drives the pw m signal, mnc1m will be an output high or low. if mnc1m drives the pwm signal, mnc1p will be an out put high or low. this results in motor recirculation currents on the high side drivers ( mcctl1 [recirc] = 0) while the pwm signal is at a logic high level, or motor recirculation currents on the low side drivers ( mcctl1 [recirc] = 1) while the pwm signal is at a logic low level. the pin driving the pwm signal is determined by the sign bit mcdcx [sign[4]] for the corresponding channel and the state of the mcctl1 [recirc] bit. the value of the pwm duty cycle is determined by the value of the duty cycle bits mcdcx [duty] for the corresponding channel. 1 mccc2 mcdc2 pwm channel 2 m1c0m m1c0p mccc3 mcdc3 pwm channel 3 m1c1m m1c1p 2 mccc4 mcdc4 pwm channel 4 m2c0m m2c0p mccc5 mcdc5 pwm channel 5 m2c1m m2c1p 3 mccc6 mcdc6 pwm channel 6 m3c0m m3c0p mccc7 mcdc7 pwm channel 7 m3c1m m3c1p 4 mccc8 mcdc8 pwm channel 8 m4c0m m4c0p mccc9 mcdc9 pwm channel 9 m4c1m m4c1p 5 mccc10 mcdc10 pwm channel 10 m5c0m m5c0p mccc11 mcdc11 pwm channel 11 m5c1m m5c1p table 35-19. corresponding registers and pin names for each pwm channel pair (continued) pwm channel pair number pwm channel control register duty cycle register channel number pin names
pxd10 microcontroller reference manual, rev. 1 35-20 freescale semiconductor preliminary?subject to change without notice figure 35-17. typical dual full h-bridge mode configuration 16-bit write accesses to the duty cycle registers ar e allowed, 8-bit write accesse s can lead to unpredictable duty cycles. the following sequence should be used to update the current magnitude and direction for coil 0 and coil 1 of the motor to achieve consistent pwm output: 1. write to duty cycle register x 2. write to duty cycle register x + 1 at the next timer counter overflow, the duty cycle re gisters will be copied to the working duty cycle registers. sequential writes to the duty cycle register x will result in the previous data being overwritten. 35.4.1.1.2 full h-bridge mode in full h-bridge mode ( mcccx [mcom]=0x2), the pwm channels x and x + 1 operate independently. the duty cycle working registers are updated whenever a timer counter overflow occurs. 35.4.1.1.3 half h-bridge mode in half h-bridge mode ( mcccx [mcom] = 0x0 or 0x1), the pwm channels x and x + 1 operate independently. in this mode, each pwm channel can be configured such that one pin is released and the other pin is a pwm output. figure 35-18 shows a typical configurati on in half h-bridge mode. the two pins associated with each channel are sw itchable between released mode and pwm output dependent upon the state of the output mode bits mcccx [mcom]. see register description in section 35.3.2.4, motor controller channel control register (mccc0..11)? . in half h-bridge mode, the state of the mcdcx [sign[4]] bit has no effect. pwm channel x pwm channel x + 1 mnc0p mnc0m mnc1p mnc1m motor n, coil 0 motor n, coil 1
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-21 preliminary?subject to change without notice figure 35-18. typical quad half h-bridge mode configuration 35.4.1.2 relationship between pw m mode and pwm channel enable the pair of smc channels cannot be placed into dua l full h-bridge mode unles s both smc channels have been enabled ( mcccx [mcam] not equal to 0) and dual full h- bridge mode is selected for both pwm channels ( mcccx [mcom] = 0x3). if only one channe l is set to dual full h-bri dge mode, this channel will operate in full h-bridge m ode, the other as programmed. 35.4.1.3 relationship between sign , duty, dither, recirc, period, and pwm mode functions 35.4.1.3.1 pwm alignment modes each pwm channel can be programmed individually to three different alignment modes. the alignment mode is determined by the mcccx [mcam] bits in the corresponding channel control register. left aligned ( mcccx [mcam] = 0x1): the output wi ll start active (low if mcctl1 [recirc] = 0 or high if mcctl1 [recirc] = 1) and will turn inactive (high if mcctl1 [recirc] = 0 or low if mcctl1 [recirc] = 1) after the number of counts spec ified by the corresponding duty cycle register. pwm channel x pwm channel x + 1 mnc0p mnc0m mnc1p mnc1m released pwm output v ssm v ddm v ssm v ddm released pwm output
pxd10 microcontroller reference manual, rev. 1 35-22 freescale semiconductor preliminary?subject to change without notice figure 35-19. left aligned right aligned ( mcccx [mcam] = 0x2): the output wi ll start inactive (high if mcctl1 [recirc] = 0 and low if mcctl1 [recirc] = 1) and will turn act ive after the number of counts spec ified by the difference of the contents of period register and the corresponding duty cycle register. figure 35-20. right aligned center aligned ( mcccx [mcam] = 0x3): even periods will be out put left aligned, odd periods will be output right aligned. pwm ope ration starts with the even period af ter the channel has been enabled. pwm operation in center aligned mode might start with the od d period if the channel has not been disabled before changing the alignment mode to center aligned. 0 15 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 1 period 100 counts 15 99 99 mcctl0[dith] = 0, mcccx[mcam] = 0x1, mcdcx[duty] = 15, mcper[per] = 100, mcctl1[recirc] = 0 0 85 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 1 period 100 counts 85 99 99 mcctl0[dith] = 0, mcccx[mcam] = 0x2, mcdcx[duty] = 15, mcper[per] = 100, mcctl1[recirc] = 0
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-23 preliminary?subject to change without notice figure 35-21. center aligned 35.4.1.3.2 sign bit ( mcdcx [sign]) assuming mcctl1 [recirc] = 0 (the active state of the pwm signal is low), when the mcdcx [sign[4]] bit for the corresponding channel is cleared, mnc0p (if the pwm channel number is even, n = 0, 1, 2...5, see table 35-19 ) or mnc1p (if the pwm channel number is odd, n = 0, 1, 2...5 see table 35-19 ), outputs a logic high while in (dual) full h-br idge mode. in half h-br idge mode the state of the mcdcx [sign[4]] bit has no effect. the pwm output signal is generated on mnc0m (if the pwm channel number is even, n = 0, 1, 2...5, see table 35-19 ) or mnc1m (if the pwm channel number is odd, n = 0, 1, 2...5). assuming mcctl1 [recirc] = 0 (the active state of the pwm signal is low), when the mcdcx [sign[4]] bit for the corresponding channel is set, mnc0m (if th e pwm channel number is even, n = 0, 1, 2...5, see table 35-19 ) or mnc1m (if the pwm channel number is odd, n = 0, 1, 2...5, see table 35-19 ), outputs a logic high while in (dual) full h-br idge mode. in half h-br idge mode the state of the mcdcx [sign[4]] bit has no effect. the pwm output signal is generated on mnc0p (if the pwm channel number is even, n = 0, 1, 2...5, see table 35-19 ) or mnc1p (if the pwm channel number is odd, n = 0, 1, 2...5). setting mcctl1 [recirc] = 1 will also i nvert the effect of the mcdcx [sign[4]] bit such that while mcdcx [sign[4]] = 0, mnc0p or mnc1p will generate the pwm signal and mnc0m or mnc1m will be a static low output. while mcdcx [sign[4]] = 1, mnc0m or mnc1m w ill generate the pwm signal and mnc0p or mnc1p will be a static lo w output. in this case the active state of the pwm signal will be high. see table 35-20 for detailed information about the impact of mcdcx [sign[4]] and mcctl1 [recirc] bit on the pwm output. table 35-20. impact of mcctl1 [recirc] and mcdcx [sign[4]] bit on the pwm output output mode mcctl1 [recirc] mcdcx [sign[4]] mncym mncyp (dual) full h-bridge 0 0 pwm 1 1 (dual) full h-bridge 0 1 1 pwm 0 85 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 1 period 100 counts 15 99 99 mcctl0[dith] = 0, mcccx[mca m] = 0x3, mcdcx[duty] = 15, mcper[per] = 100, mcctl1[recirc] = 0
pxd10 microcontroller reference manual, rev. 1 35-24 freescale semiconductor preliminary?subject to change without notice 35.4.1.3.3 recirculation bit ( mcctl1 [recirc]) the mcctl1 [recirc] bit controls the flow of the r ecirculation current of the load. setting mcctl1 [recirc] = 0 will cause recirc ulation current to fl ow through the high side transistors, and mcctl1 [recirc] = 1 will cause the recirculation current to flow through the low side transistors. the mcctl1 [recirc] bit is only active in (dual) full h-bridge modes. effectively, mcctl1 [recirc] = 0 will cause a static high out put on the output terminal not driven by the pwm, mcctl1 [recirc] = 1 will cause a st atic low output on the output terminals not driven by the pwm. to achieve the same current direction, the mcdcx [sign[4]] bit behavior is inverted if mcctl1 [recirc] = 1. figure 35-22 , figure 35-23 , figure 35-24 , and figure 35-25 illustrate the effect of the mcctl1 [recirc] bit in (dual) full h-bridge modes. mcctl1 [recirc] bit must be changed onl y while no pwm channel is operat ed in (dual) full h-bridge mode. (dual) full h-bridge 1 0 0 pwm 2 (dual) full h-bridge 1 1 pwm 0 half h-bridge: pwm on mncym don?t care don?t care pwm ? 3 half h-bridge: pwm on mncyp don?t care don?t care ? pwm 1 pwm : the pwm signal is low active. e.g., the waveform starts with 0 in left aligned mode. output m generates the pwm signal. output p is static high. 2 pwm: the pwm signal is high active. e.g., the waveform st arts with 1 in left aligned mode. output p generates the pwm signal. output m is static low. 3 the state of the output transist ors is not controlled by the smc. table 35-20. impact of mcctl1 [recirc] and mcdcx [sign[4]] bit on the pwm output (continued) output mode mcctl1 [recirc] mcdcx [sign[4]] mncym mncyp
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-25 preliminary?subject to change without notice figure 35-22. pwm active phase, mcctl1 [recirc] = 0, mcdcx [sign[4]] = 0 figure 35-23. pwm passive phase, mcctl1 [recirc] = 0, mcdcx [sign[4]] = 0 v ddm v ssm mnc0p mnc0m static 0 pwm 1 pwm 1 static 0 v ddm v ssm mnc0p mnc0m static 0 pwm 0 static 0 pwm 0
pxd10 microcontroller reference manual, rev. 1 35-26 freescale semiconductor preliminary?subject to change without notice figure 35-24. pwm active phase, mcctl1 [recirc] = 1, mcdcx [sign[4]] = 0 figure 35-25. pwm passive phase, mcctl1 [recirc] = 1, mcdcx [sign[4]] = 0 35.4.1.3.4 relationship between mcctl1 [recirc] bit, mcdcx [sign[4]] bit, mcccx [mcom] bits, pwm state, and output transistors please refer to figure 35-26 for the output tran sistor assignment. v ssm mnc0p mnc0m v ddm static 1 static 1 pwm 0 pwm 0 v ddm v ssm mnc0p mnc0m static 1 static 1 pwm 1 pwm 1
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-27 preliminary?subject to change without notice figure 35-26. output transistor assignment table 35-21 illustrates the state of the out put transistors in diff erent states of the smc module. ??? means that the state of the output transi stor is not controlled by the smc. table 35-21. state of output transistors in various modes mode mcccx [mcom] pwm duty 1 1 when in (dual) full mode and recirc=0, the pwm is 0 when the duty cycle is active and 1 when it is passive. when recirc = 1, the opposite is true. mcctl1 [recirc] mcdcx [sign[4]] t1 t2 t3 t4 mnc ym mnc yp off don?t care ? don?t care don?t care?????? half h-bridge 0x0 active don?t care don?t care ? ? off on 0 ? half h-bridge 0x0 passive don?t care don?t care ? ? on off 1 ? half h-bridge 0x1 active don?t care don?t care off on ? ? ? 0 half h-bridge 0x1 passive don?t care don?t care on off ? ? ? 1 (dual) full 0x2 or 0x3 active 0 0 on off off on 0 1 (dual) full 0x2 or 0x3 passive 0 0 on off on off 1 1 (dual) full 0x2 or 0x3 active 0 1 off on on off 1 0 (dual) full 0x2 or 0x3 passive 0 1 on off on off 1 1 (dual) full 0x2 or 0x3 active 1 0 on off off on 0 1 (dual) full 0x2 or 0x3 passive 1 0 off on off on 0 0 (dual) full 0x2 or 0x3 active 1 1 off on on off 1 0 (dual) full 0x2 or 0x3 passive 1 1 off on off on 0 0 v ddm v ssm mncyp mncym t1 t2 t3 t4
pxd10 microcontroller reference manual, rev. 1 35-28 freescale semiconductor preliminary?subject to change without notice 35.4.1.3.5 dither bit ( mcctl0 [dith]) the purpose of the dither mode is to increase the minimum length of output pulses without decreasing the pwm resolution, in order to limit the pulse distortion in troduced by the slew rate control of the outputs. if dither mode is selected the output pattern will repeat after tw o timer counter overflows. for the same output frequency, the shortest output pulse will have twice the length while dither feature is selected. to achieve the same output frame frequency, the presca ler of the smc module has to be set to twice the division rate if dither mode is sele cted; e.g., with the same prescaler di vision rate the repeat rate of the output pattern is the same as well as the shortest output pulse with or without dither mode selected. the mcctl0 [dith] bit enables or disables the dither function. mcctl0 [dith] = 0: dither function is disabled. when mcctl0 [dith] is cleared and assumin g left aligned operation and mcctl1 [recirc] = 0, the pwm output will start at a logic lo w level at the beginning of the pw m period (motor controller timer counter = 0x000). the pwm output re mains low until the motor contro ller timer counter matches the 11-bit pwm duty cycle value mcdcx [duty]. when a match (output co mpare between motor controller timer counter and mcdcx [duty]) occurs, the pwm output will t oggle to a logic high level and will remain at a logic high leve l until the motor controller timer counter overflows (r eaches the contents of mcper [per] ? 1). after the motor controller timer c ounter resets to 0x000, the pwm output will return to a logic low level. this completes one pwm period. the pwm period repeats every mcper [per] counts of the motor controller timer counter. if mcdcx [duty] >= mcper [per], the output will be static low. if mcdcx [duty] = 0, the output will be continuously at a logic high level. the relationship between the motor controll er timer counter clock, motor controller timer counter value, and pwm output while mcctl0 [dith] = 0 is shown in figure 35-27 . figure 35-27. pwm output: mcctl0 [dith] = 0, mcccx [mcam] = 0x1, mcdcx [duty] = 100, mcper [per] = 200, mcctl1 [recirc] = 0 mcctl0 [dith] = 1: dither function is enabled please note if mcctl0 [dith] = 1, the bit mcper [per[0]] will be internally forced to 0 and read always as 0. when mcctl0 [dith] is set and assuming left aligned operation and mcctl1 [recirc] = 0, the pwm output will start at a logic low le vel at the beginning of the pwm peri od (when the motor controller timer counter = 0). the pwm output remain s low until the motor controller timer counter matches the 10-bit 0100 0 100 0 pwm output 1 period 200 counts 200 counts 1 period motor controller timer counter clock motor controller timer counter 199 199
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-29 preliminary?subject to change without notice pwm duty cycle value mcdcx [duty]. when a match (output compar e between motor controller timer counter and mcdcx [duty]) occurs, the pwm output will toggle to a logic high level and will remain at a logic high level until the motor controller timer counter overflows (reach es the value defined by mcper [per[10:1]] ? 1). after the motor controller time r counter resets to 0x000, the pwm output will return to a logic low level. this completes the first half of the pwm pe riod. during the second half of the pwm period, the pwm output will remain at a logic low level until either the motor controller timer counter matches the 10-bit pwm duty cycle value mcdcx [duty] if mcdcx [duty[0]]= 0, or the motor controller timer counter matches the 10-bit pwm duty cycle value + 1 (the value of mcdcx [duty[10:1]] is incremented by 1 and is compared with the motor controller timer counter value) if mcdcx [duty[0]] = 1 for the corresponding channel. when a match occurs, the pwm output will toggle to a logic high level and will remain at a logi c high level until the motor controller timer counter overflows (reaches th e value defined by mcper [per[10:1]] ? 1). af ter the motor controller timer counter resets to 0x000, the pwm output will return to a logic low level. this process will repeat every numbe r of counts of the moto r controller timer count er defined by the period register contents ( mcper [per]). if the output is neither set to 0% nor to 100% there will be four edges on the pwm output per pwm period in this case. th erefore, the pwm output compare function will alternate between mcdcx [duty] and mcdcx [duty] + 1 every half pwm period if mcdcx [duty[0]] for the corresponding channel is se t to 1. the relationship between the motor controller timer counter clock (f tc ), motor controller timer counter va lue, and left ali gned pwm output if mcctl0 [dith] = 1 is shown in figure 35-28 and figure 35-29 . figure 35-30 and figure 35-31 show right aligned and center aligned pwm operation re spectively, with dither feature enabled and mcdcx [duty[0]] = 1. please note: in the following examples, the mcper [per] value, which is, if mcctl0 [dith] = 1, always an even number. note the mcctl0 [dith] bit must be changed only if the smc is disabled (all channels disabled or pe riod register cleared) to avoid erroneous waveforms. figure 35-28. pwm output: mcctl0 [dith] = 1, mcccx [mcam] = 0x1, mcdcx [duty] = 31, mcper [per] = 200, mcctl1 [recirc] = 0 0 15 pwm output 16 0 100 counts motor controller timer counter motor controller timer counter clock 0 16 1 period 100 counts 15 99 99
pxd10 microcontroller reference manual, rev. 1 35-30 freescale semiconductor preliminary?subject to change without notice figure 35-29. pwm output: mcctl0 [dith] = 1, mcccx [mcam] = 0x1, mcdcx [duty] = 30, mcper [per] = 200, mcctl1 [recirc] = 0 . figure 35-30. pwm output: mcctl0 [dith] = 1, mcccx [mcam] = 0x2, mcdcx [duty] = 31, mcper [per] = 200, mcctl1 [recirc] = 0 figure 35-31. pwm output: mcctl0 [dith] = 1, mcccx [mcam] = 0x3, mcdcx [duty] = 31, mcper [per] = 200, mcctl1 [recirc] = 0 pwm output 1 period 100 counts motor controller timer counter motor controller timer counter clock 100 counts 015 16 0 0 16 15 99 99 0 84 pwm output 85 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 85 100 counts 84 99 99 0 84 pwm output 0 1 period 100 counts motor controller timer counter motor controller timer counter clock 0 100 counts 15 99 99
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-31 preliminary?subject to change without notice 35.4.2 pwm duty cycle the pwm duty cycle for the smc cha nnel x can be determined by dividi ng the decimal representation of the bits mcdcx [duty] by the decimal representation of the bits mcper [per] and multiplying the result by 100% as shown in equation 35-1 . eqn. 35-1 note x = pwm channel number = 0, 1, 2, 3 ... 11. this equa tion is only valid if mcdcx [duty] <= mcper [per] and mcper [per] is not equal to 0. whenever mcdcx [duty] >= mcper [per], a constant low level ( mcctl1 [recirc] = 0) or high level ( mcctl1 [recirc] = 1) wi ll be output. 35.4.3 motor controller counter clock source figure 35-32 shows how the pwm motor controller tim er counter clock source is selected. figure 35-32. motor controller counter clock selection the peripheral bus clock is the source for the motor controller counter prescaler. the motor controller counter clock rate, f tc , is set by selecting the appropriate prescaler value. the prescaler is selected with the mcctl0 [mcpre] bits. the smc channel frequency of operation can be calculated using equation 35-2 if mcctl0 [dith] = 0. eqn. 35-2 the smc channel freque ncy of operation can be calculated using equation 35-3 if mcctl0 [dith] = 1. eqn. 35-3 effective pwm channel x % duty cycle duty mcper ------------ --------- 100% ? = 1 1/2 1/4 1/8 motor controller timer counter prescaler motor controller timer counter clock prescaler select mppre0, mppre1 11-bit motor controller timer counter peripheral bus clock f bus clock generator clk clocks and reset generator module motor controller timer counter clock f tc motor channel frequency (hz) f tc mcper m ? ----------------- -------------- = motor channel frequency (hz) f tc mcper m 2 ? ? -------------------- ------------------ =
pxd10 microcontroller reference manual, rev. 1 35-32 freescale semiconductor preliminary?subject to change without notice note both equations ar e only valid if mcper [per] is not equal to 0. m = 1 for left or right aligned mode, m = 2 for center aligned mode. table 35-22 shows examples of the smc channel frequenc ies that can be generated based on different peripheral bus clock frequenc ies and the prescaler value. note due to the selectable slew rate contro l of the outputs, cl ipping may occur on short output pulses. 35.4.4 output switching delay in order to prevent large peak curr ent draw from the motor power supply, selectable delays can be used to stagger the high logic level to low logic level tr ansitions on the smc outputs. the timing delay, t d , is determined by the mcccx [cd] bits in the corresponding channel control register and is selectable between 0, 1, 2, or 3 motor controller timer counter clock cycles. note a pwm channel gets disabled at the next timer counter overflow without notice of the switching delay. 35.4.5 operation in smc stop mode all module clocks are stoppe d and the associated port pins are set to their inactive state, which is defined by the state of the mcctl1 [recirc] bit. the smc modul e registers stay the same as they were prior to entering stop mode. therefore, after exiting from stop mode, the associat ed port pins will resume to the same functionality they had prior to entering stop mode. 35.4.6 short-circuit detection each pwm pin is equipped with a s hort-circuit detection f unction. hence, 24 instances (4 for each pwm module) of the short-ci rcuit detector exist. table 35-22. smc channel frequencies (hz), mcper [per] = 256, mcctl0 [dith] = 0, mcccx [mcam] = 0x2, 0x1 prescaler peripheral bus clock frequency 16 mhz 10 mhz 8 mhz 5 mhz 4 mhz 1 62500 39063 31250 19531 15625 1/2 31250 19531 15625 9766 7813 1/4 15625 9766 7813 4883 3906 1/8 7813 4883 3906 2441 1953
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-33 preliminary?subject to change without notice each single short-circuit detector is a timer, meas uring the time during which th e signals pwm and fb are not equal (see figure 35-33 ). if this time is greater than or equal to the ti me represented by mcsdto [tout], then a short- circuit is assumed. to enable the short-circuit detector on a pin, ensure that the pin?s input buffer is enabled in the corresponding pad configuration register in the siu module. table 35-23. cross-reference pwm signal to short-circuit detector register bits short- circuit detector index sd pwm channel pin name related sd enable bit (see 35.3.2.7) related sd int enable bit (see 35.3.2.10) related sd int bit (see 35.3.2.13) 23 10 m5c0m mcsde2[sden[7]] mcsdien2[sdie[7]] mcsdi2[sdif[7]] 22 8 m4c0m mcsde2[sden[6]] mcsdien2[sdie[6]] mcsdi2[sdif[6]] 21 6 m3c0m mcsde2[sden[5]] mcsdien2[sdie[5]] mcsdi2[sdif[5]] 20 4 m2c0m mcsde2[sden[4]] mcsdien2[sdie[4]] mcsdi2[sdif[4]] 19 2 m1c0m mcsde2[sden[3]] mcsdien2[sdie[3]] mcsdi2[sdif[3]] 18 0 m0c0m mcsde2[sden[2]] mcsdien2[sdie[2]] mcsdi2[sdif[2]] 17 11 m5c1m mcsde2[sden[1]] mcsdien2[sdie[1]] mcsdi2[sdif[1]] 16 9 m4c1m mcsde2[sden[0]] mcsdien2[sdie[0]] mcsdi2[sdif[0]] 15 7 m3c1m mcsde1[sden[7]] mcsdien1[sdie[7]] mcsdi1[sdif[7]] 14 5 m2c1m mcsde1[sden[6]] mcsdien1[sdie[6]] mcsdi1[sdif[6]] 13 3 m1c1m mcsde1[sden[5]] mcsdien1[sdie[5]] mcsdi1[sdif[5]] 12 1 m0c1m mcsde1[sden[4]] mcsdien1[sdie[4]] mcsdi1[sdif[4]] 11 10 m5c0p mcsde1[sden[3]] mcsdien1[sdie[3]] mcsdi1[sdif[3]] 10 8 m4c0p mcsde1[sden[2]] mcsdien1[sdie[2]] mcsdi1[sdif[2]] 9 6 m3c0p mcsde1[sden[1]] mcsdien1[sdie[1]] mcsdi1[sdif[1]] 8 4 m2c0p mcsde1[sden[0]] mcsdien1[sdie[0]] mcsdi1[sdif[0]] 7 2 m1c0p mcsde0[sden[7]] mcsdien0[sdie[7]] mcsdi0[sdif[7]] 6 0 m0c0p mcsde0[sden[6]] mcsdien0[sdie[6]] mcsdi0[sdif[6]] 5 11 m5c1p mcsde0[sden[5]] mcsdien0[sdie[5]] mcsdi0[sdif[5]] 4 9 m4c1p mcsde0[sden[4]] mcsdien0[sdie[4]] mcsdi0[sdif[4]] 3 7 m3c1p mcsde0[sden[3]] mcsdien0[sdie[3]] mcsdi0[sdif[3]] 2 5 m2c1p mcsde0[sden[2]] mcsdien0[sdie[2]] mcsdi0[sdif[2]] 1 3 m1c1p mcsde0[sden[1]] mcsdien0[sdie[1]] mcsdi0[sdif[1]] 0 1 m0c1p mcsde0[sden[0]] mcsdien0[sdie[0]] mcsdi0[sdif[0]]
pxd10 microcontroller reference manual, rev. 1 35-34 freescale semiconductor preliminary?subject to change without notice figure 35-33. short-circuit detector overview pwm generator pwm fb timer tout mcsden[sden[sd]] mcsdin[sdif[sd]] motor pin i dff dff and synchronizer
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-35 preliminary?subject to change without notice figure 35-34. example for mcsdto [tout] = 4 ? hence, if pwm != fb, the timer starts counting if the short-circuit detector is enabled at least one clock cycle before (see mcsde0 , mcsde1 or mcsde2 ?) ? if pwm == fb, the timer stops and is reset to the time-out value mcsdto [tout] in order to be ready for the next transaction ? if pwm != fb and the timer state is larger or equal mcsdto [tout], than ? one of the interrupt flags mcsdi0 [sdif], mcsde1 [sdif] or mcsdi2 [sdif] is set in order to flag a short-circuit. ? the interrupt flag is cleared by writing one, by reset or by disabling th e short-circuit detector ? the timer is stopped and reloaded with the time-out value mcsdto [tout] in order to be ready for the next transaction ? if a short-circuit det ector is disabled ( mcsden [sden[ sd ]] == 0), the related short-circuit detector counter is halted and preloaded with the register value of mcsdto [tout]. the related bit in mcsdin [sdif[ sd ]] of this specific short-ci rcuit detector is set to 0. this means that, if all short-circuit detectors ar e disabled, all bits of mcsdin stay at 0. no interrupt from the detector can be generated independently of the interrupt mask in mcsdienn . ? in case of low power-modes, the state of the short-ci rcuit detector is frozen. after exit of the low power mode, the short-circ uit detector will resume operation from the previous state. if the short-circuit detector s hould restart with define d state (counter value = mcsdto [tout], than the related detector shall be disabled and enabled again. this will reload the counter with the mcsdto [tout] value and restart th e short-circuit detector. pwm fb_sample 4 2 1 04 counter mcsdin[sdif[sd ]] interrupt flag clk t_sample :sample and synchronization delay t_diff :delay between fb at pin and the internal pwm signal pwm :signal from motor controller fb at pin :this is the signal directly after the input driver of the pad s ignal fb_sample :pad signal after sampling and synchronization t_sample 3 fb at pin 4 t_diff
pxd10 microcontroller reference manual, rev. 1 35-36 freescale semiconductor preliminary?subject to change without notice the maximum time span which the timer can cover depends on the cloc k frequency f of the main clock. the maximum delay d covered by the counter is d = mcsdto [tout]* f. due to sampling and syn- chronization of the feedback signal, the value of mcsdto [tout] must always be larger than 2. the two synchronizer stages imply also, that a a short-circuit with a duration of less than or equal to 2 clock cycles cannot be detected. two special cases shall be highlighted: ? static short-circuit to ground and pwm signal = 1 see figure 35-35 : in this case, the enable of the short-circuit detector starts the sampli ng process and the interrupt bit is set mcsdto [tout]+1 cycles after enabling th e short-circuit detector ? static short-circuit to vd d and pwm signal = 0 see figure 35-36 : in this case. the enable of the short-circuit detector starts the sampli ng process and the interrupt bit is set mcsdto [tout]+3 cycles after enabling the short-ci rcuit detector due to the sync hronizer which has been cleared during disable of the short-circuit detector figure 35-35. static short-circuit, pwm signal always at 1 and fb always at 0, mcsdto [tout]=3 pwm=1 fb_sample=0 3 2 1 00 counter mcsdin[sdif[sd ]] interrupt flag clk t_sample :sample and synchronization delay t_diff :delay between fb at pin and the internal pwm signal pwm :signal from motor controller fb at pin :this is the signal directly after the input driver of the pad s ignal fb_sample :pad signal after sampling and synchronization 3 fb at pin=0 3 en
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 35-37 preliminary?subject to change without notice figure 35-36. static short-circuit, pwm signal always at 0 and fb always at 1, mcsdto [tout]=3 note the short-circuit detection block doe s not disable a port in case of a short-circuit. it is task of the micr ocontroller to manage the event of a short-circuit. 35.5 reset the smc is reset by system reset. al l associated ports are released, al l registers of the smc module will switch to their reset state as defined in section 35.3.2, register description ?. 35.6 interrupts the smc has one interrupt output which is the bitwis e or function of 25 individual interrupt request sources: ? one time counter overflow interrupt: an interrupt will be requested when the mcctl1 [mctoie] bit in is set and the running pwm frame is finished. the interrupt is cleared by either setting the mcctl1 [mctoie] bit to 0 or to write a one to the mcctl0 [mctoif] bit ? 24 interrupts for the short-circuit detection, one for each pwm pin: whenever a short-circuit is detected on one pwm pin and the s hort-circuit detector enable bit mcsden [sden[ sd ]] is set, than the related interrupt flag mcsdin [sdif[ sd ]] is set according to the mapping shown in table 35-23 . the interrupt flag in mcsdin [sdif[ sd ]] will also rise an external interrupt if the pwm=0 fb_sample=1 3 3 2 10 counter mcsdin[sdif[sd ]] interrupt flag clk t_sample :sample and synchronization delay t_diff :delay between fb at pin and the internal pwm signal pwm :signal from motor controller fb at pin :this is the signal directly after the input driver of the pad s ignal fb_sample :pad signal after sampling and synchronization 3 fb at pin=1 en due to synchronizer
pxd10 microcontroller reference manual, rev. 1 35-38 freescale semiconductor preliminary?subject to change without notice interrupt enable bit mcsdienn [sdie[ sd ]] is set. to clear the interrupt flag, either write a one into the related bit position mcsdin [sdif[ sd ]] or disable the related shor t-circuit detect or by writing zero to mcsden [sden[ sd ]]. if the short-circuit detector is enabled and a static short-circuit exists, then the mcsdin [sdif[ sd ]] flag will be asserted direct ly after clearing it, because the short-circuit detector is still enab led and will detect the short-circuit again. to avoid this behavior, disable the short-circuit detector channe l after detection of the short-circuit. figure 35-37. smc interrupt generation mcsdi0 mcsdi1 mcsdi2 mctoif mcsdie0 mcsdie1 mcsdie2 mctoie 25 bits 25 bits bitwise and or of all input bits 25 bits interrupt request to host
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-1 preliminary?subject to change without notice chapter 36 stepper stall detect (ssd) 36.1 introduction 36.1.1 overview the ssd block connects to one stepper motor (sm) with two coils. it can be used to monitor the movement of the sm to detect that the attached gauge poi nter has reached the stal l position of the scale. basis of the movement detection is to drive one of the coil s and to integrate the back emf (electromotive force) induced in the other coil. this back emf is present only if the sm is rotating. therefore, if the integral of the back emf exceeds a certain threshold, th e sm is still rotating; othe rwise it can be regarded as being stalled. the ssd block shares the pins connected to the sm coils together with the motor controller block responsible for driving the sm in the main applicat ion (e.g. moving the gauge pointer to a certain position of the scale).
pxd10 microcontroller reference manual, rev. 1 36-2 freescale semiconductor preliminary?subject to change without notice figure 36-1. ssd overall block diagram the names of the sub blocks given in the diagra m above relate to the descriptions given in section 36.4.1, main building blocks of the ssd : ? ?analog block? relates to section 36.4.1.1, analog block . ? ?analog wrapper and port control? relates to section 36.4.1.2, analog wrapper + port control . analog block digital block sine cosine to/from stepper motor pads bis control analog wrapper + port control ?? - output ?? - fdbk register if ?? - output port control ips if port control offset cancellation down counter integration accumulator bis control ?? - fdbk
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-3 preliminary?subject to change without notice ? ?register interface? relates to section 36.4.1.3, register interface . ? ?bis (blanking-integration sequen ce) control logic? relates to section 36.4.1.4, bis control . 36.1.2 features the most important features of the ssd block are listed below: ? programmable full step states according to 2 coil stepper motors (4 states). ? programmable integration polarity ? integration accumulator of 16 bits with programmable clock divider. ? programmable down c ounter (16 bit timer). ? 64 mhz bus clock: finest resolution in time down to 125 ns, maximum length of blanking or integration phase for this case is ~8.2 ms. ? 64 mhz bus clock: maximum length of blanking or integration phase is 1.05 s, resolution in time reduced to 16 ? s for this case. ? automatic sequence of blanki ng followed by integration (bis) triggered by the user. ? full flexibility over blanking a nd integration phase of the bis: ? separate down counter initializati on values and divider factors. ? separate interrupt flags and interrupt enable bits ? separate coil drive enable bits. ? polarity switching to cancel dc offset erro rs programmable. the down counter value for the integration phase can be divided by 2, 4 or 8 to switch the polarity durin g the integration phase. additionally the offset cancellation can be switched off completely. ? seamless changeover into or from ssd (stepper stall detect) mode: the coil control signals outside of the bis are fully programmable. 36.1.3 modes of operation this section describes the different modes of operation of the ssd block. 36.1.3.1 disabled mode in this mode the ssd block is disabl ed. none of the sm coils is driven nor one of th e coils sensed. this is the case if the rtze bit in the control register is cleared. 36.1.3.2 normal mode in this mode the ssd block needs exclusive control over the sm coils. this must be ensured on at the device level. setting the rtze bit in the control register is not sufficient since the ssd does not provide a global port enable signal. refer to section 36.4, functional description ? for more details. 36.1.3.3 power down modes there are 2 different power down modes of the ssd block:
pxd10 microcontroller reference manual, rev. 1 36-4 freescale semiconductor preliminary?subject to change without notice 36.1.3.3.1 doze mode the cpu can send a signal to the ssd block to put it into doze mode. whethe r the ssd block obeys the signal and goes into doze mode depends on the setting of the dzdis bit in the control register. in doze mode the system clocks continue to run, but the cl ock signals are prevented fr om reaching the ssd block. when the ssd block is in doze mode, the analog block is also disabled. 36.1.3.3.2 stop mode the cpu can activate stop mode. in stop mode, the sy stem clocks driving the ssd block are stopped. in stop mode, the analog block is also disabled. 36.2 external signal description each of the four analog i/os of the ssd block is us ed either as the output of a half-bridge sourcing or sinking the current of the sm coil dr iven currently or - in case of acting as an input - the back emf of the non-driven coil with respect to an internally-generated refere nce voltage is supplied to the ?? -modulator of the analog block. the si gnal properties are given in table 36-1 . 36.3 memory map and register definition this section provides a detailed description of the re gisters of the ssd block. no te that all registers are 16 bits in width. there is no access on byte level. 36.3.1 memory map table 36-2 lists the registers of the ssd block. table 36-1. signal properties name port coil coil node i/o reset cosp cosp cosine plus analog i/o z cosm cosm minus analog i/o z sinp sinp sine plus analog i/o z sinm sinm minu sanalog i/oz table 36-2. block memory map offset register name (long) re gister name (short) access 1 location 0x00 ssd control and status register control r/w on page 6 0x02 ssd interrupt flag and enable register irq r/w on page 7 0x04 ssd integrator accumulator register itgacc r on page 8 0x06 ssd down counter count register dcnt r on page 8 0x08 ssd blanking counter load register blncntld r/w on page 9 0x0a ssd integration counter load register itgcntld r/w on page 9
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-5 preliminary?subject to change without notice 36.3.2 register summary figure 36-2 and table 36-3 below illustrate the different acce ss modes of some register bits. table 36-3 provides a key for regist er figures and tables. 36.3.3 register descriptions this section describes the individual bits of all the ssd registers. note that the details of the functional description linked to these bits is given in section 36.4, functional description ?. 0x0c ssd prescaler register prescale r/w on page 10 0x0e reserved 2 n/a ? 1 note that r/w registers may contain some read-only or write-only bits. 2 read access provides 0x0000. no write allowed. always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 36-2. key to register fields table 36-3. register conventions convention description depending on its placement in the read or write row, indicates that the bit is not readable or not writeable. fieldname identifies the field. its presence in the read or write row indicates that it can be read or written. register field types r read only. writing this bit has no effect . register content is updated in hardware. w write only. if no read value is given any read access will provide undefined results. refer to description of individual bits for additional effects of read. r/w standard read/write bit. only software can chang e the bit?s value (other than a hardware reset). w1c write one to clear. a status bit that can be read, and is cleared by writing a one. reset values 0 resets to zero. 1 resets to one. ? undefined at reset. u unaffected by reset. [ signal_name ] reset value is determined by polarity of indicated signal. table 36-2. block memory map (continued) offset register name (long) re gister name (short) access 1 location
pxd10 microcontroller reference manual, rev. 1 36-6 freescale semiconductor preliminary?subject to change without notice 36.3.3.1 ssd control and status register (control) figure 36-3 below describes the fields of th e main control (control) register: the function of the control register bits is shown in table 36-4 . offse t 0x00 access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0 step rcir itgdir blndcl itgdcl rtze 0blnst itgst 0 0 0 sdcpu dzdis wtrig reset0 0 0 0 0 0 0 0 0 0 0 000 0 0 figure 36-3. ssd control and status register (control) table 36-4. control register field description field description 15 trig - trigger blanking -> integration sequence (bis). 1 sequence of blanking -> integration is triggered. 0 no effect. 14-13 step - full step state. these bits determine which coil is driven for sm movement,. refer to table 36-11 for details of the step states. 00 select0 ? angle (east pole) state for the electromagnetic field in the sm. 01 select90 ? angle (north pole) state for the electromagnetic field in the sm. 10 select180 ? angle (west pole) state for the electromagnetic field in the sm. 11 select270 ? angle (south pole) state for the electromagnetic field in the sm. 12 rcir - blanking polarity for coil recirculation. refer to section 36.4, functional description,? for details of the recirculation mode. 1 coil recirculation via low side transistors (vssm, analog gnd). 0 coil recirculation via high side transistors (vddm, analog supply voltage). 11 itgdir - direction (polarity) of integration. refer to section 36.4.1.4.3, dc offset cancellation ? for details 10 blndcl - drive coil during blanking. 1 during the bis blanking phase the other coil is actually driven by the ssd block (genuine use case). 0 during the bis blanking phase the other coils is no t driven by the ssd. the sm will not move during blanking. 9 itgdcl - drive coil during integration and outside of any bis. 1 during the bis integration phase and outside of any bis the other coil is actually driven by the ssd block (genuine use case). outside of any bis the same coil is driven. 0 during the bis integration phase the other coils is not driven by the ssd. outside of any bis no coil is driven. the sm will not move during integration (not useful for ssd). 8 rtze - return to zero enable. this is in fact the enable bit of the ssd logic to take over control of the sm coils 1 . 1 control of the sm coils by the ssd block is enabled. 0 control of the sm coils by the ssd block is disabled. 6 blnst - blanking status. refer to section 36.1.3.2, normal mode ? for details. 1 the ssd block is currently in the blanking phase of an ongoing bis. 0 the ssd block is not in the blanking phase of an ongoing bis.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-7 preliminary?subject to change without notice 36.3.3.2 interrupt enable and flag register (irq) figure 36-4 below describes the fields of the inte rrupt enable and flag (irq) register: the function of the irq register bits is shown in table 36-5 . 5 itgst - integration status. refer to section 36.1.3.2, normal mode ? for details. 1 the ssd block is currently in the integration phase of an ongoing bis. 0 the ssd block is not in the integration phase of an ongoing bis. 1 sdcpu - ?? -modulator power up. setting this bit enables the analog block of the ssd and enables the clocking of the port control logic of the digital part. 1 analog block of the ssd is enabled. 0 analog block of the ssd is not enabled. 0 dzdis - doze mode disables ssd. refer to section 36.1.3.3.1, doze mode ?. 1 the digital part of the ssd is not clocked in doze mode. 0 the digital part of the ssd is clocked in doze mode 1 the application must switch off any other blocks possibly interfering with port control of the ssd block. offse t 0x02 access: user read/write 1514131211109876543210 r blnif itgif 00000 acov if blni e itgie 00 0 0 0 acov ie ww1c w1c w1c reset0000000000000000 figure 36-4. ssd interrupt flag and enable register (irq) table 36-5. irq register field description field description 15 blnif - blanking expired interrupt flag. 1 this flag is set when the bis blanking phase has expired. 0 no such event. 14 itgif - integration expired interrupt flag. 1 this flag is set when the bis integration phase has expired. 0 no such event. 8 acovif - accumulator overflow interrupt flag. 1 this flag is set when during the bis integration phase the integration logic attempted either to increment the itgacc register abov e 0x7fff or to decrement it below 0x8000. 0 no such event. 7 blnie - blanking expired interrupt enable. 1 a module interrupt will occur if the blnif bit is set. 0 the blnif flag will not trigger an interrupt on the ips_int output. table 36-4. control register field description (continued) field description
pxd10 microcontroller reference manual, rev. 1 36-8 freescale semiconductor preliminary?subject to change without notice 36.3.3.3 integration accumulator register (itgacc) figure 36-5 below describes the fields of the inte gration accumulator (itgacc) register: the function of the itgacc register bits is shown in table 36-6 . 36.3.3.4 down counter register (dcnt) figure 36-6 below describes the fields of th e down counter (dcnt) register: the function of the dcnt register bits is shown in table 36-7 . 6 itgie - integration expired interrupt enable. 1 a module interrupt will occur if the itgif bit is set. 0 the itgif flag will not trigger an interrupt on the ips_int output. 0 acovie - accumulator interrupt enable. 1 a module interrupt will occur if the acovif bit is set. 0 the acovif flag will not trigger an interrupt on the ips_int output. offset 0x04 access: user read/write 1514131211109876543210 ritgacc w reset0000000000000000 figure 36-5. ssd integration accumulator register (itgacc) table 36-6. itgacc register field description field description 15-0 itgacc - integration accumulator readout value. this 2?s complement register represents the accumulator register of the back emf integrator of the ssd block. refer to the functional description of the integrator for further details. offset 0x06 access: user read/write 1514131211109876543210 r dcnt w reset0000000000000000 figure 36-6. ssd down counter register (dcnt) table 36-5. irq register field description (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-9 preliminary?subject to change without notice 36.3.3.5 blanking counter load register (blncntld) figure 36-7 below describes the fields of the bl anking counter load (blncntld) register: the function of the blncntld register bits is shown in table 36-8 . 36.3.3.6 integration counter load register (itgcntld) figure 36-8 below describes the fields of the inte gration counter load (itgcntld) register: the function of the itgcntld register bits is shown in table 36-9 . table 36-7. dcnt regist er field description field description 15-0 dcnt - down counter value. this register represents the actual value of the down counter in unsigned format. refer to the functional description of the integrator for further details. offset 0x08 access: user read/write 1514131211109876543210 r blncntld w reset0000000000000000 figure 36-7. ssd blan king counter load re gister (blncntld) table 36-8. blncntld register field description field description 15-0 blncntld - blanking count load value. this register is programmed with the number of down counter periods belonging to the blanking phase of the followi ng biss. number format is unsigned. refer to the functional description of the integrator for further details. programming all 0?s into the blncntld register bits disables blanking completely. offset 0x0a access: user read/write 1514131211109876543210 r itgcntld w reset0000000000000000 figure 36-8. ssd integration count er load register (itgcntld)
pxd10 microcontroller reference manual, rev. 1 36-10 freescale semiconductor preliminary?subject to change without notice 36.3.3.7 ssd prescale and di vider register (prescale) figure 36-9 below describes the fields of the prescale and divider factor (prescale) register: the function of the prescale re gister bits is shown in table 36-10 below: table 36-9. itgcntld register field description field description 15-0 itgcntld - integration count load value. this regi ster is programmed with the number of down counter periods belonging to the integration phase of the foll owing biss. number format is unsigned. refer to the functional description of the integrator for further details. programming all 0?s into the itgcntld register bits disables integration completely. offset 0x0c access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r blndiv 0 itgdiv 00 offcnc 0 acdiv w reset0000000000000000 figure 36-9. ssd prescale and divider factor register (prescale) table 36-10. prescale register field description field description 14-12 blndiv - blanking counter clock divider select. t he frequency for updating the down counter in the blanking phase of the next biss is derived from the bus clock according to the formula = / (8 * 2 blndiv ) according to this formula the divider factors are: 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024 10-8 itgdiv - integration counter clock divider select. the frequency for updating the down counter in the integration phase of the next biss is derive d from the bus clock according to the formula = / (8 * 2 itgdiv ) according to this formula the divider factors are: 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-11 preliminary?subject to change without notice 36.4 functional description for all the descriptions given here it is assumed that the ssd block has gained exclusive control of the sm coils and the analog block is enabled appropriately. 36.4.1 main building blocks of the ssd the functional description given in th is chapter deals with the main f unctional blocks. it concentrates on the description of the implem ented functionality. refer to figure 36-1 for details. 36.4.1.1 analog block an overview of the analog block of the ssd block is given in figure 36-10 below. additionally the most important sub blocks of the digital part which are connected to the an alog blocks are shown in order to clarify the joint operation of the analog block and the digital part. 5-4 offcnc - offset cancellation polarity flip select. refer to section 36.4.1.4.3, dc offset cancellation ? for details of the offset cancellation mechanism. the offcnc bits set the pr eset value of the internal counter which determines the polarity flips during the integration phase. the preset value is derived from the itgcntld register value with the following divider factor: 00 0: selected polarity remains unchanged for all the time of the integration phase. 01 2: 1st polarity switch (and possibly a succeedin g one) occurs after [itgcntld div 2] dcnt ticks. 10 4: 1st polarity switch and succeeding one s occur after [itgcntld div 4] dcnt ticks. 11 8: 1st polarity switch and succeeding one s occur after [itgcntld div 8] dcnt ticks. if the itgcntld register value cannot be divided by the required factor an additi onal polarity flip occurs with a duration corresponding to the bits shifted out. 2-0 acdiv - accumulator sample clock divider select. the accumulator sample clock is derived from the bus clock according to the formula =/(8*2 acdiv ) according to this formula the divider factors are: 000 8 001 16 010 32 011 64 100 128 101 256 110 512 111 1024 the first itgacc register update occurs when (8 * 2 acdiv ) bus clocks have expired after the itgst bit has been set by the ssd block. table 36-10. prescale register field description (continued) field description
pxd10 microcontroller reference manual, rev. 1 36-12 freescale semiconductor preliminary?subject to change without notice figure 36-10. ssd block di agram, analog block main part of the analog block is the ?? -modulator. it is oper ational during the bis integration phase only (step 5 in section 36.4.2.2, details of the ssd measurement ?). the clock to update the feedback path is derived from the bus clock using the acdiv setting. the 1-bit output value provided to the digital part is used to increment or decrement the itgacc register. sine coil cosine coil bus vddm cosp cosm t1 t2 t3 vssm vddm t4 vssm s1 s3 s2 s4 vddm sinp sinm t5 t6 t7 vssm vddm t8 vssm s5 s7 s6 s8 offset cancellation vddm vssm r2 r2 r1 c1 + ? + ? down counter load register sigma-delta modulator + ref. voltage generation p a d p a d p a d p a d integrator reference dac integration accumulator down counter prescaler accumulator prescaler dff ssd_1mot analog block clock signals bis control separate for blanking and integration shaded down counter blocks: + ? down counter obe to pads clock
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-13 preliminary?subject to change without notice for the correct movement of the sm the sine and cosi ne coil connections to v ddm and vdds need to be set properly, depending from the a ngular position. this is achieved by enabling and disabling of the pad transistors t1 to t8. these pad transistors are not part of the ssd block, onl y the obe (output buffer enable) signals for the pads are provided. for the switch characteristics refer to section 36.4.1.2.1, transistor condition states ?. aside from the pad transistors the switches s1 to s8 determine which coil provides the back emf to the integrator in which polarity w.r.t. the reference vol tage. the switches are impl emented in the analog block of the ssd (denoted by shading them in the same manner like the analog block). the ?? -modulator is enabled by setting the sdcpu bit in the control register. to compensate for switching effects of the analog circui try the user must take into account sufficient start up time, described in section 36.5.1, analog block startup time ? prior to starting the bis. 36.4.1.2 analog wrapper + port control this sub block controls the outputs to the coils and the inputs to the analog block. refer to figure 36-10 for details. the most relevant bits of the control regi ster belonging to that functional block are: ? step bits: these 2 bit v ector has two functions. one function is to determine which coil is driven and whic h coil is connected to the ?? -modulator. additionally the direction of the current flow is selected with these bits. for cloc kwise direction of the sm movement the value must be decremented and for counter-clo ckwise movement it must be incremented when advancing from one step setting to the next. ? blndcl: this bit is the enable of the supply vo ltage to be routed to the coil driven in the appropriate step setting during the blanking phase of an ongoing bis. ? itgdcl: this bit is the enable of the supply vol tage to be routed to the coil driven in the appropriate step setting during the integrat ion phase of an ongoing bis. additionally it determines the coil drive se tting outside of any bis. ? itgdir: this bit is rele vant only in the integrati on phase. together with th e step bits the polarity of the integration is determined by enabling or di sabling the appropriate an alog switches. refer to section 36.4.1.4.3, dc offset cancellation ?. these control bits are translated into the appropriate switching sche me of the pad transistors and the ?? -modulator switches describe d below. note that it must be ensure d at the device level that the ssd block has exclusive control over the analog pads connected to the sm coils. additionally it is a preconditi on that the rtze bit in the control register is set. 36.4.1.2.1 transistor condition states the pad transistors t1 to t8 are responsible for connecting the sm coils to the analog supply voltages vddm and vdds. table 36-11 below shows the pad tr ansistor condition states implemented in the analog block. in the table the columns have the following meaning: ? step denotes the setting of the corr esponding bits in the control register. ? itgst reflects the status indicat or of the bis integration phase.
pxd10 microcontroller reference manual, rev. 1 36-14 freescale semiconductor preliminary?subject to change without notice ? ?resulting dcoil? is the (bis state depe ndent) resulting coil drive setting. see table 36-12 for how this setting is derived from the value of the control register. ? rcir denotes the setting of the corr esponding bit in the control register. table 36-12 below shows the logic dependency of the resulting coil drive from the internal state of the ssd block and from the setting of the different coil control bits in the control register: table 36-11. transistor condition states 1 1 ?x? means ?don?t care? ste p itgs t resulting dcoil rcirt1t2t3t4t5t6t7t8 remarks xx 1 0 x off off off off off off off off integration with no drive 00 0 0 0 off off off off on off on off blanking withno drive (rcir bit determines supply voltage for recirculation) 00 0 0 1 off off off off off on off on 01 0 0 0 on off on off off off off off 01 0 0 1 off on off on off off off off 10 0 0 0 off off off off on off on off 10 0 0 1 off off off off off on off on 11 0 0 0 on off on off off off off off 11 0 0 1 off on off on off off off off 00 0 1 0 on off off on on off on off cosine coil driven p->m 00 0 1 1 on off off on off on off on 00 1 1 x on off off on off off off off 01 0 1 0 on off on off on off off on sine coil driven p->m 01 0 1 1 off on off on on off off on 01 1 1 x off off off off on off off on 10 0 1 0 off on on off on off on off cosine coil driven m->p 10 0 1 1 off on on off off on off on 10 1 1 x off on on off off off off off 11 0 1 0 on off on off off on on off sine coil driven m->p 11 0 1 1 off on off on off on on off 11 1 1 x off off off off off on on off
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-15 preliminary?subject to change without notice 36.4.1.2.2 switch condition states the analog switches s1 to s8 are used to select the appropriate source and polar ity of the non-driven coil into the ?? -modulator for integration during the integrat ion phase of an ongoing bis. outside of the integration phase none of the switches is enabled. refer to table 36-13 below for details. note the value given in the column ?integration polarity? in table 36-13 is linked to the itgdir bit in the control register in the way described in section 36.4.1.4.3, dc offset cancellation ? below. 36.4.1.3 register interface the register interface processes the ips accesses from the device level. access size is 32 bits, the ssd block supports 16- and 32-bit accesses. table 36-12. generation of the ?resulting dcoil? blnst blndcl itgst itgdcl resulting dcoil remarks 0x 00 0 no running bis itgdcl determines result 11 1 0 0 x 0 running bis in blanking phase blndcl determines result 11 0 x 1 0 0 running bis in integration phase itgdcl determines result 11 table 36-13. switch condition states itgst step (register bit) integration polarity (input to analog block) s1 s2 s3 s4 s5 s6 s7 s8 0 xx x open open open open open open open open 1 00 0 open open open open close open open close 1 00 1 open open open open open close close open 1 01 0 open close close open open open open open 1 01 1 close open open close open open open open 1 10 0 open open open open open close close open 1 10 1 open open open open close open open close 1 11 0 close open open close open open open open 1 11 1 open close close open open open open open
pxd10 microcontroller reference manual, rev. 1 36-16 freescale semiconductor preliminary?subject to change without notice any write access on byte-level is ignored. all reserved registers provide 0x0000 on read. write access is not allowed. 36.4.1.4 bis control once triggered the sequence control logic walks through a single individua l bis. in the normal application one bis corresponds to a single step (90 ? movement of the sm). in detail the bis is implemented in the ssd block in the following way: ? each bis starts with setting the trig bit. ending a running bis manually is only possibly by clearing the rtze bit. ? if the blncntld register is set to a valu e other than 0x0000 the dcnt is loaded with (blncntld - 1) and is started using the blndiv bit setting for the clock divider. the blnst is set. the blanking phase of the bis is executed, the bl ndcl bit is used to determine whether one of the coils is driven during the blanking phase. if the appropriate number of dow n counter periods (equal to th e blncntld register value) expires the blnif is set, the interrupt is triggered according to the blnie bit and the blnst bit is cleared. ? if the itgcntld register is set to a valu e other than 0x0000 the dcnt is loaded with (itgcntld - 1) and is started usi ng the itgdiv bit setting for the clock divider. the itgst is set and the itgacc register is initialized with 0x0000. the integration phase of the bis is executed, the it gdcl bit is used to de termine whether one of the coils is driven during the integration phase. the ?? -modulator of the anal og block is functional and the itgacc register is updated. during the integration phase the polarity is switched according to the offcnc bits. if the appropriate number of down counter periods (equal to the itgc ntld register value) expires the itgif is set, the interrupt is triggered accord ing to the itgie bit and the itgst bit is cleared. the state of the ongoing bis can be m onitored by the following status bits: ? the blnst bit is set during the blanking phase exclusively. ? the itgst bit is set during the integration phase exclusively. when it is set, the bis control enables the ?? -modulator in the analog block together with the integrati on circuitry. as long as the integration phase is active the it gacc register content is modified depending from the output of the ?? -modulator. in the normal use case the end of the bis is the end of the integration phase. i ndependent from the time required by the software to detect and act upon the end of the bis the itgacc register is not changed after the end of th e integration phase. the sequence control logic itself ma kes use of the following sub blocks: 36.4.1.4.1 down counter the down counter is basically a timer with the divider factor (blndiv or itgdiv) and length (blncntld or itgcntld) determined by the current state of the bis. additionally to defining the
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-17 preliminary?subject to change without notice length of the integration phase the itgcntld sett ing determines the dcnt value to switch the integration polarity for dc offset cancella tion depending from the offcnc bit setting. when the down counter re aches 0x0000 and the associat ed divider period has expi red the appropriate flag is set and the corresponding in terrupt is triggered dependi ng from the interrupt enable bit. note that polling the dcnt register for 0x0000 is misleading since the dcnt ti me out is reached at the end of the divider period belonging to the value of 0x0000. refer to section 36.6.3, watching intern al states of the ssd ?. table 36-14 below shows details how the blndiv/i tgdiv and blncntld/itgcntld settings determine the length and granularit y of the blanking and in tegration phase dependi ng from the bus clock frequency. 36.4.1.4.2 integration accumulator this is the fundamental sub block of the ssd, it is responsible for collecting the result of the back emf integration from the ?? -modulator located in the analog block. the only time when the value of the accumulator can change is during the integration phase of a bis. in terms of signal processing the itgacc register is the counterpart of the ?? -modulator in the analog block, working as the ?? -demodulator: depending from the acdiv bits in the prescale register the output of the analog block is samp led periodically and the content of the accumulator incremented or decremented. therefore the itgacc register in fact counts the ?imbalance? between 1 and 0 output samples from the analog block. the value of the itgacc register can change only during the integration phase of an ongoing bis. before the first update the content is initia lized to 0x0000 and starting from that it is incremented or decremented according to the ?? -modulator output. number format is two?s complement, if an overflo w (attempt to increment itgacc register value of 0x7fff) or an underflow (attempt to decrement it gacc register value of 0x8000) the acovif bit indicates the over-/underflow condition, the ssd interrupt is triggered if the acovie bit is set and the itgacc register values is not changed. for the rest of the integration phase of the current bis the itgacc register value does not change. reaching the accumulator end values without an over-/underflow condition does not prevent the itga cc register from incr ementing 0x8000 (-32768) or decrementing 0x7fff (+32767). table 36-15 below shows details how the acdiv setting determines the ?? -demodulator sampling clock w.r.t. the bus clock. the recomme nded setting for the sampling is a resulting clock between 500 khz and 2 mhz. therefore the acdiv values for sampling cloc k values in this recomm ended range are given: table 36-14. blanking and integration phase length vs. bus clock 1 1 numbers rounded appropriately bus clock 40 mhz 64 mhz 80 mhz blndiv/itgdiv 0 7 0 7 0 7 timing granularity 0.2 ? s 25.6 ? s0.125 ? s16 ? s0.1 ? s12.8 ? s max. length of bln/itg 13.107 m s 1.678 s 8.192 ms 1.049 s 6.554 ms 0.839 s
pxd10 microcontroller reference manual, rev. 1 36-18 freescale semiconductor preliminary?subject to change without notice 36.4.1.4.3 dc offset cancellation due to deviations from th e mid point of the analog s upply voltages and other effect s in the hardware of the analog blocks a dc offset may be introduced into the output of the ?? -modulator. as a consequence of such a dc offset the value obtained in the integrat ion accumulator would depend from the ?direction? of the integration (e.g. accumulator increment for positive back emf in clockwise movement). the dc offset cancellation implemented in the ssd block can eliminate (or at least re duce) the influence of such a dc offset: when active the dc offset cancellation reverts tw o internal settings in the ssd block during the integration phase of the current bis: ? the input into the analog block controlling the integration polarity which sets the switch condition state (third column in table 36-13 ): initial value (when the integration starts at step 5 in section 36.4.2.2, details of the ssd measurement ?) is the bit value given in the itgd ir register in the control register. ? the output of the ?? -modulator being applied to the integration accumulator (itgacc register): initially it is applied without cha nge to the integration accumulator. as a result the switch conditions in the analog circui try change the direction of the voltage representing the back emf measured by the ?? -modulator. but the change directi on of the itgacc register is maintained because the interpretation of the ?? -modulator output is reverted, too. the offset cancellation is implemen ted as an additional counter runni ng during the integration phase with the same clock setting like the dc nt register. the preset value for this counter is derived from the itgcntld register by shifting right by 0, 1, 2 or 3 bits, depending from the offcnc bit setting. clearing all the offcnc bits obvious ly disables the offset cancellation completely. note that increasing the number of flips improves the offset cancellation becaus e the different polarities are distributed equally over the complete integration phase (if itgcntld can be divided by the appropriate number). refer to figure 36-11 for more details. table 36-15. itgacc update clock vs. bus clock - recommended settings 1 1 numbers rounded appropriately bus clock 40 mhz 64 mhz 80 mhz acdiv 3?b010 3?b011 3?b 011 3?b100 3?b011 3?b100 divider factor 32 64 64 128 64 128 sampling frequency 1.25 mhz 625 khz 1.00 mhz 500 khz 1.25 mhz 625 khz update interval 0.8 ? s1.6 ? s1.00 ? s2.00 ? s0.8 ? s1.6 ? s
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-19 preliminary?subject to change without notice figure 36-11. offset cancellation polarity distribution if the shift process shifts out ls bits from the itgcntld register (non-integer di vide) the number shifted out creates an additional polarity flip which lasts the appropriate number of dcnt update periods. 36.4.2 stepper stall detection measurement this part of the functional descript ion deals with the main intended use case of the ssd block, this is the detection of the scale end boundaries of the gauge pointer moved by the sm which, in turn, is driven by the ssd block. for details of th e related sub blocks refer to section 36.4.1, main building blocks of the ssd ?. 36.4.2.1 overview of the ssd measurement the generic flow of ssd measurement is given in figure 36-12 below, the numbers de noted at each step belong to the detailed explanations given in section 36.4.2.2, details of the ssd measurement ?. the two phases of the bis are executed in sequence: 1. blanking phase: since the non-driven coil used fo r measurement was driven in the previous step switching transients are induced when changing from the driven into the non-driven state. therefore both pins of the non-driven coil are connected to one of the analog supply voltages vddm or vssm (depending from the rcir bit) to allow recirculation of these transient currents. 2. integration phase: this is the actual meas urement where the itgacc register is changed according to the results of the ?? -modulator of the analog block. time of integration phase offcnc = 2?b00 offcnc = 2?b01 offcnc = 2?b10 offcnc = 2?b11 initial polarity setting reverted polarity setting sample down counter for itgcntld = 0x1fff 0x1fff 0x0x000 0x1bff 0x17ff 0x13ff 0x0fff 0x0bff 0x07ff 0x03ff
pxd10 microcontroller reference manual, rev. 1 36-20 freescale semiconductor preliminary?subject to change without notice figure 36-12. generic ssd flow 36.4.2.2 details of the ssd measurement this section describes in detail the steps introduced in figure 36-12 . note that it describes only the measurement process. the decision whether the stall position has been reached or another sm step is required must be made by the controlling cpu dependi ng from the measurement result. all control bits are assumed to have their (inact ive) reset values prior to ente ring the ssd measurement flow. the following paragraphs relate to one complete bis including the (optiona l) blanking phase followed by the integration phase: 1. start of measurement start of measurement 1 initialize ssd 2 start blanking 3 start integration 5 end of measurement 9 end of blanking? 4 end of integration? 6 yes no yes no stop integration 7 read integration result 8 bis executed automatically
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-21 preliminary?subject to change without notice for proper usage of the ssd block it must have exclusive control over the coils belonging to the sm whose stall position must be de tected. this must be ensured at the device level. following this the ssd must be enabled by setting the rtze bit in the control register, this bit must be left asserted for the complete ssd flow. it is at this point in time that application-dependent control setti ngs are set which remain constant over the complete ssd flow. these settings cons ist of the integrate direction of the itgacc register, which is set by the itgdir bit and the di rection to advance the s tep setting (increment or decrement influence clockwise or counter-clo ckwise movement of the sm). additionally the prescale and the irq re gister must be programmed (it is not recommended to change the content of the prescale re gister during a running bis). 2. initialize ssd at this point the step bits are set according to the angular position of the sm for the current position. after programming the step bits the analog block can be enabled by setting the sdcpu bit. 3. start blanking this step starts with setting the trig bit together with the step bits initializing the complete bis for the next step. depending from th e direction of the rotation the pr evious step setting is either decremented or incremented, wrapping from 2?b11 to 2?b00 or vice versa. if the blndcl bit is set this step marks the start of the sm movement , during blanking both pins of the non-driven coil are connected either to vddm or vssm for reci rculation, depending from the rcir bit. the bus clock is divided accordingly to the blndiv bits to decrement the dcnt. th e blnst bit is set to allow the user to monitor the status. 4. end of blanking? the end of the blanking phase is automaticall y detected. if the dc nt reaches 0x0000 and the complete blanking time is expired the blnif flag is set and the inte rrupt triggered according to the blnie bit. the blnst bit is cleared. 5. start integration after the end of the blanking phase the ssd bloc k continues automaticall y with the integration phase: the itgcntld register is used to initialize the dcnt and is decrem ented according to the itgdiv bits setting. the driving coils is powered according to the itgdcl bit. during the integration phase the polarity flip for offset cancel lation is triggered according to the offcnc bits. the itgst bit is set to allow th e user to monitor the status. 6. end of integration? the down counter is monitored in the same way like in step 4. the itgif flag is set and the interrupt is triggered according to the itgie bit. the itgst bit is cleared. 7. stop integration on the expiration of the current bis the integration is stopped, the ?? -modulator is disabled, the itgacc register is frozen. note that the current to the coil dr iven by the ssd block continues according to the itgdcl and the step setting. 8. read integration result
pxd10 microcontroller reference manual, rev. 1 36-22 freescale semiconductor preliminary?subject to change without notice now the result of the back emf integration over the time set with the blncntld register value can be read from the itgacc register. 9. end of measurement depending from the result of the measurement th e ssd block now can be disabled by clearing the rtze bit or another m easurement can be started. any additi onal measurement should start from step 2. 36.4.3 additional modes of operation there are several addi tional modes how the ssd block can operate with the sm co ils. they are aside from the main use case. 36.4.3.1 blanking with no drive during blanking of one coil (refer to step 3 in section 36.4.2, stepper stall detection measurement ?) the user can disable the drive of the ot her coil by not setting the blndcl bi t. since the sm has moved in the integration phase of the previous bis this means th at the sm movement is interrupted during blanking. this mode is not useful for ssd. 36.4.3.2 integration with no drive if the itgdcl bit is switched off the driving coil of the sm is not powered during the integration phase, the sm will not move. only the ?? -modulator output is integrated wi th the reference voltage setting belonging to that step. this mode makes no sense fo r stall detection, but it can be used for certain measurements of the analog sub blocks. 36.5 initialization information 36.5.1 analog block startup time no specific initialization af ter a hard reset or after leaving one of the power dow n modes is necessary, but the user should allow a suff icient startup time of th e analog block after hard re set or enabling of the ssd block to compensate switching transients. the st artup time specified for the analog block is 20 ? s. 36.5.2 analog block polarity switching time if the offset cancellation is used the polarity of the back emf measurem ent in the analog block is reverted during the integration phase. no te that the time for the ?? -modulator to achieve a stable output depends strongly from the external circuitry, e.g. coil inductance, parasitic capacitance of the leads. as an initial estimation for typical applications a ti me of maximum 10 ? s should be taken into account by the user.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-23 preliminary?subject to change without notice 36.5.3 ssd startup the ssd block takes care of smooth tr ansitions between the different step s to avoid current glitches when the coil driven by the block (sine or cosine) changes. single-cycle glitches in the coil drive current at startup of the ssd flow can be avoided in the following way: ? program the step bits reflecting the current posi tion of the sm prior to the ssd flow with the sdcpu bit still cleared. ? after programming the step bits enable the analog block by setting the sdcpu bit. 36.6 application information this is additional information intended for use by the customer. 36.6.1 current flow examples figure 36-13 below shows the current flow for a co mplete sequence of the step bits for counter-clockwise movement in cluding the recirc ulation time: figure 36-13. full step sequence for counter-clockwise movement different examples of the current flow in the sm coil s for different settings of the control bits are given in figure 36-14 to figure 36-17 below: figure 36-14 below shows the recirculation at the beginning of step = 0. the co sine coil is driven in the direction p -> m and the sine coil is recirculated against vddm. 0 1 2 3 0 imax + _ imax 0 imax + _ imax sine coil current cosine coil current recirculation
pxd10 microcontroller reference manual, rev. 1 36-24 freescale semiconductor preliminary?subject to change without notice figure 36-14. current flow for blan king (step = 0, blndcl = 1, rcir = 0) in figure 36-15 below the recirculation at the beginning of the next bis for step = 1 with changed setting of the rcir bit is shown. the sine coil is driven again in p -> m direction and the cosine coil is recirculated against vssm. figure 36-15. current flow for blan king (step = 1, blndcl = 1, rcir = 1) in figure 36-16 below it is shown that for the next step (s tep = 2) the cosine coil is driven in reverse direction with respect to step = 0 (m -> p direction). because it is the integration phase of the bis, the sine coil is isolated from the analog suppl y voltages. instead, it is connected to the ?? -modulator (not shown). vddm cosp cosm t1 t2 t3 t4 vssm vddm sinp sinm t5 t6 t7 t8 vssm vddm cosp cosm t1 t2 t3 t4 vssm vddm sinp sinm t5 t6 t7 t8 vssm
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-25 preliminary?subject to change without notice figure 36-16. current flow for integration (step = 2, itgdcl = 1) figure 36-17 below shows that the sine coil is driven fo r step = 3 in reverse direction with respect to step = 1 (m -> p direction). again the other coil (cos ine) is isolated from the analog supply voltages because it is the integration phase of the current bis. figure 36-17. current flow for integration (step = 3, itgdcl = 1) 36.6.2 setting of the prescale register 36.6.2.1 timing resolution considerations set the acdiv bits to the lowest di vision factor possible, resulting in the highest possible clock frequency for the integration accumulator. this will give the most precise result. vddm cosp cosm t1 t2 t3 t4 vssm vddm sinp sinm t5 t6 t7 t8 vssm vddm cosp cosm t1 t2 t3 t4 vssm vddm sinp sinm t5 t6 t7 t8 vssm
pxd10 microcontroller reference manual, rev. 1 36-26 freescale semiconductor preliminary?subject to change without notice setting the blndiv or itgdiv bi ts will influence the resoluti on of the down counter in the corresponding phase of the bis (fine resolution required for blanking) as well as the available (absolute) time interval that can be covered by the length of the dcnt register (must be l ong enough to cover almost one sm step movement for integrati on). due to the different prescaler se ttings for blanking and integration no compromise is necessary between fine resolution for bla nking and long time for in tegration when using high bus frequencies. it is recommended to select the setting with the best timing resolution for the blanking phase for the blndiv bit setting (lowest value). most likely a di fferent value must be chosen for the itgdiv bit setting, neverthele ss the lowest possible value should be chosen, too. note that in normal operation it shoul d not occur that the acovif bit in the irq register reads out to be set during the integration. if this happens the bit indicates that either an ove rflow or an underflow occurred in the itgacc register. the result should be discar ded because the setup of the ssd block was wrong for the current ssd attempt. 36.6.2.2 offset cancellation considerations note that the polarity switching for of fset cancellation like depicted in figure 36-11 is controlled by the dcnt register update which is update d depending from the itgdiv setti ngs. all the divider settings are powers of 2, so the distance in time between two dcnt regi ster updates is always an integer multiple or divider of the itgacc regi ster update, depending which divider f actor is greater than the other one. if the offset cancellation is used the measurement pol arity in the analog block is reverted at least once during the integration phase . as a consequence the ?? -modulator needs some time after each polarity flip to achieve a stable output. an estim ation for that time is given in section 36.5.2, analog block polarity switching time ?. if the itgacc register is updated before the ?? -modulator output is stable at least one count is incorrect. since the next polarit y flip takes place in the opposite direction this incorrect count will be compensated for by the following polarity flip. therefore it may be useful to add a small number of dcnt register updates to the integration phase to have an even num ber of polarity flips in the offset cancellation. another mean to improve accuracy is to adjust the dcnt register updates where the polarity switches occur with respect to the follo wing itgacc register update to al low enough settling time for the ?? -modulator output. 36.6.3 watching internal states of the ssd for some applications it might be required by the applicat ion to know the current state of an ongoing bis. it is recommended to do that by reading the blnst and the itgst bits of the control register. if necessary the dcnt register value may be read to know how far the dcnt register period has expired. do not poll the dcnt register value for 0x0000 to find out the end of the blanking or integration phase. aside from generating more cpu load than required th is introduces an inaccuracy. not earlier than the dcnt register divider period belonging to the 0x0000 value has expired th e complete blanking or integration phase has been processed.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 36-27 preliminary?subject to change without notice it should be kept in mind that the recommended way of operati on is to enable the appropriate interrupt flag instead of polling the ssd registers. 36.6.4 stepper motor transition considerations 36.6.4.1 ssd phase-in and phase-out prior to starting the ssd flow the sm gauge is usually moved in the proxi mity of the expected stall position using another sm driver module. to change the driving source of the sm without visible interruption to the ssd block it is essential for the user to replicate the coil drive setting valid at the end of the sm drive into the ssd control register. given that the transfer of the port control from the previous sm driver module to the ssd block can be done sufficiently fast the sm will not move but will start at a know position with the ssd flow. the same applies to the end of the ssd flow when the sm control is transferred to another module. it is essential for the application in this use case that the coil drive setting at th e end of the ssd flow is replicated in this other module. basically the seamless hand over of the sm coils to another block can be handled by appropriately programming the step bits and the itgdcl bit in th e control register prior to pass pad control to the ssd block. this ensures that one of the sm coil s is driven and the sm retains its position when the ssd block gets pad control. vice versa the step and itgdcl setting at the end of the last bis where the gauge stall was detected allow the user to replicate this specific coil driv e setting to the module taking over pad control from the ssd block. for more details refer to specific application notes describing the us age of the ssd block. 36.6.4.2 changing of ssd internal states depending from the applicat ion it may be required to lock the sm into the current angular position to prevent occasional movement prior to the next step. this is especially useful after the integration phase of a bis. to achieve this the internal logic of the ss d block does the following af ter the integration phase has expired: ? the coil drive setting of the in tegration phase is held active: th e itgdcl bit determines the coil drive; the coil and coil directi on is determined by the step bits. ? the undriven coil is set (back to) r ecirculation like in the blanking phase. this leaves both coils in a well-defined state, nevert heless the user should keep this time outside of the bis as short as possible to avoid visible interruptions of th e gauge movement. when changing to the next step within the ssd flow it should be noted that the update of the step bits should coincide (done in the same write to the control re gister) like the trigger of the bis by writing 1 into the trig bit. this ensures seamless changeover fr om one step to the next as well as immediate start of the bis when the coil driven has changed.
pxd10 microcontroller reference manual, rev. 1 36-28 freescale semiconductor preliminary?subject to change without notice 36.6.5 legacy modes - separate blanking and integration phase despite the automatic bis it is still possible to us e the ssd block in a way similar to the old design. separate blanking and integration ph ases can be obtained very easily by setting the down counter preload value for the undesired phase to 0x0000. when the corr esponding bis is executed this phase is simply skipped. note that in this case the blnif bit will be importa nt for the user because its assertion marks the end of the blanking phase. to ease the programming of separa te blncntld and itgcntld regi ster values on-the-fly the two adjacent registers are placed into one single 32-bit access. therefore the user who wants to implement programmed-control switching betw een blanking and integration need s only one single 32-bit register write (to switch the down counter pr eload values) prior to the executi on of the blanking or integration phase.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-1 preliminary?subject to change without notice chapter 37 system integration unit lite (siul) 37.1 introduction this chapter describes the system in tegration unit lite (siul), which is used for the management of the pads and their configuration. it controls the multiplexi ng of the alternate functions used on all pads as well as being responsible for the management of the external interrupts to the device. 37.2 overview the siul controls the mcu pad c onfiguration, ports, gene ral-purpose input and out put (gpio) signals and external interrupts with trigger event configuration. figure 37-1 is a block diagram of the siul and its interfaces to other system components. the module provides dedicated general-purpose pads that can be conf igured as either inputs or outputs. when configured as an output, you can write to an inte rnal register to control the state driven on the associated output pad. when configured as an input , you can detect the state of the associated pad by reading the value from an internal register. when conf igured as an input and out put, the pad value can be read back, which can be used a method of chec king if the written value appeared on the pad.
pxd10 microcontroller reference manual, rev. 1 37-2 freescale semiconductor preliminary?subject to change without notice figure 37-1. siul block diagram 1 up to 105 i/o pins in the 144-pin packages; up to 133 i/o pins in the 176- and 208-pin packages ips bus data pad input io interrupt interrupt controller ips master - configuration - glitch filter pad config (iomuxc) pad cfg (pcrs) gpio functionality 133 1 133 1 133 1 14 2 mux pa ds 133 1 siul module interrupt functionality
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-3 preliminary?subject to change without notice 37.3 features the siul supports these distinctive features: ?gpio ? gpio function on up to 133 i/o pins ? dedicated input and output re gisters for each gpio pin ? external interrupts ? 2 system interrupt vectors for up to 14 interrupt sources ? 14 programmable digi tal glitch filters ? independent interrupt mask ? edge detection ? system configuration ? pad configuration control 37.4 external signal description the pad configuration allows flexible , centralized control of the pin el ectrical characteristics of the mcu with the gpio control providing cent ralized general purpose i/o for an mcu that multiplexes gpio with other signals at the i/o pads. these other signals, or alternate functions , will normally be the peripherals functions. the internal multiplexing al lows user selection of the input to chip-level signal multiplexors. each gpio port communicates via 16 i/o channels. in order to use the pad as a gpio, the corresponding pad configuration registers (pcr) for all pads used in the port must be configured as gpio rather than as the alternate pad function. table 37-1 lists the external pins used by the siul. table 37-1. siul signal properties external irq flag pcr port package 144 176 208 irq_0 eif[0] pcr[1] pa[1] x x x eif[1] pcr[8] pa[8] x x x eif[2] pcr[9] pa[9] x x x eif[3] pcr[16] pb[0] x x x eif[4] pcr[18] pb[2] x x x eif[5] pcr[27] pb[11] x x x eif[6] pcr[29] pb[13] x x x eif[7] pcr[71] pf[1] x x x
pxd10 microcontroller reference manual, rev. 1 37-4 freescale semiconductor preliminary?subject to change without notice 37.4.1 detailed signal descriptions 37.4.1.1 general-purpose i/o pins (gpio[0:132]) the gpio pins provide general-purpose input a nd output function. the gpio pins are generally multiplexed with other i/o pin functions. each gpio input and output is separately cont rolled by an input (gpdi n_n ) or output (gpdo n_n ) register. 37.4.1.2 external interrupt request input pins (eirq[0:13]) 1 the eirq[0:13] are connected to the siu inputs. rising or falling edge events are enabled by setting the corresponding bits in the siu_ireer or the siu_ifeer register. 37.5 memory map and register description this section provides a detailed description of all registers accessibl e in the siul module. 37.5.1 siul memory map table 37-2 gives an overview on the siul registers implemented. irq_1 eif[8] pcr[80] pf[10] x x x eif[9] pcr[86] pg[0] x x x eif[10] pcr[87] pg[1] x x x eif[11] pcr[98] pg[12] x x x eif[12] pcr[131] pk[10] ? x x eif[13] pcr[132] pk[11] ? x x 1. eirq[0:11] in the 144-pin lqfp; eirq[0:13] in all other packages table 37-2. siul memory map address name description size (bits) location base (0xc3f9_0000) - reserved - base + 0x0004 midr1 mcu id register #1 32-bit on page 6 base + 0x0008 midr2 mcu id register #2 32-bit on page 7 base + (0x000c - 0x0013) - reserved - base + 0x0014 isr interrupt status flag register 32-bit on page 9 table 37-1. siul signal properties (continued) external irq flag pcr port package 144 176 208
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-5 preliminary?subject to change without notice note a transfer error will be issued when trying to access reserved register space. base + 0x0018 irer interrupt request enable register 32-bit on page 9 base + (0x001c - 0x0027) - reserved - base + 0x0028 ireer interrupt rising edge event enable 32-bit on page 10 base + 0x002c ifeer interrupt falling-edge event enable 32-bit on page 10 base + 0x0030 ifer ifer interrupt filter enable register 32-bit on page 11 base + (0x0034 - 0x003f) - reserved - base + 0x0040 - base + 0x0148 pcr0 - pcr132 1 pad configuration registers 0 - 132 16-bit on page 11 base + (0x014c - 0x04ff) - reserved - base + 0x0500 - base + 0x0528 psmi0_3 - psmi40_42 pad selection for multiplexed inputs 32-bit on page 14 base + (0x052c - 0x05ff) - reserved - base + 0x0600 - base + 0x0684 gpdo0_3 - gpdo132_135 1 gpio pad data output register 32-bit on page 18 base + (0x0688- 0x07ff) - reserved - base + 0x0800 - base + 0x0884 gpdi0_3 - gpdi132_135 1 gpio pad data input register 32-bit on page 18 base + (0x088c- 0x0bff) - reserved - base + 0x0c00 - base + 0x0c10 pgpdo0 - pgpdo4 parallel gpio pad data out register 32-bit on page 19 base + (0x0c14- 0x0c3f) - reserved - base + 0x0c40 - base + 0x0c50 pgpdi0 - pgpdi4 parallel gpio pad data in register 32-bit on page 21 base + (0x0c54- 0x0c7f) - reserved - base + 0x0c80 - base + 0x0ca4 mpgpdo0 - mpgpdo8 masked parallel gpio pad data out register 32-bit on page 22 base + (0x0ca8 - 0x0fff) - reserved - base + 0x1000 - base + 0x103c ifmc0 - ifmc15 1 interrupt filter maximum counter register 32-bit on page 23 base + (0x1040 - 0x107c) - reserved - base + 0x1080 ifcp interrupt filter clock prescaler register 32-bit on page 23 base + (0x1084 - 0x3fff) - reserved - 1 not all port pins are available in all packages. table 37-2. siul memory map (continued) address name description size (bits) location
pxd10 microcontroller reference manual, rev. 1 37-6 freescale semiconductor preliminary?subject to change without notice 37.5.2 register protection the individual registers of siul are protected from accidental writes. the following registers are protected: ?irer ( interrupt request enable register ) ? ireer ( interrupt rising-edge event enable register ) ? ifeer ( interrupt falling-edge event enable register ) ?ifer ( interrupt filter enable register ), entire porta, portb[0:3] and portc[2:15] ? psmi[n] ( pad selection for multiplexed inputs ) ? ifmc[n] ( interrupt filter maximum counter ) ?ifpc ( interrupt filter clock prescaler ) refer to appendix a, registers under protection, for details. 37.5.3 register description this section describes in a ddress order all the siul regi sters. each description incl udes a standard register diagram. details of register bit a nd field function follow the register diagrams, in bit or der. the numbering convention of register is msb=0, however the numbering of intern al field is lsb=0, e.g. partnum[5] = midr1[10]. figure 37-2. key to register fields 37.5.3.1 mcu id register #1 (midr1) this register holds identificat ion information about the device. always 1 always 0 r/w bit read - bit write - write 1 bit self - 0 n/a reads 1 reads 0 bit only bit only bit bit to clear w1c clear bit bit address: base + 0x0004 access: none 0123456789101112131415 r partnum[15:0] w reset 0101011000000100 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r csp pkg[4:0] major_mask[3:0] minor_mask[3:0] w reset 0011010000000000 figure 37-3. mcu id register #1 (midr1)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-7 preliminary?subject to change without notice 37.5.3.2 mcu id register #2 (midr2) field description same as ss cm mcu id register #2 (see section 38.2.2, register description ). table 37-3. midr1 field descriptions field description partnum [15:0] mcu part number device part number of the mcu. 0101_0110_0000_0001: 128k 0101_0110_0000_0010: 256k 0101_0110_0000_0011: 320/384k 0101_0110_0000_0100: 512k for the full part number this field needs to be combined with midr2.partnum[0:7] csp always reads back 0 pkg[4:0] package settings can be read by software to determine the package type that is used for the particular device: 0b01001: 100-pin qfp 0b01101: 144-pin qfp major_mask[3:0] major mask revision counter starting at 0x0. incremented each time when there is a resynthesis. minor_mask[3:0] minor mask revision counter starting at 0x0. incremented each time a mask change is done. address: base + 0x0008 access: none 0123456789101112131415 r sf flash_size_1[3: 0] flash_size_2[3:0] w reset 0010100000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r partnum[23:16] ee w reset 01000010/10001s 1 1 static bit fixed in hardware s 1 s 1 0 figure 37-4. mcu id register #2 (midr2) table 37-4. midr2 field descriptions field description sf manufacturer 0: freescale semiconductor 1: reserved
pxd10 microcontroller reference manual, rev. 1 37-8 freescale semiconductor preliminary?subject to change without notice flash_size_1 coarse granularity for flash memory size needs to be added to the memory size indicated by flash_size_2 to calculate the actual memory size. 0b0011: 128k 0b0100: 256k 0b0101: 512k flash_size_2 fine granularity for flash memory size needs to be added to the memory size indicated by flash_size_1 to calculate the actual memory size. 0b0000: 0 x (flash_size_1 / 8) 0b0010: 2 x (flash_size_1 / 8) 0b0100: 4 x (flash_size_1 / 8) partnum ascii character in mcu part number 0x52: character ?r? (this device) ee data flash present 0: no data flash is present 1: data flash is present table 37-4. midr2 field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-9 preliminary?subject to change without notice 37.5.3.3 interrupt status flag register (isr) this register holds the external interrupt flags. 37.5.3.4 interrupt request enable register (irer) this register is used to enable the external interrupt messaging to the interrupt controller. address: base + 0x0014 access: user read/write (write 1 to clear) 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r eif[13:0] 1 1 eif[11:0] is valid in the 144-pin lqfp. w w1c reset 00000000000000000000000000000000 figure 37-5. interrupt status flag register (isr) table 37-5. isr field descriptions field description eif[x] external interrupt status flag x this flag can be cleared only by writing a 1. writin g a 0 has no effect. if enabled (irer[x]), eif[x] causes an interrupt request. 0: no interrupt event has occurred on the pad 1: an interrupt event as defined by ireer[x] and ifeer[x] has occurred address: base + 0x0018 access: user read/write 012345678910111213141516171819202122232425262728293031 r ire[13:0] 1 1 ire[11:0] is valid in the 144-pin lqfp. w reset 00000000000000000000000000000000 figure 37-6. interrupt request enable register (irer) table 37-6. irer field descriptions field description ire[x] external interr upt request enable x 1: a set eif[x] bit causes an interrupt request 0: interrupt requests from the corre sponding eif[x] bit are disabled
pxd10 microcontroller reference manual, rev. 1 37-10 freescale semiconductor preliminary?subject to change without notice 37.5.3.5 interrupt rising-edge event enable register (ireer) this register is used to enable rising-edge triggered events to be enabled on the corresponding external interrupt pads. 37.5.3.6 interrupt falling-edge ev ent enable register (ifeer) this register is used to enable falling-edge trigge red events to be enabled on the corresponding external interrupt pads. note if both the iree and ifee bit is cleared for the same interrupt source, the interrupt status flag for the corres ponding external interr upt will never be set. address: base + 0x0028 access: user read/write 012345678910111213141516171819202122232425262728293031 r iree[13:0] 1 1 iree[11:0] is valid in the 144-pin lqfp. w reset 00000000000000000000000000000000 figure 37-7. interrupt rising-edge event enable register (ireer) table 37-7. ireer field descriptions field description iree[x] enable rising-edge events to cause the eif[x] bit to be set. 1: rising-edge event is enabled 0: rising-edge event is disabled address: base + 0x002c access: user read/write 012345678910111213141516171819202122232425262728293031 r ifee[13:0] 1 1 ifee[11:0] is valid in the 144-pin lqfp. w reset 00000000000000000000000000000000 figure 37-8. interrupt falling-edge event enable register (ifeer) table 37-8. ifeer field descriptions field description ifee[x] enable falling-edge events to cause the eif[x] bit to be set. 1: falling-edge event is enabled 0: falling-edge event is disabled
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-11 preliminary?subject to change without notice 37.5.3.7 interrupt filter enable register (ifer) this register is used to enable a digital filt er counter on the corresponding exte rnal interrupt pads to filter out glitches on the inputs. 37.5.3.8 pad configuration registers (pcr0 - pcr132) the pad configuration regist ers allow configuration of the static electrical and functional characteristics associated with i/o pads. each pcr cont rols the characteristics of a single pad. note 16/32-bit access supported in addition to the bit map above, the following table 37-11 describes the pcr register depending on the pad type. the bits in shaded fields are not implemented for the particul ar i/o type. the pa field selecting address: base + 0x0030 access: user read/write 012345678910111213141516171819202122232425262728293031 r ife[13:0] 1 1 ife[11:0] is valid in the 144-pin lqfp. w reset 00000000000000000000000000000000 figure 37-9. interrupt filter enable register (ifer) table 37-9. ifer field descriptions field description ife[x] enable digital glitch filter on the interrupt pad input. 1: filter is enabled 0: filter is disabled address: base + 0x0040 (pcr0)(133 registers) base + 0x0042 (pcr1) ... base + 0x0148 (pcr132) access: user read/write 0123456789101112131415 r smc apc pa[1:0] obe ibe ode src[1:0] wpe wps w reset 1 0000000000000000 1 reset value shown is for the most of the pcrs, however, some pcrs are initialized to different values dependent on the requirements of the device. see chapter 3, signal description,? for the reset configurations of each pcr on this device. figure 37-10. pad configuration registers (pcrx)
pxd10 microcontroller reference manual, rev. 1 37-12 freescale semiconductor preliminary?subject to change without notice the number of alternate functions may or may not be present depending on th e number of alternate functions actually mapped on the pad. figure 37-11. pad configuration register (pcr) for the different pad types in pxd10 pad type 0123456789101112131415 pad with gpio and digital alternate function smc apc pa[1:0] obe ibe ode src[1:0] wpe wps pad with slew rate control smc apc pa[1:0] obe ibe ode src [1] wpe wps pad with gpio and analog functionality smc apc pa[1:0] obe ibe ode src[1:0] wpe wps table 37-10. pcrx field descriptions field description smc safe mode control this bit supports the overriding of the automatic de activation of the output buffer of the associated pad upon entering safe mode of the soc. 1: in soc safe mode, the output buffer remains functional. 0: in soc safe mode, the output buffer of the pad is disabled. apc analog pad control this bit enables the usage of the pad as analog input. 1: analog input path switch can be enabled by the adc. 0: analog input path from the pad is gated and can not be used. pa[1:0] pad output assignment this field is used to select the function that is allowed to drive the output of a multiplexed pad. 00: alternative mode 0: gpio. 01: alternative mode 1: see chapter 3, signal description? 10: alternative mode 2: see chapter 3, signal description? 11: alternative mode 3: see chapter 3, signal description? note: number of bit depending of the number of actual alternate function. please refer to datasheet obe output buffer enable this bit enables the output buffer of the pad in case the pad is in gpio mode. 1: output buffer of the pad is enabled when pa = 00. 0: output buffer of the pad is disabled when pa = 00. ibe input buffer enable this bit enables the input buffer of the pad. 1: input buffer of the pad is enabled. 0: input buffer of the pad is disabled. ode open drain output enable this bit controls output driver configuration for th e pads connected to this signal. either open drain or push/pull driver configurations can be sele cted. this feature applie s to output pads only. 1: open drain enable signal is asserted for the pad. 0: open drain enable signal is negated for the pad.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-13 preliminary?subject to change without notice src[1:0] slew rate control this field controls the slew rate control output si gnals from the siul. the output signals are driven to the value of this field. the actual slew rates are defined by the implementation of the pad devices for a given soc. note: for low-power modes, keeping these bits asserted may result in more leakage. it is recommended to not drive these bits during low-power modes. wpe weak pull up/down enable this bit controls whether the weak pull up/d own devices are enabled/disabled for the pad connected to this signal. 1: weak pull device enabled for the pad. 0: weak pull device disabled for the pad. wps weak pull up/down select this bit controls whether weak pull up or weak pull down devices are used for the pads connected to this signal when weak pull up/down devices are enabled. 1: weak pull-up selected 0: weak pull-down selected table 37-10. pcrx field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 37-14 freescale semiconductor preliminary?subject to change without notice 37.5.3.9 pad selection for multiplexed inputs registers (p smi0_3 - psmi40_42) via routing it is possible to define different pads to be possible inpu ts for a certain peripheral function. in order to multiplex different pads to the same peripheral input, the siul provides a register that controls the selection between the different sources. address: base + 0x0500 - 0x0528 (11 registers) access: user read/write 0123456789101112131415 r 0000 padsel0 0000 padsel1 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 padsel2 0000 padsel3 w reset 0000000000000000 figure 37-12. pad selection for multiplexed inputs register (psmi0_3) table 37-11. psmi0_3 field descriptions field description padsel0 - 3, padsel4 - 7, ... padsel28 - 31 pad selection bits each padsel field selects the pad currently used for a certain input function. see table 37-12 . table 37-12. peripheral input pin selection psmi register siul address offset peripheral input mapping of input pin to peripheral input 1 psmi[0] 0x500 can0_rxd 0: pcr[17] 1: pcr[109] psmi[1] 0x501 can1_rxd 0: pcr[26] 1: pcr[83] 2: pcr[111] psmi[2] 0x502 dcu_pdi[0] 0: pcr[17] 1: pcr[109] psmi[3] 0x503 dcu_pdi[1] 0: pcr[16] 1: pcr[110] psmi[4] 0x504 dcu_pdi[2] 0: pcr[26] 1: pcr[111] psmi[5] 0x505 dcu_pdi[3] 0: pcr[27] 1: pcr[112]
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-15 preliminary?subject to change without notice psmi[6] 0x506 dcu_pdi[4] 0: pcr[70] 1: pcr[113] psmi[7] 0x507 dcu_pdi[5] 0: pcr[71] 1: pcr[114] psmi[8] 0x508 dcu_pdi[6] 0: pcr[73] 1: pcr[115] psmi[9] 0x509 dcu_pdi[7] 0: pcr[74] 1: pcr[116] psmi[10] 0x50a dcu_pdi[10] 0: pcr[119] 1: pcr[123] psmi[11] 0x50b dcu_pdi[11] 0: pcr[120] 1: pcr[124] psmi[12] 0x50c dcu_pdi[12] 0: pcr[121] 1: pcr[125] psmi[13] 0x50d dcu_pdi[13] 0: pcr[122] 1: pcr[126] psmi[14] 0x50e dspi1_ss 0: pcr[43] 1: pcr[79] psmi[15] 0x50f emios0_ch8 0: pcr[69] 1: pcr[91] 2: pcr[98] psmi[16] 0x510 emios0_ch9 0: pcr[15] 1: pcr[68] 2: pcr[75] psmi[17] 0x511 emios0_ch10 0: pcr[14] 1: pcr[67] 2: pcr[74] psmi[18] 0x512 emios0_ch11 0: pcr[13] 1: pcr[66] 2: pcr[73] psmi[19] 0x513 emios0_ch12 0: pcr[12] 1: pcr[65] 2: pcr[71] psmi[20] 0x514 emios0_ch13 0: pcr[11] 1: pcr[64] 2: pcr[70] psmi[21] 0x515 emios0_ch14 0: pcr[63] 1: pcr[132] psmi[22] 0x516 emios0_ch15 0: pcr[6] 1: pcr[62] 2: pcr[131] table 37-12. peripheral input pin selection psmi register siul address offset peripheral input mapping of input pin to peripheral input 1
pxd10 microcontroller reference manual, rev. 1 37-16 freescale semiconductor preliminary?subject to change without notice psmi[23] 0x517 emios0_ch16 0: pcr[7] 1: pcr[27] 2: pcr[80] psmi[24] 0x518 emios0_ch17 0: pcr[5] 1: pcr[122] psmi[25] 0x519 emios0_ch18 0: pcr[4] 1: pcr[121] psmi[26] 0x51a emios0_ch19 0: pcr[3] 1: pcr[120] psmi[27] 0x51b emios0_ch20 0: pcr[2] 1: pcr[119] psmi[28] 0x51c emios0_ch21 0: pcr[1] 1: pcr[71] 2: pcr[112] psmi[29] 0x51d emios0_ch22 0: pcr[0] 1: pcr[70] 2: pcr[111] psmi[30] 0x51e emios0_ch23 0: pcr[26] 1: pcr[98] psmi[31] 0x51f emios1_ch16 0: pcr[53] 1: pcr[82] 2: pcr[103] psmi[32] 0x520 emios1_ch17 0: pcr[52] 1: pcr[90] 2: pcr[117] psmi[33] 0x521 emios1_ch18 0: pcr[9] 1: pcr[29] 2: pcr[51] psmi[34] 0x522 emios1_ch19 0: pcr[28] 1: pcr[50] 2: pcr[88] psmi[35] 0x523 emios1_ch20 0: pcr[10] 1: pcr[25] 2: pcr[49] 3: pcr[118] psmi[36] 0x524 emios1_ch21 0: pcr[24] 1: pcr[48] 2: pcr[89] psmi[37] 0x525 emios1_ch22 0: pcr[23] 1: pcr[47] psmi[38] 0x526 emios1_ch23 0: pcr[8] 1: pcr[46] 2: pcr[81] table 37-12. peripheral input pin selection psmi register siul address offset peripheral input mapping of input pin to peripheral input 1
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-17 preliminary?subject to change without notice psmi[39] 0x527 i2c_scl_1 0: pcr[79] 1: pcr[132] psmi[40] 0x528 i2c_sda_1 0: pcr[78] 1: pcr[131] psmi[41] 0x529 i2c_rxd_1 0: pcr[28] 1: pcr[78] psmi[42] 0x52a evti 0: pcr[126] 1: evti 1 connecting a peripheral input to a pad requires assigning both the psmi value for the peripheral input and the pad assignment in the siu_pcr register for that signal. table 37-12. peripheral input pin selection psmi register siul address offset peripheral input mapping of input pin to peripheral input 1
pxd10 microcontroller reference manual, rev. 1 37-18 freescale semiconductor preliminary?subject to change without notice 37.5.3.10 gpio pad data output re gisters (gpdo0_3 - gpdo132_135) these registers can be used to set or clear a single gpio pa d with a byte access. the gpio pad data output re gisters are a group of 133 one- byte registers used to set or clear the logic value on their associated pads. each word contains four registers. the word beginning at base + 0x0600 contains gpdo0 - gpdo3, the word beginning at base + 0x0604 contains gpdo3 - gpdo07, and so on. 37.5.3.11 gpio pad data input regi sters (gpdi0_3 - gpdi132_135) these registers can be used to read the gpio pad data with a byte access. the gpio pad data input re gisters are a group of 133 one- byte registers used to set or clear the logic value on their associated pads. each word contains four registers. the word beginning at base + 0x0600 contains gpdi0 - gpdi3, the word beginning at base + 0x0604 contains gpdi3 - gpdi07, and so on. address: base + 0x0600 - 0x0684 (34 registers) access: user read/write 0123456789101112131415 r 0000000pdo [0] 0000000pdo [1] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000pdo [2] 0000000pdo [3] w reset 0000000000000000 figure 37-13. port gpio pad data output register 0 - 3 (gpdo0_3) table 37-13. gpdo field descriptions field description pdo[x] pad data out this bit stores the data to be driven out on the ex ternal gpio pad controlled by this register. 1: logic high value is driven on the corresponding gpio pad when the pad is configured as an output 0: logic low value is driven on the corresponding gpio pad when the pad is configured as an output
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-19 preliminary?subject to change without notice 37.5.3.12 parallel gpio pad data out register s (pgpdo0 - pgpdo4) these registers are used to set or clear the respective pads of the device. address: base + 0x0800 - 0x0884 (34 registers) access: user read 0123456789101112131415 r 0000000pdi [0] 0000000pdi [1] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000pdi [2] 0000000pdi [3] w reset 0000000000000000 figure 37-14. port gpio pad data input register 0 - 3 (gpdi0_3) table 37-14. gpdi field descriptions field description pdi[x] pad data in this bit stores the value of the external gpio pad associated with this register. 1: the value of the data in signal for the corresponding gpio pad is logic high 0: the value of the data in signal for the corresponding gpio pad is logic low address: base + 0x0c00 - 0x0c10 (5 registers) access: user read/write 0123456789101112131415 r ppdo[x][15:0] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ppdo[x+1][15:0] w reset 0000000000000000 figure 37-15. parallel gpio pad data out register (pgpdo0)
pxd10 microcontroller reference manual, rev. 1 37-20 freescale semiconductor preliminary?subject to change without notice note the pgpdo registers access the same physical resource as the pdo and mpgpdo address locations. so me examples of the mapping: ppdo[0][0] = pdo[0] ppdo[2][0] = pdo[32] table 37-15. pgpdo0_4 field descriptions field description ppdo[x] parallel pad data out write or read the data register that stores the value to be driven on the pad in output mode. accesses to this register location are coherent with accesses to the bit-wise gpio pad data output registers (gpd o0_3 - gpdo132_135). the x and bit index define which ppdo register bit is equivalent to which pdo register bit according to the following equation: ppdo[x][y] = pdo[(x*16)+y]
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-21 preliminary?subject to change without notice 37.5.3.13 parallel gpio pad data in register (pgpdi0?pgpdi4) these registers hold the synchroni zed input value from the pads. address: base + 0x0c40 - 0x0c50 (5 registers) access: user read 0123456789101112131415 r ppdi[x][15:0] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ppdi[x+1][15:0] w reset 0000000000000000 figure 37-16. parallel gpio pad data in register (pgpdi0) table 37-16. pgpdi field descriptions field description ppdi[x] parallel pad data in read the current pad value. accesses to this register location are coherent with accesses to the bit-wise gpio pad data input registers (gpdi0_3 - gpdi132_135). the x and bit index define which ppdi register bit is equivalent to which pdi register bit according to the following equation: ppdi[x][y] = pdi[(x*16)+y]
pxd10 microcontroller reference manual, rev. 1 37-22 freescale semiconductor preliminary?subject to change without notice 37.5.3.14 masked parallel gpio pad data out regi ster (mpgpdo0?mpgpdo8) this register can be used to selectively modify the pad values associated to ppdo[x][15:0]. the mpgpdo[x] register may only be accessed with 32-bit writes. 8-bit or 16-bit writes will not modify any bits in the register and cause a transfer error response by the module. read accesses will return 0. address: base + 0x0c80 - 0x0ca4 (9 registers) access: user read/write 0123456789101112131415 r 0000000000000000 w mask[x][15:0] reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w mppdo[x][15:0] reset 0000000000000000 figure 37-17. masked parallel gpio pad data out register (mpgpdo0) table 37-17. mpgpdo0_3 field descriptions field description mask[x] [15:0] mask field each bit corresponds to one data bit in the mppdo[x] register at the same bit location. 1: the associated bit value in the mppdo[x] field is written 0: the associated bit value in the mppdo[x] field is ignored mppdo[x] [15:0] masked parallel pad data out write the data register that stores the value to be driven on the pad in output mode. accesses to this register location are coherent with accesses to the bit-wise gpio pad data output registers (gpd o0_3 - gpdo132_135). the x and bit index define which mppdo register bit is equivalent to which pdo register bit according to the following equation: mppdo[x][y] = pdo[(x*16)+y]
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-23 preliminary?subject to change without notice 37.5.3.15 interrupt filter maximum counter registers (ifmc0 - ifmc15) these registers are used to confi gure the filter counter associated with each digita l glitch filter. 37.5.3.16 interrupt filter cloc k prescaler register (ifcpr) this register is used to configure a clock prescaler which is used to select the clock for all digital filter counters in the siul. address: base + 0x1000 - 0x103c ( 16 registers) access: user read/write 0123456789101112131415 r 0000000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 maxcntx[3:0] w reset 0000000000000000 figure 37-18. interrupt filter maximum counter registers (ifmc0 - ifmc15) table 37-18. ifmc field descriptions field description maxcntx [3:0] maximum interrupt filter counter setting. filter period = t(ck)*maxcntx + n*t(ck) where (n can be -1 to 3) maxcntx can be 0 to 15 t(ck): prescaled filter clock period, which is irc clock prescaled to ifcp value t(irc): basic filter clock period: 62.5 ns (f = 16 mhz) address: base + 0x1080 access: user read/write 0123456789101112131415 r 0000000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 ifcp[3:0] w reset 0000000000000000 figure 37-19. interrupt filter clock prescaler register (ifcpr)
pxd10 microcontroller reference manual, rev. 1 37-24 freescale semiconductor preliminary?subject to change without notice 37.6 functional description 37.6.1 general this section provides a functional descripti on of the system integration unit lite. 37.6.2 pad control the siul controls the configurat ion and electrical characteristic of the device pads. it provides a consistent interface for all pads, both on a by-port a nd a by-bit basis. the pad configuration registers (pcr n , see section 37.5.3.8, pad configurati on registers (pcr0 - pcr132) ) allow software control of the static electrical char acteristics of external pins with a single write. these are used to configure the following pad features: ? open drain output enable ? slew rate control ? pull control ? pad assignment ? control of analog path switches ? safe mode behavi or configuration 37.6.3 general purpose input and output pads (gpio) the siul allows each pad to be c onfigured as either a ge neral purpose input out put pad (gpio), and as one or more alternate functions (i nput or output), the function of wh ich is normally determined by the peripheral that will use the pad. the siul manages 133 gpio pads organized as ports th at can be accessed for da ta reads and writes as 32-bit, 16-bit or 8-bit. as shown in figure 37-20 , all port accesses are identical with each read or write being performed only at a different location to access a different port width. table 37-19. ifcpr field descriptions field description ifpc [3:0] interrupt filter clock prescaler setting prescaled filter clock period = t(irc) x (ifcp + 1) t(irc) is the internal oscillator period. ifcp can be 0 to 15
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-25 preliminary?subject to change without notice figure 37-20. data port example arrangement showing configuration for different port width accesses this implementation requires that the registers are arranged in such a wa y as to support this range of port widths without having to split reads or writes into multiple accesses. the siul has separate data input (gpdi n_n , see section 37.5.3.11, gpio pad data input registers (gpdi0_3 - gpdi132_135) ) and data output (gpdo n_n , see section 37.5.3.10, gpio pad data output registers (gpdo0_3 - gpdo132_135) ) registers for all pads , allowing the pos sibility of reading back an input or output value of a pa d directly. this supports the ability to validate what is present on the pad rather than simply confirming the value that was written to the data register by accessing the data input registers. the data output registers support both read and write operations to be performed. the data input registers support read access only. when the pad is configured to use one of its alternat e functions, the data input va lue reflect the respective value of the pad. if a write operation is performed to the data output regi ster for a pad configured as an alternate function (non gpio), this write will not be reflected by th e pad value until rec onfigured to gpio. the allocation of what i nput function is connected to the pin is defined by the psmi registers (pcr n , see section 37.5.3.8, pad configurati on registers (pcr0 - pcr132) ). 37.6.4 external interrupts the siul supports 14 external interrupts, eirq0?eirq13. see table 37-1 for the map of the external interrupts on the external pins. the siul supports two interrupt vector s to the interrupt controller. each vector interrupt has up to eight external interrupts combined together with the presence of flag generating an interrupt for that vector if enabled. all of the external interrupt pads within a si ngle group have equal priority. see figure 37-21 for an overview of the external interrupt implementation. 31 23 siu base+ 0x0000 15 7 0 siu base+ 15 7 0 siu base+ 15 7 0 siu base+ 70 0x0003 siu base+ 70 0x0002 siu base+ 70 0x0001 siu base+ 70 0x0000 0x0002 0x0000 32-bit port 16-bit port 16-bit port 8-bit port 8-bit port 8-bit port 8-bit port
pxd10 microcontroller reference manual, rev. 1 37-26 freescale semiconductor preliminary?subject to change without notice figure 37-21. external interrupt pad diagram 1 this value is valid in the 176-pin lqfp and the 208-pin packages 37.6.4.1 external interrupt management each interrupt can be enabled or disabled independently. this can be performed using the interrupt request enable register (irer - section 37.5.3.4, interrupt request enable register (irer) ). a pad defined as an external in terrupt can be configured to recognize interrupts with an active rising edge, an active falling edge or both edges bei ng active. a setting of having both e dge events disabled is reserved and should not be configured. extern al interrupts require that the asso ciated input buffer for the pad is enabled (pcr[ibe]=1). the active eirq edge is controlled through th e configuration of the registers ireer and ifeer. each external interrupt supports an individual flag which is held in the flag register (isr - section 37.5.3.3, interrupt status flag register (isr) ) ? . this register is a clear- by-write-1 register type, preventing inadvertent overwriting of other flags in the same register. the external interrupt flags map to the intc vector table as follows: ? eif[7:0] map to the external irq_0 vector ? eif[13:8] map to the external irq_1 vector 37.7 pin muxing for pin muxing, please see chapter 3, signal description,? of this document. interrupt controller int vectors eif[13:8] 1 eif[7:0] ire[13:0] 1 pads iree[13:0] 1 interrupt edge enable ifee[13:0] 1 falling rising edge detection glitch filter ife[13:0] 1 maxcount[x] irq glitch filter enable glitch filter counter_n ifcp[3:0] glitch filter prescaler interrupt enable or or external irq_1 1 external irq_0
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 37-27 preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 37-28 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 38-1 preliminary?subject to change without notice chapter 38 system status and configuration module (sscm) 38.1 introduction 38.1.1 overview the system status and configurat ion module (sscm), pictured in figure 38-1 , provides central soc functionality. on devices with a se parate standby power domain, the system status block is part of that domain. figure 38-1. system status and configuration module block diagram 38.1.2 features the sscm includes these distinctive features: ? system configuration and status ? memory sizes/status ? device mode and security status ? determine boot vector ? search code flash for bootable sector ? device identification inform ation (mcu id registers) bus system status and configuration module interface password comparator revid hardmacro core logic system status peripheral interface bus debug port
pxd10 microcontroller reference manual, rev. 1 38-2 freescale semiconductor preliminary?subject to change without notice ? debug status port enable and selection ? bus and peripheral abort enable/disable 38.1.3 modes of operation the sscm operates identically in all system modes. 38.2 memory map and register description this section provides a detailed description of all memory-mapped registers in the sscm. 38.2.1 memory map table 38-1 shows the memory map for the sscm. note that all addresses are offsets; the absolute address may be calculated by adding the specified offset to the base address of the sscm. all registers are accessible via 8-bit, 16-bit or 32-bit accesses. ho wever, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be al igned to 32-bit boundaries. as an example, the status register is accessible by a 16-bit read/ write to address ?base + 0x0002?, but performing a 16-bit access to ?base + 0x0003? is illegal. 38.2.2 register description the following memory-mapped register s are available in the sscm. those bits that are shaded out are reserved for future use. to optimize future compat ibility, these bits should be masked out during any read/write operations to avoid c onflict with future revisions. table 38-1. module memory map address register size access mode 1 1 u = user mode, s = supervisor mode, t = test mode, v = dfv mode, a = all (no restrictions) base + 0x0000 system status (status) 16 bits r a base + 0x0002 system memory configuration (memconfig) 16 bits r a base + 0x0004 reserved 16 bits reads/writes have no effect a base + 0x0006 error configuration (error) 16 bits r/w a base + 0x0008 debug status port (debugport) 16 bits r/w a base + 0x000a reserved 16 bits reads/writes have no effect a base + 0x000c password comparison register high word 32 bits r/w a base + 0x0010 password comparison register low word 32 bits r/w a base + 0x0014 to base + 0x3fff reserved see note 2 2 if enabled at the soc level, accessing these register addresses will cause bus aborts.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 38-3 preliminary?subject to change without notice 38.2.2.1 system status register (status) the system status register is a read-only register that reflects the current state of the system. 38.2.2.2 system memory configuration register the system memory configur ation register is a read-o nly register that reflects the memory configuration of the system. address: base + 0x0000 access: read only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 nxen pub sec 0 bmode[2:0] 0 abd 0 0 0 w reset: 000000000/10/10/10 0000 = reserved figure 38-2. status (status) register table 38-2. status allowed register accesses 8-bit 16-bit 32-bit 1 1 all 32-bit accesses must be aligned to 32-bi t addresses (i.e. 0x0, 0x4, 0x8 or 0xc). read allowed allowed allowed write not allowed not allowed not allowed table 38-3. status field descriptions field description 4 nxen nexus enabled. pub public serial access status. this bit indicates wh ether serial boot mode with public password is allowed. 1 serial boot mode with public password is allowed 0 serial boot mode with private flash password is allowed, provided the key hasn?t been swallowed sec security status. this bit reflects t he current security state of the flash. 1 the flash is secured 0 the flash is not secured 8-10 bmode [0:2] device boot mode. 000 reserved for flexray boot serial boot loader 001 legacy bootstrap via can 010 legacy bootstrap via uart 011 single chip 100 - 111 reserved this field is only updated during reset. 12 abd autobaud. indicates that autobaud detection is active when in sci or can serial boot loader mode. no meaning in other modes.
pxd10 microcontroller reference manual, rev. 1 38-4 freescale semiconductor preliminary?subject to change without notice 38.2.2.3 error configuration the error configuration register is a read-write register that controls the error handling of the system. address : base + 0x0002 access: read only 0123456789101112131415 r ivld dvld w reset: xxxxxxxxxx1xxxx1 = reserved figure 38-3. system memory configuration (memconfig) register table 38-4. memconfig field descriptions field description ivld code flash valid. this bit identifies whether or no t the on-chip code flash is accessible in the system memory map. the flash may not be accessible due to se curity limitations, or bec ause there is no flash in the system. 1 code flash is accessible 0 code flash is not accessible dvld data flash valid. this bit identif ies whether or not the on-chip data fl ash is visible in the system memory map. the flash may not be accessible due to security limitations, or because there is no flash in the system. 1 data flash is visible 0 data flash is not visible table 38-5. memconfig allowed register accesses 8-bit 16-bit 32-bit read allowed allowed allowed (also reads status register) write not allowed not allowed not allowed address : base + 0x0006 access: read/write 0123456789101112131415 r 00000000000000 pa e r a e w reset: 0000000000000000 = reserved figure 38-4. error confi guration (error) register
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 38-5 preliminary?subject to change without notice 38.2.2.4 debug status port register the debug status port register is used to (optionally) provide debug data on a set of pins. table 38-6. error field descriptions field description 14 pa e peripheral bus abort enable. this bit enables bus aborts on any access to a peripheral slot that is not used on the device. this feature is intended to ai d in debugging when developing application code. 1 illegal accesses to non-existing peripherals pr oduce a prefetch or data abort exception 0 illegal accesses to non-existing peripherals do no t produce a prefetch or data abort exception 15 rae register bus abort enable. this bit enables bus aborts on illegal accesses to off-platform peripherals. illegal accesses are defined as reads or writes to reserved addresses within the address space for a particular peripheral. this feature is intended to aid in debugging when developing application code. 1 illegal accesses to peripherals produce a prefetch or data abort exception 0 illegal accesses to peripherals do not produce a prefetch or data abort exception transfers to peripheral bus resources may be aborted even before they reach the peripheral bus (i.e. at the aips level). in this case, the per_abort and reg_abort register bits will have no effect on the abort. table 38-7. error allowed register accesses 8-bit 16-bit 32-bit read allowed allowed allowed write allowed allowed not allowed address: base + 0x0008 access: read/write 0123456789101112131415 r 0000000000000debug_mode[2:0]] w reset: 0000000000000000 = reserved for future use figure 38-5. debug status port (debugport) register
pxd10 microcontroller reference manual, rev. 1 38-6 freescale semiconductor preliminary?subject to change without notice 38.2.2.5 password comparison registers these registers allow to unsecure the de vice, if the correct password is known. table 38-8. debugport field descriptions field description 13-15 debug _mode [0:2] debug status port mode. this field selects the alte rnate debug functionality for the debug status port 000 no alternate functionality selected 001 mode 1 selected 010 mode 2 selected 011 mode 3 selected 100 mode 4 selected 101 mode 5 selected 110 mode 6 selected 111 mode 7 selected table 38-9 describes the functionality of the debug status port in each mode. table 38-9. debug status port modes pin 1 1 all signals are active high, unless otherwise noted mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 0 status[0] status[8] memconfig[0] memconfig[8] reserved reserved reserved 1 status[1] status[9] memconfig[1] memconfig[9] reserved reserved reserved 2 status[2] status[10] memconfig[2] memconfig[10] reserved reserved reserved 3 status[3] status[11] memconfig[3] memconfig[11] reserved reserved reserved 4 status[4] status[12] memconfig[4] memconfig[12] reserved reserved reserved 5 status[5] status[13] memconfig[5] memconfig[13] reserved reserved reserved 6 status[6] status[14] memconfig[6] memconfig[14] reserved reserved reserved 7 status[7] status[15] memconfig[7] memconfig[15] reserved reserved reserved table 38-10. debugport allowed register accesses 8-bit 16-bit 32-bit 1 1 all 32-bit accesses must be aligned to 32-bi t addresses (i.e. 0x0, 0x4, 0x8 or 0xc). read allowed allowed not allowed write allowed allowed not allowed
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 38-7 preliminary?subject to change without notice address: 0x000c access: read/write 0123456789101112131415 r 0000000000000000 w pwd_hi[0:15] reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w pwd_hi[16:31] reset 0000000000000000 figure 38-6. password comparison register high word (pwcmph) address: 0x0010 access: read/write 0123456789101112131415 r 0000000000000000 w pwd_lo[0:15] reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w pwd_lo[16:31] reset 0000000000000000 figure 38-7. password comparison register low word (pwcmpl) table 38-11. password comparison register field descriptions field description 0-31 pwd_hi [0:31] upper 32 bits of the password 0-31 pwd_lo [0:31] lower 32 bits of the password
pxd10 microcontroller reference manual, rev. 1 38-8 freescale semiconductor preliminary?subject to change without notice in order to unsecure the device, the password needs to be written as follows: first the upper word to the pwcmph register, then the lower word to the pwcmpl register. the sscm compares the password and if the password is correct, unlocks the device. 38.3 functional description the primary purpose of the sscm is to provide information about the cu rrent state and configuration of the system that may be useful for configuring application softwa re and for debug of the system. 38.4 initialization/application information 38.4.1 reset the reset state of each indivi dual bit is shown within the section 38.2.2, register description . table 38-12. pwcmph/l allowed register accesses 8-bit 16-bit 32-bit 1 1 all 32-bit accesses must be aligned to 32-bi t addresses (i.e. 0x0, 0x4, 0x8 or 0xc). read allowed allowed allowed write not allowed not allowed allowed
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 39-1 preliminary?subject to change without notice chapter 39 system timer module (stm) 39.1 introduction 39.1.1 overview the system timer module (stm) is a 32-bit timer designed to suppor t commonly required system and application software timing func tions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). 39.1.2 features the stm has the following features: ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 39.1.3 modes of operation the stm supports two device mode s of operation: normal and debug. when the stm is enabled in norma l mode, its counter runs conti nuously. while debugging, operation of the counter is controlled by the st m_cr[frz] bit. if the frz bit is se t, the counter is stopped when the mcu is stopped by a debugger, ot herwise it continues to run. 39.2 external signal description the stm does not have any external interface signals. 39.3 memory map and register definition the stm programming model has fourt een 32-bit registers. the stm regi sters can only be accessed using 32-bit (word) accesses. attempted refe rences using a different size or to a reserved address generates a bus error termination. 39.3.1 memory map the stm memory map is shown in table 39-1 .
pxd10 microcontroller reference manual, rev. 1 39-2 freescale semiconductor preliminary?subject to change without notice 39.3.2 register descriptions the following sections detail the individua l registers within the stm programming model. figure 39-1 shows the conventions used in the register figures. 39.3.2.1 stm control register (stm_cr) the stm control register (stm_cr) includes the prescale value, free ze control and timer enable bits. table 39-1. stm memory map address offset register name register description size (bits) access location 0x0000 stm_cr stm control register 32 r/w on page 2 0x0004 stm_cnt stm counter value 32 r/w on page 3 0x0008 reserved 32 r/w 0x000c reserved 32 r/w 0x0010 stm_ccr0 stm channel 0 control register 32 r/w on page 4 0x0014 stm_cir0 stm channel 0 interrupt register 32 r/w on page 4 0x0018 stm_cmp0 stm channel 0 compare register 32 r/w on page 5 0x001c reserved 32 r/w 0x0020 stm_ccr1 stm channel 1 control register 32 r/w on page 4 0x0024 stm_cir1 stm channel 1 interrupt register 32 r/w on page 4 0x0028 stm_cmp1 stm channel 1 compare register 32 r/w on page 5 0x002c reserved 32 r/w 0x0030 stm_ccr2 stm channel 2 control register 32 r/w on page 4 0x0034 stm_cir2 stm channel 2 interrupt register 32 r/w on page 4 0x0038 stm_cmp2 stm channel 2 compare register 32 r/w on page 5 0x003c reserved 32 r/w 0x0040 stm_ccr3 stm channel 3 control register 32 r/w on page 4 0x0044 stm_cir3 stm channel 3 interrupt register 32 r/w on page 4 0x0048 stm_cmp3 stm channel 3 compare register 32 r/w on page 5 0x004c - 0x3fff - reserved - - always reads 1 1always reads 0 0r/w bit bit read- only bit bit write- only bit write 1 to clear bit self-clear bit 0n/a bit w1c bit figure 39-1. key to register fields
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 39-3 preliminary?subject to change without notice table 39-2. stm_cr field descriptions 39.3.2.2 stm count register (stm_cnt) the stm count register (stm_cnt) holds the timer count value. offset 0x000 access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cps 0 0 00 00 frz ten w reset0000000000000000 figure 39-2. stm control register (stm_cr) field description cps counter prescaler. selects the clock divide value for the prescaler (1 - 256). 0x00 = divide system clock by 1 0x01 = divide system clock by 2 ... 0xff = divide system clock by 256 frz freeze. allows the timer counter to be stopped when the mcu is stopped by a debugger. 0 = stm counter continues to run in debug mode. 1 = stm counter is stopped in debug mode. ten timer counter enabled. 0 = counter is disabled. 1 = counter is enabled. offset 0x004 access: read/write 012345678910111213141516171819202122232425262728293031 r cnt w reset00000000000000000000000000000000 figure 39-3. stm count register (stm_cnt)
pxd10 microcontroller reference manual, rev. 1 39-4 freescale semiconductor preliminary?subject to change without notice table 39-3. stm_cnt field descriptions 39.3.2.3 stm channel cont rol register (stm_ccrn) the stm channel control register (stm_ccrn) has the enable bit for channel n of the timer. table 39-4. stm_ccrn field descriptions 39.3.2.4 stm channel interrupt register (stm_cirn) the stm channel interrupt register (stm_cirn) has the interrupt flag for channel n of the timer. field description cnt timer count value used as the time base for all chan nels. when enabled, the counter increments at the rate of the system clock divided by the prescale value. offset 0x10+0x10*n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000 cen w reset0000000000000 0 00 figure 39-4. stm channel control register (stm_ccrn) field description cen channel enable. 0 = the channel is disabled. 1 = the channel is enabled.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 39-5 preliminary?subject to change without notice table 39-5. stm_cirn field descriptions 39.3.2.5 stm channel comp are register (stm_cmpn) the stm channel compare regi ster (stm_cmpn) holds the compare value for channel n. table 39-6. stm_cmpn register field descriptions offset 0x14+0x10*n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000cif w w1c reset0000000000000 0 00 figure 39-5. stm channel interrupt register (stm_cirn) field description cif channel interrupt flag 0 = no interrupt request. 1 = interrupt request due to a match on the channel. offset 0x18+0x10*n access: read/write 012345678910111213141516171819202122232425262728293031 r cmp w reset00000000000000000000000000000000 figure 39-6. stm channel compare register (stm_cmpn) field description cmp compare value for channel n. if the stm_ccrn[cen] bit is set and the stm_cmpn register matches the stm_cnt register, a channel interrupt request is generated and the stm_cirn[cif] bit is set.
pxd10 microcontroller reference manual, rev. 1 39-6 freescale semiconductor preliminary?subject to change without notice 39.4 functional description the system timer module (stm) is a 32-bit timer designed to suppor t commonly required system and application software timing func tions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the stm has one 32-bit up counter (stm_cnt) that is used as the time base for all channels. when enabled, the counter increments at the system clock frequency divided by a prescale value. the stm_cr[cps] field sets the divider to any value in the range from 1 to 256. the counter is enabled with the stm_cr[ten] bit. when enabled in normal mode the counter continuously increments. when the mcu is stopped by a debugger, the counter operation is c ontrolled by the stm_cr[frz] bit. when the stm_cr[frz] bit is set, the counter is stopped in debug mode, otherw ise it continues to run in debug mode. the counter rolls over at 0xffff_ffff to 0x0000_0000 with no restrictions at this boundary. the stm has four identical compare channels. e ach channel includes a channel control register (stm_ccrn), a channel interrupt re gister (stm_cirn) and a channe l compare register (stm_cmpn). the channel is enabled by setting the stm_ccrn[cen ] bit. when enabled, the channel will set the stm_cir[cif] bit and generate an interrupt request when the channel compare register matches the timer counter. the interrupt request is cl eared by writing a 1 to the stm_cirn[cif] bit. a write of 0 to the stm_cirn[cif] bit has no effect. note the stm counter does not advance wh en the system clock is stopped.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 40-1 preliminary?subject to change without notice chapter 40 voltage regulators and power supplies 40.1 introduction this device includes three on-chip voltage regulator s for power management and distribution, allowing low-power operation and optimi zation of power consumption. on this device, the general purpose inputs and outputs (gpio) are arranged in several banks with separate external gpio power supply pins, allowing groups of gpio to opera te at different supply voltages. 40.2 voltage regulators the internal voltage regulator s are used to provide a 1.2 v digital suppl y to the internal logic of the device. the main/input supply is 3.3 v to 5.0 v 10% and the digital/regulated output supply is 1.2 v 10%. the voltage regulator used in this device comprises three regulators. ? high power or main regulator (hpreg) requi ring an external npn ballast transistor. ? low power regulator (lpreg) ? ultra low power regulator (ulpreg) the hpreg and lpreg regulators are switched off in standby mode to sa ve power consumption by the regulator itself. during stop a nd halt modes only, the hpreg regul ator may be switched off. the ulpreg regulator is always kept on. the internal voltage regulators require an external cap acitance to be connected to the 1.2 v supply pins in order to provide a stable low volta ge digital supply to the device. capacitances should be placed on the board as near as possible to the associated pins. the regulator has two digital domains, one for the ma in regulator (hpreg) and the low power regulator (lpreg) called the ?high power domai n?, and one for the ultra low pow er regulator (ulpreg) called the ?standby domain?. for each domain there is a low vol tage detector (lvd) fo r the 1.2 v output voltage (ulvdd and mlvdd). additiona lly, there are two low voltage dete ctors for the main /input supply with different thresholds, one at 3.3 v (u lvdm), the other at 5 v (ulvdm5).
pxd10 microcontroller reference manual, rev. 1 40-2 freescale semiconductor preliminary?subject to change without notice 40.2.1 block diagram figure 40-1. voltage regulator diagram 40.2.2 external signals table 40-1 provides an overview of the volta ge regulator external signals. core mlvdd bkup ulvdm5 ulvdd ulvdm por hpreg lpreg ulpreg vplusio vplusio vplusio vboard npn
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 40-3 preliminary?subject to change without notice 40.2.3 detailed signal descriptions 40.2.3.1 vddr vddr is the 3.3 v to 5 v supply for the voltage regulat ors and lvd blocks. see the device data sheet for details of recommended decoupl ing capacitance on this pin. 40.2.3.2 vrc vrc is the 1.2 v regulator output that drives the base of the external npn ballast transistor. 40.3 memory map and register definition 40.3.1 voltage regulator co ntrol register (vreg_ctl) table 40-1. voltage regulator external signals name type voltage description vddr supply 3.0 v - 5.5 v power supply for the voltage regulators vssr ground - ground supply for digital core and voltage regulators vrc output - regulator drive for external npn transistor base table 40-2. voltage regulator memory map address register access reset value vreg_base + 0x0000 vreg_ctl - voltage regulator control register r/w 0x00000001 address offset: 00h access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 000000000000 0 w reset 0 0 0 000000000000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0000000000005v_lvd _mask w reset 0 0 0 000000000000 1 figure 40-2. voltage regulator control register (vreg_ctl)
pxd10 microcontroller reference manual, rev. 1 40-4 freescale semiconductor preliminary?subject to change without notice 40.4 functional description 40.4.1 high power or main regulator (hpreg) the hpreg converts the 3.3 v to 5 v input supply voltage to the 1.2 v digital supply. the nominal target output is 1.2 v. the actual output will be in range of 1.08?1.32 v in th e full current load range 0?400 ma after trimming. the hpreg regulator requires an external npn ball ast transistor. recommende d transistors are bcp68 from on semiconductor or bcp 56 from stmicroelectronics. stabilization of the hpreg is achieved using an external capacitance. the regulator can be switched off by software. 40.4.2 low power regulator (lpreg) the lpreg generates power for the chip in stop m ode, providing the output suppl y of 1.2 v. the control part of the regulator can be used to disable the low power regulator . this action is managed by mc_me. 40.4.3 ultra low power regulator (ulpreg) the ulpreg generates power for th e standby domain as well as a part of the main domain. the control circuit of ulpreg ca n be used to disable the ultra low power regulator by sw. this action is managed by mc_me. 40.4.4 low voltage detectors (lvd) and power on reset (por) four lvds are available (see figure 40-1 ). ? ulvdm for the 3.3 v to 5 v input supply with threshold at the 3.3 v level ? ulvdm5 for the 3.3 v to 5 v input suppl y with threshold at the 5 v level ? two lvd_digs, ulvdd and mlvdd, for the 1.2 v output voltage ulvdm and ulvdm5 sense the 3.3 v to 5 v power supply for core, shared with the gpio ring supply, and indicate when the 3.3 v to 5 v supply is stable. the threshold levels of ulvd m5 are trimmable with the help of lvdm5[0:3] trim bits. table 40-3. vreg_ctl field descriptions field description 0-30 reserved. 31 5v lvd mask : mask bit for 5 v lvd from regulator this is a read/write bit and must be unmasked by writing a ?1? by software to generate lvd functional reset request to mc_rgm for 5 v trip. 15v lvd is masked 0 5 v lvd is not masked.
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 40-5 preliminary?subject to change without notice two lvd_digs are provided in the design. one lvd_di g is placed in the high power domain and senses the hpreg/lpreg output, indicating that the 1.2 v output is stable. the other lvd_dig is placed in the standby domain and senses the stand by 1.2 v supply level, indicating that the 1.2 v output is stable. the reference voltage used for all lvds is generated by the low power refe rence generator a nd is trimmed for lvd_dig, using the bits lp[4:7]. therefore, dur ing the pre-trimming period, lvd_dig exhibits higher thresholds whereas, after trimming, the thresholds come within the desired range. power-down pins are provided for lvds. when lvds are power ed down, their outputs are pulled high. por is required to initialize the ch ip during the voltage s upply rise time. por works only on the rising edge of the main supply voltage. to ensure that it functions during the following rising edge of the supply voltage, it is reset by the output of the ulvdm block when the main supply goes below the lower voltage threshold of ulvdm. por is asserted on power-up when the vdd supply is above the minimum value of v porup (refer to the device data sheet for this valu e). it will be released only after the vdd supply goes above v porh (refer to the device data sheet for this value). vdd above v porh ensures that the power management module, including the internal lvd modules, are fully functional. 40.4.5 vreg digital interface the voltage regulator digital interface provides the temporization delay at initial power-up and at exit from low-power modes. a signal, indicating that ultra lo w power domain is powered, is used at power-up to release reset to temporization count er. at exit from low-power mode s, the power-down for high power regulator request signal is monitored by the digital interface and used to release reset to the temporization counter. in both cases, on co mpletion of the delay counter , an end-of-count signal is released; this is gated with an other signal indicating that the main domain voltage is fine, in order to release the vregok signal. this is used by mc_rgm to release the reset to the device. it manages other specific requirements, including the transition be tween high power or low power mode to ultra lo w power mode, avoiding a voltage drop below the permissi ble threshold limit of 1.08v. the vreg digital interface also contai ns a control register to mask th e 5 v lvd status from the voltage regulator at power-up.
pxd10 microcontroller reference manual, rev. 1 40-6 freescale semiconductor preliminary?subject to change without notice 40.5 gpio power supply configuration the gpio pins on this device are organized in five separate banks. each ba nk has associated vdd/vss power supply pairs. the five banks of gpio can be powered independent ly, allowing these banks to be run at different voltages in the 3.0 v to 5.5 v range. table 40-4 describes the gpio banks, their main functions, supply pins and associated port pins. for full details of gpio functionality, refer to chapter 3, signal description . table 40-4. gpio power bank supplies and functionality gpio bank available functions 1 1 not all functions are available simultaneously. refer to chapter 3. supply pins port pins stepper motor bank stepper motors [1:0], emios stepper motors [3:2], emios stepper motors [5:4], emios vddma 2 , vssma vddmb 2 , vssmb vddmc 2 , vssmc 2 if vddma, vddmb, and vddmc are all powered, the must all be connected to the same supply level. portd[7:0] portd[15:8] porte[7:0] analog bank 0 adc, 32 khz sxosc vdde_c, vsse_c portc[15:0] digital bank 0 dcu, quadspi, lcd, emios, i2c, can, lin vdde_a, vsse_a porta[15:0] portf[15:3, 1:0] portg[12:0] porth[5] digital bank 1 can, lin, i2c, spi, emios, pdi, adc-mux, nexus 3 3 nexus available on dedicated pins in digital bank 1 for 208mapbga package option and as a multiplexed option on 176lqfp package option vdde_b, vsse_b portb[13:12, 9:4] portf[2] porth[4:0] portj[7:4] portk[11:2] reset digital bank 2 can, lin, emios, pdi vdde_e, vsse_e portb[11:10, 3:0] portj[15:8, 3:0] portk[1:0]
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 40-7 preliminary?subject to change without notice figure 40-3. power supply configuration 40.6 power domain organization to satisfy stringent require ments for current consumption in the di fferent operational modes, this device is partitioned into different power domains. orga nization into these power domains primarily means having separate power suppl ies that are separated from each othe r by the use of power switches. these r analog bank 0 stepper motor bank digital bank 1 digital bank 0 digital bank 2 vreg 4-16 mhz fmpll fxosc vddr vrc_ctrl vddmc vddmb vddma vdde_c vdde_a vdde_e vdde_b vdde_b vdde_a vdde_a vddpll vsspll vss-osc vdda vssa 3.0 v to 5.5 v 3.0 v to 3.6 v to 3-5 v or 3.3 v supply to 3-5 v or 3.3 v supply to 3-5 v or 3.3 v supply to 3-5 v or 3.3 v supply to 3-5 v or 3.3 v supply vdd12 vss vdd12 vss vss vssmc vssmb vssma vdd12 vss vdd12 vss vdd12 vss vdd12 vss vss vss vss vss to 3-5 v or 3.3 v supply vlcd vpp prog external ballast npn
pxd10 microcontroller reference manual, rev. 1 40-8 freescale semiconductor preliminary?subject to change without notice different separated power supplies are hence able to switch off power to certain regions of the device, to avoid even leakage current consumption in logic supplied by the co rresponding power supply. this device employs three prim ary power domains: power domains pd0 and pd1, and a ram power domain rd1. power domain organization and connections to the internal regulator are depicted in figure 40-4 .
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 40-9 preliminary?subject to change without notice figure 40-4. power domain organization vdd_lv_bkp power domain 0 (pd0) power domain 1 (pd1) mc_pcu hpvdd ulpvdd lpvdd sw1 128 khz rc mc_rgm 16 mhz rc vrc_ctrl hv por1hv por2hv nbypass hppd lppd vreg api can sampler wkpu cflash 160k rc dig wakeup pads siul option reset e200z0h platform pa 0 mc_cgm mc_me peripheral set fmpll0 peripheral set adc 8k ram power domain 2 40k ram sw2 pa x pbx pcx pfx pjx bits rtc 4-16 mhz 32 khz osc osc fmpll1 vdd5 pa 1 pa 2 ph5 : : vdd12 (pd2) graphics ram display control unit dflash
pxd10 microcontroller reference manual, rev. 1 40-10 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 41-1 preliminary?subject to change without notice chapter 41 wakeup unit (wkpu) 41.1 overview the wakeup unit supports up to 19 1 external sources that can genera te interrupts or wakeup events, of which one can cause non-mask able interrupt requests. figure 41-1 is a block diagram of the wakeup unit and its interfaces to other system components. the wakeup lines are mapped to the interrupt vectors as shown in table 41-1 . figure 41-1. wakeup unit block diagram 1. up to 19 external sources in the 176-pin and the 208bga packages; up to 17 external sources in the 144-pin packages ips bus pads interrupt controller aips mode / power ctl irqs sys wakeup wakeup 18 platform 3 nmi / wakeup - configuration irq / wakeup - configuration wakeup unit iomux rtc, etc. 0-18 filter filter filter bypass filter bypass nmi enable
pxd10 microcontroller reference manual, rev. 1 41-2 freescale semiconductor preliminary?subject to change without notice 41.2 features the wakeup unit supports th ese distinctive features: ? non-maskable interrupt support with ? 1 nmi source with bypassable glitch filter ? independent interrupt destinatio n: non-maskable interrupt, criti cal interrupt, or machine check request ? edge detection ? external wakeup/interrupt support with ? up to 3 system interrupt vectors for 18 interrupt sources ? analog glitch filter per each wakeup line table 41-1. wakeup vector mapping wakeup vector wakeup number function package port #1 #2 #3 special 144 176 208 0 wkup0 pa0 dcu_r0 emiosa22 sound fp23 x x x wkup1 pb1 canrx_0 pdi0 x x x wkup2 pb3 rxd_0 x x x wkup3 pb4 sck_1 ma0 x x x wkup4 pb9 sck_0 emiosb20 x x x wkup5 pb10 canrx_1 pdi2 emiosa23 x x x wkup6 pb12 rxd_1 emiosb19 pcs2_0 x x x 1 wkup7 pc0 an0 xxx wkup8 pc10 an10(mux) sound x x x wkup9 pf0 emiosa13 pdi4 emiosa22 fp39 x x x wkup10 pf2 nmi xxx wkup11 pf3 emiosa11 pdi6 fp37 x x x wkup12 pf5 emiosa9 dcu_tag fp35 x x x wkup13 pf6 sda_0 fp34 x x x 2 wkup14 pf8 sda_1 pcs1_1 rxd_1 fp32 x x x wkup15 pf11 emiosb23 pcs_c1 fp28 x x x wkup16 pf13 sin_2 canrx_1 fp26 x x x wkup17 pj4 pdi_0 canrx_0 x x wkup18 pj6 pdi_2 canrx_1 emiosa22 x x wkup19 api x x x wkup20 rtc xxx
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 41-3 preliminary?subject to change without notice ? independent interrupt mask ? edge detection ? configurable system wakeup trigge ring from all interrupt sources ? configurable pullup ? on-chip wakeup support ? up to 18 wakeup sources ? wakeup status mapped to same register as external wakeup/interrupt status 41.3 external signal description the wakeup unit has 19 signal inputs that can be used as external interrupt s ources in normal run mode or as system wakeup sources in certain power down modes. these 19 external signal inputs include one signal i nput that can be used as a non-maskable interrupt source in normal run mode or a system wakeup sources in certain power down modes. note be aware that the wake-up pins are en abled in all modes. therefore, the wake-up pins should be correctly term inated to ensure minimal current consumption. any unused wake-up signa l input should be terminated by using an external pull-up or pull-dow n, or by internal pull-up enabled at wipuer. also, care has to be taken on packages where the wake-up signal inputs are not bonded. for these packages you must ensure the internal pull-ups are enabled for those signals not bonded. 41.4 memory map and register description this section provides a detailed description of all registers accessibl e in the wkpu module. 41.4.1 memory map table 41-2 gives an overview on the wkpu registers implemented. table 41-2. wkpu memory map address offset use abbreviation size supported access sizes 0x0000 nmi status flag register nsr 32 32/16/8 0x0004 - 0x0007 reserved 0x0008 nmi configuration register ncr 32 32/16/8 0x000c - 0x0013 reserved 0x0014 wakeup/interrupt stat us flag register wisr 32 32 0x0018 interrupt request enable register irer 32 32 0x001c wakeup request enable register wrer 32 32
pxd10 microcontroller reference manual, rev. 1 41-4 freescale semiconductor preliminary?subject to change without notice note reserved registers will read as 0, writ es will have no effect . if supported and enabled by the soc, a transfer error wi ll be issued when trying to access completely reserved register space. 41.4.2 register description this section describes in address order all the wakeup unit registers. each description includes a standard register diagram with an associated figure number. details of register bit and field function follow the register diagrams, in bit order. the numbering conven tion of register is msb=0, however the numering of internal field is lsb=0, e.g. eif[5] = wisr[26]. 41.4.2.1 nmi status flag register (nsr) this register holds the non-mask able interrupt status flags. 0x0020 - 0x0027 reserved 0x0028 wakeup/interrupt rising-edge event enable register wireer 32 32 0x002c wakeup/interrupt falling-edge event enable register wifeer 32 32 0x0030 wakeup/interrupt filter enable register wifer 32 32 0x0034 wakeup/interrupt pull up enable register wipuer 32 32 0x0038 - 0x03fff reserved always reads 1 1 always reads 0 0 r/w bit bit read- only bit bit write-o nly bit write 1 to clear bit self-clear bit 0 n/a bit w1c bit figure 41-2. key to register fields address:0x0000 access: user read/write (write 1 to clear) 0 1 2345678 9101112131415 r nifnovf0000000 0 000000 w w1c w1c reset 0 0 0000000 0 000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0000000 0 000000 w reset 0 0 0000000 0 000000 figure 41-3. nmi status flag register (nsr) table 41-2. wkpu memory map (continued) address offset use abbreviation size supported access sizes
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 41-5 preliminary?subject to change without notice 41.4.2.2 nmi configurat ion register (ncr) this register holds the configuration bits for the non-maskable interrupt settings. table 41-3. nsr field descriptions field description 0 nif nmi status flag this flag can be cleared only by writing a 1. writing a 0 has no effect. if enabled (nree or nfee set), nif causes an interrupt request. 1 an event as defined by nree and nfee has occurred 0 no event has occurred on the pad 1 novf nmi overrun status flag this flag can be cleared only by writing a 1. writin g a 0 has no effect. it will be a copy of the current nif value whenever an nmi event occurs, thereby indicating to the software that an nmi occurred while the last one was not yet serviced. if enabled (nree or nfee set), novf causes an interrupt request. 1 an overrun has occurred on nmi input 0 no overrun has occurred on nmi input address: 0x0008 access: user read/write 0123456789101112131415 r nloc k ndss nwre 0 nree nfee nfe 00000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000000000 w reset 0000000000000000 figure 41-4. nmi config uration register (ncr) table 41-4. ncr field descriptions field description 0 nlock nmi configuration lock register writing a 1 to this bit locks the c onfiguration for the nmi until it is unlocked by a system reset. writing a 0 has no effect. 1-2 ndss nmi destination source select 00 non-maskable interrupt 01 critical interrupt 10 machine check request 11 reserved - no nmi, critical interrup t, or machine check request generated 3 nwre[x] nmi wakeup request enable 1 a set nif bit or set novf bit causes a system wakeup request 0 system wakeup requests from t he corresponding nif bit are disabled
pxd10 microcontroller reference manual, rev. 1 41-6 freescale semiconductor preliminary?subject to change without notice note writing a ?0? to both nree and nfee disables the nmi functionality completely (i.e. no system wakeup or interrupt will be generated on any pad activity)! 41.4.2.3 wakeup/interrupt stat us flag register (wisr) this register holds the wakeup/interrupt flags. note status bits associated with on-chip wa keup sources are located to the left of the external wakeup/interrupt status bi ts and are read onl y. the wakeup for these sources must be configured and cleared at the on-ch ip wakeup source. also, the configuration registers for the external interrupts/wakeups do not have corresponding bits. 5 nree nmi rising-edge events enable 1 rising-edge event is enabled 0 rising-edge event is disabled 6 nfee nmi falling-edge events enable 1 falling-edge event is enabled 0 falling-edge event is disabled 7 nfe nmi filter enable enable analog glitch filter on the nmi pad input. 1 filter is enabled 0 filter is disabled address : 0x0014 access: user read/write (write 1 to clear) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000000 eif[20:0] 1 1 not all bits are available in the 144-pin package. w w1c reset 00000000000000000000000000000000 figure 41-5. wakeup/interrupt status flag register (wisr) table 41-5. wisr field descriptions field description eif[x] external wakeup/interrupt status flag x. this flag can be cleared only by writing a 1. writin g a 0 has no effect. if enabled (irer[x]), eif[x] causes an interrupt request. 1 an event as defined by wireer and wifeer has occurred 0 no event has occurred on the pad table 41-4. ncr field descriptions (continued) field description
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 41-7 preliminary?subject to change without notice 41.4.2.4 interrupt request enable register (irer) this register is used to enable the interrupt messa ging from the wakeup/interrupt pads to the interrupt controller. 41.4.2.5 wakeup request en able register (wrer) this register is used to enable the system wakeup messaging from the wakeup/in terrupt pads to the mode entry and power control modules. 41.4.2.6 wakeup/interrupt rising-edge event enable register (wireer) this register is used to enable rising-edge trig gered events on the corresponding wakeup/interrupt pads. note: the rc_api can only be configured on the rising edge. address: 0x0018 access: user read/write 012345678910111213141516171819202122232425262728293031 r 00000000000 eire[20:0] 1 1 not all bits are available in the 144-pin package. w reset 00000000000000000000000000000000 figure 41-6. interrupt request enable register (irer) table 41-6. irer field descriptions field description eire[x] external interrupt request enable x. 1 a set eif[x] bit causes an interrupt request 0 interrupt requests from the co rresponding eif[x] bit are disabled address: 0x001c access: user read/write 012345678910111213141516171819202122232425262728293031 r 00000000000 wre[20:0] 1 1 not all bits are available in the 144-pin package. w reset 00000000000000000000000000000000 figure 41-7. wakeup request enable register (wrer) table 41-7. wrer field descriptions field description wre[x] external wakeup request enable x. 1 a set eif[x] bit causes a system wakeup request 0 system wakeup requests from the corresponding eif[x] bit are disabled
pxd10 microcontroller reference manual, rev. 1 41-8 freescale semiconductor preliminary?subject to change without notice . 41.4.2.7 wakeup/interrupt falling-edge event enable register (wifeer) this register is used to enable falling-edge tri ggered events on the corresponding wakeup/interrupt pads. 41.4.2.8 wakeup/interrupt filter enable register (wifer) this register is used to enable an analog filter on the corresponding interr upt pads to filter out glitches on the inputs. note there is no analog filter for the rc_api. address: 0x0028 access: user read/write 012345678910111213141516171819202122232425262728293031 r 00000000000 iree[20:0] 1 1 not all bits are available in the 144-pin package. w reset 00000000000000000000000000000000 figure 41-8. wakeup/interrupt rising-edge event enable register (wireer) table 41-8. wireer field descriptions field description iree[x] external interrupt rising-edge events enable x. 1 rising-edge event is enabled 0 rising-edge event is disabled address: 0x002c access: user read/write 012345678910111213141516171819202122232425262728293031 r 00000000000 ifee[20:0] 1 1 not all bits are available in the 144-pin package. w reset 00000000000000000000000000000000 figure 41-9. wakeup/interrupt falling-edge event enable register (wifeer) table 41-9. wifeer field descriptions field description ifeex external interrupt falling-edge events enable x. 1 falling-edge event is enabled 0 falling-edge event is disabled
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 41-9 preliminary?subject to change without notice 41.4.2.9 wakeup/interrupt pullup enable register (wipuer) this register is used to enable a pullup on the corresponding interrupt pads to pull an unconnected wakeup/interrupt input to a value of ?1?. 41.5 functional description 41.5.1 general this section provides a complete func tional description of the wakeup unit. 41.5.2 non-maskable interrupts the wakeup unit supports one non-maskable interrupt which is allocated to pin 37 of the 144-pin packages, to pin 45 of the 176-pin packages and to pin l3 of the bga packages. address: 0x0030 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000000 ife[20:0] 1 1 not all bits are available in the 144-pin package. w reset 00000000000000000000000000000000 figure 41-10. wakeup/interrupt filter enable register (wifer) table 41-10. wifer field descriptions field description ife[x] external interrupt filter enable x. enable analog glitch filter on the external interrupt pad input. 1 filter is enabled 0 filter is disabled address: 0x0034 access: user read/write 012345678910111213141516171819202122232425262728293031 r 00000000000 ipue[20:0] 1 1 not all bits are available in the 144-pin package. w reset 00000000000000000000000000000000 figure 41-11. wakeup/interrupt pullup enable register (wipuer) table 41-11. wipuer field descriptions field description ipue[x] external interrupt pullup enable x. 1 pullup is enabled 0 pullup is disabled
pxd10 microcontroller reference manual, rev. 1 41-10 freescale semiconductor preliminary?subject to change without notice the wakeup unit supports the genera tion of three types of interrupts from the nmi. the wakeup unit supports the capturing of a second ev ent per nmi input before the interr upt is cleared, thus reducing the chance of losing an nmi event. each nmi passes through a bypassable analog glitch filter. note glitch filter control a nd pad configuration should be done while the nmi is disabled in order to avoid erroneou s triggering by glitches caused by the configuration process itself. figure 41-12. nmi pad diagram 41.5.2.1 nmi management the nmi can be enabled or disabled using the single ncr register laid out to cont ain all configuration bits for an nmi in a single byte (see figure 41-4 ). the pad defined as an nmi can be configured by the user to recognize interrupts with an active rising edge, an active falling edge or both edges being active. a setting of having both edge events disabled results in no interrupt being detected and should not be configured. the active nmi edge is controlled by the user th rough the configuration of the nree and nfee bits. glitch filter edge detect flag overrun destination nmi critical irq machine check wakeup enable cpu mode/ pwr ctl ndss nwre nree nfee nfe nmi configuration register (ncr)
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 41-11 preliminary?subject to change without notice note after reset, nree and nfee are set to ?0?, therefore the nmi functionality is disabled after reset and must be enabled explicitly by software. once the pad?s nmi functionality has been enabled, the pad cannot be reconfigured in the iomux to override or disable the nmi. the nmi destination interrupt is c ontrolled by the user through the c onfiguration of the ndss bits. see table 41-4 for details. an nmi supports a status flag and an overrun flag which are lo cated in the nsr register (see table 41-3 ). this register is a clear-by-write-1 register type, pr eventing inadvertent overwriti ng of other flags in the same register. the stat us flag is set whenever an nmi event is detected. the overrun flag is set whenever an nmi event is detected and the status fl ag is set (i.e. has not yet been cleared). note the overrun flag is cleared by writing a ?1? to the appropriate overrun bit in the nsr register. if the status bit is cl eared and the overrun b it is still set, the pending interrupt will not be cleared. 41.5.3 external wakeups/interrupts the wakeup unit supports up to 19 external wakeup/ interrupts which can be allocated to any pad necessary at the soc level. th is allocation is fixed per soc. the wakeup unit supports three interrupt vectors to th e interrupt controller of the soc. each interrupt vector can support up to the number of external interrupt sources from the device pads with the total across all vectors being equal to the numbe r of external interrupt sources. ea ch external interrupt source is assigned to exactly one inte rrupt vector. the interrupt vector assignm ent is sequential so that one interrupt vector is for external interrupt sources 0 through n-1, the next is for n through n+m-1, and so forth. refer to figure 41-13 for an overview of the external interrupt implementation for th e example of three interrupt vectors with up to eight external interrupt sources each.
pxd10 microcontroller reference manual, rev. 1 41-12 freescale semiconductor preliminary?subject to change without notice figure 41-13. external interrupt pad diagram all of the external interrupt pads within a single group have equal priori ty. it is the responsibility of the user software to search through th e group of sources in the most a ppropriate way for their application. note glitch filter control and pad configuration should be done while the external interrupt line is disabled in order to avoid erroneous triggering by glitches caused by the configuration process itself. 41.5.3.1 external interrupt management each external interrupt can be enabled or disabled independently. this can be performed using a single rolled up register ( table 41-6 ). a pad defined as an external interru pt can be configured by the user to recognize external interrupts with an active rising edge, an active falling edge or both edge s being active. note writing a ?0? to both iree[x] and ifee[ x] disables the external interrupt functionality for that pad completely (i .e. no system wakeup or interrupt will be generated on any activity on that pad)! the active irq edge is controlled by the users th rough the configuration of the registers wireer and wifeer. each external interrupt supports an i ndividual flag which is held in the fl ag register (wisr). this register is a clear-by-write-1 register type, preventing inadvertent overwriting of other flags in the same register. interrupt controller int vectors pads wireer[17:0] interrupt edge enable wifeer[17:0] falling rising edge detection analog glitch filter wifer[17:0] glitch filter enable interrupt enable or or or irq_17_16 irq_15_08 irq_07_00 flag[17:16] flag[15:8] wisr[17:0] flag[7:0] wrer[17:0] wakeup enable mode/ pwr ctl irer[17:0]
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor 41-13 preliminary?subject to change without notice 41.5.4 on-chip wakeups the wakeup unit supports one on-chip wakeup source. it combines the on- chip wakeups with the external ones to generate a single wakeup to the system. 41.5.4.1 on-chip wakeup management in order to allow software to dete rmine the wakeup source at one location, on-c hip wakeups are reported along with external wakeups in the wisr register (see table 41-5 for details). enab ling and clearing of these wakeups are done via the on-chip wakeup source?s own registers.
pxd10 microcontroller reference manual, rev. 1 41-14 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor a-1 preliminary?subject to change without notice appendix a registers under protection for this device the regist er protection module is operable on the registers of table a-1 . note registers protected in the dcu are described in chapter 12, display control unit (dcu), in section 12.6.2, list of protected registers . table a-1. register under protection module register register size module base register offset protected bitfields code flash, 4 registers to protect code flash mcr 32 c3f88000 000 bits[0:31] code flash biu0 32 c3f88000 01c bits[0:31] code flash biu1 32 c3f88000 020 bits[0:31] code flash biu2 32 c3f88000 024 bits[0:31] data flash,1 registers to protect data flash mcr 32 c3f8c000 000 bits[0:31] siu lite, 64 registers to protect siul irer 32 c3f90000 018 bits[0:31] siul ireer 32 c3f90000 028 bits[0:31] siul ifeer 32 c3f90000 02c bits[0:31] siul ifer 32 c3f90000 030 bits[0:31] siul pcr0 16 c3f90000 040 bits[0:15] siul pcr1 16 c3f90000 042 bits[0:15] siul pcr2 16 c3f90000 044 bits[0:15] siul pcr3 16 c3f90000 046 bits[0:15] siul pcr4 16 c3f90000 048 bits[0:15] siul pcr5 16 c3f90000 04a bits[0:15] siul pcr6 16 c3f90000 04c bits[0:15] siul pcr7 16 c3f90000 04e bits[0:15] siul pcr8 16 c3f90000 050 bits[0:15] siul pcr9 16 c3f90000 052 bits[0:15] siul pcr10 16 c3f90000 054 bits[0:15] siul pcr11 16 c3f90000 056 bits[0:15] siul pcr12 16 c3f90000 058 bits[0:15]
pxd10 microcontroller reference manual, rev. 1 a-2 freescale semiconductor preliminary?subject to change without notice siul pcr13 16 c3f90000 05a bits[0:15] siul pcr14 16 c3f90000 05c bits[0:15] siul pcr15 16 c3f90000 05e bits[0:15] siul pcr16 16 c3f90000 060 bits[0:15] siul pcr17 16 c3f90000 062 bits[0:15] siul pcr18 16 c3f90000 064 bits[0:15] siul pcr19 16 c3f90000 066 bits[0:15] siul pcr34 16 c3f90000 084 bits[0:15] siul pcr35 16 c3f90000 086 bits[0:15] siul pcr36 16 c3f90000 088 bits[0:15] siul pcr37 16 c3f90000 08a bits[0:15] siul pcr38 16 c3f90000 08c bits[0:15] siul pcr39 16 c3f90000 08e bits[0:15] siul pcr40 16 c3f90000 090 bits[0:15] siul pcr41 16 c3f90000 092 bits[0:15] siul pcr42 16 c3f90000 094 bits[0:15] siul pcr43 16 c3f90000 096 bits[0:15] siul pcr44 16 c3f90000 098 bits[0:15] siul pcr45 16 c3f90000 09a bits[0:15] siul pcr46 16 c3f90000 09c bits[0:15] siul pcr47 16 c3f90000 09e bits[0:15] siul psmi0 8 c3f90000 500 bits[0:31] siul psmi4 8 c3f90000 504 bits[0:31] siul psmi8 8 c3f90000 508 bits[0:31] siul psmi12 8 c3f90000 50c bits[0:31] siul psmi16 8 c3f90000 510 bits[0:31] siul ifmc0 32 c3f90000 1000 bits[0:31] siul ifmc1 32 c3f90000 1004 bits[0:31] siul ifmc2 32 c3f90000 1008 bits[0:31] siul ifmc3 32 c3f90000 100c bits[0:31] siul ifmc4 32 c3f90000 1010 bits[0:31] siul ifmc5 32 c3f90000 1014 bits[0:31] table a-1. register under protection (continued) module register register size module base register offset protected bitfields
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor a-3 preliminary?subject to change without notice siul ifmc6 32 c3f90000 1018 bits[0:31] siul ifmc7 32 c3f90000 101c bits[0:31] siul ifmc8 32 c3f90000 1020 bits[0:31] siul ifmc9 32 c3f90000 1024 bits[0:31] siul ifmc10 32 c3f90000 1028 bits[0:31] siul ifmc11 32 c3f90000 102c bits[0:31] siul ifmc12 32 c3f90000 1030 bits[0:31] siul ifmc13 32 c3f90000 1034 bits[0:31] siul ifcpr 32 c3f90000 1080 bits[0:31] mc mode entry, 41 registers to protect mc_me me_me 32 c3fdc000 008 bits[0:31] mc_me me_im 32 c3fdc000 010 bits[0:31] mc_me me_test_mc 32 c3fdc000 024 bits[0:31] mc_me me_safe_mc 32 c3fdc000 028 bits[0:31] mc_me me_drun_mc 32 c3fdc000 02c bits[0:31] mc_me me_run0_mc 32 c3fdc000 030 bits[0:31] mc_me me_run1_mc 32 c3fdc000 034 bits[0:31] mc_me me_run2_mc 32 c3fdc000 038 bits[0:31] mc_me me_run3_mc 32 c3fdc000 03c bits[0:31] mc_me me_halt0_mc 32 c3fdc000 040 bits[0:31] mc_me me_stop0_mc 32 c3fdc000 048 bits[0:31] mc_me me_standby0_mc 32 c3fdc000 054 bits[0:31] mc_me me_run_pc0 32 c3fdc000 080 bits[0:31] mc_me me_run_pc1 32 c3fdc000 084 bits[0:31] mc_me me_run_pc2 32 c3fdc000 088 bits[0:31] mc_me me_run_pc3 32 c3fdc000 08c bits[0:31] mc_me me_run_pc4 32 c3fdc000 090 bits[0:31] mc_me me_run_pc5 32 c3fdc000 094 bits[0:31] mc_me me_run_pc6 32 c3fdc000 098 bits[0:31] mc_me me_run_pc7 32 c3fdc000 09c bits[0:31] mc_me me_lp_pc0 32 c3fdc000 0a0 bits[0:31] mc_me me_lp_pc1 32 c3fdc000 0a4 bits[0:31] table a-1. register under protection (continued) module register register size module base register offset protected bitfields
pxd10 microcontroller reference manual, rev. 1 a-4 freescale semiconductor preliminary?subject to change without notice mc_me me_lp_pc2 32 c3fdc000 0a8 bits[0:31] mc_me me_lp_pc3 32 c3fdc000 0ac bits[0:31] mc_me me_lp_pc4 32 c3fdc000 0b0 bits[0:31] mc_me me_lp_pc5 32 c3fdc000 0b4 bits[0:31] mc_me me_lp_pc6 32 c3fdc000 0b8 bits[0:31] mc_me me_lp_pc7 32 c3fdc000 0bc bits[0:31] mc_me me_pctl[4..7] 32 c3fdc000 0c4 bits[0:31] mc_me me_pctl[16..19] 32 c3fdc000 0d0 bits[0:31] mc_me me_pctl[20..23] 32 c3fdc000 0d4 bits[0:31] mc_me me_pctl[32..35] 32 c3fdc000 0e0 bits[0:31] mc_me me_pctl[44..47] 32 c3fdc000 0ec bits[0:31] mc_me me_pctl[48..51] 32 c3fdc000 0f0 bits[0:31] mc_me me_pctl[56..59] 32 c3fdc000 0f8 bits[0:31] mc_me me_pctl[60..63] 32 c3fdc000 0fc bits[0:31] mc_me me_pctl[68..71] 32 c3fdc000 104 bits[0:31] mc_me me_pctl[72..75] 32 c3fdc000 108 bits[0:31] mc_me me_pctl[88.91] 32 c3fdc000 118 bits[0:31] mc_me me_pctl[92..95] 32 c3fdc000 11c bits[0:31] mc_me me_pctl[104..107] 32 c3fdc000 128 bits[0:31] mc clock generation module, 3 registers to protect mc_cgm cgm_oc_en 8 c3fe0000 373 bits[0:7] mc_cgm cgm_ocds_sc 8 c3fe0000 374 bits[0:7] mc_cgm cgm_sc_dc[0..3] 32 c3fe0000 37c bits[0:31] cmu 0, 1 register to protect cmu 0 cmu_csr 32 c3fe0100 000 bits[24:31] mc reset generati on module, 9 registers to protect mc_rgm rgm_fes 16 c3fe4000 000 bits[0:15] mc_rgm rgm_des 16 c3fe4000 002 bits[0:15] mc_rgm rgm_ferd 16 c3fe4000 004 bits[0:15] mc_rgm rgm_derd 16 c3fe4000 006 bits[0:15] mc_rgm rgm_fear 16 c3fe4000 010 bits[0:15] table a-1. register under protection (continued) module register register size module base register offset protected bitfields
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor a-5 preliminary?subject to change without notice mc_rgm rgm_dear 16 c3fe4000 012 bits[0:15] mc_rgm rgm_fess 16 c3fe4000 018 bits[0:15] mc_rgm rgm_stdby 16 c3fe4000 01a bits[0:15] mc_rgm rgm_fbre 16 c3fe4000 01c bits[0:15] mc power control unit, 1 registers to protect mc_pcu pconf2 32 c3fe8000 008 bits[0:31] table a-1. register under protection (continued) module register register size module base register offset protected bitfields
pxd10 microcontroller reference manual, rev. 1 a-6 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-1 preliminary?subject to change without notice appendix b register map table b-1. module base addresses module name base addresses location adc 0 0xffe0_0000 on page 31 can sampler 0xffe7_0000 on page 38 clock generation module (mc_cgm) 0xc3fe_0370 on page 28 cmu0 0xc3fe_0100 on page 28 code flash configuration 0xc3f8_8000 on page 2 data flash 0 configuration 0xc3f8_c000 on page 3 dcu 0xffe7_c000 see chapter dma_mux 0xfffd_c000 see chapter dspi 0 0xfff9_0000 on page 47 dspi 1 0xfff9_4000 on page 48 ecsm 0xfff4_0000 on page 41 emios 0 0xc3fa_0000 on page 12 emios 1 0xc3fa_4000 on page 18 flexcan 0 (can0) 0xfffc_0000 on page 49 flexcan 1 (can1) 0xfffc_4000 on page 52 i2c 0 0xffe3_0000 on page 33 i2c 1 0xffe3_4000 on page 33 i2c 2 0xffe3_8000 on page 33 i2c 3 0xffe3_c000 on page 33 intc 0xfff4_8000 on page 43 linflex 0 0xffe4_0000 on page 34 linflex 1 0xffe4_4000 on page 37 mode entry module (mc_me) 0xc3fd_c000 on page 25 mpu 0xfff1_0000 on page 39 osc 0xc3fe_0000 on page 28 periodic interrupt timer (pit/rti) 0xc3ff_0000 on page 30 pll0 0xc3fe_00a0 on page 28 power control unit (mc_pcu) 0xc3fe_8000 on page 29 quadspi 0xfffa_8000 see chapter rcosc16m 0xc3fe_0060 on page 28
pxd10 microcontroller reference manual, rev. 1 b-2 freescale semiconductor preliminary?subject to change without notice rcosc128k 0xc3fe_0080 on page 28 real time counter (rtc/api) 0xc3fe_c000 on page 30 reset generation module (mc_rgm) 0xc3fe_4000 on page 29 sgl 0xffe7_8000 see chapter smc 0xffe6_0000 see chapter ssd 0 0xffe6_1000 see chapter ssd 1 0xffe6_1800 see chapter ssd 2 0xffe6_2000 see chapter ssd 3 0xffe6_2800 see chapter ssd 4 0xffe6_3000 see chapter ssd 5 0xffe6_3800 see chapter stm 0xfff3_c000 on page 41 swt 0 0xfff3_8000 on page 40 sxosc 0xc3fe_0040 on page 28 system integration unit lite (siul) 0xc3f9_0000 on page 3 system status and configuration module (sscm) 0xc3fd_8000 on page 24 wakeup unit 0xc3f9_4000 on page 3 table b-2. detailed register map register description register name used size address program flash 0 configuration section 17.4.3, memory map and register definition 0xc3f8_8000 module configuration register cflash_mcr 32-bit base + 0x0000 low/mid address space block locking register cflash_lml 32-bit base + 0x0004 high address space block locking register cflash_hbl 32-bit base + 0x0008 secondary low/mid address space block locking register cflash_sll 32-bit base + 0x000c low/mid address space block select r egister cflash_lms 32-bit base + 0x0010 high address space block select register cflash_hbs 32-bit base + 0x0014 address register cflash_adr 32-bit base + 0x0018 bus interface unit register 0 cflash_biu0 32-bit base + 0x001c bus interface unit register 1 cflash_biu1 32-bit base + 0x0020 bus interface unit register 2 cflash_biu2 32-bit base + 0x0024 reserved --- --- (base + 0x0028) - (base + 0x003b) table b-1. module base addresses (continued) module name base addresses location
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-3 preliminary?subject to change without notice user test register 0 cflash_ut0 32-bit base + 0x003c user test register 1 cflash_ut1 32-bit base + 0x0040 user test register 2 cflash_ut2 32-bit base + 0x0044 user multiple input signature register 0 cflash_umisr0 32-bit base + 0x0048 user multiple input signature register 1 cflash_umisr1 32-bit base + 0x004c user multiple input signature register 2 cflash_umisr2 32-bit base + 0x0050 user multiple input signature register 3 cflash_umisr3 32-bit base + 0x0054 user multiple input signature register 4 cflash_umisr4 32-bit base + 0x0058 data flash 0 configuration section 17.4.3.2, re gister descriptions 0xc3f8_c000 module configuration register cflash_mcr 32-bit base + 0x0000 low/mid address space block locking register dflash_lml 32-bit base + 0x0004 high address space block locking register dflash_hbl 32-bit base + 0x0008 secondary low/mid address space block locking register dflash_sll 32-bit base + 0x000c low/mid address space block select r egister dflash_lms 32-bit base + 0x0010 high address space block select register dflash_hbs 32-bit base + 0x0014 address register dflash_adr 32-bit base + 0x0018 reserved --- --- (base + 0x001c) - (base + 0x003b) user test register 0 dflash_ut0 32-bit base + 0x003c user test register 1 dflash_ut1 32-bit base + 0x0040 user test register 2 dflash_ut2 32-bit base + 0x0044 user multiple input signature register 0 dflash_umisr0 32-bit base + 0x0048 user multiple input signature register 1 dflash_umisr1 32-bit base + 0x004c user multiple input signature register 2 dflash_umisr2 32-bit base + 0x0050 user multiple input signature register 3 dflash_umisr3 32-bit base + 0x0054 user multiple input signature register 4 dflash_umisr4 32-bit base + 0x0058 system integration unit lite (siul) section 37.5, memory map and register description 0xc3f9_0000 reserved - - base + (0x0000 - 0x0003) mcu id register 1 midr1 32-bit base + 0x0004 mcu id register 2 midr2 32-bit base + 0x0008 reserved - - base + (0x000c - 0x0013) table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-4 freescale semiconductor preliminary?subject to change without notice interrupt status flag register isr 32-bit base + 0x0014 interrupt request enable register irer 32-bit base + 0x0018 reserved - - base + (0x001c - 0x0027) interrupt rising edge event enable ireer 32-bit base + 0x0028 interrupt falling-edge event enable ifeer 32-bit base + 0x002c ifer interrupt filter enable register ifer 32-bit base + 0x0030 reserved - - base + (0x0034 - 0x003f) pad configuration register 0 pcr0 16-bit base + 0x0040 pad configuration register 1 pcr1 16-bit base + 0x0042 pad configuration register 2 pcr2 16-bit base + 0x0044 pad configuration register 3 pcr3 16-bit base + 0x0046 pad configuration register 4 pcr4 16-bit base + 0x0048 pad configuration register 5 pcr5 16-bit base + 0x004a pad configuration register 6 pcr6 16-bit base + 0x004c pad configuration register 7 pcr7 16-bit base + 0x004e pad configuration register 8 pcr8 16-bit base + 0x0050 pad configuration register 9 pcr9 16-bit base + 0x0052 pad configuration register 10 pcr10 16-bit base + 0x0054 pad configuration register 11 pcr11 16-bit base + 0x0056 pad configuration register 12 pcr12 16-bit base + 0x0058 pad configuration register 13 pcr13 16-bit base + 0x005a pad configuration register 14 pcr14 16-bit base + 0x005c pad configuration register 15 pcr15 16-bit base + 0x005e pad configuration register 16 pcr16 16-bit base + 0x0060 pad configuration register 17 pcr17 16-bit base + 0x0062 pad configuration register 18 pcr18 16-bit base + 0x0064 pad configuration register 19 pcr19 16-bit base + 0x0066 pad configuration register 20 pcr20 16-bit base + 0x0068 pad configuration register 21 pcr21 16-bit base + 0x006a pad configuration register 22 pcr22 16-bit base + 0x006c pad configuration register 23 pcr23 16-bit base + 0x006e table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-5 preliminary?subject to change without notice pad configuration register 24 pcr24 16-bit base + 0x0070 pad configuration register 25 pcr25 16-bit base + 0x0072 pad configuration register 26 pcr26 16-bit base + 0x0074 pad configuration register 27 pcr27 16-bit base + 0x0076 pad configuration register 28 pcr28 16-bit base + 0x0078 pad configuration register 29 pcr29 16-bit base + 0x007a pad configuration register 30 pcr30 16-bit base + 0x007c pad configuration register 31 pcr31 16-bit base + 0x007e pad configuration register 32 pcr32 16-bit base + 0x0080 pad configuration register 33 pcr33 16-bit base + 0x0082 pad configuration register 34 pcr34 16-bit base + 0x0084 pad configuration register 35 pcr35 16-bit base + 0x0086 pad configuration register 36 pcr36 16-bit base + 0x0088 pad configuration register 37 pcr37 16-bit base + 0x008a pad configuration register 38 pcr38 16-bit base + 0x008c pad configuration register 39 pcr39 16-bit base + 0x008e pad configuration register 40 pcr40 16-bit base + 0x0090 pad configuration register 41 pcr41 16-bit base + 0x0092 pad configuration register 42 pcr42 16-bit base + 0x0094 pad configuration register 43 pcr43 16-bit base + 0x0096 pad configuration register 44 pcr44 16-bit base + 0x0098 pad configuration register 45 pcr45 16-bit base + 0x009a pad configuration register 46 pcr46 16-bit base + 0x009c pad configuration register 47 pcr47 16-bit base + 0x009e pad configuration register 48 pcr48 16-bit base + 0x00a0 pad configuration register 49 pcr49 16-bit base + 0x00a2 pad configuration register 50 pcr50 16-bit base + 0x00a4 pad configuration register 51 pcr51 16-bit base + 0x00a6 pad configuration register 52 pcr52 16-bit base + 0x00a8 pad configuration register 53 pcr53 16-bit base + 0x00aa pad configuration register 54 pcr54 16-bit base + 0x00ac pad configuration register 55 pcr55 16-bit base + 0x00ae table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-6 freescale semiconductor preliminary?subject to change without notice pad configuration register 56 pcr56 16-bit base + 0x00b0 pad configuration register 57 pcr57 16-bit base + 0x00b2 pad configuration register 58 pcr58 16-bit base + 0x00b4 pad configuration register 59 pcr59 16-bit base + 0x00b6 pad configuration register 60 pcr60 16-bit base + 0x00b8 pad configuration register 61 pcr61 16-bit base + 0x00ba pad configuration register 62 pcr62 16-bit base + 0x00bc pad configuration register 63 pcr63 16-bit base + 0x00be pad configuration register 64 pcr64 16-bit base + 0x00c0 pad configuration register 65 pcr65 16-bit base + 0x00c2 pad configuration register 66 pcr66 16-bit base + 0x00c4 pad configuration register 67 pcr67 16-bit base + 0x00c6 pad configuration register 68 pcr68 16-bit base + 0x00c8 pad configuration register 69 pcr69 16-bit base + 0x00ca pad configuration register 70 pcr70 16-bit base + 0x00cc pad configuration register 71 pcr71 16-bit base + 0x00ce pad configuration register 72 pcr72 16-bit base + 0x00d0 pad configuration register 73 pcr73 16-bit base + 0x00d2 pad configuration register 74 pcr74 16-bit base + 0x00d4 pad configuration register 75 pcr75 16-bit base + 0x00d6 pad configuration register 76 pcr76 16-bit base + 0x00d8 pad configuration register 77 pcr77 16-bit base + 0x00da pad configuration register 78 pcr78 16-bit base + 0x00dc pad configuration register 79 pcr79 16-bit base + 0x00de pad configuration register 80 pcr80 16-bit base + 0x00e0 pad configuration register 81 pcr81 16-bit base + 0x00e2 pad configuration register 82 pcr82 16-bit base + 0x00e4 pad configuration register 83 pcr83 16-bit base + 0x00e6 pad configuration register 84 pcr84 16-bit base + 0x00e8 pad configuration register 85 pcr85 16-bit base + 0x00ea pad configuration register 86 pcr86 16-bit base + 0x00ec pad configuration register 87 pcr87 16-bit base + 0x00ee table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-7 preliminary?subject to change without notice pad configuration register 88 pcr88 16-bit base + 0x00f0 pad configuration register 89 pcr89 16-bit base + 0x00f2 pad configuration register 90 pcr90 16-bit base + 0x00f4 pad configuration register 91 pcr91 16-bit base + 0x00f6 pad configuration register 92 pcr92 16-bit base + 0x00f8 pad configuration register 93 pcr93 16-bit base + 0x00fa pad configuration register 94 pcr94 16-bit base + 0x00fc pad configuration register 95 pcr95 16-bit base + 0x00fe pad configuration register 96 pcr96 16-bit base + 0x0100 pad configuration register 97 pcr97 16-bit base + 0x0102 pad configuration register 98 pcr98 16-bit base + 0x0104 pad configuration register 99 pcr99 16-bit base + 0x0106 pad configuration register 100 pcr100 16-bit base + 0x0108 pad configuration register 101 pcr101 16-bit base + 0x010a pad configuration register 102 pcr102 16-bit base + 0x010c pad configuration register 103 pcr103 16-bit base + 0x010e pad configuration register 104 pcr104 16-bit base + 0x0110 pad configuration register 105 pcr105 16-bit base + 0x0112 pad configuration register 106 pcr106 16-bit base + 0x0114 pad configuration register 107 pcr107 16-bit base + 0x0116 pad configuration register 108 pcr108 16-bit base + 0x0118 pad configuration register 109 pcr109 16-bit base + 0x011a pad configuration register 110 pcr110 16-bit base + 0x011c pad configuration register 111 pcr111 16-bit base + 0x011e pad configuration register 112 pcr112 16-bit base + 0x0120 pad configuration register 113 pcr113 16-bit base + 0x0122 pad configuration register 114 pcr114 16-bit base + 0x0124 pad configuration register 115 pcr115 16-bit base + 0x0126 pad configuration register 116 pcr116 16-bit base + 0x0128 pad configuration register 117 pcr117 16-bit base + 0x012a pad configuration register 118 pcr118 16-bit base + 0x012c pad configuration register 119 pcr119 16-bit base + 0x012e table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-8 freescale semiconductor preliminary?subject to change without notice pad configuration register 120 pcr120 16-bit base + 0x0130 reserved - - base + (0x0132- 0x04ff) pad selection for multiplexed inputs psmi0_3 32-bit base + 0x0500 pad selection for multiplexed inputs psmi4_7 32-bit base + 0x0504 pad selection for multiplexed inputs psmi8_11 32-bit base + 0x0508 pad selection for multiplexed inputs psmi12_15 32-bit base + 0x050c pad selection for multiplexed inputs psmi16_19 32-bit base + 0x0510 pad selection for multiplexed inputs psmi20_23 32-bit base + 0x0514 pad selection for multiplexed inputs psmi24_27 32-bit base + 0x0518 pad selection for multiplexed inputs psmi28_31 32-bit base + 0x051c reserved - - base + (0x0520- 0x05ff) gpio pad data output register gpdo0_3 32-bit base + 0x0600 gpio pad data output register gpdo4_7 32-bit base + 0x0604 gpio pad data output register gpdo8_11 32-bit base + 0x0608 gpio pad data output register gpdo12_15 32-bit base + 0x060c gpio pad data output register gpdo16_19 32-bit base + 0x0610 gpio pad data output register gpdo20_23 32-bit base + 0x0614 gpio pad data output register gpdo24_27 32-bit base + 0x0618 gpio pad data output register gpdo28_31 32-bit base + 0x061c gpio pad data output register gpdo32_35 32-bit base + 0x0620 gpio pad data output register gpdo36_39 32-bit base + 0x0624 gpio pad data output register gpdo40_43 32-bit base + 0x0628 gpio pad data output register gpdo44_47 32-bit base + 0x062c gpio pad data output register gpdo48_51 32-bit base + 0x0630 gpio pad data output register gpdo52_55 32-bit base + 0x0634 gpio pad data output register gpdo56_59 32-bit base + 0x0638 gpio pad data output register gpdo60_63 32-bit base + 0x063c gpio pad data output register gpdo64_67 32-bit base + 0x0640 gpio pad data output register gpdo68_71 32-bit base + 0x0644 gpio pad data output register gpdo72_75 32-bit base + 0x0648 gpio pad data output register gpdo76_79 32-bit base + 0x064c table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-9 preliminary?subject to change without notice gpio pad data output register gpdo80_83 32-bit base + 0x0650 gpio pad data output register gpdo84_87 32-bit base + 0x0654 gpio pad data output register gpdo88_91 32-bit base + 0x0658 gpio pad data output register gpdo92_95 32-bit base + 0x065c gpio pad data output register gpdo96_99 32-bit base + 0x0660 gpio pad data output register gpdo100_103 32-bit base + 0x0664 gpio pad data output register gpdo104_107 32-bit base + 0x0668 gpio pad data output register gpdo108_111 32-bit base + 0x066c gpio pad data output register gpdo112_115 32-bit base + 0x0670 gpio pad data output register gpdo116_119 32-bit base + 0x0674 gpio pad data output register gpdo120_123 32-bit base + 0x0678 reserved - - base + (0x067c- 0x07ff) gpio pad data input register gpdi0_3 32-bit base + 0x0800 gpio pad data input register gpdi4_7 32-bit base + 0x0804 gpio pad data input register gpdi8_11 32-bit base + 0x0808 gpio pad data input register gpdi12_15 32-bit base + 0x080c gpio pad data input register gpdi16_19 32-bit base + 0x0810 gpio pad data input register gpdi20_23 32-bit base + 0x0814 gpio pad data input register gpdi24_27 32-bit base + 0x0818 gpio pad data input register gpdi28_31 32-bit base + 0x081c gpio pad data input register gpdi32_35 32-bit base + 0x0820 gpio pad data input register gpdi36_39 32-bit base + 0x0824 gpio pad data input register gpdi40_43 32-bit base + 0x0828 gpio pad data input register gpdi44_47 32-bit base + 0x082c gpio pad data input register gpdi48_51 32-bit base + 0x0830 gpio pad data input register gpdi52_55 32-bit base + 0x0834 gpio pad data input register gpdi56_59 32-bit base + 0x0838 gpio pad data input register gpdi60_63 32-bit base + 0x083c gpio pad data input register gpdi64_67 32-bit base + 0x0840 gpio pad data input register gpdi68_71 32-bit base + 0x0844 gpio pad data input register gpdi72_75 32-bit base + 0x0848 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-10 freescale semiconductor preliminary?subject to change without notice gpio pad data input register gpdi76_79 32-bit base + 0x084c gpio pad data input register gpdi80_83 32-bit base + 0x0850 gpio pad data input register gpdi84_87 32-bit base + 0x0854 gpio pad data input register gpdi88_91 32-bit base + 0x0858 gpio pad data input register gpdi92_95 32-bit base + 0x085c gpio pad data input register gpdi96_99 32-bit base + 0x0860 gpio pad data input register gpdi100_103 32-bit base + 0x0864 gpio pad data input register gpdi104_107 32-bit base + 0x0868 gpio pad data input register gpdi108_111 32-bit base + 0x086c gpio pad data input register gpdi112_115 32-bit base + 0x0870 gpio pad data input register gpdi116_119 32-bit base + 0x0874 gpio pad data input register gpdi120_123 32-bit base + 0x0878 reserved - - base + (0x087c- 0x0bff) parallel gpio pad data out register pgpdo0 32-bit base + 0x0c00 parallel gpio pad data out register pgpdo1 32-bit base + 0x0c04 parallel gpio pad data out register pgpdo2 32-bit base + 0x0c08 parallel gpio pad data out register pgpdo3 32-bit base + 0x0c0c reserved - - (base + 0x0c10) - (base + 0x0c3f) parallel gpio pad data in regi ster pgpdi0 32-bit base + 0x0c40 parallel gpio pad data in regi ster pgpdi1 32-bit base + 0x0c44 parallel gpio pad data in regi ster pgpdi2 32-bit base + 0x0c48 parallel gpio pad data in regi ster pgpdi3 32-bit base + 0x0c4c reserved - - (base + 0x0c50) - (base + 0x0c7f) masked parallel gpio pad data out register mpgpdo0 32-bit base + 0x0c80 masked parallel gpio pad data out register mpgpdo1 32-bit base + 0x0c84 masked parallel gpio pad data out register mpgpdo2 32-bit base + 0x0c88 masked parallel gpio pad data out register mpgpdo3 32-bit base + 0x0c8c masked parallel gpio pad data out register mpgpdo4 32-bit base + 0x0c90 masked parallel gpio pad data out register mpgpdo5 32-bit base + 0x0c94 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-11 preliminary?subject to change without notice masked parallel gpio pad data out register mpgpdo6 32-bit base + 0x0c98 masked parallel gpio pad data out register mpgpdo7 32-bit base + 0x0c9c reserved - - base + (0x0ca0- 0x0fff) interrupt filter maximum counter register ifmc0 32-bit base + 0x1000 interrupt filter maximum counter register ifmc1 32-bit base + 0x1004 interrupt filter maximum counter register ifmc2 32-bit base + 0x1008 interrupt filter maximum counter register ifmc3 32-bit base + 0x100c interrupt filter maximum counter register ifmc4 32-bit base + 0x1010 interrupt filter maximum counter register fmc5 32-bit base + 0x1014 interrupt filter maximum counter register ifmc6 32-bit base + 0x1018 interrupt filter maximum counter register ifmc7 32-bit base + 0x101c interrupt filter maximum counter register ifmc8 32-bit base + 0x1020 interrupt filter maximum counter register ifmc9 32-bit base + 0x1024 interrupt filter maximum counter register ifmc10 32-bit base + 0x1028 interrupt filter maximum counter register ifmc11 32-bit base + 0x102c interrupt filter maximum counter register ifmc12 32-bit base + 0x1030 interrupt filter maximum counter register ifmc13 32-bit base + 0x1034 interrupt filter maximum counter register ifmc14 32-bit base + 0x1038 interrupt filter maximum counter register ifmc15 32-bit base + 0x103c reserved - - (base + 0x1044- 0x107c) inerrupt filter clock prescaler register ifcp 32-bit base + 0x1080 reserved - - base + (0x1084- 0x3fff) wakeup unit section 41.4, memory map and register description 0xc3f94000 nmi status flag register wkpu_nsr 32-bit base+0x0000 reserved - - (base + 0x0004) - (base + 0x0007) nmi configuration register wkpu_ncr 32-bit base+0x0008 reserved - - (base + 0x000c) - (base + 0x0013) wakeup/interrupt status flag r egister wkpu_wisr 32-bit base+0x0014 interrupt request enable register wkpu_irer 32-bit base+0x0018 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-12 freescale semiconductor preliminary?subject to change without notice wakeup request enable register wkpu_wrer 32-bit base+0x001c reserved - - (base + 0x0020) - (base + 0x0027) wakeup/interrupt rising-edge event enab le register wkpu_wireer 32-bit base+0x0028 wakeup/interrupt falling-edge event enab le register wkpu_wifeer 32-bit base+0x002c wakeup/interrupt filter enable register wkpu_wifer 32-bit base+0x0030 wakeup/interrupt pullup enable re gister wkpu_wipuer 32-bit base+0x0034 reserved - - (base + 0x0038) - (base + 0xffff) emios 0 section 9.4, memory map and register description 0xc3fa_0000 emios module configuration register emios0_mcr 32-bit base+0x0000 emios global flag register emios0_gflag 32-bit base+0x0004 emios output update disable register emios0_oudis 32-bit base+0x0008 emios disable channel register emios0_ucdis 32-bit base+0x000c reserved - - (base + 0x0010) - (base + 0x001f) emios0 uc0 a register emios0_uc0_a 32-bit base_0x0020 emios0 uc0 b register emios0_uc0_b 32-bit base_0x0024 emios0 uc0 cnt emios0_uc0_cnt 32-bit base_0x0028 emios0 uc0 control register emios0_uc0_sc 32-bit base_0x002c emios0 uc0 status register emios0_uc0_ss 32-bit base_0x0030 reserved ----- ----- base_0x0034 - base_0x003f emios0 uc1 a register emios0_uc1_a 32-bit base_0x0040 emios0 uc1 b register emios0_uc1_b 32-bit base_0x0044 reserved ----- ----- base_0x0048 - base_0x004b emios0 uc1 control register emios0_uc1_sc 32-bit base_0x004c emios0 uc1 status register emios0_uc1_ss 32-bit base_0x0050 reserved ----- ----- base_0x0054-ba se_0x005f emios0 uc2 a register emios0_uc2_a 32-bit base_0x0060 emios0 uc2 b register emios0_uc2_b 32-bit base_0x0064 reserved ----- ----- base_0x0068 - base_0x006b table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-13 preliminary?subject to change without notice emios0 uc2 control register emios0_uc2_sc 32-bit base_0x006c emios0 uc2 status register emios0_uc2_ss 32-bit base_0x0070 reserved ----- ----- base_0x0074-ba se_0x007f emios0 uc3 a register emios0_uc3_a 32-bit base_0x0080 emios0 uc3 b register emios0_uc3_b 32-bit base_0x0084 reserved ----- ----- base_0x0088 - base_0x008b emios0 uc3 control register emios0_uc3_sc 32-bit base_0x008c emios0 uc3 status register emios0_uc3_ss 32-bit base_0x0090 reserved ----- ----- base_0x0094-ba se_0x009f emios0 uc4 a register emios0_uc4_a 32-bit base_0x00a0 emios0 uc4 b register emios0_uc4_b 32-bit base_0x00a4 reserved ----- ----- base_0x00a8 - base_0x00ab emios0 uc4 control register emios0_uc4_sc 32-bit base_0x00ac emios0 uc4 status register emios0_uc4_ss 32-bit base_0x00b0 reserved ----- ----- base_0x00b4-ba se_0x00bf emios0 uc5 a register emios0_uc5_a 32-bit base_0x00c0 emios0 uc5 b register emios0_uc5_b 32-bit base_0x00c4 reserved ----- ----- base_0x00c8 - base_0x00cb emios0 uc5 control register emios0_uc5_sc 32-bit base_0x00cc emios0 uc5 status register emios0_uc5_ss 32-bit base_0x00d0 reserved ----- ----- base_0x00d4-ba se_0x00df emios0 uc6 a register emios0_uc6_a 32-bit base_0x00e0 emios0 uc6 b register emios0_uc6_b 32-bit base_0x00e4 reserved ----- ----- base_0x00e8 - base_0x00eb emios0 uc6 control register emios0_uc6_sc 32-bit base_0x00ec emios0 uc6 status register emios0_uc6_ss 32-bit base_0x00f0 reserved ----- ----- base_0x00f4-ba se_0x00ff table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-14 freescale semiconductor preliminary?subject to change without notice emios0 uc7 a register emios0_uc7_a 32-bit base_0x0100 emios0 uc7 b register emios0_uc7_b 32-bit base_0x0104 reserved ----- ----- base_0x0108 - base_0x010b emios0 uc7 control register emios0_uc7_sc 32-bit base_0x010c emios0 uc7 status register emios0_uc7_ss 32-bit base_0x0110 reserved ----- ----- base_0x0114-ba se_0x011f emios0 uc8 a register emios0_uc8_a 32-bit base_0x0120 emios0 uc8 b register emios0_uc8_b 32-bit base_0x0124 emios0 uc8 cnt emios0_uc8_cnt 32-bit base_0x0128 emios0 uc8 control register emios0_uc8_sc 32-bit base_0x012c emios0 uc8 status register emios0_uc8_ss 32-bit base_0x0130 reserved ----- ----- base_0x0134-ba se_0x013f emios0 uc9 a register emios0_uc9_a 32-bit base_0x0140 emios0 uc9 b register emios0_uc9_b 32-bit base_0x0144 reserved ----- ----- base_0x0148 - base_0x014b emios0 uc9 control register emios0_uc9_sc 32-bit base_0x014c emios0 uc9 status register emios0_uc9_ss 32-bit base_0x0150 reserved ----- ----- base_0x0154-ba se_0x015f emios0 uc10 a register emios0_uc10_a 32-bit base_0x0160 emios0 uc10 b register emios0_uc10_b 32-bit base_0x0164 reserved ----- ----- base_0x0168 - base_0x016b emios0 uc10 control register emios0_uc10_sc 32-bit base_0x016c emios0 uc10 status register emios0_uc10_ss 32-bit base_0x0170 reserved ----- ----- base_0x0174-ba se_0x017f emios0 uc11 a register emios0_uc11_a 32-bit base_0x0180 emios0 uc11 b register emios0_uc11_b 32-bit base_0x0184 reserved ----- ----- base_0x0188 - base_0x018b table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-15 preliminary?subject to change without notice emios0 uc11 control register emios0_uc11_sc 32-bit base_0x018c emios0 uc11 status register emios0_uc11_ss 32-bit base_0x0190 reserved ----- ----- base_0x0194-ba se_0x019f emios0 uc12 a register emios0_uc12_a 32-bit base_0x01a0 emios0 uc12 b register emios0_uc12_b 32-bit base_0x01a4 reserved ----- ----- base_0x01a8 - base_0x01ab emios0 uc12 control register emios0_uc12_sc 32-bit base_0x01ac emios0 uc12 status register emios0_uc12_ss 32-bit base_0x01b0 reserved ----- ----- base_0x01b4-ba se_0x01bf emios0 uc13 a register emios0_uc13_a 32-bit base_0x01c0 emios0 uc13 b register emios0_uc13_b 32-bit base_0x01c4 reserved ----- ----- base_0x01c8 - base_0x01cb emios0 uc13 control register emios0_uc13_sc 32-bit base_0x01cc emios0 uc13 status register emios0_uc13_ss 32-bit base_0x01d0 reserved ----- ----- base_0x01d4-ba se_0x01df emios0 uc14 a register emios0_uc14_a 32-bit base_0x01e0 emios0 uc14 b register emios0_uc14_b 32-bit base_0x01e4 reserved ----- ----- base_0x01e8 - base_0x01eb emios0 uc14 control register emios0_uc14_sc 32-bit base_0x01ec emios0 uc14 status register emios0_uc14_ss 32-bit base_0x01f0 reserved ----- ----- base_0x01f4-ba se_0x01ff emios0 uc15 a register emios0_uc15_a 32-bit base_0x0200 emios0 uc15 b register emios0_uc15_b 32-bit base_0x0204 reserved ----- ----- base_0x0208 - base_0x020b emios0 uc15 control register emios0_uc15_sc 32-bit base_0x020c emios0 uc15 status register emios0_uc15_ss 32-bit base_0x0210 reserved ----- ----- base_0x0214-ba se_0x021f table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-16 freescale semiconductor preliminary?subject to change without notice emios0 uc16 a register emios0_uc16_a 32-bit base_0x0220 emios0 uc16 b register emios0_uc16_b 32-bit base_0x0224 emios0 uc16 cnt emios0_uc16_cnt 32-bit base_0x0228 emios0 uc16 control register emios0_uc16_sc 32-bit base_0x022c emios0 uc16 status register emios0_uc16_ss 32-bit base_0x0230 reserved ----- ----- base_0x0234-ba se_0x023f emios0 uc17 a register emios0_uc17_a 32-bit base_0x0240 emios0 uc17 b register emios0_uc17_b 32-bit base_0x0244 reserved ----- ----- base_0x0248 - base_0x024b emios0 uc17 control register emios0_uc17_sc 32-bit base_0x024c emios0 uc17 status register emios0_uc17_ss 32-bit base_0x0250 reserved ----- ----- base_0x0254-ba se_0x025f emios0 uc18 a register emios0_uc18_a 32-bit base_0x0260 emios0 uc18 b register emios0_uc18_b 32-bit base_0x0264 reserved ----- ----- base_0x0268 - base_0x026b emios0 uc18 control register emios0_uc18_sc 32-bit base_0x026c emios0 uc18 status register emios0_uc18_ss 32-bit base_0x0270 reserved ----- ----- base_0x0274-ba se_0x027f emios0 uc19 a register emios0_uc19_a 32-bit base_0x0280 emios0 uc19 b register emios0_uc19_b 32-bit base_0x0284 reserved ----- ----- base_0x0288 - base_0x028b emios0 uc19 control register emios0_uc19_sc 32-bit base_0x028c emios0 uc19 status register emios0_uc19_ss 32-bit base_0x0290 reserved ----- ----- base_0x0294-ba se_0x029f emios0 uc20 a register emios0_uc20_a 32-bit base_0x02a0 emios0 uc20 b register emios0_uc20_b 32-bit base_0x02a4 reserved ----- ----- base_0x02a8 - base_0x02ab table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-17 preliminary?subject to change without notice emios0 uc20 control register emios0_uc20_sc 32-bit base_0x02ac emios0 uc20 status register emios0_uc20_ss 32-bit base_0x02b0 reserved ----- ----- base_0x02b4-ba se_0x02bf emios0 uc21 a register emios0_uc21_a 32-bit base_0x02c0 emios0 uc21 b register emios0_uc21_b 32-bit base_0x02c4 reserved ----- ----- base_0x02c8 - base_0x02cb emios0 uc21 control register emios0_uc21_sc 32-bit base_0x02cc emios0 uc21 status register emios0_uc21_ss 32-bit base_0x02d0 reserved ----- ----- base_0x02d4-ba se_0x02df emios0 uc22 a register emios0_uc22_a 32-bit base_0x02e0 emios0 uc22 b register emios0_uc22_b 32-bit base_0x02e4 reserved ----- ----- base_0x02e8 - base_0x02eb emios0 uc22 control register emios0_uc22_sc 32-bit base_0x02ec emios0 uc22 status register emios0_uc22_ss 32-bit base_0x02f0 reserved ----- ----- base_0x02f4-ba se_0x02ff emios0 uc23 a register emios0_uc23_a 32-bit base_0x0300 emios0 uc23 b register emios0_uc23_b 32-bit base_0x0304 emios0 uc23 cnt emios0_uc23_cnt 32-bit base_0x0308 emios0 uc23 control register emios0_uc23_sc 32-bit base_0x030c emios0 uc23 status register emios0_uc23_ss 32-bit base_0x0310 reserved ----- ----- base_0x0314-ba se_0x031f emios0 uc24 a register emios0_uc24_a 32-bit base_0x0320 emios0 uc24 b register emios0_uc24_b 32-bit base_0x0324 emios0 uc24 cnt emios0_uc24_cnt 32-bit base_0x0328 emios0 uc24 control register emios0_uc24_sc 32-bit base_0x032c emios0 uc24 status register emios0_uc24_ss 32-bit base_0x0330 reserved ----- ----- base_0x0334-ba se_0x033f emios0 uc25 a register emios0_uc25_a 32-bit base_0x0340 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-18 freescale semiconductor preliminary?subject to change without notice reserved ----- ----- base_0x0344 - base_0x034b emios0 uc25 control register emios0_uc25_sc 32-bit base_0x034c emios0 uc25 status register emios0_uc25_ss 32-bit base_0x0350 reserved ----- ----- base_0x0354-ba se_0x035f emios0 uc26 a register emios0_uc26_a 32-bit base_0x0360 reserved ----- ----- base_0x0364- base_0x036b emios0 uc26 control register emios0_uc26_sc 32-bit base_0x036c emios0 uc26 status register emios0_uc26_ss 32-bit base_0x0370 reserved ----- ----- base_0x0374- base_0x037f emios0 uc27 a register emios0_uc27_a 32-bit base_0x0380 reserved ----- ----- base_0x0384 - base_0x038b emios0 uc27 control register emios0_uc27_sc 32-bit base_0x038c emios0 uc27 status register emios0_uc27_ss 32-bit base_0x0390 reserved ----- ----- base_0x0394-ba se_0x03ff emios 1 section 9.4, memory map and register description 0xc3fa_4000 emios module configuration register emios1_mcr 32-bit base+0x0000 emios global flag register emios1_gflag 32-bit base+0x0004 emios output update disable regi ster emios1_oudis 32-bit base+0x0008 emios disable channel register emios1_ucdis 32-bit base+0x000c reserved - - (base + 0x001c) - (base + 0x001f) emios1 uc0 a register emios1_uc0_a 32-bit base_0x0020 emios1 uc0 b register emios1_uc0_b 32-bit base_0x0024 emios1 uc0 cnt emios1_uc0_cnt 32-bit base_0x0028 emios1 uc0 control register emios1_uc0_sc 32-bit base_0x002c emios1 uc0 status register emios1_uc0_ss 32-bit base_0x0030 reserved ----- ----- base_0x0034-ba se_0x003f emios1 uc1 a register emios1_uc1_a 32-bit base_0x0040 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-19 preliminary?subject to change without notice emios1 uc1 b register emios1_uc1_b 32-bit base_0x0044 reserved ----- ----- base_0x0048 - base_0x004b emios1 uc1 control register emios1_uc1_sc 32-bit base_0x004c emios1 uc1 status register emios1_uc1_ss 32-bit base_0x0050 reserved ----- ----- base_0x0054-ba se_0x005f emios1 uc2 a register emios1_uc2_a 32-bit base_0x0060 emios1 uc2 b register emios1_uc2_b 32-bit base_0x0064 reserved ----- ----- base_0x0068 - base_0x006b emios1 uc2 control register emios1_uc2_sc 32-bit base_0x006c emios1 uc2 status register emios1_uc2_ss 32-bit base_0x0070 reserved ----- ----- base_0x0074-ba se_0x007f emios1 uc3 a register emios1_uc3_a 32-bit base_0x0080 emios1 uc3 b register emios1_uc3_b 32-bit base_0x0084 reserved ----- ----- base_0x0088 - base_0x008b emios1 uc3 control register emios1_uc3_sc 32-bit base_0x008c emios1 uc3 status register emios1_uc3_ss 32-bit base_0x0090 reserved ----- ----- base_0x0094-ba se_0x009f emios1 uc4 a register emios1_uc4_a 32-bit base_0x00a0 emios1 uc4 b register emios1_uc4_b 32-bit base_0x00a4 reserved ----- ----- base_0x00a8 - base_0x00ab emios1 uc4 control register emios1_uc4_sc 32-bit base_0x00ac emios1 uc4 status register emios1_uc4_ss 32-bit base_0x00b0 reserved ----- ----- base_0x00b4-ba se_0x00bf emios1 uc5 a register emios1_uc5_a 32-bit base_0x00c0 emios1 uc5 b register emios1_uc5_b 32-bit base_0x00c4 reserved ----- ----- base_0x00c8 - base_0x00cb emios1 uc5 control register emios1_uc5_sc 32-bit base_0x00cc table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-20 freescale semiconductor preliminary?subject to change without notice emios1 uc5 status register emios1_uc5_ss 32-bit base_0x00d0 reserved ----- ----- base_0x00d4-ba se_0x00df emios1 uc6 a register emios1_uc6_a 32-bit base_0x00e0 emios1 uc6 b register emios1_uc6_b 32-bit base_0x00e4 reserved ----- ----- base_0x00e8 - base_0x00eb emios1 uc6 control register emios1_uc6_sc 32-bit base_0x00ec emios1 uc6 status register emios1_uc6_ss 32-bit base_0x00f0 reserved ----- ----- base_0x00f4-ba se_0x00ff emios1 uc7 a register emios1_uc7_a 32-bit base_0x0100 emios1 uc7 b register emios1_uc7_b 32-bit base_0x0104 reserved ----- ----- base_0x0108 - base_0x010b emios1 uc7 control register emios1_uc7_sc 32-bit base_0x010c emios1 uc7 status register emios1_uc7_ss 32-bit base_0x0110 reserved ----- ----- base_0x0114-ba se_0x011f emios1 uc8 a register emios1_uc8_a 32-bit base_0x0120 emios1 uc8 b register emios1_uc8_b 32-bit base_0x0124 emios1 uc8 cnt emios1_uc8_cnt 32-bit base_0x0128 emios1 uc8 control register emios1_uc8_sc 32-bit base_0x012c emios1 uc8 status register emios1_uc8_ss 32-bit base_0x0130 reserved ----- ----- base_0x0134-ba se_0x013f emios1 uc9 a register emios1_uc9_a 32-bit base_0x0140 emios1 uc9 b register emios1_uc9_b 32-bit base_0x0144 reserved ----- ----- base_0x0148 - base_0x014b emios1 uc9 control register emios1_uc9_sc 32-bit base_0x014c emios1 uc9 status register emios1_uc9_ss 32-bit base_0x0150 reserved ----- ----- base_0x0154-ba se_0x015f emios1 uc10 a register emios1_uc10_a 32-bit base_0x0160 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-21 preliminary?subject to change without notice emios1 uc10 b register emios1_uc10_b 32-bit base_0x0164 reserved ----- ----- base_0x0168 - base_0x016b emios1 uc10 control register emios1_uc10_sc 32-bit base_0x016c emios1 uc10 status register em ios1_uc10_ss 32-bit base_0x0170 reserved ----- ----- base_0x0174-ba se_0x017f emios1 uc11 a register emios1_uc11_a 32-bit base_0x0180 emios1 uc11 b register emios1_uc11_b 32-bit base_0x0184 reserved ----- ----- base_0x0188 - base_0x018b emios1 uc11 control register emios1_uc11_sc 32-bit base_0x018c emios1 uc11 status register em ios1_uc11_ss 32-bit base_0x0190 reserved ----- ----- base_0x0194-ba se_0x019f emios1 uc12 a register emios1_uc12_a 32-bit base_0x01a0 emios1 uc12 b register emios1_uc12_b 32-bit base_0x01a4 reserved ----- ----- base_0x01a8 - base_0x01ab emios1 uc12 control register emios1_uc12_sc 32-bit base_0x01ac emios1 uc12 status register em ios1_uc12_ss 32-bit base_0x01b0 reserved ----- ----- base_0x01b4-ba se_0x01bf emios1 uc13 a register emios1_uc13_a 32-bit base_0x01c0 emios1 uc13 b register emios1_uc13_b 32-bit base_0x01c4 reserved ----- ----- base_0x01c8 - base_0x01cb emios1 uc13 control register emios1_uc13_sc 32-bit base_0x01cc emios1 uc13 status register em ios1_uc13_ss 32-bit base_0x01d0 reserved ----- ----- base_0x01d4-ba se_0x01df emios1 uc14 a register emios1_uc14_a 32-bit base_0x01e0 emios1 uc14 b register emios1_uc14_b 32-bit base_0x01e4 reserved ----- ----- base_0x01e8 - base_0x01eb emios1 uc14 control register emios1_uc14_sc 32-bit base_0x01ec table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-22 freescale semiconductor preliminary?subject to change without notice emios1 uc14 status register em ios1_uc14_ss 32-bit base_0x01f0 reserved ----- ----- base_0x01f4-ba se_0x01ff emios1 uc15 a register emios1_uc15_a 32-bit base_0x0200 emios1 uc15 b register emios1_uc15_b 32-bit base_0x0204 reserved ----- ----- base_0x0208 - base_0x020b emios1 uc15 control register emios1_uc15_sc 32-bit base_0x020c emios1 uc15 status register em ios1_uc15_ss 32-bit base_0x0210 reserved ----- ----- base_0x0214-ba se_0x021f emios1 uc16 a register emios1_uc16_a 32-bit base_0x0220 emios1 uc16 b register emios1_uc16_b 32-bit base_0x0224 emios1 uc16 cnt emios1_uc16_cnt 32-bit base_0x0228 emios1 uc16 control register emios1_uc16_sc 32-bit base_0x022c emios1 uc16 status register em ios1_uc16_ss 32-bit base_0x0230 reserved ----- ----- base_0x0234-ba se_0x023f emios1 uc17 a register emios1_uc17_a 32-bit base_0x0240 emios1 uc17 b register emios1_uc17_b 32-bit base_0x0244 reserved ----- ----- base_0x0248 - base_0x024b emios1 uc17 control register emios1_uc17_sc 32-bit base_0x024c emios1 uc17 status register em ios1_uc17_ss 32-bit base_0x0250 reserved ----- ----- base_0x0254-ba se_0x025f emios1 uc18 a register emios1_uc18_a 32-bit base_0x0260 emios1 uc18 b register emios1_uc18_b 32-bit base_0x0264 reserved ----- ----- base_0x0268 - base_0x026b emios1 uc18 control register emios1_uc18_sc 32-bit base_0x026c emios1 uc18 status register em ios1_uc18_ss 32-bit base_0x0270 reserved ----- ----- base_0x0274-ba se_0x027f emios1 uc19 a register emios1_uc19_a 32-bit base_0x0280 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-23 preliminary?subject to change without notice emios1 uc19 b register emios1_uc19_b 32-bit base_0x0284 reserved ----- ----- base_0x0288 - base_0x028b emios1 uc19 control register emios1_uc19_sc 32-bit base_0x028c emios1 uc19 status register em ios1_uc19_ss 32-bit base_0x0290 reserved ----- ----- base_0x0294-ba se_0x029f emios1 uc20 a register emios1_uc20_a 32-bit base_0x02a0 emios1 uc20 b register emios1_uc20_b 32-bit base_0x02a4 reserved ----- ----- base_0x02a8 - base_0x02ab emios1 uc20 control register emios1_uc20_sc 32-bit base_0x02ac emios1 uc20 status register em ios1_uc20_ss 32-bit base_0x02b0 reserved ----- ----- base_0x02b4-ba se_0x02bf emios1 uc21 a register emios1_uc21_a 32-bit base_0x02c0 emios1 uc21 b register emios1_uc21_b 32-bit base_0x02c4 reserved ----- ----- base_0x02c8 - base_0x02cb emios1 uc21 control register emios1_uc21_sc 32-bit base_0x02cc emios1 uc21 status register em ios1_uc21_ss 32-bit base_0x02d0 reserved ----- ----- base_0x02d4-ba se_0x02df emios1 uc22 a register emios1_uc22_a 32-bit base_0x02e0 emios1 uc22 b register emios1_uc22_b 32-bit base_0x02e4 reserved ----- ----- base_0x02e8 - base_0x02eb emios1 uc22 control register emios1_uc22_sc 32-bit base_0x02ec emios1 uc22 status register em ios1_uc22_ss 32-bit base_0x02f0 reserved ----- ----- base_0x02f4-ba se_0x02ff emios1 uc23 a register emios1_uc23_a 32-bit base_0x0300 emios1 uc23 b register emios1_uc23_b 32-bit base_0x0304 emios1 uc23 cnt emios1_uc23_cnt 32-bit base_0x0308 emios1 uc23 control register emios1_uc23_sc 32-bit base_0x030c table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-24 freescale semiconductor preliminary?subject to change without notice emios1 uc23 status register em ios1_uc23_ss 32-bit base_0x0310 reserved ----- ----- base_0x0314-ba se_0x031f emios1 uc24 a register emios1_uc24_a 32-bit base_0x0320 emios1 uc24 b register emios1_uc24_b 32-bit base_0x0324 emios1 uc24 cnt emios1_uc24_cnt 32-bit base_0x0328 emios1 uc24 control register emios1_uc24_sc 32-bit base_0x032c emios1 uc24 status register em ios1_uc24_ss 32-bit base_0x0330 reserved ----- ----- base_0x0334-ba se_0x033f emios1 uc25 a register emios1_uc25_a 32-bit base_0x0340 reserved ----- ----- base_0x0344 - base_0x034b emios1 uc25 control register emios1_uc25_sc 32-bit base_0x034c emios1 uc25 status register em ios1_uc25_ss 32-bit base_0x0350 reserved ----- ----- base_0x0354-ba se_0x035f emios1 uc26 a register emios1_uc26_a 32-bit base_0x0360 reserved ----- ----- base_0x0364- base_0x036b emios1 uc26 control register emios1_uc26_sc 32-bit base_0x036c emios1 uc26 status register em ios1_uc26_ss 32-bit base_0x0370 reserved ----- ----- base_0x0374- base_0x037f emios1 uc27 a register emios1_uc27_a 32-bit base_0x0380 reserved ----- ----- base_0x0384 - base_0x038b emios1 uc27 control register emios1_uc27_sc 32-bit base_0x038c emios1 uc27 status register em ios1_uc27_ss 32-bit base_0x0390 reserved ----- ----- base_0x0394-ba se_0x07ff system status and configuration module (sscm) section 38.2, memory map and register description 0xc3fd_8000 system status register status 16-bit base + 0x0000 system memory configuration regi ster memconfig 16-bit base + 0x0002 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-25 preliminary?subject to change without notice reserved - - base + (0x0004- 0x0005) error configuration error 16-bit base + 0x0006 debug status port register debugport 16-bit base + 0x0008 reserved - - base + (0x000a- 0x000b) password comparison register high word pwcmph 32-bit base + 0x000c password comparison register low word pwcmpl 32-bit base + 0x0010 reserved - - base + (0x0014- 0x3fff) mode entry mo dule (mc_me) section 25.3, memory map and register definition 0xc3fd_c000 global status me_gs 32-bit base+0x0000 mode control me_mctl 32-bit base+0x0004 mode enable me_me 32-bit base+0x0008 interrupt status me_is 32-bit base+0x000c interrupt mask me_im 32-bit base+0x0010 invalid mode transition status me_imts 32-bit base+0x0014 reserved ---- ---- base+0x0018 - base+0x001f reset mode configuration me_reset_mc 32-bit base+0x0020 test mode configuration m e_test_mc 32-bit base+0x0024 safe mode configuration me_safe_mc 32-bit base+0x0028 drun mode configuration me_drun_mc 32-bit base+0x002c run0 mode configuration me_run0_mc 32-bit base+0x0030 run1 mode configuration me_run1_mc 32-bit base+0x0034 run2 mode configuration me_run2_mc 32-bit base+0x0038 run3 mode configuration me_run3_mc 32-bit base+0x003c halt0 mode configuration me_halt0_mc 32-bit base+0x0040 reserved ---- ---- base+0x0044 - base+0x0047 stop0 mode configuration me_stop0_mc 32-bit base+0x0048 reserved ---- ---- base+0x004c- base+0x0053 standby0 mode configuration me_standby0_mc 32-bit base+0x0054 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-26 freescale semiconductor preliminary?subject to change without notice reserved ---- ---- base+0x0058 - base+0x005f peripheral status registers me_ps0 32-bit base + 0x0060 peripheral status registers me_ps1 32-bit base + 0x0064 peripheral status registers me_ps2 32-bit base + 0x0068 peripheral status registers me_ps3 32-bit base + 0x006c reserved - - (base+0x0070) - (base+0x007f) run peripheral configuration registers me_run_pc0 32-bit base + 0x0080 run peripheral configuration registers me_run_pc1 32-bit base + 0x0084 run peripheral configuration registers me_run_pc2 32-bit base + 0x0088 run peripheral configuration registers me_run_pc3 32-bit base + 0x008c run peripheral configuration registers me_run_pc4 32-bit base + 0x0090 run peripheral configuration registers me_run_pc5 32-bit base + 0x0094 run peripheral configuration registers me_run_pc6 32-bit base + 0x0098 run peripheral configuration registers me_run_pc7 32-bit base + 0x009c low power peripheral configuration registers me_lp_pc0 32-bit base + 0x00a0 low power peripheral configuration registers me_lp_pc1 32-bit base + 0x00a4 low power peripheral configuration registers me_lp_pc2 32-bit base + 0x00a8 low power peripheral configuration registers me_lp_pc3 32-bit base + 0x00ac low power peripheral configuration registers me_lp_pc4 32-bit base + 0x00b0 low power peripheral configuration registers me_lp_pc5 32-bit base + 0x00b4 low power peripheral configuration registers me_lp_pc6 32-bit base + 0x00b8 low power peripheral configuration registers me_lp_pc7 32-bit base + 0x00bc reserved - - (base+0x00c0) - (base+0x00c3) peripheral control registers me_pctl4 8-bit base + 0x00c4 peripheral control registers me_pctl5 8-bit base + 0x00c5 peripheral control registers me_pctl6 8-bit base + 0x00c6 reserved - - (base+0x00c7) - (base+0x00cf) peripheral control registers me_pctl16 8-bit base + 0x00d0 peripheral control registers me_pctl17 8-bit base + 0x00d1 peripheral control registers me_pctl18 8-bit base + 0x00d2 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-27 preliminary?subject to change without notice peripheral control registers me_pctl19 8-bit base + 0x00d3 peripheral control registers me_pctl20 8-bit base + 0x00d4 peripheral control registers me_pctl21 8-bit base + 0x00d5 reserved - - (base+0x00d6) - (base+0x00df) peripheral control registers me_pctl32 8-bit base + 0x00e0 reserved - - (base+0x00e1) - (base+0x00eb) peripheral control registers me_pctl44 8-bit base + 0x00ec reserved - - (base+0x00ed) - (base+0x00ef) peripheral control registers me_pctl48 8-bit base + 0x00f0 peripheral control registers me_pctl49 8-bit base + 0x00f1 peripheral control registers me_pctl50 8-bit base + 0x00f2 peripheral control registers me_pctl51 8-bit base + 0x00f3 reserved - - (base+0x00f4) - (base+0x00f8) peripheral control registers me_pctl57 8-bit base + 0x00f9 reserved - - (base+0x00fa) - (base+0x00fb) peripheral control registers me_pctl60 8-bit base + 0x00fc reserved - - (base+0x00fd) - (base+0x0103) peripheral control registers me_pctl68 8-bit base + 0x0104 peripheral control registers me_pctl69 8-bit base + 0x0105 reserved - - (base+0x0106) - (base+0x0107) peripheral control registers me_pctl72 8-bit base + 0x0108 peripheral control registers me_pctl73 8-bit base + 0x0109 reserved - - (base+0x010a) - (base+0x011a) peripheral control registers me_pctl91 8-bit base + 0x011b peripheral control registers me_pctl92 8-bit base + 0x011c reserved - - (base+0x011d) - (base+0x0127) peripheral control registers me_pctl104 8-bit base + 0x0128 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-28 freescale semiconductor preliminary?subject to change without notice reserved - - (base+0x0129) - (base+0x014f) fxosc section 8.5.3, register description 0xc3fe_0000 high frequency oscillator control register osc_ctl 32-bit base+0x0000 reserved - - (base+0x0004) - (base+0x003f) sxosc section 8.6.4, register description 0xc3fe_0040 low frequency oscillator control register osc_ctl 32-bit base+0x0000 reserved - - (base+0x0004) - (base+0x005f) rc digital interface registers section 8.8.3, register description ) 0xc3fe_0060 rc digital interface registers rc_ctl 32-bit base+0x0000 reserved - - (base+0x0004) - (base+0x007f) lprc digital interface section 8.7.3, register description n 0xc3fe_0080 low power rc control register lprc_ctl 32-bit base+0x0000 reserved - - (base+0x0004) - (base+0x009f) plld0 section 8.9.5, register description 0xc3fe_00a0 control register plld0_cr 32-bit base + 0x0000 plld modulation register plld0_mr 32-bit base + 0x0004 reserved - - (base+0x0008) - (base+0x00ff) cmu0 section 8.10.5, memory map and register description 0xc3fe_0100 control status register cmu0_csr 32-bit base + 0x0000 frequency display register cmu0_fdr 32-bit base + 0x0004 high frequency reference register cmu0_hfrefr_a 32-bit base + 0x0008 low frequency reference register cmu0_lfrefr_a 32-bit base + 0x000c interrupt status register cmu0_isr 32-bit base + 0x0010 interrupt mask register cmu0_imr 32-bit base + 0x0014 measurement duration register cmu0_mdr 32-bit base + 0x0018 reserved - - (base+0x001c) - (base+0x036f) clock generation module (mc_cgm) section 8.4.3, memory map and register definition 0xc3fe_0370 output clock enable register cgm_oc_en 32-bit base + 0x0000 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-29 preliminary?subject to change without notice output clock division select regi ster cgm_ocds_sc 32-bit base + 0x0004 system clock select status regi ster cgm_sc_ss 32-bit base + 0x0008 system clock divider configuration registers cgm_sc_dc0 8-bit base + 0x000c system clock divider configuration registers cgm_sc_dc1 8-bit base + 0x000d system clock divider configuration registers cgm_sc_dc2 8-bit base + 0x000e system clock divider configuration registers cgm_sc_dc3 8-bit base + 0x000f reset generation module (mc_rgm) section 32.3, memory map and register definition 0xc3fe_4000 functional event status rgm_fes 16-bit base+0x0000 destructive event status rgm_des 16-bit base+0x0002 functional event reset disable rgm_ferd 16-bit base+0x0004 destructive event reset disable rgm_derd 16-bit base+0x0006 reserved - - (base+0x0008) - (base+0x000f) functional event alternate request rgm_fear 16-bit base+0x0010 destructive event alternate request rgm_dear 16-bit base+0x0012 reserved - - (base+0x0014) - (base+0x0017) functional event short sequence rgm_fess 16-bit base+0x0018 standby reset sequence rgm_stdby 16-bit base+0x001a functional bidirectional reset enable rgm_fbre 16-bit base+0x001c reserved - - (base+0x001e) - (base+0x3fff) power control unit (mc_pcu) section 29.3, memory map and register definition 0xc3fe_8000 power domain #0 configuration register pconf0 32-bit base+0x0000 power domain #1 configuration register pconf1 32-bit base+0x0004 power domain #1 configuration register pconf2 32-bit base+0x0008 reserved - - (base+0x000c) - (base+0x003f) power domain status register pstat 32-bit base+0x0040 reserved - - (base+0x0044) - (base+0x007c) voltage regulator control register vctl 32-bit base+0x0080 reserved - - (base+0x0084) - (base+0x3fff) table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-30 freescale semiconductor preliminary?subject to change without notice real time counter (rtc/api) section 31.6, register descriptions 0xc3fe_c000 rtc supervisor control register rtcsupv 32-bit base+0x0000 rtc control register rtcc 32-bit base+0x0004 rtc status register rtcs 32-bit base+0x0008 rtc counter register rtccnt 32-bit base+0x000c reserved - - (base+0x0010) - (base+0x3fff) periodic interrupt timer (pit/rti) section 27.3, memory map and register description 0xc3ff_0000 pit module control register pitmcr 32-bit base + 0x0000 reserved - - base + (0x0004- 0x00fc) timer load value register ldval0 32-bit base + 0x0100 current timer value register 0 cval0 32-bit base + 0x0104 timer control register 0 tctrl0 32-bit base + 0x0108 timer flag register 0 tflg0 32-bit base + 0x010c timer load value register 1 ldval1 32-bit base + 0x0110 current timer value register 1 cval1 32-bit base + 0x0114 timer control register 1 tctrl1 32-bit base + 0x0118 timer flag register 1 tflg1 32-bit base + 0x011c timer load value register 2 ldval2 32-bit base + 0x0120 current timer value register 2 cval2 32-bit base + 0x0124 timer control register 2 tctrl2 32-bit base + 0x0128 timer flag register 2 tflg2 32-bit base + 0x012c timer load value register 3 ldval3 32-bit base + 0x0130 current timer value register 3 cval3 32-bit base + 0x0134 timer control register 3 tctrl3 32-bit base + 0x0138 timer flag register 3 tflg3 32-bit base + 0x013c timer load value register 4 ldval4 32-bit base + 0x0140 current timer value register 4 cval4 32-bit base + 0x0144 timer control register 4 tctrl4 32-bit base + 0x0148 timer flag register 4 tflg4 32-bit base + 0x014c timer load value register 5 ldval5 32-bit base + 0x0150 current timer value register 5 cval5 32-bit base + 0x0154 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-31 preliminary?subject to change without notice timer control register 5 tctrl5 32-bit base + 0x0158 timer flag register 5 tflg5 32-bit base + 0x015c reserved - - base+0x0160 - 0x01ff adc 0 section 5.4, register descriptions 0xffe0_0000 main configuration register mcr 32-bit base + 0x000 main status register msr 32-bit base + 0x004 reserved - base + 0x008 .. 00c interrupt status register isr 32-bit base + 0x010 reserved - base + 0x014 channel pending register ceocfr1 32-bit base + 0x018 channel pending register ceocfr2 32-bit base + 0x01c interrupt mask register imr 32-bit base + 0x020 reserved - base + 0x024 channel interrupt mask register cimr1 32-bit base + 0x028 channel interrupt mask register cimr2 32-bit base + 0x02c watchdog threshold interrupt status register wtisr 32-bit base + 0x030 watchdog threshold interrupt mask register wtimr 32-bit base + 0x034 reserved - base + 0x038 .. 03c dma enable register dmae 32-bit base + 0x040 reserved - base + 0x044 dma channel select register 1 dmar1 32-bit base + 0x048 dma channel select register 2 dmar2 32-bit base + 0x04c threshold control register 0 trc0 32-bit base + 0x050 threshold control register 1 trc1 32-bit base + 0x054 threshold control register 2 trc2 32-bit base + 0x058 threshold control register 3 trc3 32-bit base + 0x05c threshold register 0 thrhlr0 32-bit base + 0x060 threshold register 1 thrhlr1 32-bit base + 0x064 threshold register 2 thrhlr2 32-bit base + 0x068 threshold register 3 thrhlr3 32-bit base + 0x06c table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-32 freescale semiconductor preliminary?subject to change without notice reserved - base + 0x070 .. 094 conversion timing register 1 ctr1 32-bit base + 0x098 conversion timing register 2 ctr2 32-bit base + 0x09c reserved - base + 0x0a0 .. 0a4 normal conversion mask register 1 ncmr1 32-bit base + 0x0a8 normal conversion mask register 2 ncmr2 32-bit base + 0x0ac reserved - base + 0x0b0 .. 0b4 injected conversion mask register 1 jcmr1 32-bit base + 0x0b8 injected conversion mask register 2 jcmr2 32-bit base + 0x0bc reserved - base + 0x0c0 decode signals delay register dsdr 32-bit base + 0x0c4 power-down exit delay register pdedr 32-bit base + 0x0c8 reserved - base + 0x0cc .. 17c channel 32 data register cdr32 32-bit base + 0x180 channel 33 data register cdr33 32-bit base + 0x184 channel 34 data register cdr34 32-bit base + 0x188 channel 35 data register cdr35 32-bit base + 0x18c channel 36 data register cdr36 32-bit base + 0x190 channel 37 data register cdr37 32-bit base + 0x194 channel 38 data register cdr38 32-bit base + 0x198 channel 39 data register cdr39 32-bit base + 0x19c channel 40 data register cdr40 32-bit base + 0x1a0 channel 41 data register cdr41 32-bit base + 0x1a4 channel 43 data register cdr43 32-bit base + 0x1ac channel 44 data register cdr44 32-bit base + 0x1b0 channel 45 data register cdr45 32-bit base + 0x1b4 channel 46 data register cdr46 32-bit base + 0x1b8 channel 47 data register cdr47 32-bit base + 0x1bc channel 48 data register cdr48 32-bit base + 0x1c0 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-33 preliminary?subject to change without notice reserved - base + 0x1c4 .. 1fc channel 64 data register cdr64 32-bit base + 0x200 channel 65 data register cdr65 32-bit base + 0x204 channel 66 data register cdr66 32-bit base + 0x208 channel 67 data register cdr67 32-bit base + 0x20c channel 68 data register cdr68 32-bit base + 0x210 channel 69 data register cdr69 32-bit base + 0x214 channel 70 data register cdr70 32-bit base + 0x218 channel 71 data register cdr71 32-bit base + 0x21c reserved - base + 0x220 .. 2fc i2c 0 section 20.4, memory map and register description 0xffe3_0000 i2c bus address register ibad 8-bit base+0x0000 i2c bus frequency divider register ibfd 8-bit base+0x0001 i2c bus control register ibcr 8-bit base+0x0002 i2c bus status register ibsr 8-bit base+0x0003 i2c bus data i/o register ibdr 8-bit base+0x0004 i2c bus interrupt config register ibic 8-bit base+0x0005 reserved - - (base+0x0006) - (base+0xffff) i2c 1 section 20.4, memory map and register description 0xffe3_4000 i2c bus address register ibad 8-bit base+0x0000 i2c bus frequency divider register ibfd 8-bit base+0x0001 i2c bus control register ibcr 8-bit base+0x0002 i2c bus status register ibsr 8-bit base+0x0003 i2c bus data i/o register ibdr 8-bit base+0x0004 i2c bus interrupt config register ibic 8-bit base+0x0005 reserved - - (base+0x0006) - (base+0xffff) i2c 2 section 20.4, memory map and register description 0xffe3_8000 i2c bus address register ibad 8-bit base+0x0000 i2c bus frequency divider register ibfd 8-bit base+0x0001 i2c bus control register ibcr 8-bit base+0x0002 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-34 freescale semiconductor preliminary?subject to change without notice i2c bus status register ibsr 8-bit base+0x0003 i2c bus data i/o register ibdr 8-bit base+0x0004 i2c bus interrupt config register ibic 8-bit base+0x0005 reserved - - (base+0x0006) - (base+0xffff) i2c 3 section 20.4, memory map and register description 0xffe3_c000 i2c bus address register ibad 8-bit base+0x0000 i2c bus frequency divider register ibfd 8-bit base+0x0001 i2c bus control register ibcr 8-bit base+0x0002 i2c bus status register ibsr 8-bit base+0x0003 i2c bus data i/o register ibdr 8-bit base+0x0004 i2c bus interrupt config register ibic 8-bit base+0x0005 reserved - - (base+0x0006) - (base+0xffff) linflex 0 section 23.7, memory map and registers description 0xffe4_0000 lin control register lincr1 16-bit base + 0x0000 reserved - - (base+0x0002) - (base+0x0003) lin interrupt enable register linier 16-bit base + 0x0004 reserved - - (base+0x0006) - (base+0x0007) lin status register li nsr 16-bit base + 0x0008 reserved - - (base+0x000a) - (base+0x000b) lin error status register linesr 16-bit base + 0x000c reserved - - (base+0x000e) - (base+0x000f) uart mode control register uartcr 16-bit base + 0x0010 reserved - - (base+0x0012) - (base+0x0013) uart mode status register uartsr 16-bit base + 0x0014 reserved - - (base+0x0016) - (base+0x0017) lin time-out control status register lintcsr 16-bit base + 0x0018 reserved - - (base+0x001a) - (base+0x001b) table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-35 preliminary?subject to change without notice lin output compare register linocr 16-bit base + 0x001c reserved - - (base+0x001e) - (base+0x001f) lin time-out control register lintocr 16-bit base + 0x0020 reserved - - (base+0x0022) - (base+0x0023) lin fractional baud rate register linfbrr 16-bit base + 0x0024 reserved - - (base+0x0026) - (base+0x0027) lin integer baud rate register linibrr 16-bit base + 0x0028 reserved - - (base+0x002a) - (base+0x002b) lin checksum field register lincfr 16-bit base + 0x002c reserved - - (base+0x002e) - (base+0x002f) lin control register 2 lincr2 16-bit base + 0x0030 reserved - - (base+0x0032) - (base+0x0033) buffer identifier register bidr 16-bit base + 0x0034 reserved - - (base+0x0036) - (base+0x0037) buffer data register least significant bdrl 16-bit base + 0x0038 reserved - - (base+0x003a) - (base+0x003b) buffer data register most significant bdrm 16-bit base + 0x003c reserved - - (base+0x003e) - (base+0x003f) identifier filter enable register ifer 16-bit base + 0x0040 reserved - - (base+0x0042) - (base+0x0043) identifier filter match index ifmi 16-bit base + 0x0044 reserved - - (base+0x0046) - (base+0x0047) identifier filter mode register ifmr 16-bit base + 0x0048 reserved - - (base+0x004a) - (base+0x004b) identifier filter control register ifcr0 16-bit base + 0x004c table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-36 freescale semiconductor preliminary?subject to change without notice reserved - - (base+0x004e) - (base+0x004f) identifier filter control register ifcr1 16-bit base + 0x0050 reserved - - (base+0x0052) - (base+0x0053) identifier filter control register ifcr2 16-bit base + 0x0054 reserved - - (base+0x0056) - (base+0x0057) identifier filter control register ifcr3 16-bit base + 0x0058 reserved - - (base+0x005a) - (base+0x005b) identifier filter control register ifcr4 16-bit base + 0x005c reserved - - (base+0x005e) - (base+0x005f) identifier filter control register ifcr5 16-bit base + 0x0060 reserved - - (base+0x0062) - (base+0x0063) identifier filter control register ifcr6 16-bit base + 0x0064 reserved - - (base+0x0066) - (base+0x0067) identifier filter control register ifcr7 16-bit base + 0x0068 reserved - - (base+0x006a) - (base+0x006b) identifier filter control register ifcr8 16-bit base + 0x006c reserved - - (base+0x006e) - (base+0x006f) identifier filter control register ifcr9 16-bit base + 0x0070 reserved - - (base+0x0072) - (base+0x0073) identifier filter control register ifcr10 16-bit base + 0x0074 reserved - - (base+0x0076) - (base+0x0077) identifier filter control register ifcr11 16-bit base + 0x0078 reserved - - (base+0x007a) - (base+0x007b) identifier filter control register ifcr12 16-bit base + 0x007c table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-37 preliminary?subject to change without notice reserved - - (base+0x007e) - (base+0x007f) identifier filter control register ifcr13 16-bit base + 0x0080 reserved - - (base+0x0082) - (base+0x0083) identifier filter control register ifcr14 16-bit base + 0x0084 reserved - - (base+0x0086) - (base+0x0087) identifier filter control register ifcr15 16-bit base + 0x0088 reserved - - (base+0x009a) - (base+0x3fff) linflex 1 section 23.7, memory map and registers description 0xffe4_4000 lin control register lincr1 16-bit base + 0x0000 reserved - - (base+0x0002) - (base+0x0003) lin interrupt enable register linier 16-bit base + 0x0004 reserved - - (base+0x0006) - (base+0x0007) lin status register li nsr 16-bit base + 0x0008 reserved - - (base+0x000a) - (base+0x000b) lin error status register linesr 16-bit base + 0x000c reserved - - (base+0x000e) - (base+0x000f) uart mode control register uartcr 16-bit base + 0x0010 reserved - - (base+0x0012) - (base+0x0013) uart mode status register uartsr 16-bit base + 0x0014 reserved - - (base+0x0016) - (base+0x0017) lin time-out control status register lintcsr 16-bit base + 0x0018 reserved - - (base+0x001a) - (base+0x001b) lin output compare register linocr 16-bit base + 0x001c reserved - - (base+0x001e) - (base+0x001f) lin time-out control register lintocr 16-bit base + 0x0020 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-38 freescale semiconductor preliminary?subject to change without notice reserved - - (base+0x0022) - (base+0x0023) lin fractional baud rate register linfbrr 16-bit base + 0x0024 reserved - - (base+0x0026) - (base+0x0027) lin integer baud rate register linibrr 16-bit base + 0x0028 reserved - - (base+0x002a) - (base+0x002b) lin checksum field register lincfr 16-bit base + 0x002c reserved - - (base+0x002e) - (base+0x002f) lin control register 2 lincr2 16-bit base + 0x0030 reserved - - (base+0x0032) - (base+0x0033) buffer identifier register bidr 16-bit base + 0x0034 reserved - - (base+0x0036) - (base+0x0037) buffer data register least significant bdrl 16-bit base + 0x0038 reserved - - (base+0x003a) - (base+0x003b) buffer data register most significant bdrm 16-bit base + 0x003c reserved - - (base+0x003e) - (base+0x3fff) reserved --- --- ffe6_4000- ffe6_ffff can sampler section 7.3, register description 0xffe7_0000 control status register cans_cr 32-bit base_0x0000 sample register 0 can_sr0 32-bit base_0x0004 sample register 1 can_sr1 32-bit base_0x0008 sample register 2 can_sr2 32-bit base_0x000c sample register 3 can_sr3 32-bit base_0x0010 sample register 4 can_sr4 32-bit base_0x0014 sample register 5 can_sr5 32-bit base_0x0018 sample register 6 can_sr6 32-bit base_0x001c sample register 7 can_sr7 32-bit base_0x0020 sample register 8 can_sr8 32-bit base_0x0024 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-39 preliminary?subject to change without notice sample register 9 can_sr9 32-bit base_0x0028 sample register 10 can_sr10 32-bit base_0x002c sample register 11 can_sr11 32-bit base_0x0030 reserved --- --- (base+0x0034)- fff0_ffff mpu section 24.2, memory map and register description 0xfff1_0000 mpu control/error status register mpu_cesr 32-bit 0x0000 reserved 0x0004- 0x000f mpu error address register, slave port 0 mpu_ear0 32-bit 0x0010 mpu error detail register, slave port 0 mpu_edr0 32-bit 0x0014 mpu error address register, slave port 1 mpu_ear1 32-bit 0x0018 mpu error detail register, slave port 1 mpu_edr1 32-bit 0x001c mpu error address register, slave port 2 mpu_ear2 32-bit 0x0020 mpu error detail register, slave port 2 mpu_edr2 32-bit 0x0024 mpu error address register, slave port 3 mpu_ear3 32-bit 0x0028 mpu error detail register, slave port 3 mpu_edr3 32-bit 0x002c reserved for mpu extended error detail register, slave port 0 mpu_xedr0 64-bit 0x0030 reserved for mpu extended error detail register, slave port 1 mpu_xedr1 64-bit 0x0038 reserved for mpu extended error detail register, slave port 2 mpu_xedr2 64-bit 0x0040 reserved for mpu extended error detail register, slave port 3 mpu_xedr3 64-bit 0x0048 reserved 0x0050-0x03ff mpu region descriptor 0 mpu_rgd0 128-bit 0x0400 mpu region descriptor 1 mpu_rgd1 128-bit 0x0410 mpu region descriptor 2 mpu_rgd2 128-bit 0x0420 mpu region descriptor 3 mpu_rgd3 128-bit 0x0430 mpu region descriptor 4 mpu_rgd4 128-bit 0x0440 mpu region descriptor 5 mpu_rgd5 128-bit 0x0450 mpu region descriptor 6 mpu_rgd6 128-bit 0x0460 mpu region descriptor 7 mpu_rgd7 128-bit 0x0470 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-40 freescale semiconductor preliminary?subject to change without notice mpu region descriptor 8 mpu_rgd8 128-bit 0x0480 mpu region descriptor 9 mpu_rgd9 128-bit 0x0490 mpu region descriptor 10 mpu_rgd10 128-bit 0x04a0 mpu region descriptor 11 mpu_rgd11 128-bit 0x04b0 mpu region descriptor 12 mpu_rgd12 128-bit 0x04c0 mpu region descriptor 13 mpu_rgd13 128-bit 0x04d0 mpu region descriptor 14 mpu_rgd14 128-bit 0x04e0 mpu region descriptor 15 mpu_rgd15 128-bit 0x04f0 reserved 0x0500- 0x07ff mpu rgd alternate access control 0 mpu_rgdaac0 32-bit 0x0800 mpu rgd alternate access control 1 mpu_rgdaac1 32-bit 0x0804 mpu rgd alternate access control 2 mpu_rgdaac2 32-bit 0x0808 mpu rgd alternate access control 3 mpu_rgdaac3 32-bit 0x080c mpu rgd alternate access control 4 mpu_rgdaac4 32-bit 0x0810 mpu rgd alternate access control 5 mpu_rgdaac5 32-bit 0x0814 mpu rgd alternate access control 6 mpu_rgdaac6 32-bit 0x0818 mpu rgd alternate access control 7 mpu_rgdaac7 32-bit 0x081c mpu rgd alternate access control 8 mpu_rgdaac8 32-bit 0x0820 mpu rgd alternate access control 9 mpu_rgdaac9 32-bit 0x0824 mpu rgd alternate access control 10 mpu_rgdaac10 32-bit 0x0828 mpu rgd alternate access control 11 mpu_rgdaac11 32-bit 0x082c mpu rgd alternate access control 12 mpu_rgdaac12 32-bit 0x0830 mpu rgd alternate access control 13 mpu_rgdaac13 32-bit 0x0834 mpu rgd alternate access control 14 mpu_rgdaac14 32-bit 0x0838 mpu rgd alternate access control 15 mpu_rgdaac15 32-bit 0x083c reserved 0x0840- 0x3fff swt 0 section 4.2.5, memory map and register description 0xfff3_8000 control register swt_cr 32-bit base + 0x0000 swt interrupt register swt_ir 32-bit base + 0x0004 swt time-out register swt_to 32-bit base + 0x0008 swt window register swt_wn 32-bit base + 0x000c table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-41 preliminary?subject to change without notice swt service register swt_sr 32-bit base + 0x0010 swt counter output register swt_co 32-bit base + 0x0014 reserved --- --- (base+0x0018)- 0xfff3_bfff stm section 39.3, memory map and register definition 0xfff3_c000 control register stm_cr 32-bit base + 0x0000 stm count register stm_cnt 32-bit base + 0x0004 reserved - - base + (0x0008 - 0x000f) stm channel 0 control register stm_ccr0 32-bit base + 0x00010 stm channel 0 interrupt register stm_cir0 32-bit base + 0x00014 stm channel 0 compare register stm_cmp0 32-bit base + 0x00018 reserved - - base + (0x001c - 0x001f) stm channel 1 control register stm_ccr1 32-bit base + 0x00020 stm channel 1 interrupt register stm_cir1 32-bit base + 0x00024 stm channel 1 compare register stm_cmp1 32-bit base + 0x00028 reserved - - base + (0x002c - 0x002f) stm channel 2 control register stm_ccr2 32-bit base + 0x00030 stm channel 2 interrupt register stm_cir2 32-bit base + 0x00034 stm channel 2 compare register stm_cmp2 32-bit base + 0x00038 reserved - - base + (0x003c - 0x003f) stm channel 3 control register stm_ccr3 32-bit base + 0x00040 stm channel 3 interrupt register stm_cir3 32-bit base + 0x00044 stm channel 3 compare register stm_cmp3 32-bit base + 0x00048 reserved - - base + (0x003c - 0x03fff) ecsm section 16.4, memory map and register description 0xfff4_0000 processor core type ecsm_pct 16-bit base + 0x0000 soc-defined platform revision ecsm_plrev 16-bit base + 0x0002 reserved - - base + (0x0004 - 0x0007) ips on-platform module configurat ion ecsm_iopmc 32-bit base + 0x0008 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-42 freescale semiconductor preliminary?subject to change without notice reserved - - base + (0x000c - 0x000e) miscellaneous reset status register ecsm_mrsr 8-bit base + 0x000f reserved - - base + (0x00010 - 0x0012) miscellaneous wakeup control register ecsm_mwcr 8-bit base + 0x0013 reserved - - base + (0x0014 - 0x001e) miscellaneous interrupt register ecsm_mir 8-bit base + 0x001f reserved - - base + (0x0020 - 0x0023) miscellaneous user defined control register ecsm_mudcr 32-bit base + 0x0024 reserved - - base + (0x0028 - 0x0042) ecc configuration register ecsm_ecr 8bit base + 0x0043 reserved - - base + (0x0044 - 0x0046) ecc status register ecsm_esr 8bit base + 0x0047 reserved - - base + (0x0048 - 0x0049) ecc error generation register ecsm_eegr 16-bit base + 0x004a reserved - - base + (0x04c - 0x004f) platform flash ecc error address register ecsm_pfear 32-bit base + 0x0050 reserved - - base + (0x054 - 0x0055) platform flash ecc master number register ecsm_pfemr 8-bit base + 0x0056 platform flash ecc attributes r egister ecsm_pfeat 8-bit base + 0x0057 reserved - - base + (0x058 - 0x005b) platform flash ecc data register ecsm_pfedr 32-bit base + 0x005c platform ram ecc address register ecsm_prear 32-bit base + 0x0060 reserved - - base + 0x064 platform ram ecc syndrome register ecsm_presr 8-bit base + 0x0065 platform ram ecc master number re gister ecsm_premr 8-bit base + 0x0066 platform ram ecc attributes register ecsm_preat 8-bit base + 0x0067 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-43 preliminary?subject to change without notice reserved - - base + (0x068 - 0x006b) platform ram ecc data register ecsm_predr 32-bit base + 0x006c reserved - - base + (0x0070 - 0x3fff) intc section 21.5, memory map and register description 0xfff4_8000 block configuration register intc_pbcr 32-bit base + 0x0000 reserved - - base + (0x0004 - 0x0007) current priority register intc_cpr 32-bit base + 0x0008 reserved - - base + (0x000c - 0x000f) interrupt acknowledge register intc_iackr 32-bit base + 0x0010 reserved - - base + (0x0014 - 0x0017) end of interrupt register intc_eoir 32-bit base + 0x0018 reserved - - base + (0x001c - 0x001f) software set/clear interrupt register intc_sscir0_3 32-bit base + 0x0020 software set/clear interrupt register intc_sscir4_7 32-bit base + 0x0024 reserved - - base + (0x0028 - 0x003f) priority select register intc_psr0_3 32-bit base + 0x0040 priority select register intc_psr4_7 32-bit base + 0x0044 priority select register intc_psr8_11 32-bit base + 0x0048 priority select register intc_psr12_15 32-bit base + 0x004c priority select register intc_psr16_19 32-bit base + 0x0050 priority select register intc_psr20_23 32-bit base + 0x0054 priority select register intc_psr24_27 32-bit base + 0x0058 priority select register intc_psr28_31 32-bit base + 0x005c priority select register intc_psr32_35 32-bit base + 0x0060 priority select register intc_psr36_39 32-bit base + 0x0064 priority select register intc_psr40_43 32-bit base + 0x0068 priority select register intc_psr44_47 32-bit base + 0x006c priority select register intc_psr48_51 32-bit base + 0x0070 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-44 freescale semiconductor preliminary?subject to change without notice priority select register intc_psr52_55 32-bit base + 0x0074 priority select register intc_psr56_59 32-bit base + 0x0078 priority select register intc_psr60_63 32-bit base + 0x007c priority select register intc_psr64_67 32-bit base + 0x0080 priority select register intc_psr68_71 32-bit base + 0x0084 priority select register intc_psr72_75 32-bit base + 0x0088 priority select register intc_psr76_79 32-bit base + 0x008c priority select register intc_psr80_83 32-bit base + 0x0090 priority select register intc_psr84_87 32-bit base + 0x0094 priority select register intc_psr88_91 32-bit base + 0x0098 priority select register intc_psr92_95 32-bit base + 0x009c priority select register intc_psr96_99 32-bit base + 0x00a0 priority select register intc_psr100_103 32-bit base + 0x00a4 priority select register intc_psr104_107 32-bit base + 0x00a8 priority select register intc_psr108_111 32-bit base + 0x00ac priority select register intc_psr112_115 32-bit base + 0x00b0 priority select register intc_psr116_119 32-bit base + 0x00b4 priority select register intc_psr120_123 32-bit base + 0x00b8 priority select register intc_psr124_127 32-bit base + 0x00bc priority select register intc_psr128_131 32-bit base + 0x00c0 priority select register intc_psr132_135 32-bit base + 0x00c4 priority select register intc_psr136_139 32-bit base + 0x00c8 priority select register intc_psr140_143 32-bit base + 0x00cc priority select register intc_psr144_147 32-bit base + 0x00d0 priority select register intc_psr148_151 32-bit base + 0x00d4 priority select register intc_psr152_155 32-bit base + 0x00d8 priority select register intc_psr156_159 32-bit base + 0x00dc priority select register intc_psr160_163 32-bit base + 0x00e0 priority select register intc_psr164_167 32-bit base + 0x00e4 priority select register intc_psr168_171 32-bit base + 0x00e8 priority select register intc_psr172_175 32-bit base + 0x00ec priority select register intc_psr176_179 32-bit base + 0x00f0 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-45 preliminary?subject to change without notice priority select register intc_psr180_183 32-bit base + 0x00f4 priority select register intc_psr184_187 32-bit base + 0x00f8 priority select register intc_psr188_191 32-bit base + 0x00fc priority select register intc_psr192_195 32-bit base + 0x0100 priority select register intc_psr196_199 32-bit base + 0x0104 priority select register intc_psr200_203 32-bit base + 0x0108 priority select register intc_psr204_207 32-bit base + 0x010c priority select register intc_psr208_211 32-bit base + 0x0110 priority select register intc_psr212_215 32-bit base + 0x0114 priority select register intc_psr216_219 32-bit base + 0x0118 priority select register intc_psr220_223 32-bit base + 0x011c priority select register intc_psr224_227 32-bit base + 0x0120 priority select register intc_psr228_231 32-bit base + 0x0124 priority select register intc_psr232_235 32-bit base + 0x0128 priority select register intc_psr236_239 32-bit base + 0x012c priority select register intc_psr240_243 32-bit base + 0x0130 priority select register intc_psr244_247 32-bit base + 0x0134 priority select register intc_psr248_251 32-bit base + 0x0138 priority select register intc_psr252_255 32-bit base + 0x013c priority select register intc_psr256_259 32-bit base + 0x0140 priority select register intc_psr260_263 32-bit base + 0x0144 priority select register intc_psr264_267 32-bit base + 0x0148 priority select register intc_psr268_271 32-bit base + 0x014c priority select register intc_psr272_275 32-bit base + 0x0150 priority select register intc_psr276_279 32-bit base + 0x0154 priority select register intc_psr280_283 32-bit base + 0x0158 priority select register intc_psr284_287 32-bit base + 0x015c priority select register intc_psr288_291 32-bit base + 0x0160 priority select register intc_psr292_295 32-bit base + 0x0164 priority select register intc_psr296_299 32-bit base + 0x0168 priority select register intc_psr300_303 32-bit base + 0x016c priority select register intc_psr304_307 32-bit base + 0x0170 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-46 freescale semiconductor preliminary?subject to change without notice priority select register intc_psr308_311 32-bit base + 0x0174 priority select register intc_psr312_315 32-bit base + 0x0178 priority select register intc_psr316_319 32-bit base + 0x017c priority select register intc_psr320_323 32-bit base + 0x0180 priority select register intc_psr324_327 32-bit base + 0x0184 priority select register intc_psr328_331 32-bit base + 0x0188 priority select register intc_psr332_335 32-bit base + 0x018c priority select register intc_psr336_339 32-bit base + 0x0190 priority select register intc_psr340_343 32-bit base + 0x0194 priority select register intc_psr344_347 32-bit base + 0x0198 priority select register intc_psr348_351 32-bit base + 0x019c priority select register intc_psr352_355 32-bit base + 0x01a0 priority select register intc_psr356_359 32-bit base + 0x01a4 priority select register intc_psr360_363 32-bit base + 0x01a8 priority select register intc_psr364_367 32-bit base + 0x01ac priority select register intc_psr368_371 32-bit base + 0x01b0 priority select register intc_psr372_375 32-bit base + 0x01b4 priority select register intc_psr376_379 32-bit base + 0x01b8 priority select register intc_psr380_383 32-bit base + 0x01bc priority select register intc_psr384_387 32-bit base + 0x01c0 priority select register intc_psr388_391 32-bit base + 0x01c4 priority select register intc_psr392_395 32-bit base + 0x01c8 priority select register intc_psr396_399 32-bit base + 0x01cc priority select register intc_psr400_403 32-bit base + 0x01d0 priority select register intc_psr404_407 32-bit base + 0x01d4 priority select register intc_psr408_411 32-bit base + 0x01d8 priority select register intc_psr412_415 32-bit base + 0x01dc priority select register intc_psr416_419 32-bit base + 0x01e0 priority select register intc_psr420_423 32-bit base + 0x01e4 priority select register intc_psr424_427 32-bit base + 0x01e8 priority select register intc_psr428_431 32-bit base + 0x01ec priority select register intc_psr432_435 32-bit base + 0x01f0 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-47 preliminary?subject to change without notice priority select register intc_psr436_439 32-bit base + 0x01f4 priority select register intc_psr440_443 32-bit base + 0x01f8 priority select register intc_psr444_447 32-bit base + 0x01fc priority select register intc_psr448_451 32-bit base + 0x0200 priority select register intc_psr452_455 32-bit base + 0x0204 priority select register intc_psr456_459 32-bit base + 0x0208 priority select register intc_psr460_463 32-bit base + 0x020c priority select register intc_psr464_467 32-bit base + 0x0210 priority select register intc_psr468_471 32-bit base + 0x0214 priority select register intc_psr472_475 32-bit base + 0x0218 priority select register intc_psr476_479 32-bit base + 0x021c priority select register intc_psr480_483 32-bit base + 0x0220 priority select register intc_psr484_487 32-bit base + 0x0224 priority select register intc_psr488_491 32-bit base + 0x0228 priority select register intc_psr492_495 32-bit base + 0x022c priority select register intc_psr496_499 32-bit base + 0x0230 priority select register intc_psr500_503 32-bit base + 0x0234 priority select register intc_psr504_507 32-bit base + 0x0238 priority select register intc_psr508_511 32-bit base + 0x023c dspi 0 section 11.7, memory map and register description 0xfff9_0000 module configuration register pmcr 32-bit base + 0x0000 reserved - - (base+0x0004) - (base+0x0007) transfer count register tcr 32-bit base + 0x0008 clock and transfer attribute registers ctar0 32-bit base + 0x000c clock and transfer attribute registers ctar1 32-bit base + 0x0010 clock and transfer attribute registers ctar2 32-bit base + 0x0014 clock and transfer attribute registers ctar3 32-bit base + 0x0018 clock and transfer attribute registers ctar4 32-bit base + 0x001c clock and transfer attribute registers ctar5 32-bit base + 0x0020 clock and transfer attribute registers ctar6 32-bit base + 0x0024 clock and transfer attribute registers ctar7 32-bit base + 0x0028 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-48 freescale semiconductor preliminary?subject to change without notice status register sr 32-bit base + 0x002c dma/interrupt request register rser 32-bit base + 0x0030 push tx fifo register pushr 32-bit base + 0x0034 pop rx fifo register popr 32-bit base + 0x0038 dspi transmit fifo registers txfr0 32-bit base + 0x003c dspi transmit fifo registers txfr1 32-bit base + 0x0040 dspi transmit fifo registers txfr2 32-bit base + 0x0044 dspi transmit fifo registers txfr3 32-bit base + 0x0048 reserved - - (base+0x004c) - (base+0x007b) receive fifo registers rxfr0 32-bit base + 0x007c receive fifo registers rxfr1 32-bit base + 0x0080 receive fifo registers rxfr2 32-bit base + 0x0084 receive fifo registers rxfr3 32-bit base + 0x0088 reserved - - (base+0x008c) - (base+0x3fff) dspi 1 section 11.7, memory map and register description 0xfff9_4000 module configuration register pmcr 32-bit base + 0x0000 reserved - - (base+0x0004) - (base+0x0007) transfer count register tcr 32-bit base + 0x0008 clock and transfer attribute registers ctar0 32-bit base + 0x000c clock and transfer attribute registers ctar1 32-bit base + 0x0010 clock and transfer attribute registers ctar2 32-bit base + 0x0014 clock and transfer attribute registers ctar3 32-bit base + 0x0018 clock and transfer attribute registers ctar4 32-bit base + 0x001c clock and transfer attribute registers ctar5 32-bit base + 0x0020 clock and transfer attribute registers ctar6 32-bit base + 0x0024 clock and transfer attribute registers ctar7 32-bit base + 0x0028 status register sr 32-bit base + 0x002c dma/interrupt request register rser 32-bit base + 0x0030 push tx fifo register pushr 32-bit base + 0x0034 pop rx fifo register popr 32-bit base + 0x0038 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-49 preliminary?subject to change without notice dspi transmit fifo registers txfr0 32-bit base + 0x003c dspi transmit fifo registers txfr1 32-bit base + 0x0040 dspi transmit fifo registers txfr2 32-bit base + 0x0044 dspi transmit fifo registers txfr3 32-bit base + 0x0048 reserved - - (base+0x004c) - (base+0x007b) receive fifo registers rxfr0 32-bit base + 0x007c receive fifo registers rxfr1 32-bit base + 0x0080 receive fifo registers rxfr2 32-bit base + 0x0084 receive fifo registers rxfr3 32-bit base + 0x0088 reserved - - (base+0x0090) - (base+0x3fff) flexcan 0 section 18.3, memory map and register description 0xfffc0000 module configuration mcr 32-bit base + 0x0000 control register ctrl 32-bit base + 0x0004 free running timer timer 32-bit base + 0x0008 reserved - - base + (0x000c - 0x000f) rx global mask register rxgmask 32-bit base + 0x0010 rx 14 mask register rx14mask 32-bit base + 0x0014 rx 15 mask register rx15mask 32-bit base + 0x0018 error counter register ecr 32-bit base + 0x001c error and status register esr 32-bit base + 0x0020 interrupt mask high register imrh 32-bit base + 0x0024 interrupt mask low register imrl 32-bit base + 0x0028 interrupt flag high register ifrh 32-bit base + 0x002c interrupt flag low register ifrl 32-bit base + 0x0030 reserved - - base + (0x0034 - 0x007f) message buffer 0 mb0 128 bits per mb base + 0x0080 message buffer 1 mb1 128 bits per mb base + 0x0090 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-50 freescale semiconductor preliminary?subject to change without notice message buffer 2 mb2 128 bits per mb base + 0x00a0 message buffer 3 mb3 128 bits per mb base + 0x00b0 message buffer 4 mb4 128 bits per mb base + 0x00c0 message buffer 5 mb5 128 bits per mb base + 0x00d0 message buffer 6 mb6 128 bits per mb base + 0x00e0 message buffer 7 mb7 128 bits per mb base + 0x00f0 message buffer 8 mb8 128 bits per mb base + 0x0100 message buffer 9 mb9 128 bits per mb base + 0x0110 message buffer 10 mb10 128 bits per mb base + 0x0120 message buffer 11 mb11 128 bits per mb base + 0x0130 message buffer 12 mb12 128 bits per mb base + 0x0140 message buffer 13 mb13 128 bits per mb base + 0x0150 message buffer 14 mb14 128 bits per mb base + 0x0160 message buffer 15 mb15 128 bits per mb base + 0x0170 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-51 preliminary?subject to change without notice message buffer 16 mb16 128 bits per mb base + 0x0180 message buffer 17 mb17 128 bits per mb base + 0x0190 message buffer 18 mb18 128 bits per mb base + 0x01a0 message buffer 19 mb19 128 bits per mb base + 0x01b0 message buffer 20 mb20 128 bits per mb base + 0x01c0 message buffer 21 mb21 128 bits per mb base + 0x01d0 message buffer 22 mb22 128 bits per mb base + 0x01e0 message buffer 23 mb23 128 bits per mb base + 0x01f0 message buffer 24 mb24 128 bits per mb base + 0x0200 message buffer 25 mb25 128 bits per mb base + 0x0210 message buffer 26 mb26 128 bits per mb base + 0x0220 message buffer 27 mb27 128 bits per mb base + 0x0230 message buffer 28 mb28 128 bits per mb base + 0x0240 message buffer 29 mb29 128 bits per mb base + 0x0250 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-52 freescale semiconductor preliminary?subject to change without notice message buffer 30 mb30 128 bits per mb base + 0x0260 message buffer 31 mb31 128 bits per mb base + 0x0270 message buffer 32 mb32 128 bits per mb base+0x0280 message buffer 33 mb33 128 bits per mb base+0x0290 message buffer 34 mb34 128 bits per mb base+0x02a0 message buffer 35 mb35 128 bits per mb base+0x02b0 message buffer 36 mb36 128 bits per mb base+0x02c0 message buffer 37 mb37 128 bits per mb base+0x02d0 message buffer 38 mb38 128 bits per mb base+0x02e0 flexcan 1 section 18.3, memory map and register description 0xfffc4000 module configuration mcr 32-bit base + 0x0000 control register ctrl 32-bit base + 0x0004 free running timer timer 32-bit base + 0x0008 reserved - - base + (0x000c - 0x000f) rx global mask register rxgmask 32-bit base + 0x0010 rx 14 mask register rx14mask 32-bit base + 0x0014 rx 15 mask register rx15mask 32-bit base + 0x0018 error counter register ecr 32-bit base + 0x001c error and status register esr 32-bit base + 0x0020 interrupt mask high register imrh 32-bit base + 0x0024 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-53 preliminary?subject to change without notice interrupt mask low register imrl 32-bit base + 0x0028 interrupt flag high register ifrh 32-bit base + 0x002c interrupt flag low register ifrl 32-bit base + 0x0030 reserved - - base + (0x0034 - 0x007f) message buffer 0 mb0 128 bits per mb base + 0x0080 message buffer 1 mb1 128 bits per mb base + 0x0090 message buffer 2 mb2 128 bits per mb base + 0x00a0 message buffer 3 mb3 128 bits per mb base + 0x00b0 message buffer 4 mb4 128 bits per mb base + 0x00c0 message buffer 5 mb5 128 bits per mb base + 0x00d0 message buffer 6 mb6 128 bits per mb base + 0x00e0 message buffer 7 mb7 128 bits per mb base + 0x00f0 message buffer 8 mb8 128 bits per mb base + 0x0100 message buffer 9 mb9 128 bits per mb base + 0x0110 message buffer 10 mb10 128 bits per mb base + 0x0120 message buffer 11 mb11 128 bits per mb base + 0x0130 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-54 freescale semiconductor preliminary?subject to change without notice message buffer 12 mb12 128 bits per mb base + 0x0140 message buffer 13 mb13 128 bits per mb base + 0x0150 message buffer 14 mb14 128 bits per mb base + 0x0160 message buffer 15 mb15 128 bits per mb base + 0x0170 message buffer 16 mb16 128 bits per mb base + 0x0180 message buffer 17 mb17 128 bits per mb base + 0x0190 message buffer 18 mb18 128 bits per mb base + 0x01a0 message buffer 19 mb19 128 bits per mb base + 0x01b0 message buffer 20 mb20 128 bits per mb base + 0x01c0 message buffer 21 mb21 128 bits per mb base + 0x01d0 message buffer 22 mb22 128 bits per mb base + 0x01e0 message buffer 23 mb23 128 bits per mb base + 0x01f0 message buffer 24 mb24 128 bits per mb base + 0x0200 message buffer 25 mb25 128 bits per mb base + 0x0210 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-55 preliminary?subject to change without notice message buffer 26 mb26 128 bits per mb base + 0x0220 message buffer 27 mb27 128 bits per mb base + 0x0230 message buffer 28 mb28 128 bits per mb base + 0x0240 message buffer 29 mb29 128 bits per mb base + 0x0250 message buffer 30 mb30 128 bits per mb base + 0x0260 message buffer 31 mb31 128 bits per mb base + 0x0270 message buffer 32 mb32 128 bits per mb base+0x0280 message buffer 33 mb33 128 bits per mb base+0x0290 message buffer 34 mb34 128 bits per mb base+0x02a0 message buffer 35 mb35 128 bits per mb base+0x02b0 message buffer 36 mb36 128 bits per mb base+0x02c0 message buffer 37 mb37 128 bits per mb base+0x02d0 message buffer 38 mb38 128 bits per mb base+0x02e0 message buffer 39 mb39 128 bits per mb base+0x02f0 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-56 freescale semiconductor preliminary?subject to change without notice message buffer 40 mb40 128 bits per mb base+0x0300 message buffer 41 mb41 128 bits per mb base+0x0310 message buffer 42 mb42 128 bits per mb base+0x0320 message buffer 43 mb43 128 bits per mb base+0x0330 message buffer 44 mb44 128 bits per mb base+0x0340 message buffer 45 mb45 128 bits per mb base+0x0350 message buffer 46 mb46 128 bits per mb base+0x0360 message buffer 47 mb47 128 bits per mb base+0x0370 message buffer 48 mb48 128 bits per mb base+0x0380 message buffer 49 mb49 128 bits per mb base+0x0390 message buffer 50 mb50 128 bits per mb base+0x03a0 message buffer 51 mb51 128 bits per mb base+0x03b0 message buffer 52 mb52 128 bits per mb base+0x03c0 message buffer 53 mb53 128 bits per mb base+0x03d0 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-57 preliminary?subject to change without notice message buffer 54 mb54 128 bits per mb base+0x03e0 message buffer 55 mb55 128 bits per mb base+0x03f0 message buffer 56 mb56 128 bits per mb base+0x0400 message buffer 57 mb57 128 bits per mb base+0x0410 message buffer 58 mb58 128 bits per mb base+0x0420 message buffer 59 mb59 128 bits per mb base+0x0430 message buffer 60 mb60 128 bits per mb base+0x0440 message buffer 61 mb61 128 bits per mb base+0x0450 message buffer 62 mb62 128 bits per mb base+0x0460 message buffer 63 mb63 128 bits per mb base+0x0470 reserved --- --- (base+0x0480) - (base+0x087f) rx individual mask register 0 rximr0 32-bit base+0x0880 rx individual mask register 1 rximr1 32-bit base+0x0884 rx individual mask register 2 rximr2 32-bit base+0x0888 rx individual mask register 3 rximr3 32-bit base+0x088c rx individual mask register 4 rximr4 32-bit base+0x0890 rx individual mask register 5 rximr5 32-bit base+0x0894 rx individual mask register 6 rximr6 32-bit base+0x0898 rx individual mask register 7 rximr7 32-bit base+0x089c table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-58 freescale semiconductor preliminary?subject to change without notice rx individual mask register 8 rximr8 32-bit base+0x08a0 rx individual mask register 9 rximr9 32-bit base+0x08a4 rx individual mask register 10 rximr10 32-bit base+0x08a8 rx individual mask register 11 rximr11 32-bit base+0x08ac rx individual mask register 12 rximr12 32-bit base+0x08b0 rx individual mask register 13 rximr13 32-bit base+0x08b4 rx individual mask register 14 rximr14 32-bit base+0x08b8 rx individual mask register 15 rximr15 32-bit base+0x08bc rx individual mask register 16 rximr16 32-bit base+0x08c0 rx individual mask register 17 rximr17 32-bit base+0x08c4 rx individual mask register 18 rximr18 32-bit base+0x08c8 rx individual mask register 19 rximr19 32-bit base+0x08cc rx individual mask register 20 rximr20 32-bit base+0x08d0 rx individual mask register 21 rximr21 32-bit base+0x08d4 rx individual mask register 22 rximr22 32-bit base+0x08d8 rx individual mask register 23 rximr23 32-bit base+0x08dc rx individual mask register 24 rximr24 32-bit base+0x08e0 rx individual mask register 25 rximr25 32-bit base+0x08e4 rx individual mask register 26 rximr26 32-bit base+0x08e8 rx individual mask register 27 rximr27 32-bit base+0x08ec rx individual mask register 28 rximr28 32-bit base+0x08f0 rx individual mask register 29 rximr29 32-bit base+0x08f4 rx individual mask register 30 rximr30 32-bit base+0x08f8 rx individual mask register 31 rximr31 32-bit base+0x08fc rx individual mask register 32 rximr32 32-bit base+0x0900 rx individual mask register 33 rximr33 32-bit base+0x0904 rx individual mask register 34 rximr34 32-bit base+0x0908 rx individual mask register 35 rximr35 32-bit base+0x090c rx individual mask register 36 rximr36 32-bit base+0x0910 rx individual mask register 37 rximr37 32-bit base+0x0914 rx individual mask register 38 rximr38 32-bit base+0x0918 rx individual mask register 39 rximr39 32-bit base+0x091c table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-59 preliminary?subject to change without notice rx individual mask register 40 rximr40 32-bit base+0x0920 rx individual mask register 41 rximr41 32-bit base+0x0924 rx individual mask register 42 rximr42 32-bit base+0x0928 rx individual mask register 43 rximr43 32-bit base+0x092c rx individual mask register 44 rximr44 32-bit base+0x0930 rx individual mask register 45 rximr45 32-bit base+0x0934 rx individual mask register 46 rximr46 32-bit base+0x0938 rx individual mask register 47 rximr47 32-bit base+0x093c rx individual mask register 48 rximr48 32-bit base+0x0940 rx individual mask register 49 rximr49 32-bit base+0x0944 rx individual mask register 50 rximr50 32-bit base+0x0948 rx individual mask register 51 rximr51 32-bit base+0x094c rx individual mask register 52 rximr52 32-bit base+0x0950 rx individual mask register 53 rximr53 32-bit base+0x0954 rx individual mask register 54 rximr54 32-bit base+0x0958 rx individual mask register 55 rximr55 32-bit base+0x095c rx individual mask register 56 rximr56 32-bit base+0x0960 rx individual mask register 57 rximr57 32-bit base+0x0964 rx individual mask register 58 rximr58 32-bit base+0x0968 rx individual mask register 59 rximr59 32-bit base+0x096c rx individual mask register 60 rximr60 32-bit base+0x0970 rx individual mask register 61 rximr61 32-bit base+0x0974 rx individual mask register 62 rximr62 32-bit base+0x0978 rx individual mask register 63 rximr63 32-bit base+0x097c reserved --- --- (base+0x0980) - (base+0x3fff) message buffer 39 mb39 128 bits per mb base+0x02f0 message buffer 40 mb40 128 bits per mb base+0x0300 message buffer 41 mb41 128 bits per mb base+0x0310 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-60 freescale semiconductor preliminary?subject to change without notice message buffer 42 mb42 128 bits per mb base+0x0320 message buffer 43 mb43 128 bits per mb base+0x0330 message buffer 44 mb44 128 bits per mb base+0x0340 message buffer 45 mb45 128 bits per mb base+0x0350 message buffer 46 mb46 128 bits per mb base+0x0360 message buffer 47 mb47 128 bits per mb base+0x0370 message buffer 48 mb48 128 bits per mb base+0x0380 message buffer 49 mb49 128 bits per mb base+0x0390 message buffer 50 mb50 128 bits per mb base+0x03a0 message buffer 51 mb51 128 bits per mb base+0x03b0 message buffer 52 mb52 128 bits per mb base+0x03c0 message buffer 53 mb53 128 bits per mb base+0x03d0 message buffer 54 mb54 128 bits per mb base+0x03e0 message buffer 55 mb55 128 bits per mb base+0x03f0 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-61 preliminary?subject to change without notice message buffer 56 mb56 128 bits per mb base+0x0400 message buffer 57 mb57 128 bits per mb base+0x0410 message buffer 58 mb58 128 bits per mb base+0x0420 message buffer 59 mb59 128 bits per mb base+0x0430 message buffer 60 mb60 128 bits per mb base+0x0440 message buffer 61 mb61 128 bits per mb base+0x0450 message buffer 62 mb62 128 bits per mb base+0x0460 message buffer 63 mb63 128 bits per mb base+0x0470 reserved --- --- (base+0x0480) - (base+0x087f) rx individual mask register 0 rximr0 32-bit base+0x0880 rx individual mask register 1 rximr1 32-bit base+0x0884 rx individual mask register 2 rximr2 32-bit base+0x0888 rx individual mask register 3 rximr3 32-bit base+0x088c rx individual mask register 4 rximr4 32-bit base+0x0890 rx individual mask register 5 rximr5 32-bit base+0x0894 rx individual mask register 6 rximr6 32-bit base+0x0898 rx individual mask register 7 rximr7 32-bit base+0x089c rx individual mask register 8 rximr8 32-bit base+0x08a0 rx individual mask register 9 rximr9 32-bit base+0x08a4 rx individual mask register 10 rximr10 32-bit base+0x08a8 rx individual mask register 11 rximr11 32-bit base+0x08ac rx individual mask register 12 rximr12 32-bit base+0x08b0 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-62 freescale semiconductor preliminary?subject to change without notice rx individual mask register 13 rximr13 32-bit base+0x08b4 rx individual mask register 14 rximr14 32-bit base+0x08b8 rx individual mask register 15 rximr15 32-bit base+0x08bc rx individual mask register 16 rximr16 32-bit base+0x08c0 rx individual mask register 17 rximr17 32-bit base+0x08c4 rx individual mask register 18 rximr18 32-bit base+0x08c8 rx individual mask register 19 rximr19 32-bit base+0x08cc rx individual mask register 20 rximr20 32-bit base+0x08d0 rx individual mask register 21 rximr21 32-bit base+0x08d4 rx individual mask register 22 rximr22 32-bit base+0x08d8 rx individual mask register 23 rximr23 32-bit base+0x08dc rx individual mask register 24 rximr24 32-bit base+0x08e0 rx individual mask register 25 rximr25 32-bit base+0x08e4 rx individual mask register 26 rximr26 32-bit base+0x08e8 rx individual mask register 27 rximr27 32-bit base+0x08ec rx individual mask register 28 rximr28 32-bit base+0x08f0 rx individual mask register 29 rximr29 32-bit base+0x08f4 rx individual mask register 30 rximr30 32-bit base+0x08f8 rx individual mask register 31 rximr31 32-bit base+0x08fc rx individual mask register 32 rximr32 32-bit base+0x0900 rx individual mask register 33 rximr33 32-bit base+0x0904 rx individual mask register 34 rximr34 32-bit base+0x0908 rx individual mask register 35 rximr35 32-bit base+0x090c rx individual mask register 36 rximr36 32-bit base+0x0910 rx individual mask register 37 rximr37 32-bit base+0x0914 rx individual mask register 38 rximr38 32-bit base+0x0918 rx individual mask register 39 rximr39 32-bit base+0x091c rx individual mask register 40 rximr40 32-bit base+0x0920 rx individual mask register 41 rximr41 32-bit base+0x0924 rx individual mask register 42 rximr42 32-bit base+0x0928 rx individual mask register 43 rximr43 32-bit base+0x092c rx individual mask register 44 rximr44 32-bit base+0x0930 table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor b-63 preliminary?subject to change without notice rx individual mask register 45 rximr45 32-bit base+0x0934 rx individual mask register 46 rximr46 32-bit base+0x0938 rx individual mask register 47 rximr47 32-bit base+0x093c rx individual mask register 48 rximr48 32-bit base+0x0940 rx individual mask register 49 rximr49 32-bit base+0x0944 rx individual mask register 50 rximr50 32-bit base+0x0948 rx individual mask register 51 rximr51 32-bit base+0x094c rx individual mask register 52 rximr52 32-bit base+0x0950 rx individual mask register 53 rximr53 32-bit base+0x0954 rx individual mask register 54 rximr54 32-bit base+0x0958 rx individual mask register 55 rximr55 32-bit base+0x095c rx individual mask register 56 rximr56 32-bit base+0x0960 rx individual mask register 57 rximr57 32-bit base+0x0964 rx individual mask register 58 rximr58 32-bit base+0x0968 rx individual mask register 59 rximr59 32-bit base+0x096c rx individual mask register 60 rximr60 32-bit base+0x0970 rx individual mask register 61 rximr61 32-bit base+0x0974 rx individual mask register 62 rximr62 32-bit base+0x0978 rx individual mask register 63 rximr63 32-bit base+0x097c reserved --- --- (base+0x0980) - (base+0x3fff) table b-2. detailed register map (continued) register description register name used size address
pxd10 microcontroller reference manual, rev. 1 b-64 freescale semiconductor preliminary?subject to change without notice
pxd10 microcontroller reference manual, rev. 1 freescale semiconductor c-1 preliminary?subject to change without notice appendix c revision history this appendix describe s corrections to the pxd10 reference manual . for convenience, the corrections are grouped by revision. this is the first revision of this manual.
pxd10 microcontroller reference manual, rev. 1 c-2 freescale semiconductor preliminary?subject to change without notice


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